A bootstrap switch circuit

Abstract

The present invention discloses a bootstrap switch circuit for an input circuit of an analog-to-digital converter, comprising: a precharge clock control circuit (10) connected to a clock (CLK), and a bootstrap voltage generation circuit (20) connected to the precharge clock control circuit (10), wherein the precharge clock control circuit (10) is configured to generate a precharge signal, a hold signal, and a follow signal; and the bootstrap voltage generation circuit (20) is configured to achieve voltage multiplication and includes only one bootstrap capacitor (C boot ).

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and particularly to a bootstrap switch circuit. Background Art

[0002] The bootstrap switch circuit is a commonly used switch technology for the input stage of high-precision analog-to-digital converters, which can reduce the non-linearity of the sampling system. Figure 5 It is a traditional bootstrap switch sampling circuit, including two parts: a voltage multiplier circuit and a switch circuit. The multiplied voltage first charges the voltages at both ends of the upper and lower plates of C1 and C2 to VDD. Then, the voltage of the lower plate of C1 and C2 jumps between 0 and VDD, and the voltage of the upper plate of C1 jumps between VDD and 2VDD, and is used as the control signal of M3. When CLK is high, the bootstrap capacitor C boot is charged to VDD through M3. When CLK is low, M3, M 12 is turned off, and C boot is floating and isolated from the voltage multiplier circuit. During the switching control operation, when CLK is high, the gate of M 11 is pulled low to ground by M7 and M 10 , and the bootstrap capacitor C boot enters the holding state. At the same time, M8 and M9 are turned off, cutting off the path between the bootstrap capacitor and the sampling switch. When the clock CLK is low, M8 and M9 are turned on, and the bootstrap capacitor C boot is connected to the source and gate of M 11 , and M7 and M 10 are turned off, cutting off the path from the gate of M 11 to ground. This switch can increase the on-voltage of the input transistor M 11 to VDD, effectively reducing the on-resistance and the on-voltage does not change with the input signal, having strong linearity. However, this bootstrap switch circuit has a large area due to the additional two capacitors in the voltage multiplier circuit, increasing the cost of the chip.

[0003] Aiming at the technical problem in the above-mentioned prior art that the traditional bootstrap switch circuit has an increased capacitance and area due to the multiplied voltage, resulting in an increase in the cost of the chip, no effective solution has been proposed yet. Summary of the Invention

[0004] The present invention discloses and provides a bootstrap switch circuit to at least solve the technical problem in the prior art that the traditional bootstrap switch circuit has an increased capacitance and area due to the multiplied voltage, resulting in an increase in the cost of the chip.

[0005] According to one aspect of the present invention, a bootstrap switch circuit for an input circuit of an analog converter is provided, including: a precharge clock control circuit connected to a clock and a bootstrap voltage generation circuit connected to the precharge clock control circuit, wherein the precharge clock control circuit is configured to generate a precharge signal, a hold signal, and a follow signal; and the bootstrap voltage generation circuit is configured to achieve voltage multiplication and includes only one bootstrap capacitor.

[0006] Optionally, the precharge clock control circuit includes: a delay unit, a precharge signal generation circuit, a hold signal generation circuit, and a follow signal generation circuit, wherein an input end of the delay unit is connected to the clock.

[0007] Optionally, the precharge signal generation circuit includes: a first inverter, a first AND gate, and a second inverter, wherein an input end of the first inverter is connected to an output end of the delay unit; two input ends of the first AND gate are respectively connected to the output end of the delay unit and the output end of the first inverter; and an input end of the second inverter is connected to an output end of the first AND gate, and an output end of the second inverter is connected to the bootstrap voltage generation circuit.

[0008] Optionally, the hold signal generation circuit includes: a second AND gate, wherein two input ends of the second AND gate are respectively connected to an input end and an output end of the delay unit, and an output end of the second AND gate is connected to the bootstrap voltage generation circuit.

[0009] Optionally, the follow signal generation circuit includes: a third inverter, wherein an input end of the third inverter is connected to the input end of the delay unit, and an output end of the third inverter is connected to the bootstrap voltage generation circuit.

[0010] Optionally, the bootstrap voltage generation circuit is composed of a bootstrap capacitor, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, and a load capacitor, wherein the fourth transistor, the fifth transistor, the eighth transistor, the tenth transistor, the eleventh transistor, the fourteenth transistor, and the fifteenth transistor are PMOS transistors; and the first transistor, the second transistor, the third transistor, the sixth transistor, the seventh transistor, the ninth transistor, the twelfth transistor, and the thirteenth transistor are NMOS transistors.

[0011] Optionally, the drain of the first transistor is connected to the source of the second transistor and the signal input terminal Vin, the source is connected to the drain of the third transistor, the source of the ninth transistor, and the lower plate of the bootstrap capacitor, and the gate is connected to the gate of the fifth transistor, the source of the eleventh transistor, the drain of the fifteenth transistor, the gate of the second transistor, and the drain of the seventh transistor; the drain of the second transistor is connected to the load capacitor to ground; the gate of the third transistor is connected to the gate of the sixth transistor and the output terminal of the third inverter, and the source is connected to the source of the thirteenth transistor, the source of the sixth transistor, and ground; the gate of the fourth transistor is connected to the output terminal of the second AND gate; the drain of the fifth transistor is connected to the drain of the fourth transistor; the gate of the sixth transistor is connected to the source of the seventh transistor; the source of the eighth transistor is connected to the power supply, the source of the fourth transistor and the tenth transistor, and the gates of the seventh transistor and the twelfth transistor; the drain of the ninth transistor is connected to the gates of the fourteenth transistor and the fifteenth transistor and the drain of the eighth transistor, and the gate is connected to the output terminal of the second AND gate, the gates of the eighth transistor and the fourth transistor; the gate of the tenth transistor is connected to the output terminal of the second inverter; the drain of the eleventh transistor is connected to the drain of the tenth transistor; the gate of the thirteenth transistor is connected to the output terminal of the first AND gate; the drain of the fourteenth transistor is connected to the gate of the eleventh transistor and the drain of the twelfth transistor; and the upper plate of the bootstrap capacitor is connected to the sources of the fifth transistor, the fourteenth transistor, and the fifteenth transistor.

[0012] Thus, according to a bootstrap switch circuit provided by the present invention, a precharge signal, a hold signal, and a follow signal are generated by a precharge clock control circuit, and then voltage multiplication is achieved through a connected bootstrap voltage generation circuit. Among them, there is only one bootstrap capacitor C in the bootstrap voltage generation circuit boot , and compared with the traditional bootstrap switch, it has a smaller capacitance area, greatly reducing the chip cost. Furthermore, it solves the technical problem in the prior art that the traditional bootstrap switch circuit adds an extra capacitor for the multiplied voltage, resulting in an increased area and thus an increase in the chip cost.

[0013] Those skilled in the art will become more apparent about the above and other objects, advantages, and features of the present invention according to the following detailed description of the specific embodiments of the present invention in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Some specific embodiments of the present invention will be described in detail hereinafter with reference to the accompanying drawings in an exemplary but not restrictive manner. The same reference numerals in the drawings denote the same or similar components or parts. Those skilled in the art should understand that these drawings are not necessarily drawn to scale. In the drawings:

[0015] Figure 1 is a schematic diagram of the bootstrap switch circuit according to an embodiment of the present invention;

[0016] Figure 2 isFigure 1 Schematic diagram of the precharge clock control circuit shown;

[0017] Figure 3 is Figure 1 Schematic diagram of the bootstrap voltage generation circuit shown;

[0018] Figure 4 is a schematic diagram for the clock logic in an embodiment of the present invention to control the bootstrap switch circuit; and

[0019] Figure 5 is a conventional bootstrap switch sampling circuit. Specific embodiments

[0020] It should be noted that, without conflict, the embodiments in this disclosure and the features in the embodiments may be combined with each other. The following will describe this disclosure in detail with reference to the drawings and in combination with the embodiments.

[0021] In order to enable those skilled in the art to better understand the solutions of this disclosure, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the drawings in the embodiments of this disclosure. Obviously, the described embodiments are only a part of the embodiments of this disclosure, rather than all of the embodiments. Based on the embodiments in this disclosure, all other embodiments obtained by those of ordinary skill in the art without making creative efforts shall fall within the protection scope of this disclosure.

[0022] It should be noted that the terms "first", "second", etc. in the description and claims of this disclosure and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily need to be used to describe a specific order or sequence. It should be understood that such terms can be interchanged under appropriate circumstances so as to describe the embodiments of this disclosure here. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0023] It should be noted that the terms used here are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present invention. As used here, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components and / or combinations thereof.

[0024] Figure 1It is a schematic diagram of the bootstrap switch circuit according to an embodiment of the present invention. Refer to Figure 1 As shown, the bootstrap switch circuit is used for the input circuit of the analog-to-digital converter, and includes: a pre-charge clock control circuit 10 connected to the clock CLK and a bootstrap voltage generation circuit 20 connected to the pre-charge clock control circuit 10. The pre-charge clock control circuit 10 is used to generate a pre-charge signal, a hold signal, and a follow signal; and the bootstrap voltage generation circuit 20 is used to achieve voltage multiplication and includes only one bootstrap capacitor C boot .

[0025] As described in the background art, a traditional switch can increase the on-voltage to VDD, effectively reduce the on-resistance, and the on-voltage does not change with the input signal, having strong linearity. However, this kind of bootstrap switch circuit has a large area due to the additional two capacitors in the voltage multiplication circuit, increasing the cost of the chip.

[0026] In view of this, an embodiment of the present invention provides a bootstrap switch circuit. Refer to Figure 1 As shown, the pre-charge clock control circuit 10 generates a pre-charge signal, a hold signal, and a follow signal, and then the connected bootstrap voltage generation circuit 20 realizes voltage multiplication. There is only one bootstrap capacitor C in the bootstrap voltage generation circuit 20 boot , having a smaller capacitor area compared with the traditional bootstrap switch, greatly reducing the technical effect of the chip cost. Furthermore, it solves the technical problem in the prior art that the traditional bootstrap switch circuit has an increased capacitor due to the voltage multiplication, resulting in an increased area and thus an increased chip cost.

[0027] Optionally, the pre-charge clock control circuit 10 includes a delay unit DELAY, a pre-charge signal generation circuit 110, a hold signal generation circuit 120, and a follow signal generation circuit 130, where the input end of the delay unit DELAY is connected to the clock CLK.

[0028] Specifically, refer to Figure 2 As shown, one end of the pre-charge clock control circuit 10 is connected to the clock CLK and includes a delay unit DELAY. The pre-charge signal is generated by the pre-charge signal generation circuit 110, the hold signal is generated by the hold signal generation circuit 120, and the follow signal is generated by the follow signal generation circuit 130. Thus, through the above settings of the pre-charge clock control circuit 10, the pre-charge signal, the hold signal, and the follow signal for realizing voltage multiplication are generated.

[0029] Optionally, refer to Figure 2As shown, the pre-charge signal generation circuit 110 includes: a first inverter INV1, a first AND gate AND1, and a second inverter INV2, where the input terminal of the first inverter INV1 is connected to the output terminal of the delay unit DELAY; two input terminals of the first AND gate AND1 are respectively connected to the output terminal of the delay unit DELAY and the output terminal of the first inverter INV1; and the input terminal of the second inverter INV2 is connected to the output terminal of the first AND gate AND1, and the output terminal of the second inverter INV2 is connected to the bootstrap voltage generation circuit 20. Thus, the generation of the pre-charge signal is achieved through the above settings.

[0030] Optionally, referring to Figure 2 As shown, the hold signal generation circuit 120 includes: a second AND gate AND2, where two input terminals of the second AND gate AND2 are respectively connected to the input terminal and the output terminal of the delay unit DELAY, and the output terminal of the second AND gate AND2 is connected to the bootstrap voltage generation circuit 20. Thus, the generation of the hold signal is achieved through the above settings.

[0031] Optionally, referring to Figure 2 As shown, the follow signal generation circuit 130 includes: a third inverter INV3, where the input terminal of the third inverter INV3 is connected to the input terminal of the delay unit DELAY, and the output terminal of the third inverter INV3 is connected to the bootstrap voltage generation circuit 20. Thus, the generation of the follow signal is achieved through the above settings.

[0032] Optionally, referring to Figure 3 As shown, the bootstrap voltage generation circuit 20 consists of a bootstrap capacitor C boot , a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M 10 , an eleventh transistor M 11 , a twelfth transistor M 12 , a thirteenth transistor M 13 , a fourteenth transistor M 14 , a fifteenth transistor M 15 and a load capacitor C load constitute. Among them, the fourth transistor M4, the fifth transistor M5, the eighth transistor M8, the tenth transistor M 10 , the eleventh transistor M 11 , the fourteenth transistor M 14 and the fifteenth transistor M15 are PMOS transistors; and the first transistor M1, the second transistor M2, the third transistor M3, the sixth transistor M6, the seventh transistor M7, the ninth transistor M9, the twelfth transistor M 12 and the thirteenth transistor M13 is an NMOS transistor. Through the above settings, the bootstrap voltage generation circuit achieves the effect of voltage multiplication.

[0033] In addition, referring to Figure 3 as shown, the bootstrap voltage generation circuit 20 can also be composed of a charging circuit, a hold signal circuit, and a follow signal circuit. Among them, the pre-charge voltage circuit is a circuit for generating a pre-charge voltage. The pre-charge voltage circuit includes two control signal transistors (the tenth transistor M 10 and the thirteenth transistor M 13 ) and voltage generating transistors (the eleventh transistor M 11 and the twelfth transistor M 12 ). The hold signal circuit includes control signal switches (the third transistor M3 and the sixth transistor M6) and a bootstrap capacitor C boot . The control signal switches are used to control the circuit to be in the hold state, and the bootstrap capacitor is used to store the bootstrap voltage. The follow signal circuit includes a sampling switch (the first transistor M1) and a sample-and-hold control switch (the fourth transistor M4, the eighth transistor M8, and the ninth transistor M9). The sampling switch is used to receive the input voltage signal and the gate voltage signal, and the sample-and-hold control switch is used to control the working state of the bootstrap capacitor.

[0034] Optionally, referring to Figure 3 as shown, the drain of the first transistor M1 is connected to the source of the second transistor M2 and the signal input terminal Vin. The source is connected to the drain of the third transistor M3, the source of the ninth transistor M9, and the lower plate of the bootstrap capacitor C boot . The gate is connected to the gate of the fifth transistor M5, the source of the eleventh transistor M 11 , the drain of the fifteenth transistor M 15 , the gate of the second transistor M2, and the drain of the seventh transistor M7. The drain of the second transistor M2 is connected to the load capacitor C load to ground. The gate of the third transistor M3 is connected to the gate of the sixth transistor M6 and the output terminal of the third inverter INV3. The source is connected to the source of the thirteenth transistor M 13 , the source of the sixth transistor M6, and ground. The gate of the fourth transistor M4 is connected to the output terminal of the second AND gate AND2. The drain of the fifth transistor M5 is connected to the drain of the fourth transistor M4. The drain of the sixth transistor M6 is connected to the source of the seventh transistor M7. The source of the eighth transistor M8 is connected to the power supply VDD, the fourth transistor M4, and the source of the tenth transistor M 10 , as well as the gate of the seventh transistor M7 and the twelfth transistor M 12 . The drain of the ninth transistor M9 is connected to the fourteenth transistor M 14 and the fifteenth transistor M 15The gate of the [transistor] and the drain of the eighth transistor M8, the gate is connected to the output terminal of the second AND gate AND2, the gates of the eighth transistor M8 and the fourth transistor M4; the gate of the tenth transistor M 10 is connected to the output terminal of the second inverter INV2; the drain of the eleventh transistor M 11 is connected to the drain of the tenth transistor M 10 ; the gate of the thirteenth transistor M 13 is connected to the output terminal of the first AND gate AND1; the drain of the fourteenth transistor M 14 is connected to the gate of the eleventh transistor M 11 and the drain of the twelfth transistor M 12 ; and the upper plate of the bootstrap capacitor C boot is connected to the sources of the fifth transistor M5, the fourteenth transistor M 14 and the fifteenth transistor M 15 . Through the above connections, the bootstrap voltage generation circuit achieves the effect of voltage multiplication.

[0035] In addition, as shown in Figure 4 , a schematic diagram showing the clock logic for controlling the bootstrap switch circuit is shown. During the signal holding stage, the Hld signal is high, the Trk signal and the Prech signal are low, M6, M7, and M8 are turned on, the gates of M1 and M2 are pulled low, and the gate of M 15 is pulled high, M1, M2, and M 15 are turned off, M3, M4, and M5 are turned on, and the upper plate of Cboot is charged to VDD; subsequently, during the pre-charge stage, the Prech signal is high, the Prech_b signal is low, the Hld signal and the Trk signal are low, and M 10 , M 11 , M 12 , M 13 are all turned on, and the gates of M1 and M2 are pulled high to VDD; subsequently, during the tracking stage, the Trk signal is high, the Hld signal and the Prech signal are low, M9 is turned on, and the source-gate voltage of M 14 and M 15 is the holding voltage VDD on the bootstrap capacitor Cboot. M 14 and M 15 are turned on, so that the gate-source voltage clock of M5 and M 11 is 0, M5 and M 11 remain in the off state, the upper plate of Cboot is in a high-impedance environment, and the gate-source voltage of M1 and M2 continues to maintain the voltage VDD between the two plates of the bootstrap capacitor Cboot. When there is an input voltage Vin, the gate voltage of M2 rises to VDD + Vin, and the gate-source voltage of M2 remains VDD unchanged. The input switch transistor M2 has high linearity. Therefore, there is only one switching holding capacitor in the circuit of the present invention, and it has a smaller capacitor area compared with the traditional bootstrap switch, reducing the cost of the chip.

[0036] According to an embodiment of the present invention, a bootstrap switch circuit is provided. The pre-charge clock control circuit 10 generates a pre-charge signal, a hold signal, and a follow signal, and then the bootstrap voltage generation circuit 20 connected thereto realizes voltage multiplication. There is only one bootstrap capacitor C in the bootstrap voltage generation circuit 20 boot , which has a smaller capacitance area compared with the traditional bootstrap switch, and greatly reduces the technical effect of the chip cost. Furthermore, it solves the technical problem in the prior art that the traditional bootstrap switch circuit adds capacitance due to the multiplied voltage, resulting in an increased area and thus an increased chip cost.

[0037] In addition, the trend of TWS products is to use higher-performance and smaller-area voice codec chips to support the increasingly fierce market competition. The working characteristics of the analog-to-digital conversion module in the codec chip directly determine the voice fidelity of the chip and the performance of the active noise reduction module. A bootstrap switch circuit with high linearity and low area cost is designed for the input stage of this module and can be implemented in a 28nm complementary metal-oxide-semiconductor (CMOS) process.

[0038] Unless otherwise specifically stated, the relative arrangement, digital expressions, and numerical values of the components and steps described in these embodiments do not limit the scope of the present disclosure. At the same time, it should be understood that, for the sake of description, the dimensions of the various parts shown in the drawings are not drawn in actual proportional relationships. Technologies, methods, and devices known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, the said technologies, methods, and devices should be regarded as part of the authorization specification. In all the examples shown and discussed here, any specific value should be construed as merely exemplary and not as a limitation. Therefore, other examples of the exemplary embodiments may have different values. It should be noted that like reference numerals and letters denote like items in the following drawings, and thus, once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0039] For ease of description, spatial relative terms such as "above", "over", "on the upper surface", "upper" etc. can be used here to describe the spatial positional relationship of a device or feature shown in the figure with other devices or features. It should be understood that the spatial relative terms are intended to cover different orientations in use or operation in addition to the orientation depicted in the figure. For example, if the device in the figure is inverted, the device described as "above or over other devices or structures" will then be positioned "below or under other devices or structures". Thus, the exemplary term "above" can include both the orientations of "above" and "below". The device can also be positioned in other different ways (rotated 90 degrees or in other orientations), and corresponding interpretations should be made for the spatial relative descriptions used here.

[0040] In the description of the present disclosure, it should be understood that the orientation or positional relationship indicated by orientation words such as "front, rear, upper, lower, left, right", "lateral, vertical, perpendicular, horizontal" and "top, bottom" etc. is usually based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present disclosure and simplifying the description. Without contrary description, these orientation words do not indicate or imply that the device or element referred to must have a specific orientation or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation on the protection scope of the present disclosure; the orientation words "inside, outside" refer to the inside and outside relative to the contour of each component itself.

[0041] As described above, only the preferred specific embodiments of the present invention are given, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered by the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

1. A bootstrap switch circuit for an input circuit of an analog-to-digital converter, characterized in that, Comprising: A precharge clock control circuit (10) connected to a clock (CLK) and a bootstrap voltage generation circuit (20) connected to the precharge clock control circuit (10), wherein The precharge clock control circuit (10) is used to generate a precharge signal, a hold signal, and a follow signal, and includes: a delay unit (DELAY), a precharge signal generation circuit (110), a hold signal generation circuit (120), and a follow signal generation circuit (130); The precharge signal generation circuit (110) includes: a first inverter (INV1), a first AND gate (AND1), and a second inverter (INV2), wherein The input terminal of the first inverter (INV1) is connected to the output terminal of the delay unit (DELAY); Two input terminals of the first AND gate (AND1) are respectively connected to the output terminal of the delay unit (DELAY) and the output terminal of the first inverter (INV1); and The input terminal of the second inverter (INV2) is connected to the output terminal of the first AND gate (AND1), and the output terminal of the second inverter (INV2) is connected to the bootstrap voltage generation circuit (20); The hold signal generation circuit (120) includes: a second AND gate (AND2), wherein Two input terminals of the second AND gate (AND2) are respectively connected to the input terminal and the output terminal of the delay unit (DELAY), and the output terminal of the second AND gate (AND2) is connected to the bootstrap voltage generation circuit (20); The follow signal generation circuit (130) includes: a third inverter (INV3), wherein The input terminal of the third inverter (INV3) is connected to the input terminal of the delay unit (DELAY), and the output terminal of the third inverter (INV3) is connected to the bootstrap voltage generation circuit (20); and The bootstrap voltage generation circuit (20) is used to achieve voltage multiplication and includes only one bootstrap capacitor (C boot ). The composition structure of the bootstrap voltage generation circuit (20) is as follows: the drain of the first transistor (M1) is connected to the source of the second transistor (M2) and the signal input terminal (Vin), the source is connected to the drain of the third transistor (M3), the source of the ninth transistor (M9), and the lower plate of the bootstrap capacitor (C boot ), the gate is connected to the gate of the fifth transistor (M5), the source of the eleventh transistor (M 11 ), the drain of the fifteenth transistor (M 15 ), the gate of the second transistor (M2), and the drain of the seventh transistor (M7); The drain of the second transistor (M2) is connected to the load capacitor (C load ) to ground; The gate of the third transistor (M3) is connected to the gate of the sixth transistor (M6) and the output terminal of the third inverter (INV3), and the source is connected to the source of the thirteenth transistor (M 13 ) and the source of the sixth transistor (M6) and ground; The gate of the fourth transistor (M4) is connected to the output terminal of the second AND gate (AND2); The drain of the fifth transistor (M5) is connected to the drain of the fourth transistor (M4); The drain of the sixth transistor (M6) is connected to the source of the seventh transistor (M7); The source of the eighth transistor (M8) is connected to the power supply (VDD), the sources of the fourth transistor (M4) and the tenth transistor (M 10 ), and the gates of the seventh transistor (M7) and the twelfth transistor (M 12 ), and the gate is connected to the output terminal of the second AND gate (AND2); The drain of the ninth transistor (M9) is connected to the gates of the fourteenth transistor (M 14 ) and the fifteenth transistor (M 15 ), and the drain of the eighth transistor (M8). The gate is connected to the output terminal of the second AND gate (AND2), and the gates of the eighth transistor (M8) and the fourth transistor (M4); The gate of the tenth transistor (M 10 ) is connected to the output terminal of the second inverter (INV2); The drain of the eleventh transistor (M 11 ) is connected to the drain of the tenth transistor (M 10 ); The gate of the thirteenth transistor (M 13 ) is connected to the output terminal of the first AND gate (AND1); The fourteenth transistor (M 14 ) has its drain connected to the gate of the eleventh transistor (M 11 ) and the drain of the twelfth transistor (M 12 ); and The upper plate of the bootstrap capacitor (C boot ) is connected to the sources of the fifth transistor (M5), the fourteenth transistor (M 14 ), and the fifteenth transistor (M 15 ).

2. The bootstrap switch circuit according to claim 1, characterized in that, The input terminal of the delay unit (DELAY) is connected to the clock (CLK).

3. The bootstrap switch circuit according to claim 1, characterized in that, The fourth transistor (M4), the fifth transistor (M5), the eighth transistor (M8), the tenth transistor (M 10 ), the eleventh transistor (M 11 ), the fourteenth transistor (M 14 ), and the fifteenth transistor (M 15 ) are PMOS transistors; and The first transistor (M1), the second transistor (M2), the third transistor (M3), the sixth transistor (M6), the seventh transistor (M7), the ninth transistor (M9), the twelfth transistor (M 12 ) and the thirteenth transistor (M 13 ) are NMOS transistors.

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