Multi-standard low-density parity-check decoder

Abstract

The present disclosure relates to multi-standard low-density parity-check decoders. A wireless receiving device includes low-density parity-check (LDPC) decoding circuitry including a cyclic shifter structured and arranged to simultaneously process multiple codewords for parity check matrices configured for different wireless communication standards, including performing cyclic shift operations of the multiple codewords to align with one or more required check nodes of a decoder; and logic circuitry at an output of the cyclic shifter structured and arranged for greater than a matrix of the parity check matrices and including components having excess hardware due to the structure and arrangement for the greater matrix to decode the multiple codewords for the smaller parity check matrices to output to the one or more required check nodes.

Description

Technical Field

[0001] This disclosure generally relates to error correction in data communications, and more specifically to a low-density parity-check (“LDPC”) decoder that processes code characterized by a parity-check matrix for correcting channel errors, regardless of the industry standards followed by the data. Background Technology

[0002] Modern wireless devices typically include a combination of encoders and decoders that employ various error-correcting decoding techniques to handle noise, interference, and other factors associated with the communication channel formed between the transmitter and receiver. For example, a receiver can apply a decoder to determine whether a received signal has been corrupted after transmission and to correct any detected errors. Low-density parity-check (“LDPC”) codes are one type of error-correcting code. However, LDPC encoders and decoders often communicate according to various industry or technical standards, requiring different hardware for each standard, which consumes valuable space on computer chips.

[0003] Additionally, extra silicon area is required to house multiple decoders, specifically various processors such as the Check Node Update (CNU) processor and the Variable Node Update (VNU) processor, which operate in parallel to meet increasing system throughput requirements. In doing so, data dependencies and RAM access conflicts can limit the number of parallel CNUs and VNUs in the LDPC decoder. For example, a CNU processes rows on a parity matrix, the results of which are processed by a VNU. Here, a VNU cannot process a specific row and column until the CNU has finished processing the entire previous row. Summary of the Invention

[0004] As should be understood, the disclosed embodiments include at least the following embodiments. In one embodiment, a wireless receiving device includes a low-density parity-check (LDPC) decoding circuit, the LDPC decoding circuit including: a cyclic shifter (310) configured and arranged to simultaneously process a plurality of codewords of parity-check matrices configured for different wireless communication standards, including performing cyclic shift operations on the plurality of codewords to align with one or more required parity-check nodes of the decoder; and logic circuitry (312, 313, 314) at the output of the cyclic shifter, the logic circuitry (312, 313, 314) configured and arranged for matrices larger than the parity-check matrices and including components having redundant hardware due to the construction and arrangement for the larger matrices, to decode the plurality of codewords of smaller parity-check matrices for output to the one or more required parity-check nodes.

[0005] Alternative embodiments of the wireless receiving device include one or any combination of the following features.

[0006] The redundant hardware includes one or more of a data path, random access memory, and trigger storage device that are reused to decode the plurality of codewords.

[0007] The LDPC decoding circuit further includes at least one parity node update (CNU) processor and at least one variable node update (VNU) processor, the at least one CNU processor including the cyclic shifter and the at least one VNU processor receiving the output of the logic circuit operating on the submatrices of the parity check matrix in each clock cycle.

[0008] The logic circuit includes a minimum data generator unit that identifies a first minimum and a second minimum in the rows of the parity check matrix, wherein the CNU processor includes a memory that stores the current minimum of the row when updating the memory for each column of the parity check matrix, wherein a copy of the minimum is stored, and wherein the VNU processor processes the stored copy of the minimum to process the row previously processed by the at least one CNU processor.

[0009] The memory stores the minimum value of two or more rows of the parity matrix processed by the at least one CNU processor.

[0010] The memory includes one or more trigger circuits.

[0011] The cyclic shifter shifts one row of the CNU processor at a time and stores the results from the two rows separately, wherein the VNU processor processes the submatrix of the parity matrix from the results of the two rows.

[0012] The cyclic shifter simultaneously shifts the multiple codewords.

[0013] The cyclic shifter shifts a group of codewords in the parity check matrix to the right by a predetermined number of positions at a time, in order to receive and process the next group of codewords in the parity check matrix.

[0014] In another embodiment, a low-density parity-check (LDPC) decoding circuit for a wireless device includes: a variable node update (VNU) processor; a check node update (CNU) processor; and a matrix processing system including: a dedicated memory device storing at least a first row and a second row of CNU data generated by the CNU processor; and a decoding processor processing the results of the at least first row and the second row of the CNU data to output to the VNU processor.

[0015] Alternative embodiments of the LDPC decoding circuitry include one or any combination of the following features. At least one of the VNU processor, the CNU processor, and the matrix processing system includes additional circuitry configured and arranged to process matrices larger than the matrix comprising rows of CNU data, wherein said additional circuitry simultaneously processes multiple codewords from the first and second rows of CNU data. The redundant hardware includes one or more of a data path, random access memory, and trigger memory repurposed for decoding the multiple codewords.

[0016] The matrix processing system further includes a shifter that receives the output of operations performed on a submatrix in each clock cycle. The shifter shifts one row at a time, the dedicated memory device stores two results from the first and second rows, and the VNU processor processes the submatrix of the parity matrix from the results of the two rows. The cyclic shifter shifts a set of codewords of the parity matrix to the right a predetermined number of positions at a time to receive and process the next set of codewords of the parity matrix. The LDPC decoding circuit further includes a minimum data generator unit that identifies a first minimum and a second minimum value in the first and second rows, wherein the CNU processor stores the current minimum value of the row when updating memory for each column of the parity matrix, wherein a copy of the minimum value is stored, and wherein the VNU processor processes the stored copy of the minimum value to process the row previously processed by at least one CNU processor.

[0017] The memory includes one or more trigger circuits.

[0018] In another embodiment, a method of operating a low-density parity-check (LDPC) decoder includes: simultaneously processing multiple codewords of a parity-check matrix configured for different wireless communication standards by a cyclic shifter, including: performing a cyclic shift operation on the multiple codewords to align them with one or more required parity check nodes; processing the multiple codewords by redundant hardware of the LDPC decoder constructed and arranged for a matrix larger than the parity-check matrix, including: decoding the multiple codewords of the parity-check matrix to output to the one or more required parity check nodes; storing two or more rows of results including the multiple codewords; and processing the parity-check matrix from the stored two or more rows of results by a variable node update (VNU) processor.

[0019] Alternative embodiments of the method include one or any combination of the following features. Performing the cyclic shift operation includes shifting one row of the CNU processor corresponding to the plurality of codewords at a time, storing the results of the two rows of the results, and processing a submatrix of the parity check matrix from the two rows of results by the VNU processor.

[0020] Perform a cyclic shift, while shifting the plurality of codewords to the right by a predetermined number of positions to receive and process the next set of plurality of codewords in the parity check matrix. Attached Figure Description

[0021] This invention is illustrated by way of example and is not limited to the accompanying drawings, in which similar reference numerals indicate similar elements. The elements in the drawings are shown for simplicity and clarity, and these elements are not necessarily drawn to scale.

[0022] Figure 1 This is a block diagram of a system in which the concept of the present invention is practiced, the system including a wireless transceiver for exchanging and processing signals encoded using LDPC codes.

[0023] Figure 2 This is a block diagram of a multi-standard LDPC decoder according to some embodiments.

[0024] Figure 3 According to some embodiments Figure 2 A schematic diagram of the matrix processing system of the LDPC decoder.

[0025] Figure 4 This is a view of the data arrangement during the operation of a cyclic shifter according to some embodiments.

[0026] Figure 5 This is a view of the data arrangement during the operation of a cyclic shifter according to other embodiments.

[0027] Figure 6This is a flowchart illustrating the operation method of a multi-standard LDPC decoder according to some embodiments.

[0028] Figure 7 This is a block diagram of a multi-standard LDPC decoder according to some embodiments.

[0029] Figure 8 This is a flowchart illustrating the operation method of a multi-standard LDPC decoder according to some embodiments.

[0030] Figure 9 A graphical representation of a parity check matrix according to some embodiments is shown. Detailed Implementation

[0031] Quasi-cyclic low-density parity-check (“QC-LDPC”) codes are a class of error-correcting LDPC codes used in a variety of applications, including 5G and / or other wireless communication processors, such as computer chips supporting some or all of the current global cellular standards, like 5G. LDPC decoders typically implement a combination of a check node update (CNU) processor, a variable node update (VNU) processor, and a shared memory structure for transferring messages between the VNU and CNU. However, despite physical constraints on the chip, such as the number of processors consuming chip silicon area, it is desirable to increase the throughput of the LDPC decoder, particularly to enable the decoder to perform multi-standard LDPC processing.

[0032] In simple terms, embodiments of the error correction decoder architecture are adaptable to increased data throughput. Compared to conventional techniques that require a large number of CNUs and VNUs to achieve the same or similar desired throughput, the error correction decoder architecture requires fewer silicon-intensive LDPC encoders and decoders, including the encoder and decoder combination. The error correction decoder architecture reuses data paths, RAM, trigger storage devices, and / or other logic circuitry configured for large matrices to simultaneously decode multiple smaller codewords of submatrices. In some embodiments, the LPDC decoder is an iterative error correction decoder that includes a massively parallel network of parity nodes and variable nodes for processing the largest possible parity matrix. The LDPC decoder includes hardware components to house this matrix. However, in conventional configurations, because the decoder is configured to process the largest possible matrix, some hardware components of the decoder are not used when processing smaller matrices, resulting in inefficiency. Some embodiments of the LDPC decoder of the present invention are more efficient because the LDPC decoder processes multiple code blocks at a time—including using this additional hardware—and can therefore handle matrices of varying sizes due to adherence to different standards (e.g., various different wireless communication standards). Other embodiments include cyclic shifters configured and arranged to address any unused data paths in RAM by accommodating multiple codewords from different matrices or submatrices, regardless of the standards followed by the different matrices or submatrices.

[0033] In some embodiments, the decoder utilizes hardware components capable of processing larger individual codeword sub-blocks to process multiple code blocks with small sub-block LDPC codes. As previously mentioned, multiple sub-matrices can be processed simultaneously. In doing so, the results produced by the CNU are stored in memory, allowing the VNU to process any sub-matrices from two or more rows. Therefore, a smaller LDPC decoder is needed to meet throughput requirements that would otherwise require a larger number of LDPC decoders. Some conventional architectures require doubling the number of CNUs to increase throughput. On the other hand, some embodiments of the LDPC decoder of the present invention double the CNU output storage space but not the CNU data path. This feature allows processing one sub-matrice at a time but storing additional rows (e.g., two rows) of CNU results (different from CNU messages) so that the VNU can process any sub-matrices from two rows of CNU results, and in doing so, reduces RAM access contention and facilitates data dependency. For example, the VNU and CNU can operate on the sub-matrices in each clock cycle. In doing so, the VNU and CNU require data input and memory locations to store their output data. This data is stored in RAM embedded in the silicon chip. RAM that uses minimal silicon area and allows only a single read or write access per clock cycle is called single-port RAM. Contention can occur if multiple processing units need to access RAM within the same cycle. This can be resolved by requiring some requesting units to wait, but this reduces throughput. To address VNU and CNU contention, embodiments of this invention use RAM that allows both read and write operations within the same cycle. This type of RAM is only slightly larger than single-port RAM because it does not repeatedly read or write to the hardware. The challenge here is that using multiple VNUs and CNUs can exacerbate the risk of contention, as both CNU and VNU require data per cycle.

[0034] Furthermore, the CNU output storage device, used to store the results of additional rows of CNU, provides greater flexibility in reordering operations for the VNU without requiring repeated CNU operations that consume area. For example, the CNU finds the first and second minimum values ​​in a row. The CNU stores the current minimum value of the row as it updates the memory for each column it processes. After the CNU completes the entire row, it saves the minimum value as a saved copy. The VNU then uses this saved copy to process the rows previously completed by the CNU.

[0035] In some embodiments, the aforementioned processing follows a set of predetermined rules. Columns must be processed alternately as follows: CNU-VNU-CNU-VNU, and so on. The CNU cannot process the same column again until the VNU updates it. Due to RAM contention, the CNU and VNU cannot process the same column in the same cycle. The CNU cannot update its saved minimum value until the VNU has finished processing it. The VNU cannot begin processing a row until the CNU has finished processing it. Consider... Figure 9 The CNU processing for line 4 is shown. Here, the CNU has only three non-blank entries in this line, indicating that the CNU will complete within 3 cycles. However, since the conventional implementation only saves the value of a single line, and due to the rules mentioned above, the CNU cannot update its saved minimum value based on line 3 until the VNU completes line 3. This is because the VNU is still using the saved minimum value. The VNU will need 19 cycles (number of non-blank entries) to process line 3. This means the CNU will be idle for 16 cycles (19-3). This will reduce throughput and require more hardware decoders to accommodate the desired data rate.

[0036] In some embodiments of the present invention, the decoder stores the minimum value of 2 (or more) lines. See again... Figure 9 This allows the CNU to update its minimum value after processing row 4 and continue processing row 5. Additionally, due to the aforementioned rules regarding the alternating processing by the CNU and VNU, the CNU operations in row 5 are reordered to handle columns with blank spaces in row 4. For example, the CNU will skip columns 0 and 1 and start with columns 3, 12, and so on.

[0037] refer to Figure 1 Wireless transmitter 102 and wireless receiver 104 exchange data via one or more transmission channels 110, collectively referred to as communication paths, channels, or links. As previously described, transmission channels 110 may be susceptible to noise, interference, etc., which may cause errors in the data received by wireless receiver 104. In some embodiments, wireless transmitter 102 and wireless receiver 104 follow different technical standards. For example, wireless receiver 104 may decode messages or related data according to different wireless networking standards, including but not limited to 5G New Radio (NR), IEEE 802.11ad, etc. In some embodiments, wireless transmitter 102 and / or wireless receiver 104 are implemented as system-on-a-chip (SoC) or other integrated circuits in various industrial, commercial, and consumer applications (e.g., digital networking devices).

[0038] In order to detect, demodulate, and / or decode signals received from wireless receiver 104 and to correct errors identified in the received data, in some embodiments, wireless receiver 104 includes I / O port 122, LDPC decoder 124, processor 126, and memory 128. Some or all of the components of wireless receiver 104—such as LDPC decoder 124—may be implemented in an application-specific integrated circuit (“ASIC”), a system-on-a-chip (SoC), or a field-programmable gate array (“FPGA”), but are not limited thereto. Other embodiments include components of wireless receiver 104 such as LDPC decoder 124 implemented as software-programmed and executed by processor 126. Some embodiments of wireless receiver 104 include LDPC decoder 124 and / or Figure 1 The implementation is a combination of software and other electronic circuits and other components.

[0039] I / O port 122 is adapted to detect signals from transmit channel 110 of transmitter 102. I / O port 122 may include any suitable protocol for receiving encoded signals from transmitter 102. The encoded signals detected by I / O port 122 are provided to LDPC decoder 124. LDPC decoder 124 is constructed and arranged to detect and correct errors introduced onto transmit channel 110. In some embodiments, LDPC decoder 124 calculates LDPC codes according to one or more different technical standards, such as, but not limited to, 5G New Radio (NR) described herein, IEEE 802.11ad, etc.

[0040] Processor 126 may be any suitable computer processor for executing code stored in memory 128 and is configured and arranged to process received data in the form of encoded messages (e.g., posterior log-likelihood ratio (LLR) messages). Memory 128 may be any suitable type of storage device for computer-related data and / or programming, and may be, for example, but not limited to, random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), etc.

[0041] Figure 2 yes Figure 1 A block diagram of a multi-standard LDPC decoder 124. The multi-standard LDPC decoder 124 is disposed on silicon, for example as a system comprising hardware alone or in combination with software.

[0042] In some embodiments, the LDPC decoder 124 performs iterative error correction, which requires a parallel network of nodes for processing the parity check matrix. Each decoding iteration includes updating data in the form of a message received from the transmit channel 110 by the RAM 202, and exchanging data between the nodes of the VNU processor 204 and the CNU processor 206. In some embodiments, the variable node and the parity node are updated once per iteration. Messages with predetermined bit values ​​can be represented in the form of posterior log-likelihood ratio (LLR) values ​​from the communication channel 110, and these messages are exchanged between the variable node 204 and the parity node 206.

[0043] As previously described, the LDPC decoder 124 is constructed and arranged to decode LDPC codes according to a variety of different technical standards. QC-LDPC codes can be implemented, for example, by a low-density parity check matrix, where most entries are zero values, such as... Figure 9 As shown. However, since some matrices follow various standards, they may have different arrangements, configurations, sizes, etc., than other matrices. An LDPC decoder 124 according to some embodiments is characterized in that it can process LDPC codes following different industry standards regardless of the size of the matrix. The LDPC decoder 124's ability to process LDPC codes used in different industry standards improves the efficiency of the decoder 124 because hardware elements of the decoder 124 not used to process a specific matrix can still process multiple code blocks of different matrices simultaneously, thereby reducing the number of decoders required to meet throughput requirements. This is because a single encoder or LDPC decoder 124 is needed to process block codes, more specifically LDPC codes or error-correcting codes using parity matrices, even if a matrix according to one industry or technical standard may differ from another matrix according to a different industry or technical standard. The parity matrix comprises multiple sub-matrices, each sub-matrix having a predetermined size (Z). c The LDPC decoder 124 processes one submatrix at a time. This differs from changing the submatrix Z. c In conventional LDPC systems where the value controls the amount of error correction, in some embodiments, the LDPC decoder 124 adapt submatrix Z c Larger values ​​are used to decode different standards and process multiple blocks of LDPC code at once to improve throughput, regardless of whether the standard uses a different matrix.

[0044] As is well known in decoding architectures, each bit of an LDPC codeword corresponds to a column of a parity check matrix, and each row of the matrix corresponds to a single parity check. Each bit in the parity check matrix with a value of "1" is represented by an edge between the corresponding variable node (i.e., the column of the VNU) and the check node (i.e., the row of the CNU). Each row / column in each submatrix of the parity check matrix requires a RAM data path for processing the data in that row / column. As described in this paper, when the LDPC decoder 124 processes data smaller than a predetermined submatrix Z... c When the submatrix is ​​of a certain size, additional data paths are used for decoding different codewords simultaneously. As described herein, the parity node signal decoding processor 206 may include a circular shifter 310 configured and arranged to process any unused data paths in RAM (see [link to documentation]). Figure 3 ). refer to Figure 5 This defines each LLR in the LDPC decoder data path. Figure 4 A shifter for a larger submatrix Zc is shown. The hardware is in... Figure 4 The operation performed is to shift the entire structure to the right, and then truncate the right half into Zc LLR. Figure 5 In this process, the entire structure is shifted to the right, and data from every other group of Zc LLR is extracted.

[0045] During operation, the LDPC encoder of the wireless transmitter 102 adds one or more parity bits for redundancy to each codeword, thereby modifying the message to include error-correcting codewords and allowing the LDPC decoder 124 to verify the validity of the codewords. In some embodiments, the decoder 124 relies on the parity bits to identify the most likely sequence of encoded bits based on, for example, samples of the modulated signal received from the encoder on the channel. In some embodiments, the modulator and demodulator of the encoder and / or decoder provide additional processing of the signal received via the transmit channel 110.

[0046] Refer again Figure 2 The LDPC decoder 124 includes one or more memory devices, such as RAM 202, which is configured and arranged to receive input data from the LDPC decoder 124 directly or indirectly (via intermediate electronics such as a modulator) from a communication channel and to store one or more codewords for subsequent processing by the matrix processing system 208. Although not shown, RAM 202 includes multiple memories, the size and arrangement of which depend on the maximum submatrix size, required throughput, etc. In some embodiments, RAM 202 may be... Figure 1 It is part of the memory 128 of the receiver 104.

[0047] The cyclic shifter 310 or associated combinational logic circuitry of the LDPC decoder 124 is constructed and arranged to support different cyclic LDPC submatrices, specifically any size cyclic shift, up to a predefined maximum submatrix size ranging from a single codeword in a large submatrix to multiple codewords in a small submatrix. The shifter 310 receives messages from RAM 202, for example via intermediate multiplexer 304, and distributes messages, specifically codewords, aligned with the necessary check nodes managed by matrix processing system 208. In some embodiments, the cyclic shifter 310 exchanges data bits between one or more VNUs 204 and CNUs 206. Therefore, the cyclic shifter 310 exchanging messages between VNUs 204 and CNUs 206 allows the LDPC decoder 124 to support different LDPC codes using different submatrices.

[0048] In some embodiments, multiple registers or similar (not shown) are configured and arranged to perform layered-LDPC decoding operations on input data codeword bits for a predetermined number of pipeline stages, thereby further contributing to high decoding throughput.

[0049] The matrix processing system 208 includes multiple logic circuits, each providing an independent data path for different codewords and decoding different codewords simultaneously or nearly simultaneously. Therefore, specifically, the matrix processing system 208, including a dedicated shifter 310, can process multiple code blocks corresponding to LDPC codes conforming to different standards.

[0050] Figure 3 This is a schematic diagram of a matrix processing system 208 according to some embodiments. As shown, the matrix processing system 208 may include, but is not limited to, a first memory 302, a second memory 303, at least one multiplexer 304, and at least one shifter 310. In some embodiments, the matrix processing system 208 may include, relative to... Figure 2 One or more hardware elements of the VNU processor 204 and / or CNU processor 206 shown and described.

[0051] In some embodiments, the first memory 302 stores the post-hoc messages of variable nodes (e.g., Figure 2 The VNU processor 204's encoded bits are stored in RAM, etc. The message is initialized using the corresponding prior (channel) reliability value of the encoded bits. A key feature of this invention is that the first memory 302 can simultaneously or almost simultaneously output the data bits of multiple LDPC code blocks to the multiplexer 304, etc. During decoding, the multiplexer 304 receives LLR values ​​within the clock cycle of the decoding process iteration. Channel values, LLR messages, etc., can be allowed to reach the multiplexer 304 in the form of blocks or codewords by shifting the cyclic shifter 310 by an appropriate amount.

[0052] Referring again to the cyclic shifter 310, the shifter 310 is constructed and arranged to handle codewords of various sizes, regardless of the parity check matrix or its submatrices. In doing so, other decoder hardware, such as at the output of the shifter 310, does not require corresponding modifications and can therefore be applied equally regardless of industry standards. In some embodiments, the second memory 303 is also referred to as branch metric RAM or parity RAM. The second memory 303 is constructed and arranged to output LLR values ​​from the output of the VNU, which may include scaler 316, to the input of the CNU 206. The output of temporary RAM 317, which is the LLR output from the CNU, such as the output of subtractor 311 before absolute value calculator 312, and the output of sign generator 313 to the input of temporary RAM 317, are used for subsequent processing by the VNU.

[0053] For example, refer to again Figure 4 In some embodiments, the cyclic shifter 310 processes a single codeword 400. The codeword 400 may be implemented according to a specific industry standard, such as the 5G cellular standard. The shifter 310 may receive and process codewords 400 of various lengths. In some embodiments, the amount of shift applied by the shifter 310 depends on the size of the codeword 400 being decoded. For example, the cyclic shifter 310 is implemented to shift two input data, such as shifting input data 401 and a copy of input data 402. When a right shift occurs, some or all bits of the input data 401 may be discarded or deleted. However, the copy data 402 may be used for further processing after being output from the shifter 310. For example, an eight-bit cyclic right shifter may operate as follows: b(n) corresponds to LLR (bytes) n. Before the shift, data b(7), b(6), b(5), b(4), b(3), b(2), b(1), and b(0) are provided. After right shifts b(0), b(7), b(6), b(5), b(4), b(3), b(2), and b(1), in some embodiments, the right shift to be applied by the cyclic shifter 310 may be applied to the input signal using multiple pipeline stages.

[0054] For reference Figure 5 In some embodiments, the cyclic shifter 310 receives and processes multiple codewords at a time. Here, the shifter 310 operates differently from processing a single codeword only because multiple copies 502, 504, 506 of the input data 501, 503, 505 are required; that is, multiple codewords and multiple truncations are needed after right shift operations, etc. For example, a right shift of one or more bits will cause the rightmost least significant bit to be truncated. However, duplicated input data is provided for output by the check node signal decoding processor 206 and subsequent processing. Therefore, the shifter 310 can avoid the repetitive hardware originally required for cyclic shifting multiple LDPC codewords.

[0055] In another example, such as Figure 3 and 5 As shown, shifter 310 can be implemented to provide a cyclic shift of a single code block with Zc = 8, where b(n) corresponds to LLR (byte) n. The initial data includes b(7), b(6), b(5), b(4), b(3), b(2), b(1), b(0). The data is copied as follows: b(7), b(6), b(5), b(4), b(3), b(2), b(1), b(0), b(7), b(6), b(5), b(4), b(3), b(2), b(1), b(0). Subsequently, the data is logically shifted to the right as follows: b(0), b(7), b(6), b(5), b(4), b(3), b(2), b(1), b(0), b(7), b(6), b(5), b(4), b(3), b(2), b(1). Then, the data is truncated back to eight elements, as shown below: b(0), b(7), b(6), b(5), b(4), b(3), b(2), b(1).

[0056] As previously mentioned, shifter 310 outputs the shifted codeword bits of the multiple stripes received from the first memory 302 in the form of a route to the correct check node signal decoding processor 206. Due to the aforementioned characteristics of shifter 310, the hardware components of check node signal decoding processor 206 do not require unique modifications for LDPC codewords of different industry standards. For example, each data path can be provided for each row in submatrix Zc. Figure 3 As shown, multiple copies of the submatrix Zc are generated at the check node signal decoding processor 206 portion of the matrix processing system 208. In this example, the bus width at this location of the system 208 is 8 × Zc bits, because each LLR is 8 bits and there are Zc LLRs.

[0057] In some embodiments, the check node signal decoding processor 206 includes a subtractor 311 that receives and processes message data outputs from a shifter 310 and a second memory 303 that stores check node messages from the same layer. Therefore, the LLR value output from the shifter 310 is subtracted. The subtractor 311 is constructed and arranged to remove contributions from the column being processed, wherein the contributions are updated using an adder (not shown) of the reproduction processor 318 and then added back.

[0058] In some embodiments, the parity node signal decoding processor 206 for providing one or more CNUs further includes an absolute value calculator 312, a symbol generator 313, and a minimum data generator unit 314. The VNU processor 320 may include a trigger circuit (not shown) at the output of temporary RAM 317, a scaler 316, and a reproduction processor 318, which are well-known LDPC components, and therefore descriptions of their functions and structures are omitted for brevity.

[0059] Figure 6 This is a flowchart illustrating a method 600 for wireless communication according to some embodiments. Some or all of the steps of method 600 can be performed in a wireless receiving device (e.g., Figure 1-5 The method is executed in receiver 104. Therefore, when describing method 600, refer to... Figure 1-5 The components of the wireless receiver 104.

[0060] In box 602, LDPC decoder 124 receives multiple LDPC codewords. (See also: ...) Figure 1 As described, the plurality of codewords can be received from signals provided via transmission channel 110. Therefore, the received codewords may be corrupted due to interference, noise, or other physical phenomena associated with transmission channel 110. Received codewords, as part of LLR messages, may include, but are not limited to, payload data and parity data, such as payload data and parity bits. In doing so, an LDPC encoder (not shown) may add parity bits to each codeword, where decoder 124 finds the most probable encoded sequence based on received samples of the codeword.

[0061] As described in this article, LDPC codes use a large parity check matrix that includes combinations of smaller submatrices. Figure 3 As shown in box 604, decoder 124 processes one submatrix (Zc) at a time. Each submatrix (Zc) is a square matrix, i.e., the number of rows is the same as the number of columns. When processing a submatrix, shifter 120 shifts its contents (e.g., rows or columns containing one or more codewords) to the right by a predetermined number of positions to receive and process the next set of codewords in the matrix. In some embodiments, shifter 120 shifts multiple codewords at a time (e.g., see...). Figure 5 ).

[0062] In block 606, in some embodiments, it is determined whether the current submatrix size is less than the maximum submatrix size. In other embodiments, not every submatrix needs to be determined, or the determination is not performed for every submatrix, and the determination is controlled by a static mode bit. For example, in the configuration, it is made to follow either an 802.11ad protocol mode that processes multiple codewords at a time or a 5G protocol mode that processes one codeword at a time.

[0063] For example, the hardware components of the decoding circuitry of the LDPC decoder 124 are constructed and arranged to receive and process the largest possible submatrix. However, when processing smaller matrices, some hardware of the LDPC decoder 124 may be unused, which is inefficient. As discussed in some examples herein, the width of components such as bus wiring, RAM, and shifter 310 may be 8Zc bits. These extra bits are wasted when the submatrix Zc is larger than the required submatrix. Furthermore, Zc copies of the hardware exist in the dashed box labeled xZc. These extra copies are not used when Zc is larger than the required size. However, in box 608, when shifter 120 is included, the extra hardware that would otherwise not be used to process smaller matrices can be used to process multiple code blocks at once. Otherwise, in box 610, the shifter 120 processes individual codewords of larger submatrices. The main difference between boxes 608 and 610 lies in the copy mode and truncation function performed by shifter 120.

[0064] Figure 7 This is a block diagram of a multi-standard LDPC decoder 700 according to some embodiments. As shown, the LDPC decoder 700 may include, but is not limited to, one or more CNU processors 706, a matrix processing system 708, and one or more VNU processors 714. Figure 7 The diagram illustrates an increase in the number of output storage devices instead of data paths for the CNU processor 706. This is achieved by processing one submatrix at a time but storing multiple CNU results, which allows the VNU 714 to process any submatrix from two or more rows of the parity matrix processed by the CNU processor 706, thereby reducing RAM access contention and improving data dependencies.

[0065] In some embodiments, the matrix processing system 708 includes a shifter 720, a memory 722, and a decoding processor 725. The shifter 720 is similar to... Figure 1-6 The shifter 310 described herein is omitted for brevity; therefore, repeated details are omitted. Although not shown, some or all of one or more of the shifter 720, memory 722, and decoding processor 725, or portions thereof, may be part of the CNU processor 706 and / or the VNU processor 714.

[0066] During operation, the CNU processor 706 processes one row at a time from a submatrix of, for example, the 5G-NR parity check matrix, but other matrices from other standards may also be applicable. After the processed row, the positions of the first minimum, second minimum, and first minimum are output to the VNU 714 via the decoding processor 725. In this example, the positions of the first minimum, second minimum, and first minimum can be determined by... Figure 3The minimum data generator unit 314 and / or other well-known LDPC components are used to process messages as quickly as possible from, for example, Figure 3 The memory routing of RAM 302 shown is to a predetermined processing unit. This may be similar to... Figure 3 The logic circuitry of the CNU 206, including at least the logic circuitry of the minimum data generator unit 314, identifies the first minimum value and the second minimum value in a specific row. For example, at memory 722, the CNU 706 stores the current minimum value of the row as it updates memory 722 for each column it processes. After the CNU has completed the entire row, it transfers the minimum value to a saved copy of the minimum value. The VNU 714 then uses this saved copy to process the row previously completed by the CNU.

[0067] VNU 714 is configured only to process rows already completed by CNU processor 706. In some embodiments, dedicated memory 722 is constructed and arranged to store the results of two rows completed by CNU processor 706. In some embodiments, dedicated memory 722 includes multiple trigger circuits, etc. In other embodiments, dedicated memory 722 is constructed and arranged to store the results of more than two rows (e.g., three rows) completed by CNU processor 706. The storage of additional rows of CNU results in memory 722 provides additional flexibility regarding reordering of VNU 714, such as allowing VNU 714 to process any submatrix from the two rows of CNU results stored in dedicated memory 722. This differs from conventional techniques where multiple CNUs are required so that the processor can process the entire CNU rather than individual CNU results. Although dedicated memory 722 is shown as part of decoding processor 725, other embodiments may include dedicated memory 722 as part of CNU processor 706. While the dedicated memory 722 requires additional silicon area, specifically for storing one or more additional lines of CNU results, this configuration offers additional throughput compared to the absence of the dedicated memory 722. This, in turn, would require additional decoder cores and therefore significantly more silicon area than the dedicated memory or similar throughput capabilities would necessitate. The flexibility of the VNU 714 also reduces RAM access contention and data dependencies. For example, as described above, greater flexibility is achieved in storing additional lines of CNU results due to the way data is processed.

[0068] Figure 8 This is a flowchart illustrating a method 800 for operating a multi-standard LDPC decoder according to some embodiments. Some or all of the steps of method 800 can be performed in a wireless receiving device (e.g., Figure 7 The method is executed in receiver 104. Therefore, when describing method 700, refer to... Figure 7 The components of the multi-standard LDPC decoder 700.

[0069] In box 802, the CNU processor 706 processes a row of the parity matrix, one submatrix at a time.

[0070] In box 804, the results of the two rows processed by the CNU processor 706 are stored in dedicated memory 720.

[0071] In box 806, VPU 714 processes a two-row submatrix from CNU processor 706, for example... Figure 9 As shown.

[0072] Figure 9 A graphical representation of a parity check matrix according to some embodiments is shown. In this example, the matrix has 68 columns and 46 rows, but relevant portions of the matrix are shown for simplicity. Each entry can be replaced by a square submatrix. Blank entries correspond to all 0s submatrices. Entry with values ​​corresponds to a shifted identity matrix and has been processed accordingly. The values ​​in the matrix determine the degree of data shift. The CNU processor 706 processes one row of the matrix, one submatrix at a time. For example, as shown, the CNU processor 706 can start with a Zc × Zc submatrix with a value of 307. Blank entries are not processed. After the CNU processor 706 processes a row, the positions of the first minimum, second minimum, and first minimum are output to the VNU 714, which processes only the row completed by the CNU processor 706. Since the results of two rows are stored in memory, additional flexibility and throughput are provided to the VNU 714 for reordering.

[0073] While the invention has been described herein with reference to specific embodiments, various modifications and changes may be made without departing from the scope of the invention as set forth in the appended claims. Therefore, the specification and drawings should be considered illustrative rather than restrictive, and all such modifications are contemplated to be included within the scope of the invention. It is not intended that any advantage, benefit, or solution to the problem described herein with reference to specific embodiments be construed as a key, necessary, or essential feature or element of any or all claims.

[0074] Unless otherwise stated, terms such as “first” and “second” are used to distinguish, arbitrarily, the elements described by such terms. Therefore, these terms are not necessarily intended to indicate temporal or other priorities of such elements.

Claims

1. A wireless receiving device, characterized in that, include: The low-density parity-check (LDPC) decoding circuit includes: A cyclic shifter, configured and arranged to simultaneously process multiple codewords of parity check matrices for different wireless communication standard configurations, including performing cyclic shift operations on the multiple codewords to align them with one or more required parity check nodes of the decoder; and The logic circuit at the output of the cyclic shifter, the logic circuit being constructed and arranged for a matrix larger than the parity check matrix and including components having redundant hardware due to the construction and arrangement for the large matrix, is used to decode the plurality of codewords of the small parity check matrix and output them to the one or more required parity check nodes. At least one parity node update CNU processor and at least one variable node update VNU processor, the at least one CNU processor including the cyclic shifter and the at least one VNU processor receiving the output of the logic circuit operating on the submatrix of the parity check matrix in each clock cycle; The logic circuitry includes a minimum data generator unit that identifies a first minimum and a second minimum in the rows of the parity matrix, wherein the CNU processor includes a memory that stores the current minimum of the row when updating the memory for each column of the parity matrix, wherein a copy of the minimum is stored, and wherein the VNU processor processes the stored copy of the minimum to process the row previously processed by the at least one CNU processor; and The memory therein stores the minimum value of two or more rows of the parity matrix processed by the at least one CNU processor.

2. The wireless receiving device according to claim 1, characterized in that, The redundant hardware includes one or more of a data path, random access memory, and trigger storage device that are reused to decode the plurality of codewords.

3. A low-density parity-check (LDPC) decoding circuit for a wireless device, characterized in that, include: Variable nodes update the VNU processor; The verification node updates the CNU processor; as well as Matrix processing system, including: A dedicated memory device storing at least the first and second rows of CNU data generated by the CNU processor; and A decoding processor that processes the results of at least the first and second lines of the CNU to output to the VNU processor; At least one of the VNU processor, the CNU processor, and the matrix processing system includes additional circuitry configured and arranged to process matrices larger than the matrix including the CNU data, wherein the additional circuitry simultaneously processes multiple codewords of rows of the CNU data; and The LDPC decoding circuit further includes a minimum data generator unit that identifies a first minimum value and a second minimum value in the first and second rows, wherein the CNU processor stores the current minimum value of the row when updating the memory for each column of the parity matrix, wherein a copy of the minimum value is stored, and wherein the VNU processor processes the stored copy of the minimum value to process the row previously completed by at least one CNU processor.

4. An operation method for a low-density parity-check (LDPC) decoder, characterized in that, include: The cyclic shifter simultaneously processes multiple codewords for parity check matrices configured for different wireless communication standards, including: Perform a cyclic shift operation on the plurality of codewords to align them with one or more required check nodes; The redundant hardware of the LDPC decoder, constructed and arranged for a matrix larger than the parity check matrix, processes the plurality of codewords, including: The multiple codewords of the parity check matrix are decoded and output to the one or more required check nodes; Store the results of two or more lines including the plurality of codewords; and The parity matrix of the results from two or more rows stored by the VNU processor is updated by the variable node; The cyclic shift operation includes shifting one row of results corresponding to the plurality of codewords by updating the CNU processor at the parity check node, storing the shifted results of the two rows of results, and processing the submatrix of the parity check matrix from the two rows of results by the VNU processor.

5. The method according to claim 4, characterized in that, The cyclic shifter simultaneously shifts the plurality of codewords to the right by a predetermined number of positions to receive and process the next set of multiple codewords in the parity check matrix.

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