Display substrate, manufacturing method thereof, and display device

Abstract

A display substrate and a manufacturing method thereof, and a display device. A sub-pixel in the display substrate includes a power signal line pattern (91), the power signal line pattern (91) includes a first power line portion (911) and a second power line portion (912); a main body portion (9120) in the second power line portion (912) and the first power line portion (911) are spaced apart along a first direction; a first end portion (9121) in the second power line portion (912) is respectively coupled to one end of the main body portion (9120) and the first power line portion (911); a second end portion (9122) is respectively coupled to the other end of the main body portion (9120) and the first power line portion (911); and a gap (50) is provided between the first power line portion (911) and the second power line portion (912).

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a manufacturing method thereof, and a display device. Background Art

[0002] With the continuous development of display technology, the application range of display screens with fingerprint recognition function is becoming more and more extensive. Such display screens generally use optical fingerprint recognition technology, which uses the principles of light refraction and reflection to realize user fingerprint recognition.

[0003] When using this display screen for fingerprint recognition, place your finger on the display screen. The light emitted by the internal light source located below the array substrate in the display screen is reflected by the uneven texture on the fingertip, producing different reflection angles. This causes the sensing element on the back of the display screen to receive different light intensities, thereby generating different photocurrents. Based on the size of this photocurrent, the fingerprint pattern can be detected and compared and identified. Summary of the Invention

[0004] The present disclosure aims to provide a display substrate, a method for manufacturing the same, and a display device.

[0005] A first aspect of the present disclosure provides a display substrate, comprising: a substrate and a plurality of sub-pixels arrayed on the substrate; the sub-pixels comprising:

[0006] A power signal line graphic, the power signal line graphic includes a first power line portion and a second power line portion; at least a portion of the first power line portion extends along a second direction; the second power line portion includes a main body, a first end portion and a second end portion, the main body portion and the first power line portion are spaced apart along the first direction, the first direction intersects with the second direction, the first end portion and the second end portion are arranged opposite to each other along the second direction, the first end portion is respectively coupled to one end of the main body portion and the first power line portion, the second end portion is respectively coupled to the other end of the main body portion and the first power line portion, and there is a gap between the first power line portion and the second power line portion.

[0007] Optionally, the plurality of sub-pixels are divided into a plurality of rows of sub-pixels, and each row of sub-pixels includes a plurality of sub-pixels sequentially arranged along the first direction; and the sub-pixels further include:

[0008] a first data line pattern and a second data line pattern arranged opposite to each other along a first direction, wherein at least a portion of the first data line pattern and at least a portion of the second data line pattern both extend along the second direction;

[0009] The orthographic projection of the first data line pattern on the substrate overlaps with the orthographic projection of the first power line portion in the sub-pixel adjacent to the sub-pixel to which it belongs along the first direction on the substrate, and the orthographic projection of the second data line pattern on the substrate overlaps with the orthographic projection of the main body on the substrate.

[0010] Optionally, the orthographic projection of the first data line pattern on the substrate does not overlap with the orthographic projection of the pore on the substrate; and / or the orthographic projection of the second data line pattern on the substrate does not overlap with the orthographic projection of the pore on the substrate.

[0011] Optionally, the sub-pixel further includes a light-emitting control signal line pattern, at least a portion of which extends along the first direction; and an orthographic projection of the light-emitting control signal line pattern on the substrate partially overlaps with an orthographic projection of the pore on the substrate.

[0012] Optionally, the first power line portion includes a second sub-portion and a first sub-portion for enclosing the aperture, and in a direction perpendicular to the second direction and on a plane parallel to the substrate, the width of the first sub-portion is smaller than the width of the second sub-portion.

[0013] Optionally, the sub-pixel further includes a light-emitting element, the light-emitting element includes an anode pattern, and an orthographic projection of the anode pattern on the substrate does not overlap with an orthographic projection of the pore on the substrate.

[0014] Optionally, the orthographic projection of the pore on the substrate is located between the orthographic projection of the first anode pattern on the substrate and the orthographic projection of the second anode pattern on the substrate; the sub-pixel to which the pore belongs includes the first anode pattern, and the next sub-pixel adjacent to the sub-pixel along the first direction includes the second anode pattern.

[0015] Optionally, the plurality of sub-pixels are divided into a plurality of pixel units, each pixel unit including one red sub-pixel, one blue sub-pixel and two green sub-pixels;

[0016] In pixel units located in the same row along the first direction, the anode patterns included in the red sub-pixels in each pixel unit and the anode patterns included in the blue sub-pixels in each pixel unit are distributed in one row, and the anode patterns included in the green sub-pixels in each pixel unit are distributed in another row;

[0017] In the pixel units located in the same row along the first direction, the anode patterns included in the red sub-pixels, the anode patterns included in the blue sub-pixels, and the anode patterns included in the green sub-pixels are alternately distributed in sequence;

[0018] In pixel units located in the same row along the first direction, one of adjacent red sub-pixels and green sub-pixels includes the first anode pattern, and the other of adjacent red sub-pixels and green sub-pixels includes the second anode pattern;

[0019] In pixel units located in the same row along the first direction, one of adjacent blue sub-pixels and green sub-pixels includes the first anode pattern, and the other of adjacent blue sub-pixels and green sub-pixels includes the second anode pattern.

[0020] Optionally, the sub-pixel further includes a light-emitting element, the light-emitting element includes an anode pattern, and an orthographic projection of a portion of the anode pattern on the substrate partially overlaps with an orthographic projection of the pore on the substrate.

[0021] Optionally, the main body portion includes a first main body portion and a second main body portion, the first main body portion is close to the first end portion, and the second main body portion is close to the second end portion, and in a plane parallel to the base and in a direction perpendicular to the second direction, the width of the first main body portion is greater than the width of the second main body portion;

[0022] The sub-pixel also includes a sub-pixel driving circuit, which includes a driving transistor and a storage capacitor. The first plate of the storage capacitor is coupled to the gate of the driving transistor, and the orthographic projection of the second plate of the storage capacitor on the substrate overlaps with the orthographic projection of the first main body part on the substrate. The second plate of the storage capacitor is coupled to the first main body part through a via arranged at the overlapping position.

[0023] Optionally, the orthographic projection of the second electrode plate of the storage capacitor on the substrate does not overlap with the orthographic projection of the pore on the substrate.

[0024] Optionally, the sub-pixel further includes a power compensation pattern, at least a portion of which extends along the first direction, and the power compensation pattern is respectively coupled to the main body and the first power line portion of the sub-pixel adjacent to the sub-pixel to which it belongs along the first direction.

[0025] Optionally, the sub-pixel further includes: a reset signal line pattern, a gate line pattern, and a light-emitting control signal line pattern sequentially distributed along the second direction; at least a portion of the reset signal line pattern extends along the first direction, at least a portion of the gate line pattern extends along the first direction, and at least a portion of the light-emitting control signal line pattern extends along the first direction;

[0026] The orthographic projection of the power compensation pattern on the substrate is located between the orthographic projection of the gate line pattern on the substrate and the orthographic projection of the light emitting control signal line pattern on the substrate.

[0027] Optionally, the sub-pixel also includes a light-emitting control signal line pattern, at least part of which extends along the first direction; the light-emitting control signal line pattern includes a first light-emitting control part and a second light-emitting control part, and the orthographic projection of the first light-emitting control part on the substrate overlaps with the orthographic projection of the main body on the substrate, the orthographic projection of the pore on the substrate, and the orthographic projection of the first power line part on the substrate; along the second direction, the orthographic projection of the second light-emitting control part on the substrate is opposite to the orthographic projection of the power compensation pattern on the substrate; on a plane parallel to the substrate and in a direction perpendicular to the first direction, the width of the second light-emitting control part is smaller than the width of the first light-emitting control part.

[0028] Optionally, the power compensation graphic includes a first part, a second part and a third part; the first part is coupled to the first power line part and one end of the third part respectively, the second part is coupled to the main body and the other end of the third part respectively, and the third part extends along the first direction, and the extension direction of the first part and the extension direction of the second part both intersect with the first direction and both intersect with the second direction.

[0029] Optionally, on a plane parallel to the substrate and in a direction perpendicular to the first direction, the end of the power compensation pattern coupled to the first power line portion has a first width, and the first width gradually increases in a direction approaching the first power line portion.

[0030] Optionally, the sub-pixel further includes a light-emitting element, the light-emitting element includes an anode pattern, and an orthographic projection of the anode pattern on the substrate overlaps with an orthographic projection of the power compensation pattern on the substrate.

[0031] Optionally, the sub-pixel further includes: a light-emitting element, an initialization signal line pattern, a reset signal line pattern, a gate line pattern, and a light-emitting control signal line pattern; at least a portion of the initialization signal line pattern, at least a portion of the reset signal line pattern, at least a portion of the gate line pattern, and at least a portion of the light-emitting control signal line pattern all extend along the first direction;

[0032] The sub-pixel further includes:

[0033] a first data line pattern and a second data line pattern arranged opposite to each other along a first direction, wherein at least a portion of the first data line pattern and at least a portion of the second data line pattern both extend along a second direction;

[0034] A sub-pixel driving circuit, the sub-pixel driving circuit comprising: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor and a storage capacitor;

[0035] The gate of the third transistor is coupled to the second electrode of the first transistor, the first electrode of the third transistor is coupled to the second electrode of the fifth transistor, and the second electrode of the third transistor is coupled to the first electrode of the first transistor;

[0036] The gate of the first transistor is coupled to the gate line pattern;

[0037] The gate of the second transistor is coupled to the reset signal line pattern, the first electrode of the second transistor is coupled to the initialization signal line pattern, and the second electrode of the second transistor is coupled to the gate of the third transistor;

[0038] The gate of the fourth transistor is coupled to the gate line pattern; the first electrode of the fourth transistor is coupled to the first data line pattern or the second data line pattern, and the second electrode of the fourth transistor is coupled to the first electrode of the third transistor;

[0039] The gate of the fifth transistor is coupled to the light emitting control signal line pattern, and the first electrode of the fifth transistor is coupled to the power signal line pattern;

[0040] The gate of the sixth transistor is coupled to the light emitting control signal line pattern, the first electrode of the sixth transistor is coupled to the second electrode of the third transistor, and the second electrode of the sixth transistor is coupled to the light emitting element;

[0041] The gate of the seventh transistor is coupled to the reset signal line pattern in the next sub-pixel adjacent to the second direction, the first electrode of the seventh transistor is coupled to the initialization signal line pattern in the next sub-pixel adjacent to the second direction, and the second electrode of the seventh transistor is coupled to the light-emitting element;

[0042] The first plate of the storage capacitor is reused as the gate of the third transistor, and the second plate of the storage capacitor is coupled to the power signal line pattern.

[0043] Based on the technical solution of the above-mentioned display substrate, a second aspect of the present disclosure provides a display device including the above-mentioned display substrate.

[0044] Based on the above technical solution of the display substrate, a third aspect of the present disclosure provides a method for manufacturing a display substrate, comprising: manufacturing a plurality of sub-pixels distributed in an array on a substrate; the steps of manufacturing the sub-pixels specifically include:

[0045] A power signal line pattern is produced, wherein the power signal line pattern includes a first power line portion and a second power line portion; at least a portion of the first power line portion extends along a second direction; the second power line portion includes a main body portion, a first end portion, and a second end portion, the main body portion and the first power line portion are arranged along the first direction, and the main body portion and the first power line portion are spaced apart, the first direction intersects with the second direction, the first end portion and the second end portion are arranged opposite to each other along the second direction, the first end portion is respectively coupled to one end of the main body portion and the first power line portion, the second end portion is respectively coupled to the other end of the main body portion and the first power line portion, and a gap is provided between the first power line portion and the second power line portion. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] The drawings described herein are used to provide a further understanding of the present disclosure and constitute a part of the present disclosure. The exemplary embodiments of the present disclosure and their descriptions are used to explain the present disclosure and do not constitute an improper limitation of the present disclosure. In the drawings:

[0047] Figure 1a It is a schematic diagram of sub-pixel layout in the prior art;

[0048] Figure 1b 1 is a schematic diagram of the layout of the active layer;

[0049] Figure 1c 1 is a schematic diagram of the layout of the first gate metal layer;

[0050] Figure 1d 1 is a schematic diagram of the layout of the second gate metal layer;

[0051] Figure 1e 1 is a schematic diagram of the layout of the source and drain metal layers;

[0052] Figure 2 A circuit diagram of a sub-pixel driving circuit provided in an embodiment of the present disclosure;

[0053] Figure 3 This is a working timing diagram of the sub-pixel driving circuit provided in an embodiment of the present disclosure;

[0054] Figure 4 A schematic diagram of a first layout of sub-pixels provided in an embodiment of the present disclosure;

[0055] Figure 5 for Figure 4 Schematic diagram of the layout of the active layer and the first gate metal layer;

[0056] Figure 6 for Figure 4 Schematic diagram of the layout of the second gate metal layer;

[0057] Figure 7 for Figure 4 Schematic diagram of the layout of the first source and drain metal layer;

[0058] Figure 8 for Figure 4 Schematic diagram of the layout of the second source and drain metal layer;

[0059] Figure 9 A schematic diagram of a second layout of sub-pixels provided in an embodiment of the present disclosure;

[0060] Figure 10 for Figure 9 A schematic structural diagram of the second power line portion;

[0061] Figure 11 for Figure 9 Schematic diagram of the layout of the first source and drain metal layer;

[0062] Figure 12 for Figure 9 Schematic diagram of the layout of the first source and drain metal layer and the second source and drain metal layer;

[0063] Figure 13 A third schematic diagram of a sub-pixel layout provided in an embodiment of the present disclosure;

[0064] Figure 14 for Figure 13 Schematic diagram of the layout of the first source and drain metal layer;

[0065] Figure 15 for Figure 13 A first connection diagram of the middle power compensation pattern and the second power line portion;

[0066] Figure 16 is a schematic diagram of a first layout of eight sub-pixels;

[0067] Figure 17 for Figure 16 Schematic diagram of the cross section along the A1A2 direction;

[0068] Figure 18 for Figure 16 Schematic diagram of the layout of the two source and drain metal layers and the anode layer;

[0069] Figure 19 for Figure 16 Schematic diagram of the layout of the second source and drain metal layer and the anode layer;

[0070] Figure 20 for Figure 16 Schematic diagram of the layout of the active layer in ;

[0071] Figure 21 for Figure 16 Schematic diagram of the layout of the first gate metal layer;

[0072] Figure 22 for Figure 16 Schematic diagram of the layout of the second gate metal layer;

[0073] Figure 23 for Figure 16 Schematic diagram of the layout of the first source and drain metal layer;

[0074] Figure 24 A fourth schematic diagram of a sub-pixel layout provided in an embodiment of the present disclosure;

[0075] Figure 25 for Figure 24 A schematic structural diagram of the second power line portion;

[0076] Figure 26 for Figure 24 Schematic diagram of the layout of the first source and drain metal layer;

[0077] Figure 27 for Figure 24 Schematic diagram of the layout of the first source and drain metal layer;

[0078] Figure 28 for Figure 24 Schematic diagram of the layout of the second source and drain metal layer;

[0079] Figure 29 for Figure 24 Schematic diagram of the layout of the first source and drain metal layer and the second source and drain metal layer;

[0080] Figure 30 A fifth schematic diagram of a sub-pixel layout provided in an embodiment of the present disclosure;

[0081] Figure 31 for Figure 30 Schematic diagram of the layout of the first source and drain metal layer;

[0082] Figure 32 for Figure 30 A second connection diagram of the middle power compensation pattern and the second power line portion;

[0083] Figure 33 is a schematic diagram of a second layout of eight sub-pixels;

[0084] Figure 34 for Figure 33 A schematic diagram of a sub-pixel driving circuit including eight sub-pixels;

[0085] Figure 35 for Figure 33 Schematic diagram of the layout of the active layer in ;

[0086] Figure 36 for Figure 33 Schematic diagram of the layout of the first source and drain metal layer;

[0087] Figure 37 for Figure 33 Schematic diagram of the layout of the second source and drain metal layer and the anode layer;

[0088] Figure 38 A schematic diagram of the layout of the first source / drain metal layer and the anode layer provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0089] In order to further illustrate the display substrate and its manufacturing method, and the display device provided by the embodiments of the present disclosure, a detailed description is given below with reference to the accompanying drawings.

[0090] The structure of an AMOLED display panel includes: a substrate, multiple sub-pixel driving circuits arranged on the substrate, and multiple light-emitting elements arranged on the side of the sub-pixel driving circuit facing away from the substrate. The light-emitting elements correspond one-to-one to the sub-pixel driving circuits. The sub-pixel driving circuits are used to drive the corresponding light-emitting elements to emit light, thereby realizing the display function of the display panel.

[0091] In the related art, the sub-pixel driving circuit generally includes a plurality of thin film transistors, such as Figure 1a As shown, Figure 1a FIG. 1 shows a specific layout of the 7 thin film transistors when the sub-pixel driving circuit includes 7 thin film transistors M1 to M7. When arranged in this manner, the sub-pixel driving circuit includes: Figure 1b The active layer shown, such as Figure 1c The first metal layer shown, such as Figure 1d The second metal layer shown, and Figure 1e The third metal layer shown; the active layer includes an active pattern (such as Figure 1b The portion within the dotted box in FIG), and the active pattern coupled to the active pattern, having conductive properties (such as Figure 1b The first metal layer includes the gates of each thin film transistor, the scanning signal line GATE coupled to the gates, one electrode plate CE1 of the storage capacitor in the sub-pixel driving circuit, the reset signal line RST, and the light-emitting control signal line EM; the second metal layer includes the initialization signal line VINT, and another electrode plate CE2 of the storage capacitor in the sub-pixel driving circuit; the third metal layer includes the data line DATA, the power signal line VDD, and some conductive connection parts (such as marks 341~343).

[0092] It is worth noting that, as shown in FIG1 , when laying out the sub-pixel driving circuit, some vias (eg, marked: 381 to 388 ) may be provided in order to achieve coupling between functional patterns provided on different layers.

[0093] See also Figures 2 to 4 The present disclosure provides a display substrate, comprising: a substrate and a plurality of sub-pixels arrayed on the substrate, each sub-pixel comprising: a light-emitting element, an initialization signal line pattern 94, a reset signal line pattern 95, a gate line pattern 92, a light-emitting control signal line pattern 93, a power signal line pattern 91, and a first data line pattern 981 and a second data line pattern 982 arranged opposite to each other along a first direction.

[0094] At least a portion of the initialization signal line pattern 94, at least a portion of the reset signal line pattern 95, at least a portion of the gate line pattern 92, and at least a portion of the light emission control signal line pattern 93 extend along the first direction.

[0095] At least a portion of the power signal line pattern 91, at least a portion of the first data line pattern 981, and at least a portion of the second data line pattern 982 all extend along a second direction, and the first direction intersects the second direction. Exemplarily, the first direction includes the X direction, and the second direction includes the Y direction.

[0096] All sub-pixels included in the display substrate can be divided into multiple rows of sub-pixels arranged in sequence along the second direction, and multiple columns of sub-pixels arranged in sequence along the first direction. The initialization signal line graphics 94 included in the sub-pixels located in the same row are electrically connected in sequence to form an integrated structure; the gate line graphics 92 included in the sub-pixels located in the same row are electrically connected in sequence to form an integrated structure; the light-emitting control signal line graphics 93 included in the sub-pixels located in the same row are electrically connected in sequence to form an integrated structure; the reset signal line graphics 95 included in the sub-pixels located in the same row are electrically connected in sequence to form an integrated structure; the first data line graphics 981 included in the sub-pixels located in the same column are electrically connected in sequence to form an integrated structure; the second data line graphics 982 included in the sub-pixels located in the same column are electrically connected in sequence to form an integrated structure; the power signal line graphics 91 included in the sub-pixels located in the same column are electrically connected in sequence to form an integrated structure.

[0097] Each sub-pixel further includes a sub-pixel driving circuit. For example, one sub-pixel driving circuit includes seven thin-film transistors and one capacitor. Each transistor in the sub-pixel driving circuit is a P-type transistor, wherein the first electrode of each transistor includes a source electrode, and the second electrode of each transistor includes a drain electrode.

[0098] The first transistor T1 has a dual-gate structure, the gate 201g of the first transistor T1 is coupled to the gate line pattern 92, the source S1 of the first transistor T1 is coupled to the drain D3 of the third transistor T3 (i.e., the driving transistor), and the drain D1 of the first transistor T1 is coupled to the gate 203g of the third transistor T3.

[0099] The second transistor T2 has a dual-gate structure, a gate 202g of the second transistor T2 is coupled to the reset signal line pattern 95, a source S2 of the second transistor T2 is coupled to the initialization signal line pattern 94, and a drain D2 of the second transistor T2 is coupled to the gate 203g of the third transistor T3.

[0100] The gate 204g of the fourth transistor T4 is coupled to the gate line pattern 92, the source S4 of the fourth transistor T4 is coupled to the first data line pattern 981 or the second data line pattern 982, and the drain D4 of the fourth transistor T4 is coupled to the source S3 of the third transistor T3.

[0101] The gate 205g of the fifth transistor T5 is coupled to the light emitting control signal line pattern 93, the source S5 of the fifth transistor T5 is coupled to the power signal line pattern 91, and the drain D5 of the fifth transistor T5 is coupled to the source S3 of the third transistor T3.

[0102] The gate 206g of the sixth transistor T6 is coupled to the light emitting control signal line pattern 93, the source S6 of the sixth transistor T6 is coupled to the drain D3 of the third transistor T3, and the drain D6 of the sixth transistor T6 is coupled to the anode of the light emitting element EL.

[0103] The gate 207g of the seventh transistor T7 is coupled to the reset signal line pattern 95' in the next sub-pixel adjacent along the second direction, the drain D7 of the seventh transistor T7 is coupled to the anode of the corresponding light-emitting element EL, and the source S7 of the seventh transistor T7 is coupled to the initialization signal line pattern 94' in the next sub-pixel adjacent along the second direction.

[0104] The first plate Cst1 of the storage capacitor Cst is multiplexed as the gate 203 g of the third transistor T3 , and the second plate Cst2 of the storage capacitor Cst is coupled to the power signal line pattern 91 .

[0105] like Figure 3 As shown, when the sub-pixel driving circuit of the above structure is in operation, each working cycle includes a reset period P1, a writing compensation period P2 and a light emitting period P3. Figure 3 In the figure, E1 represents the light-emitting control signal transmitted on the light-emitting control signal line pattern 93 in the current sub-pixel, R1 represents the reset signal transmitted on the reset signal line pattern 95 in the current sub-pixel, D1 represents the data signal transmitted on the target data line pattern in the current sub-pixel, G1 represents the gate scanning signal transmitted on the gate line pattern 92 in the current sub-pixel, and R1' represents the reset signal transmitted on the reset signal line pattern 95' in the next sub-pixel adjacent to the current sub-pixel along the second direction.

[0106] During the first reset period P1, the reset signal input by the reset signal line pattern 95 is at an effective level, the second transistor T2 is turned on, and the initialization signal transmitted by the initialization signal line pattern 94 is input to the gate 203g of the third transistor T3, so that the gate-source voltage Vgs maintained on the third transistor T3 in the previous frame is cleared, thereby resetting the gate 203g of the third transistor T3.

[0107] During the write compensation period P2, the reset signal input by the reset signal line pattern 95 is at an inactive level, the second transistor T2 is turned off, and the gate scan signal input by the gate line pattern 92 is at an active level, controlling the first transistor T1 and the fourth transistor T4 to be turned on. The target data line pattern writes the data signal and transmits it to the source S3 of the third transistor T3 through the fourth transistor T4. At the same time, the first transistor T1 and the fourth transistor T4 are turned on, so that the third transistor T3 forms a diode structure. Therefore, the threshold voltage compensation of the third transistor T3 is achieved through the cooperation of the first transistor T1, the third transistor T3 and the fourth transistor T4. When the compensation time is long enough, the gate 203g potential of the third transistor T3 can be controlled to eventually reach Vdata+Vth, where Vdata represents the data signal voltage value and Vth represents the threshold voltage of the third transistor T3.

[0108] During the writing compensation period P2, the reset signal inputted by the reset signal line pattern 95' is at an active level, controlling the seventh transistor T7 to be turned on, and the initialization signal transmitted by the initialization signal line pattern 94' is inputted to the anode of the light emitting element EL, controlling the light emitting element EL not to emit light.

[0109] During the light-emitting period P3, the light-emitting control signal written in the light-emitting control signal line pattern 93 is at an effective level, controlling the fifth transistor T5 and the sixth transistor T6 to be turned on, so that the power signal transmitted by the power signal line pattern 91 is input to the source S3 of the third transistor T3. At the same time, since the gate 203g of the third transistor T3 is maintained at Vdata+Vth, the third transistor T3 is turned on. The gate-source voltage corresponding to the third transistor T3 is Vdata+Vth-VDD, where VDD is the voltage value corresponding to the power signal. The leakage current generated based on the gate-source voltage flows to the anode of the corresponding light-emitting element EL, driving the corresponding light-emitting element EL to emit light.

[0110] When manufacturing the above sub-pixels, the layout of each film layer corresponding to the sub-pixel is as follows:

[0111] like Figure 17As shown, the active film layer, the first gate insulation layer GI1, the first gate metal layer, the second gate insulation layer GI2, the second gate metal layer, the interlayer insulation layer ILD, the first source and drain metal layer, the first flat layer PLN1, the second source and drain metal layer, the second flat layer PLN2 and the anode layer are stacked in sequence along the direction away from the substrate.

[0112] like Figure 5 As shown, the active film layer is used to form the channel region (the portion covered by the gate of each transistor), source electrodes (such as S1-S7), and drain electrodes (such as D1-D7) of each transistor in the sub-pixel driving circuit. Due to doping, the active film layer corresponding to the source and drain electrodes has better conductivity than the active film layer corresponding to the channel region. The active film layer can be made of amorphous silicon, polycrystalline silicon, oxide semiconductor materials, etc. It should be noted that the above-mentioned source and drain electrodes can be doped with n-type impurities or p-type impurities.

[0113] like Figure 5 As shown, the first gate metal layer is used to form the gate of each transistor in the sub-pixel driving circuit (such as: 201g~207g), as well as the gate line pattern 92, the light-emitting control signal line pattern 93, the reset signal line pattern 95 and other structures included in the sub-pixel. The gate 203g of the third transistor T3 in each sub-pixel driving circuit is reused as the first plate Cst1 of the second storage capacitor Cst in the sub-pixel driving circuit.

[0114] like Figure 6 As shown, the second gate metal layer is used to form the second plate Cst2 of the second storage capacitor Cst, the initialization signal line pattern 94 included in the sub-pixel, and the shielding pattern 80.

[0115] like Figure 7 As shown, the first source / drain metal layer is used to form the power signal line pattern 91 and some conductive connections included in the sub-pixel. It is worth noting that in order to ensure the stability of the power signal transmitted by the power signal line pattern 91, when laying out the power signal line pattern 91, the width of the power signal line pattern 91 in the direction perpendicular to its own extension should be maximized while avoiding the conductive connections and some vias provided in the same layer.

[0116] like Figure 8 As shown, the second source-drain metal layer is used to form a first data line pattern 981, a second data line pattern 982 and some conductive connection parts included in the sub-pixel.

[0117] In addition, if Figure 4As shown, in the display substrate provided by the present disclosure, in the second direction, the gate 204g of the fourth transistor T4, the gate 201g of the first transistor T1, and the gate 202g of the second transistor T2 are all located on the first side of the gate 203g of the third transistor T3. The gate of the seventh transistor T7, the gate 206g of the sixth transistor T6, and the gate of the fifth transistor T5 are all located on the second side of the gate of the driving transistor. Exemplarily, the first side and the second side of the gate of the driving transistor are opposite sides along the second direction. Furthermore, the first side of the gate 203g of the third transistor T3 can be the upper side of the gate 203g of the third transistor T3, and the second side of the gate 203g of the third transistor T3 can be the lower side of the gate 203g of the third transistor T3. The lower side, for example, the side of the display substrate used for bonding an IC is the lower side of the display substrate. The lower side of the gate 203g of the third transistor T3 is the side of the gate 203g of the third transistor T3 that is closer to the IC. The upper side is an opposite side to the lower side, for example, a side of the gate 203 g of the third transistor T3 that is farther away from the IC.

[0118] In the first direction, the gate 204g of the fourth transistor T4 and the gate 205g of the fifth transistor T5 are both located on a third side of the gate 203g of the third transistor T3, and the gate 201g of the first transistor T1 and the gate 206g of the sixth transistor T6 are both located on a fourth side of the gate 203g of the third transistor T3. Exemplarily, the third and fourth sides of the gate 203g of the third transistor T3 are two opposing sides along the first direction. Furthermore, the third side of the gate 203g of the third transistor T3 may be on the right side of the gate 203g of the third transistor T3, and the fourth side of the gate 203g of the third transistor T3 may be on the left side of the gate 203g of the third transistor T3. For example, in the same sub-pixel, the second data line pattern 982 is located on the right side of the gate 203g of the third transistor T3, and the first data line pattern 981 is located on the left side of the gate 203g of the third transistor T3.

[0119] When the display substrate is compatible with optical fingerprint recognition technology, the principle of optical fingerprint recognition leads to certain requirements for the transmittance of the display substrate. That is, a light signal of sufficient intensity is required to support the response of the light-sensitive sensor (English: Light-sensitive sensor, hereinafter referred to as sensor) to light, thereby shortening the response time of fingerprint recognition.

[0120] When using the display substrate with the above structure for under-screen fingerprint recognition, since the display substrate covers the sensor, the metal conductors and P-Si semiconductors (used to form the active layer) included in each sub-pixel in the display substrate as wiring and devices occupy more than 85% of the area of ​​the display substrate. These areas have a large shielding effect on electromagnetic waves, reducing the signal-to-noise ratio of optical fingerprint recognition and limiting the fingerprint detection speed.

[0121] To improve the transmittance of the display substrate, changes to the backplane layout can be considered. For example, these approaches can be used to narrow the width of metal traces, reduce the size of light-emitting elements, and reduce the size of transistors or capacitors. However, while these solutions can improve resolution, they can also negatively impact the performance of the display substrate.

[0122] See also Figures 9 to 11 , Figure 24 、 Figure 25 and Figure 27 The present disclosure provides a display substrate, comprising: a substrate and a plurality of sub-pixels arrayed on the substrate; the sub-pixels comprising:

[0123] The power signal line graphic 91 includes a first power line portion 911 and a second power line portion 912; at least a portion of the first power line portion 911 extends along the second direction; the second power line portion 912 includes a main body 9120, a first end portion 9121 and a second end portion 9122, the main body 9120 and the first power line portion 911 are arranged along the first direction, and the main body 9120 and the first power line portion 911 are spaced apart, the first direction intersects with the second direction, the first end portion 9121 and the second end portion 9122 are arranged opposite to each other along the second direction, the first end portion 9121 is respectively coupled to one end of the main body 9120 and the first power line portion 911, the second end portion 9122 is respectively coupled to the other end of the main body 9120 and the first power line portion 911, and a gap 50 is provided between the first power line portion 911 and the second power line portion 912.

[0124] Specifically, the display substrate includes a plurality of sub-pixels arrayed on a substrate, wherein the plurality of sub-pixels can be divided into a plurality of rows of sub-pixels and a plurality of columns of sub-pixels. The plurality of rows of sub-pixels are arranged along the second direction, and each row of sub-pixels includes a plurality of sub-pixels sequentially arranged along the first direction. The plurality of columns of sub-pixels are arranged along the first direction, and each column of sub-pixels includes a plurality of sub-pixels sequentially arranged along the second direction.

[0125] Each sub-pixel includes the power signal line pattern 91, and the power signal line pattern 91 includes a first power line portion 911 and a second power line portion 912; at least a portion of the first power line portion 911 extends along the second direction; in the same column of sub-pixels, the first power line portions 911 included in each sub-pixel are electrically connected in sequence to form an integrated structure.

[0126] The second power line portion 912 includes a main body 9120, a first end 9121, and a second end 9122. Exemplarily, at least a portion of the main body 9120 extends along the second direction. Exemplarily, the thickness of the main body 9120 is uniform or non-uniform in a plane parallel to the substrate and perpendicular to the second direction. Exemplarily, the main body 9120 and the first power line portion 911 are aligned along the first direction, and the main body 9120 and the first power line portion 911 are spaced apart. The distance between the main body 9120 and the first power line portion 911 along the first direction determines the width of the aperture 50 in the first direction.

[0127] Illustratively, the first end portion 9121 and the second end portion 9122 are disposed opposite each other along the second direction. The first end portion 9121 is coupled to one end of the main body 9120 and the first power cord portion 911, respectively, and the second end portion 9122 is coupled to the other end of the main body 9120 and the first power cord portion 911, respectively. The main body 9120, the first end portion 9121, the second end portion 9122, and the first power cord portion 911 collectively define the aperture 50. Along the second direction, the length of the main body 9120 and the distance between the first end portion 9121 and the second end portion 9122 determine the length of the aperture 50 in the first direction.

[0128] Exemplarily, the main body 9120, the first end portion 9121, the second end portion 9122, and the first power line portion 911 are formed into an integrated structure. It is worth noting that the integrated structure includes: the main body 9120, the first end portion 9121, the second end portion 9122, and the first power line portion 911 being simultaneously formed of the same material and in contact with each other through a single patterning process.

[0129] According to the specific structure of the display substrate described above, in the display substrate provided by the embodiment of the present disclosure, by providing the power signal line pattern 91 with the first power line portion 911 and the second power line portion 912, a gap 50 is formed between the first power line portion 911 and the second power line portion 912, thereby reducing the proportion of opaque areas in the display substrate and improving the light transmittance of the display substrate. Therefore, when the display substrate provided by the embodiment of the present disclosure is compatible with optical fingerprint recognition technology, it can provide excellent conditions for the sensor to collect optical signals, thereby effectively improving the speed and accuracy of fingerprint recognition.

[0130] In addition, in the display substrate provided by the embodiment of the present disclosure, pores are only formed on the power signal line pattern 91, and no operations such as narrowing the width of metal traces other than the power signal line pattern 91, compressing the size of light-emitting elements, compressing the size of transistors or capacitors, etc. are performed. Therefore, the display substrate provided by the embodiment of the present disclosure is not likely to have a negative impact on the performance of the display substrate while improving the resolution.

[0131] like Figure 8 、 Figure 12 、 Figure 28 and Figure 29 As shown, in some embodiments, the plurality of sub-pixels are divided into a plurality of rows of sub-pixels, and each row of sub-pixels includes a plurality of sub-pixels sequentially arranged along a first direction; the sub-pixels further include:

[0132] A first data line pattern 981 and a second data line pattern 982 are arranged opposite to each other along a first direction, wherein at least a portion of the first data line pattern 981 and at least a portion of the second data line pattern 982 extend along the second direction;

[0133] The orthographic projection of the first data line pattern 981 on the substrate overlaps with the orthographic projection of the first power line portion 911 in the sub-pixel adjacent to the sub-pixel to which it belongs along the first direction on the substrate, and the orthographic projection of the second data line pattern 982 on the substrate overlaps with the orthographic projection of the main body 9120 on the substrate.

[0134] Specifically, the display substrate includes a plurality of sub-pixels arrayed on a substrate, wherein the plurality of sub-pixels can be divided into a plurality of rows of sub-pixels and a plurality of columns of sub-pixels. The plurality of rows of sub-pixels are arranged along the second direction, and each row of sub-pixels includes a plurality of sub-pixels sequentially arranged along the first direction. The plurality of columns of sub-pixels are arranged along the first direction, and each column of sub-pixels includes a plurality of sub-pixels sequentially arranged along the second direction.

[0135] Exemplarily, the first direction includes a horizontal direction, and the second direction includes a vertical direction.

[0136] Each sub-pixel includes a first data line pattern 981 and a second data line pattern 982 arranged opposite each other along a first direction. At least a portion of the first data line pattern 981 and at least a portion of the second data line pattern 982 extend along the second direction. The first data line patterns 981 included in each sub-pixel in the same column of sub-pixels are electrically connected in sequence to form an integrated structure. The second data line patterns 982 included in each sub-pixel in the same column of sub-pixels are electrically connected in sequence to form an integrated structure.

[0137] like Figure 8 and Figure 28 As shown, illustratively, the first data line pattern 981 includes a first bump 9811, and the second data line pattern 982 includes a second bump 9812. The first bump 9811 and the second bump 9812 are used to electrically connect to the first electrode S4 of the fourth transistor T4.

[0138] Exemplarily, in the same column of sub-pixels, odd-numbered sub-pixels receive data signals provided by the first data line pattern 981 included therein, and even-numbered sub-pixels receive data signals provided by the second data line pattern 982 included therein.

[0139] Exemplarily, in the same column of sub-pixels, the even-numbered sub-pixels receive data signals provided by the first data line pattern 981 included therein, and the odd-numbered sub-pixels receive data signals provided by the second data line pattern 982 included therein.

[0140] Each sub-pixel includes a sub-pixel driving circuit. The sub-pixel driving circuit includes a storage capacitor and a plurality of thin film transistors, such as Figure 2 、 Figure 9 and Figure 24 As shown, the sub-pixel driving circuit exemplarily includes 7T1C, ie, 7 transistors and a storage capacitor. The sub-pixel driving circuit is used to generate a driving signal for driving the light-emitting element to emit light.

[0141] Exemplarily, the sub-pixel driving circuit includes a driving transistor (i.e., a third transistor) and a data writing transistor (i.e., a fourth transistor T4), the first electrode of the data writing transistor is coupled to the first data line pattern 981 or the second data line pattern 982, and can receive the data signal provided by the first data line pattern 981 or the second data line pattern 982, the second electrode of the data writing transistor is coupled to the first electrode of the driving transistor, and the data writing transistor can transmit the data signal received by its first electrode to the first electrode of the driving transistor.

[0142] In the same column of sub-pixels, the first electrodes of the data write transistors in adjacent sub-pixels are coupled to different data line patterns. More specifically, in the same column of sub-pixels, the first electrode of the data write transistor included in one of the adjacent sub-pixels is coupled to the first data line pattern 981, while the first electrode of the data write transistor included in the other of the adjacent sub-pixels is coupled to the second data line pattern 982.

[0143] In the display substrate provided by the above embodiment, by setting each sub-pixel to include a first data line pattern 981 and a second data line pattern 982, and in the same column of sub-pixels, the data line patterns coupled to the data writing transistors in adjacent sub-pixels are different, it is achieved that in the same column of sub-pixels, adjacent sub-pixels are provided with data signals by different data line patterns, ensuring that each sub-pixel has sufficient data signal writing time, thereby solving the problem of insufficient data signal writing time for sub-pixels in each row when the display substrate is displayed at high frequency.

[0144] The specific layout positions of the pores 50 are varied, for example, Figure 12 As shown, the orthographic projection of the first data line pattern 981 on the substrate overlaps with the orthographic projection of the first power line portion 911 (i.e., the first power line portion 911 included in the power signal line pattern 91') in the previous sub-pixel adjacent to the sub-pixel to which it belongs along the first direction on the substrate, and the orthographic projection of the second data line pattern 982 on the substrate overlaps with the orthographic projection of the main body 9120 on the substrate; this layout enables the pore 50 to be located near the second data line pattern 982 in the sub-pixel to which it belongs, and near the first data line pattern 981 in the next sub-pixel adjacent to the sub-pixel along the first direction.

[0145] The above layout also makes the overlapping area between the orthographic projection of the first data line pattern 981 on the substrate and the orthographic projection of the functional pattern with a fixed potential on the substrate close to the overlapping area between the orthographic projection of the second data line pattern 982 on the substrate and the orthographic projection of the functional pattern with a fixed potential on the substrate, thereby effectively reducing the load difference between the first data line pattern 981 and the second data line pattern 982.

[0146] It should be noted that if Figure 9 、 Figure 12 、 Figure 29 and Figure 30 As shown, the functional pattern with a fixed potential includes: a power signal line pattern 91, an initialization signal line pattern 94, and a conductive functional pattern 961 coupled to the power signal line pattern 91 or the initialization signal line pattern 94.

[0147] like Figure 8 、 Figure 12 、 Figure 28 and Figure 29 As shown, in some embodiments, the orthographic projection of the first data line graphic 981 on the substrate is set to not overlap with the orthographic projection of the pore 50 on the substrate; and / or, the orthographic projection of the second data line graphic 982 on the substrate is set to not overlap with the orthographic projection of the pore 50 on the substrate.

[0148] By arranging that the orthographic projection of the first data line pattern 981 on the substrate does not overlap with the orthographic projection of the pore 50 on the substrate, the first data line pattern 981 is prevented from blocking the pore 50, thereby better ensuring the light transmittance of the pore 50.

[0149] Similarly, by setting the orthographic projection of the second data line pattern 982 on the substrate to not overlap with the orthographic projection of the pore 50 on the substrate, the second data line pattern 982 is prevented from blocking the pore 50, thereby better ensuring the light transmittance of the pore 50.

[0150] like Figure 5 、 Figure 9 、 Figure 11 、 Figure 24 、 Figure 26 and Figure 27 As shown, in some embodiments, the sub-pixel also includes a light-emitting control signal line pattern 93, at least a portion of which extends along the first direction; the orthographic projection of the light-emitting control signal line pattern 93 on the substrate partially overlaps with the orthographic projection of the pore 50 on the substrate.

[0151] Specifically, the sub-pixel further includes the light-emission control signal line pattern 93. The light-emission control signal line pattern 93 is used to transmit a light-emission control signal. At least a portion of the light-emission control signal line pattern 93 extends along a first direction. The light-emission control signal line patterns 93 included in the sub-pixels located in the same row along the first direction are electrically connected in sequence to form an integrated structure.

[0152] The above-mentioned setting makes the orthographic projection of the light-emitting control signal line pattern 93 on the substrate overlap with the orthographic projection of the pore 50 on the substrate, reducing the overlapping area of ​​the light-emitting control signal line pattern 93 and the power supply signal line pattern 91 with a fixed potential, thereby effectively reducing the load of the light-emitting control signal line pattern 93 and the power consumption caused by the load.

[0153] like Figure 11 and Figure 27As shown, in some embodiments, the first power line portion 911 includes a second sub-portion 9112 and a first sub-portion 9111 for enclosing the gap 50, and in a plane parallel to the substrate, along a direction perpendicular to the second direction, the width L6 of the first sub-portion 9111 is smaller than the width L5 of the second sub-portion 9112.

[0154] Specifically, the first power line portion 911 includes a first sub-portion 9111 for enclosing the aperture 50, and a second sub-portion 9112 that is not used to enclose the aperture 50. Exemplarily, the first sub-portion 9111 and the second sub-portion 9112 are formed as an integral structure. Exemplarily, the second power line portion 912 is directly coupled to the second sub-portion 9112.

[0155] The above arrangement is on a plane parallel to the substrate, and along a direction perpendicular to the second direction, the width L6 of the first sub-portion 9111 is smaller than the width L5 of the second sub-portion 9112, so that along the first direction, the distance between the main body 9120 and the first power line portion 911 becomes larger, thereby increasing the width of the pore 50 in the first direction, further improving the transmittance of the display substrate.

[0156] like Figure 33 and Figure 34 As shown, in some embodiments, the sub-pixel further includes a light-emitting element, and the light-emitting element includes an anode pattern 70, and the orthographic projection of the anode pattern 70 on the substrate does not overlap with the orthographic projection of the aperture 50 on the substrate.

[0157] Specifically, the light-emitting element includes an anode pattern 70, a light-emitting functional layer, and a cathode, which are stacked in sequence in a direction away from the substrate. The anode pattern 70 is coupled to the sub-pixel driving circuit in the sub-pixel to which it belongs, and receives a driving signal provided by the sub-pixel driving circuit. The light-emitting functional layer includes an organic light-emitting material layer. In addition, the light-emitting functional layer may also include: an electron transporting layer (ETL), an electron injection layer (EIL), a hole transporting layer (HTL), and a hole injection layer (HIL) and other common layers of the entire layer structure. The cathode is coupled to the negative power signal line VSS in the display substrate and receives a negative power signal provided by the negative power signal line VSS. The light-emitting functional layer emits light under the joint action of the anode pattern 70 and the cathode, thereby realizing the display function of the display substrate.

[0158] The above arrangement ensures that the orthographic projection of the anode pattern 70 on the substrate does not overlap with the orthographic projection of the pore 50 on the substrate, thereby preventing the anode pattern 702 from blocking the pore 50 and better ensuring the light transmittance of the pore 50 .

[0159] like Figure 33 、 Figure 34 and Figure 38 As shown, in some embodiments, the orthographic projection of the pore 50 on the substrate is located between the orthographic projection of the first anode pattern on the substrate and the orthographic projection of the second anode pattern on the substrate; the sub-pixel to which the pore 50 belongs includes the first anode pattern, and the next sub-pixel adjacent to the sub-pixel along the first direction includes the second anode pattern.

[0160] Specifically, each sub-pixel includes a sub-pixel driving circuit and a light-emitting element located on a side of the sub-pixel driving circuit facing away from the substrate. For example, the structure of the sub-pixel driving circuit is as follows: Figure 2 As shown, the anode pattern included in the light emitting element is coupled to the drain D6 of the sixth transistor T6 in the sub-pixel driving circuit, and receives the driving signal output by the drain D6 of the sixth transistor T6.

[0161] The layout relationship between the aperture 50 and the anode pattern 70 varies. For example, the orthographic projection of the aperture 50 on the substrate is located between the orthographic projection of the first anode pattern and the orthographic projection of the second anode pattern on the substrate. The first anode pattern is the anode pattern 70 included in the sub-pixel to which the aperture 50 belongs, and the second anode pattern is the anode pattern 70 included in the next sub-pixel adjacent to the sub-pixel along the first direction.

[0162] Exemplarily, the first anode pattern and the second anode pattern are arranged along a third direction, and the third direction intersects both the first direction and the second direction. Exemplarily, the third direction is 45 degrees to the first direction. Exemplarily, the third direction is 135 degrees to the first direction.

[0163] Illustratively, the orthographic projection of the pore 50 on the substrate does not overlap with the orthographic projection of the first anode pattern on the substrate, and the orthographic projection of the pore 50 on the substrate does not overlap with the orthographic projection of the second anode pattern on the substrate.

[0164] The above-mentioned setting of the orthographic projection of the pore 50 on the substrate is located between the orthographic projection of the first anode pattern on the substrate and the orthographic projection of the second anode pattern on the substrate. While ensuring that the pore 50 is not blocked by the first anode pattern and the second anode pattern, it better utilizes the layout space on the display substrate and maximizes the size of the pore 50.

[0165] like Figure 33 and Figure 34 As shown, in some embodiments, the plurality of sub-pixels are divided into a plurality of pixel units, each pixel unit including a red sub-pixel R, a blue sub-pixel B and two green sub-pixels G;

[0166] like Figure 38 As shown, in the pixel units located in the same row along the first direction (as marked X), the anode patterns (such as R71 / R72) included in the red sub-pixels R in each pixel unit and the anode patterns (such as B71 / B72) included in the blue sub-pixels B in each pixel unit are distributed in a row (such as marked X1), and the anode patterns (such as G71 / G72 / G71' / G72') included in the green sub-pixels G in each pixel unit are distributed in another row (such as marked X2);

[0167] like Figure 33 and Figure 37 As shown, in the pixel units located in the same row along the first direction, the anode patterns 70 included in the red sub-pixel R, the anode patterns 70 included in the blue sub-pixel B, and the anode patterns 70 included in the green sub-pixel G are alternately distributed in sequence;

[0168] In pixel units located in the same row along the first direction, one of adjacent red sub-pixels R and green sub-pixels G includes the first anode pattern, and the other of adjacent red sub-pixels R and green sub-pixels G includes the second anode pattern;

[0169] In pixel units located in the same row along the first direction, one of adjacent blue sub-pixels B and green sub-pixels G includes the first anode pattern, and the other of adjacent blue sub-pixels B and green sub-pixels G includes the second anode pattern.

[0170] Specifically, the multiple sub-pixels are divided into a plurality of pixel units, and the multiple pixel units are distributed in an array. Each pixel unit includes a red sub-pixel R, a blue sub-pixel B, and two green sub-pixels G.

[0171] like Figure 38As shown, exemplarily, in the pixel units located in the same row along the first direction, the anode patterns (such as R71 / R72) included in the red sub-pixel R in each pixel unit and the anode patterns (such as B71 / B72) included in the blue sub-pixel B in each pixel unit are distributed in one row, and the anode patterns (such as G71 / G72 / G71' / G72') included in the green sub-pixel G in each pixel unit are distributed in another row; that is, in the pixel units located in the same row along the first direction, the anode patterns (such as G71 / G72 / G71' / G72') included in the green sub-pixel G are staggered from the anode patterns (such as R71 / R72) included in the red sub-pixel R along the second direction, and in the pixel units located in the same row along the first direction, the anode patterns (such as G71 / G72 / G71' / G72') included in the green sub-pixel G are staggered from the anode patterns 70 included in the blue sub-pixel (such as B71 / B72) along the second direction.

[0172] like Figure 33 As shown, exemplarily, in the pixel units located in the same row along the first direction, the anode pattern 70 included in the red sub-pixel R, the anode pattern 70 included in the blue sub-pixel B, and the anode pattern 70 included in the green sub-pixel G are alternately distributed in sequence; that is, in the pixel units located in the same row along the first direction, all the sub-pixels included are arranged in the RGBGRGBG manner; or in the pixel units located in the same row along the first direction, all the sub-pixels included are arranged in the BGRGBGRG manner.

[0173] When the display substrate adopts the pixel unit of the above structure, for example, it can be set that in the pixel units located in the same row along the first direction, one of the adjacent red sub-pixels R and green sub-pixels G includes the first anode pattern, and the other of the adjacent red sub-pixels R and green sub-pixels G includes the second anode pattern; in more detail, Figure 38 As shown, Figure 38 FIG. 5 illustrates an orthographic projection of the third aperture 53 on the substrate, which is located between an orthographic projection of the first anode pattern R71 included in the red sub-pixel R and an orthographic projection of the second anode pattern G72′ included in the green sub-pixel G on the substrate. Figure 38 , the orthographic projection of the second aperture 52 on the substrate is shown, and is located between the orthographic projection of the first anode pattern G71 included in the green sub-pixel G on the substrate and the orthographic projection of the second anode pattern R72 included in the red sub-pixel R on the substrate.

[0174] When the display substrate adopts the pixel unit structure described above, for example, it can be arranged that in the pixel units located in the same row along the first direction, one of the adjacent blue sub-pixels B and green sub-pixels G includes the first anode pattern, and the other of the adjacent blue sub-pixels B and green sub-pixels G includes the second anode pattern. In more detail, Figure 38 As shown, Figure 38 FIG. 4 illustrates an orthographic projection of the fourth aperture 54 on the substrate, which is located between an orthographic projection of the first anode pattern G71′ included in the green sub-pixel G on the substrate and an orthographic projection of the second anode pattern B72 included in the blue sub-pixel B on the substrate. Figure 38 , the orthographic projection of the first aperture 51 on the substrate is shown, which is located between the orthographic projection of the first anode pattern B71 included in the blue sub-pixel B on the substrate and the orthographic projection of the second anode pattern G72 included in the green sub-pixel G on the substrate.

[0175] The above-mentioned setting of the orthographic projection of the pore 50 on the substrate is located between the orthographic projection of the first anode pattern on the substrate and the orthographic projection of the second anode pattern on the substrate. While ensuring that the pore 50 is not blocked by the first anode pattern and the second anode pattern, it better utilizes the layout space on the display substrate and maximizes the size of the pore 50.

[0176] like Figures 16 to 19 As shown, in some embodiments, the sub-pixel further includes a light-emitting element, and the light-emitting element includes an anode pattern 70, and a portion of the orthographic projection of the anode pattern 70 on the substrate partially overlaps with the orthographic projection of the aperture 50 on the substrate.

[0177] Specifically, when actually laying out the sub-pixels, due to the limitation of the layout space, the orthographic projections of some anode patterns 70 in the display substrate on the substrate may be arranged to partially overlap with the orthographic projections of the pores 50 on the substrate.

[0178] For example, the anode pattern 70 may be made of a transparent conductive material, so that even if the orthographic projection of the anode pattern 70 on the substrate overlaps with the orthographic projection of the pore 50 on the substrate, the portion of the pore 50 covered by the anode pattern 70 can still have a certain light transmittance.

[0179] Required explanation Figure 17 Reference numeral 40 represents a substrate and some film layers (such as a buffer layer, an isolation layer, etc.) disposed on the substrate.

[0180] like Figures 16 to 19As shown, in some embodiments, the plurality of sub-pixels are divided into a plurality of pixel units, each pixel unit including a red sub-pixel R, a blue sub-pixel B, a first green sub-pixel G1 and a second green sub-pixel G2;

[0181] In the pixel units located in the same row along the first direction, the anode pattern 70 included in the red sub-pixel R, the anode pattern 70 included in the blue sub-pixel B, and the anode pattern 70 included in the first green sub-pixel G1 in each pixel unit are distributed in a row (e.g., marked X3), and the anode pattern 70 included in the second green sub-pixel G2 in each pixel unit are distributed in another row (e.g., marked X4);

[0182] The pores 50 include a first pore 501, wherein a portion of an orthographic projection of the first pore 501 on the substrate is located inside an orthographic projection of the anode pattern 70 included in the first green sub-pixel G1 on the substrate;

[0183] Another portion of the orthographic projection of the first aperture 501 on the substrate is located between the orthographic projection of the anode pattern 70 of the red sub-pixel R and the orthographic projection of the anode pattern 70 of the first green sub-pixel G1 on the substrate; the anode pattern 70 of the red sub-pixel R and the anode pattern 70 of the first green sub-pixel G1 are located in the same row;

[0184] Another part of the orthographic projection of the first pore 501 on the substrate is located between the orthographic projection of the anode pattern 70 included in the blue sub-pixel B on the substrate and the orthographic projection of the anode pattern 70 included in the first green sub-pixel G1 on the substrate; the anode pattern included in the blue sub-pixel B and the anode pattern included in the first green sub-pixel G1 are located in two adjacent rows.

[0185] Specifically, the plurality of sub-pixels are divided into a plurality of pixel units, each of which includes a red sub-pixel R, a blue sub-pixel B, a first green sub-pixel G1, and a second green sub-pixel G2. Exemplarily, in a pixel unit, the sub-pixel driving circuits included in the sub-pixels of different colors are located in the same row along the first direction.

[0186] Illustratively, in the pixel units located in the same row along the first direction, the anode pattern 70 included in the red sub-pixel R, the anode pattern 70 included in the blue sub-pixel B, and the anode pattern 70 included in the first green sub-pixel G1 in each pixel unit are distributed in a row.

[0187] The pore 50 includes a first pore 501. Exemplarily, a portion of the orthographic projection of the first pore 501 on the substrate is located within the orthographic projection of the anode pattern 70 included in the first green sub-pixel G1 on the substrate, and another portion of the orthographic projection of the first pore 501 on the substrate does not overlap with the orthographic projection of the anode pattern 70 included in the first green sub-pixel G1 on the substrate. Exemplarily, the portion occupies less than 1 / 2 of the entire first pore 501. Exemplarily, the portion occupies approximately 1 / 3 of the entire first pore 501.

[0188] Illustratively, another portion of the orthographic projection of the first aperture 501 on the substrate is located between the orthographic projection of the anode pattern 70 included in the red sub-pixel R and the orthographic projection of the anode pattern 70 included in the first green sub-pixel G1 on the substrate; the anode pattern 70 of the first green sub-pixel G1 can cover a portion of the first aperture 501. Illustratively, the anode pattern 70 included in the red sub-pixel R and the anode pattern included in the first green sub-pixel G1 are located in the same row along the first direction. Illustratively, the first aperture 501 belongs to the red sub-pixel R.

[0189] Another portion of the orthographic projection of the first aperture 501 on the substrate is also located between the orthographic projection of the anode pattern 70 included in the blue sub-pixel B and the orthographic projection of the anode pattern 70 included in the first green sub-pixel G1 on the substrate. Exemplarily, the anode pattern 70 included in the blue sub-pixel B is located in the next row adjacent to the anode pattern 70 included in the first green sub-pixel G1. Exemplarily, the anode pattern 70 included in the blue sub-pixel B and the anode pattern 70 included in the first green sub-pixel G1 are arranged along a fourth direction, and the fourth direction intersects both the first direction and the second direction.

[0190] In some embodiments, the area of ​​a portion of the orthographic projection of the first pore 501 on the substrate is less than 50% of the entire area of ​​the orthographic projection of the first pore 501 on the substrate.

[0191] like Figures 16 to 19 As shown, in some embodiments, the plurality of sub-pixels are divided into a plurality of pixel units, each pixel unit including a red sub-pixel R, a blue sub-pixel B, a first green sub-pixel G1 and a second green sub-pixel G2;

[0192] In the pixel units located in the same row along the first direction, the anode pattern 70 included in the red sub-pixel R, the anode pattern 70 included in the blue sub-pixel B, and the anode pattern 70 included in the first green sub-pixel G1 in each pixel unit are distributed in a row (e.g., marked X3), and the anode pattern 70 included in the second green sub-pixel G2 in each pixel unit are distributed in another row (e.g., marked X4);

[0193] The pores include a second pore 502, and the orthographic projection of the second pore 502 on the substrate is located between the orthographic projection of the anode pattern 70 included in the first green sub-pixel G1 on the substrate and the orthographic projection of the anode pattern 70 included in the blue sub-pixel B on the substrate. The orthographic projection of the second pore 502 on the substrate does not overlap with the orthographic projection of the anode pattern 70 included in the red sub-pixel R on the substrate. The anode pattern included in the first green sub-pixel G1 and the anode pattern included in the blue sub-pixel B are located in the same row, and the anode pattern included in the red sub-pixel R and the anode pattern included in the first green sub-pixel G1 are located in two adjacent rows.

[0194] Specifically, the aperture 50 includes a second aperture 502. Exemplarily, the orthographic projection of the second aperture 502 on the substrate is located between the orthographic projection of the anode pattern 70 included in the first green sub-pixel G1 and the orthographic projection of the anode pattern 70 included in the blue sub-pixel B. Exemplarily, the second aperture 502 belongs to the first green sub-pixel G1. Exemplarily, the anode pattern included in the first green sub-pixel G1 and the anode pattern included in the blue sub-pixel B are located in the same row along the first direction.

[0195] Illustratively, the orthographic projection of the second aperture 502 on the substrate does not overlap with the orthographic projection of the anode pattern 70 included in the first green sub-pixel G1 on the substrate; the orthographic projection of the second aperture 502 on the substrate does not overlap with the orthographic projection of the anode pattern 70 included in the blue sub-pixel B on the substrate; and the orthographic projection of the second aperture 502 on the substrate does not overlap with the orthographic projection of the anode pattern 70 included in the red sub-pixel R on the substrate. Illustratively, the anode pattern included in the red sub-pixel R is located in the next row adjacent to the anode pattern included in the first green sub-pixel G1, the anode pattern included in the red sub-pixel R is staggered from the anode pattern included in the first green sub-pixel G1 along the second direction, and the anode pattern 70 included in the red sub-pixel R is staggered from the anode pattern 70 included in the blue sub-pixel B along the second direction. Illustratively, the anode pattern 70 included in the red sub-pixel R is staggered from the anode pattern 70 included in the blue sub-pixel B along the second direction.

[0196] like Figures 16 to 19 As shown, in some embodiments, the plurality of sub-pixels are divided into a plurality of pixel units, each pixel unit including a red sub-pixel R, a blue sub-pixel B, a first green sub-pixel G1 and a second green sub-pixel G2;

[0197] In the pixel units located in the same row along the first direction, the anode pattern 70 included in the red sub-pixel R, the anode pattern 70 included in the blue sub-pixel B, and the anode pattern 70 included in the first green sub-pixel G1 in each pixel unit are distributed in a row (e.g., marked X3), and the anode pattern 70 included in the second green sub-pixel G2 in each pixel unit are distributed in another row (e.g., marked X4);

[0198] The pores include a third pore 503, and a portion of an orthographic projection of the third pore 503 on the substrate is located inside an orthographic projection of the anode pattern included in the blue sub-pixel B on the substrate;

[0199] Another part of the orthographic projection of the third aperture 503 on the substrate is located between the orthographic projection of the anode pattern included in the blue sub-pixel B on the substrate and the orthographic projection of the anode pattern 70 included in the second green sub-pixel G2 on the substrate; the anode pattern included in the blue sub-pixel B and the anode pattern included in the second green sub-pixel G2 are located in two adjacent rows.

[0200] Specifically, the pore 50 includes a third pore 503. Exemplarily, a portion of the orthographic projection of the third pore 503 on the substrate is located within the orthographic projection of the anode pattern 70 included in the blue sub-pixel B on the substrate, and another portion of the orthographic projection of the third pore 503 on the substrate does not overlap with the orthographic projection of the anode pattern 70 included in the blue sub-pixel B on the substrate. Exemplarily, the proportion of this portion is less than 1 / 3 of the entire third pore 503. Exemplarily, the proportion of this portion is approximately 1 / 4 of the entire third pore 503. Exemplarily, the third pore 503 belongs to the blue sub-pixel B.

[0201] Illustratively, another portion of the orthographic projection of the third aperture 503 on the substrate is located between the orthographic projection of the anode pattern 70 included in the blue sub-pixel B and the orthographic projection of the anode pattern 70 included in the second green sub-pixel G2 on the substrate. Illustratively, the anode pattern 70 included in the second green sub-pixel G2 is located in a next row adjacent to the anode pattern 70 included in the blue sub-pixel B. Illustratively, the anode pattern 70 included in the blue sub-pixel B and the anode pattern 70 included in the second green sub-pixel G2 are arranged along a fifth direction, and the fifth direction intersects both the first direction and the second direction.

[0202] In some embodiments, an area of ​​a portion of an orthographic projection of the third pore on the substrate is less than 30% of an entire area of ​​the orthographic projection of the third pore on the substrate.

[0203] like Figures 16 to 19 As shown, in some embodiments, the plurality of sub-pixels are divided into a plurality of pixel units, each pixel unit including a red sub-pixel R, a blue sub-pixel B, a first green sub-pixel G1 and a second green sub-pixel G2;

[0204] In the pixel units located in the same row along the first direction, the anode pattern 70 included in the red sub-pixel R, the anode pattern 70 included in the blue sub-pixel B, and the anode pattern 70 included in the first green sub-pixel G1 in each pixel unit are distributed in a row (e.g., marked X3), and the anode pattern 70 included in the second green sub-pixel G2 in each pixel unit are distributed in another row (e.g., marked X4);

[0205] The pore 50 includes a fourth pore 504, and a portion of an orthographic projection of the fourth pore 504 on the substrate is located inside an orthographic projection of the anode pattern included in the red sub-pixel R on the substrate;

[0206] Another part of the orthographic projection of the fourth aperture 504 on the substrate is located between the orthographic projection of the anode pattern included in the red sub-pixel R on the substrate and the orthographic projection of the anode pattern 70 included in the second green sub-pixel G2 on the substrate; the anode pattern included in the red sub-pixel R and the anode pattern included in the second green sub-pixel G2 are located in two adjacent rows.

[0207] Specifically, the aperture 50 includes a fourth aperture 504. Exemplarily, a portion of the orthographic projection of the fourth aperture 504 on the substrate is located within the orthographic projection of the anode pattern 70 included in the red sub-pixel R on the substrate, and another portion of the orthographic projection of the fourth aperture 504 on the substrate does not overlap with the orthographic projection of the anode pattern 70 included in the red sub-pixel R on the substrate. Exemplarily, the proportion of this portion is less than 3 / 4 of the entire fourth aperture 504. Exemplarily, the proportion of this portion is approximately 2 / 3 of the entire fourth aperture 504.

[0208] Illustratively, another portion of the orthographic projection of the fourth aperture 504 on the substrate is located between the orthographic projection of the anode pattern 70 included in the red sub-pixel R and the orthographic projection of the anode pattern 70 included in the second green sub-pixel G2 on the substrate. Illustratively, the anode pattern 70 included in the second green sub-pixel G2 is located in the next row adjacent to the anode pattern 70 included in the red sub-pixel R. Illustratively, the fourth aperture 504 belongs to the green sub-pixel G.

[0209] In some embodiments, an area of ​​a portion of an orthographic projection of the fourth aperture on the substrate is less than 75% of an entire area of ​​the orthographic projection of the fourth aperture on the substrate.

[0210] In the display substrate provided in the above embodiment, when including the first pore 501, the second pore 502, the third pore 503 and the fourth pore 504, the transmittance of the display substrate can be maximized, thereby providing good conditions for the sensor to collect light signals, effectively improving the speed and accuracy of fingerprint recognition.

[0211] like Figure 10 and Figure 25 As shown, in some embodiments, the main body 9120 includes a first main body portion 9120a and a second main body portion 9120b, wherein the first main body portion 9120a is close to the first end portion 9121, and the second main body portion 9120b is close to the second end portion 9122. In a plane parallel to the base and in a direction perpendicular to the second direction, a width L1 of the first main body portion 9120a is greater than a width L2 of the second main body portion 9120b.

[0212] The sub-pixel also includes a sub-pixel driving circuit, which includes a driving transistor (such as a third transistor T3) and a storage capacitor Cst. The first plate Cst1 of the storage capacitor Cst is coupled to the gate of the driving transistor, and the second plate Cst2 of the storage capacitor Cst is overlapped with the orthographic projection of the first main body part 9120a on the substrate. The second plate Cst2 of the storage capacitor Cst is coupled to the first main body part 9120a through a via arranged at the overlapping position.

[0213] Specifically, the above-mentioned arrangement is on a plane parallel to the substrate, and in a direction perpendicular to the second direction, the width L1 of the first main body part 9120a is greater than the width L2 of the second main body part 9120b, and the orthographic projection of the second plate Cst2 of the storage capacitor Cst on the substrate overlaps with the orthographic projection of the first main body part 9120a on the substrate, so that a larger overlapping area can be formed between the second plate Cst2 of the storage capacitor Cst and the first main body part 9120a. In this way, when the second plate Cst2 of the storage capacitor Cst is coupled to the first main body part 9120a through a via arranged at the overlapping position, the layout difficulty of the via can be reduced, thereby better improving the connection performance between the second plate Cst2 of the storage capacitor Cst and the first main body part 9120a.

[0214] like Figure 9 and Figure 24 As shown, in some embodiments, the orthographic projection of the second plate Cst2 of the storage capacitor Cst on the substrate does not overlap with the orthographic projection of the pore 50 on the substrate.

[0215] The above configuration ensures that the second electrode Cst2 of the storage capacitor Cst does not block the aperture 50 , thereby better ensuring the light transmittance of the aperture 50 .

[0216] like Figure 13 、 Figure 14 、 Figure 30 and Figure 31 As shown, in some embodiments, the sub-pixel also includes a power compensation graphic 971, at least a portion of which extends along the first direction, and the power compensation graphic 971 is respectively coupled to the main body 9120 and the first power line portion 911 in the sub-pixel adjacent to the sub-pixel to which it belongs along the first direction.

[0217] Exemplarily, the power compensation pattern 971 is formed as an integral structure with the main body 9120 and the first power line portion 911 .

[0218] The aforementioned sub-pixel configuration also includes the power compensation pattern 971, allowing the power signal line patterns 91 included in the sub-pixels in the same row to be electrically connected together via the power compensation pattern 971. This reduces the overall resistance of the power signal line patterns 91, thereby further improving the display uniformity of the display substrate. Furthermore, by sequentially electrically connecting the first power line portions 911 in the sub-pixels in the same column, all the power signal line patterns 91 included in the display substrate form a mesh structure, further improving the display uniformity of the display substrate.

[0219] like Figure 13 and Figure 30 As shown, in some embodiments, the sub-pixel further includes: a reset signal line pattern 95, a gate line pattern 92, and a light-emitting control signal line pattern 93 sequentially distributed along the second direction; at least a portion of the reset signal line pattern 95 extends along the first direction, at least a portion of the gate line pattern 92 extends along the first direction, and at least a portion of the light-emitting control signal line pattern 93 extends along the first direction; the orthographic projection of the power supply compensation pattern 971 on the substrate is located between the orthographic projection of the gate line pattern 92 on the substrate and the orthographic projection of the light-emitting control signal line pattern 93 on the substrate.

[0220] Specifically, the sub-pixel further includes: a reset signal line pattern 95, a gate line pattern 92, and a light-emission control signal line pattern 93 sequentially distributed along the second direction. The reset signal line is used to transmit a reset signal, the gate line pattern 92 is used to transmit a scan signal, and the light-emission control signal line pattern 93 is used to transmit a light-emission control signal.

[0221] At least a portion of the reset signal line pattern 95 extends along the first direction, and the reset signal line patterns 95 included in each sub-pixel located in the same row along the first direction are electrically connected in sequence to form an integrated structure. At least a portion of the gate line pattern 92 extends along the first direction, and the gate line patterns 92 included in each sub-pixel located in the same row along the first direction are electrically connected in sequence to form an integrated structure. At least a portion of the light-emitting control signal line pattern 93 extends along the first direction, and the light-emitting control signal line patterns 93 included in each sub-pixel located in the same row along the first direction are electrically connected in sequence to form an integrated structure.

[0222] The specific layout positions of the power compensation pattern 971 are varied. For example, the orthographic projection of the power compensation pattern 971 on the substrate does not overlap with the orthographic projection of the reset signal line pattern 95 on the substrate, the orthographic projection of the power compensation pattern 971 on the substrate does not overlap with the orthographic projection of the gate line pattern 92 on the substrate, and the orthographic projection of the power compensation pattern 971 on the substrate does not overlap with the orthographic projection of the light-emitting control signal line pattern 93 on the substrate.

[0223] Illustratively, the orthographic projection of the power compensation pattern 971 on the substrate is located between the orthographic projection of the gate line pattern 92 on the substrate and the orthographic projection of the light emitting control signal line pattern 93 on the substrate.

[0224] Exemplarily, along the second direction, the minimum distance between the orthographic projection of the power compensation pattern 971 on the substrate and the orthographic projection of the gate line pattern 92 on the substrate is greater than the minimum distance between the orthographic projection of the power compensation pattern 971 on the substrate and the orthographic projection of the light-emitting control signal line pattern 93 on the substrate.

[0225] Exemplarily, a minimum distance between an orthographic projection of the power compensation pattern 971 on the substrate and an orthographic projection of the light emitting control signal line pattern 93 on the substrate is greater than 5 μm.

[0226] The power compensation pattern 971 is arranged in the above manner so that there is a long distance between the power compensation pattern 971 and the reset signal line pattern 95, the gate line pattern 92 and the light-emitting control signal line pattern 93, thereby avoiding increasing the load of the reset signal line pattern 95, the gate line pattern 92 and the light-emitting control signal line pattern 93.

[0227] like Figure 5 、 Figure 13 、 Figure 26 and Figure 30 As shown, in some embodiments, the sub-pixel also includes a light-emitting control signal line pattern 93, at least part of which extends along the first direction; the light-emitting control signal line pattern 93 includes a first light-emitting control part 931 and a second light-emitting control part 932, the orthographic projection of the first light-emitting control part 931 on the substrate respectively overlaps with the orthographic projection of the main body 9120 on the substrate, the orthographic projection of the pore 50 on the substrate, and the orthographic projection of the first power line part 911 on the substrate; along the second direction, the orthographic projection of the second light-emitting control part 932 on the substrate is opposite to the orthographic projection of the power compensation pattern 971 on the substrate; on a plane parallel to the substrate and in a direction perpendicular to the first direction, the width L4 of the second light-emitting control part 932 is smaller than the width L3 of the first light-emitting control part 931.

[0228] Specifically, the light emission control signal line pattern 93 includes a first light emission control portion 931 and a second light emission control portion 932 coupled to each other. Exemplarily, the first light emission control portion 931 and the second light emission control portion 932 are formed as an integral structure.

[0229] The above-mentioned setting is along the second direction, and the orthographic projection of the second light-emitting control part 932 on the substrate is opposite to the orthographic projection of the power compensation pattern 971 on the substrate. On a plane parallel to the substrate and in a direction perpendicular to the first direction, the width L4 of the second light-emitting control part 932 is smaller than the width L3 of the first light-emitting control part 931, so that along the second direction, the distance between the power compensation pattern 971 and the second light-emitting control part 932 is farther, thereby better avoiding increasing the load of the light-emitting control signal line pattern 93.

[0230] The specific structure of the power compensation pattern 971 is various, such as Figure 14 and Figure 15 As shown, in some embodiments, the power compensation pattern 971 is a strip structure extending along the first direction.

[0231] like Figure 31 and Figure 32 As shown, in some embodiments, the power compensation graphic 971 includes a first part 9711, a second part 9712 and a third part 9713; the first part 9711 is coupled to the first power line part 911 and one end of the third part 9713 respectively, the second part 9712 is coupled to the main body 9120 and the other end of the third part 9713 respectively, and the third part 9713 extends along the first direction, and the extension direction of the first part 9711 and the extension direction of the second part 9712 both intersect with the first direction and both intersect with the second direction.

[0232] Illustratively, the third part 9713 extends along the first direction, the angle between the extension direction of the first part 9711 and the first direction is 45 degrees, the angle between the extension direction of the second part 9712 and the first direction is 45 degrees, and the extension direction of the first part 9711 is perpendicular to the extension direction of the second part 9712.

[0233] The above-mentioned setting of the power compensation pattern 971 includes the first part 9711, the second part 9712 and the third part 9713, so that the power compensation pattern 971 has a larger area, which is more conducive to reducing the overall resistance of the power signal line pattern 91 and improving the display uniformity of the display substrate.

[0234] In addition, the power compensation graphic 971 is configured to include the first part 9711, the second part 9712 and the third part 9713, so that the power compensation graphic 971 can better avoid other conductive structures arranged on the same layer as it, thereby better reducing the layout difficulty of the power compensation graphic 971 and improving the reliability of the display substrate.

[0235] like Figure 15 and Figure 32 As shown, in some embodiments, on a plane parallel to the substrate and in a direction perpendicular to the first direction, the end D of the power compensation pattern 971 directly coupled to the first power line portion 911 has a first width, and along a direction close to the first power line portion 911 (such as Figure 15 and Figure 32 The first width gradually increases.

[0236] The above setting method not only ensures better connection performance between the power compensation pattern 971 and the first power line portion 911, but also avoids the static electricity risk caused by the right-angle structure formed at the connection between the power compensation pattern 971 and the first power line portion 911.

[0237] like Figure 18 and Figure 33 As shown, in some embodiments, the sub-pixel further includes a light-emitting element, and the light-emitting element includes an anode pattern 70, and the orthographic projection of the anode pattern 70 on the substrate overlaps with the orthographic projection of the power compensation pattern 971 on the substrate.

[0238] Specifically, the above-mentioned arrangement of overlapping the orthographic projection of the anode pattern 70 on the substrate and the orthographic projection of the power compensation pattern 971 on the substrate helps to improve the flatness of the anode pattern and improve the color shift phenomenon of the display substrate.

[0239] like Figure 2 、 Figure 9 and Figure 24 As shown, in some embodiments, the sub-pixel further includes: a light-emitting element, an initialization signal line pattern 94, a reset signal line pattern 95, a gate line pattern 92, and a light-emitting control signal line pattern 93; at least a portion of the initialization signal line pattern 94, at least a portion of the reset signal line pattern 95, at least a portion of the gate line pattern 92, and at least a portion of the light-emitting control signal line pattern 93 all extend along the first direction;

[0240] The sub-pixel further includes:

[0241] A first data line pattern 981 and a second data line pattern 982 are arranged opposite to each other along the first direction, and at least a portion of the first data line pattern 981 and at least a portion of the second data line pattern 982 extend along the second direction;

[0242] A sub-pixel driving circuit, comprising: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and a storage capacitor Cst;

[0243] The gate of the third transistor T3 is coupled to the second electrode of the first transistor T1, the first electrode of the third transistor T3 is coupled to the second electrode of the fifth transistor T5, and the second electrode of the third transistor T3 is coupled to the first electrode of the first transistor T1;

[0244] The gate of the first transistor T1 is coupled to the gate line pattern 92;

[0245] The gate of the second transistor T2 is coupled to the reset signal line pattern 95, the first electrode of the second transistor T2 is coupled to the initialization signal line pattern 94, and the second electrode of the second transistor T2 is coupled to the gate of the third transistor T3;

[0246] The gate of the fourth transistor T4 is coupled to the gate line pattern 92; the first electrode of the fourth transistor T4 is coupled to the first data line pattern 981 or the second data line pattern 982; the second electrode of the fourth transistor T4 is coupled to the first electrode of the third transistor T3;

[0247] The gate of the fifth transistor T5 is coupled to the light emitting control signal line pattern 93, and the first electrode of the fifth transistor T5 is coupled to the power signal line pattern;

[0248] The gate of the sixth transistor T6 is coupled to the light emitting control signal line pattern 93 , the first electrode of the sixth transistor T6 is coupled to the second electrode of the third transistor T3 , and the second electrode of the sixth transistor T6 is coupled to the light emitting element;

[0249] A gate of the seventh transistor T7 is coupled to a reset signal line pattern 95' in a next sub-pixel adjacent along the second direction, a first electrode of the seventh transistor T7 is coupled to the initialization signal line pattern 94' in a next sub-pixel adjacent along the second direction, and a second electrode of the seventh transistor T7 is coupled to the light-emitting element;

[0250] The first plate Cst1 of the storage capacitor Cst is multiplexed as the gate of the third transistor T3 , and the second plate Cst2 of the storage capacitor Cst is coupled to the power signal line pattern.

[0251] Specifically, each sub-pixel further includes a sub-pixel driving circuit. Taking one sub-pixel driving circuit as an example, the sub-pixel driving circuit includes seven thin-film transistors and one capacitor. Each transistor included in the sub-pixel driving circuit is a P-type transistor, the first electrode of each transistor includes a source electrode, and the second electrode of each transistor includes a drain electrode. It should be noted that the power signal transmitted on the power signal line pattern 91 is a high-potential DC signal. The signal transmitted on the negative power signal line VSS is a low-potential DC signal. The initialization signal transmitted on the initialization signal line pattern 94 is a low-potential DC signal.

[0252] The first transistor T1 has a dual-gate structure, the gate 201g of the first transistor T1 is coupled to the gate line pattern 92, the source S1 of the first transistor T1 is coupled to the drain D3 of the third transistor T3 (i.e., the driving transistor), and the drain D1 of the first transistor T1 is coupled to the gate 203g of the third transistor T3.

[0253] The second transistor T2 has a dual-gate structure, a gate 202g of the second transistor T2 is coupled to the reset signal line pattern 95, a source S2 of the second transistor T2 is coupled to the initialization signal line pattern 94, and a drain D2 of the second transistor T2 is coupled to the gate 203g of the third transistor T3.

[0254] The gate 204g of the fourth transistor T4 is coupled to the gate line pattern 92, the source S4 of the fourth transistor T4 is coupled to the first data line pattern 981 or the second data line pattern 982, and the drain D4 of the fourth transistor T4 is coupled to the source S3 of the third transistor T3.

[0255] The gate 205g of the fifth transistor T5 is coupled to the light emitting control signal line pattern 93, the source S5 of the fifth transistor T5 is coupled to the power signal line pattern 91, and the drain D5 of the fifth transistor T5 is coupled to the source S3 of the third transistor T3.

[0256] The gate 206g of the sixth transistor T6 is coupled to the light emitting control signal line pattern 93, the source S6 of the sixth transistor T6 is coupled to the drain D3 of the third transistor T3, and the drain D6 of the sixth transistor T6 is coupled to the anode of the light emitting element EL.

[0257] The gate 207g of the seventh transistor T7 is coupled to the reset signal line pattern 95' in the next sub-pixel adjacent along the second direction, the drain D7 of the seventh transistor T7 is coupled to the anode of the corresponding light-emitting element EL, and the source S7 of the seventh transistor T7 is coupled to the initialization signal line pattern 94' in the next sub-pixel adjacent along the second direction.

[0258] The first plate Cst1 of the storage capacitor Cst is multiplexed as the gate 203 g of the third transistor T3 , and the second plate Cst2 of the storage capacitor Cst is coupled to the power signal line pattern 91 .

[0259] like Figures 16 to 19 As shown, in some embodiments, the sub-pixel driving circuit further includes a sixth transistor T6, and a first electrode of the sixth transistor T6 is connected to the second electrode of the driving transistor (ie, the third transistor);

[0260] The sub-pixel further includes a third conductive connection portion 963, a fourth conductive connection portion 964, and a light-emitting element stacked in sequence in a direction away from the substrate; the light-emitting element includes an anode pattern 70;

[0261] An orthographic projection of the second electrode of the sixth transistor T6 on the substrate and an orthographic projection of the third conductive connection portion 963 on the substrate have a third overlapping area, and the second electrode of the sixth transistor T6 and the third conductive connection portion 963 are coupled in the third overlapping area;

[0262] The orthographic projection of the third conductive connection portion 963 on the substrate and the orthographic projection of the fourth conductive connection portion 964 on the substrate have a fourth overlapping area, and the third conductive connection portion 963 and the fourth conductive connection portion 964 are coupled in the fourth overlapping area;

[0263] The orthographic projection of the fourth conductive connection portion 964 on the substrate and the orthographic projection of the anode pattern on the substrate have a fifth overlapping region, and the fourth conductive connection portion 964 is coupled to the anode pattern in the fifth overlapping region.

[0264] Exemplarily, the sub-pixel driving circuit also includes a sixth transistor T6, the gate of the sixth transistor T6 is coupled to the light-emitting control signal line pattern 93, the first electrode of the sixth transistor T6 is coupled to the second electrode of the driving transistor, the orthographic projection of the second electrode of the sixth transistor T6 on the substrate and the orthographic projection of the third conductive connection portion 963 on the substrate have a third overlapping area, and the second electrode of the sixth transistor T6 and the third conductive connection portion 963 are coupled through a first via 61 set in the third overlapping area.

[0265] The orthographic projection of the third conductive connection portion 963 on the substrate and the orthographic projection of the fourth conductive connection portion 964 on the substrate have a fourth overlapping area, and the third conductive connection portion 963 and the fourth conductive connection portion 964 are coupled through a second via 62 provided in the fourth overlapping area.

[0266] The orthographic projection of the fourth conductive connection portion 964 on the substrate and the orthographic projection of the anode pattern 70 on the substrate have a fifth overlapping area, and the fourth conductive connection portion 964 and the anode pattern are coupled through a third via 63 disposed in the fifth overlapping area.

[0267] During the light emitting period, the sixth transistor T6 transmits the driving signal outputted from the second electrode of the driving transistor to the anode pattern 70 of the light emitting element through the third conductive connection portion 963 and the fourth conductive connection portion 964 in sequence.

[0268] In the display substrate provided in the above embodiment, the second electrode of the sixth transistor T6 is provided and coupled to the anode pattern through the third conductive connection portion 963 and the fourth conductive connection portion 964 in sequence, thereby better ensuring the coupling performance between the second electrode of the sixth transistor T6 and the anode pattern.

[0269] It should be noted that in the drawings provided in the present disclosure, the small squares with cross lines represent vias. Figure 4 、 Figure 9 and Figure 13 In the embodiment, the active layer, the first gate metal layer, the second gate metal layer and the second source and drain metal layer are identical. Figure 5 Shown Figure 4 、 Figure 9 and Figure 13 The active layer and the first gate metal layer, Figure 6 Shown Figure 4 、 Figure 9 and Figure 13 a second gate metal layer. Figure 8 Shown Figure 4 、 Figure 9 and Figure 13 a second source / drain metal layer. Figure 20 Shown Figure 16 Active layer layout in . Figure 21 Shown Figure 16 The first gate metal layer in. Figure 22 Shown Figure 16 The second gate metal layer in. Figure 23 Shown Figure 16 The first source and drain metal layer in.

[0270] Figure 24 、 Figure 30Having the same active layer, first gate metal layer, second gate metal layer and second source and drain metal layer, that is Figure 26 Shown Figure 24 、 Figure 30 The active layer and the first gate metal layer, Figure 28 Shown Figure 24 、 Figure 30 The second source and drain metal layer. It is worth noting that Figure 24 、 Figure 30 The layout of the second gate metal layer in Figure 6 Basically the same. Figure 35 Shown Figure 33 Active layer layout in . Figure 36 Shown Figure 33 Layout of the first source and drain metal layer in. Figure 37 Shown Figure 33 The layout of the second source and drain metal layer and the anode layer.

[0271] An embodiment of the present disclosure further provides a display device, comprising the display substrate provided by the above embodiment.

[0272] In the display substrate provided in the above embodiment, by configuring the power signal line pattern 91 to include the first power line portion 911 and the second power line portion 912, a gap 50 is formed between the first power line portion 911 and the second power line portion 912, thereby reducing the proportion of opaque areas in the display substrate and improving the light transmittance of the display substrate. Therefore, when the display substrate provided in the above embodiment is compatible with optical fingerprint recognition technology, it can provide excellent conditions for the sensor to collect optical signals, thereby effectively improving the speed and accuracy of fingerprint recognition.

[0273] The display device provided by the embodiment of the present disclosure also has the above-mentioned beneficial effects when it includes the above-mentioned display substrate, which will not be described in detail here.

[0274] It should be noted that the display device may be any product or component with a display function, such as a television, a monitor, a digital photo frame, a mobile phone, or a tablet computer.

[0275] The present disclosure also provides a method for manufacturing a display substrate, which is used to manufacture the display substrate provided in the above embodiment. The above manufacturing method includes: manufacturing a plurality of sub-pixels distributed in an array on a substrate; the steps of manufacturing the sub-pixels specifically include:

[0276] A power signal line pattern is produced, wherein the power signal line pattern includes a first power line portion and a second power line portion; at least a portion of the first power line portion extends along a second direction; the second power line portion includes a main body portion, a first end portion, and a second end portion, the main body portion and the first power line portion are arranged along the first direction, and the main body portion and the first power line portion are spaced apart, the first direction intersects with the second direction, the first end portion and the second end portion are arranged opposite to each other along the second direction, the first end portion is respectively coupled to one end of the main body portion and the first power line portion, the second end portion is respectively coupled to the other end of the main body portion and the first power line portion, and a gap is provided between the first power line portion and the second power line portion.

[0277] In the display substrate manufactured using the manufacturing method provided by the embodiment of the present invention, by configuring the power signal line pattern 91 to include the first power line portion 911 and the second power line portion 912, a gap 50 is formed between the first power line portion 911 and the second power line portion 912, thereby reducing the proportion of opaque areas in the display substrate and improving the light transmittance of the display substrate. Therefore, when the display substrate manufactured using the manufacturing method provided by the embodiment of the present invention is compatible with optical fingerprint recognition technology, it can provide excellent conditions for the sensor to collect optical signals, thereby effectively improving the speed and accuracy of fingerprint recognition.

[0278] It should be noted that the various embodiments in this specification are described in a progressive manner. Similar parts between the various embodiments can be referred to in conjunction with each other. Each embodiment focuses on the differences from other embodiments. In particular, the method embodiments are described briefly because they are generally similar to the product embodiments. For relevant parts, refer to the description of the product embodiments.

[0279] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect", "couple" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0280] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, it can be “directly on” or “under” the other element or intervening elements may be present.

[0281] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0282] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display substrate, comprising: a substrate and a plurality of sub-pixels arrayed on the substrate; The sub-pixel includes: A power signal line pattern, the power signal line pattern comprising a first power line portion and a second power line portion; at least a portion of the first power line portion extends along a second direction; the second power line portion comprises a main body, a first end portion, and a second end portion, the main body portion and the first power line portion being spaced apart along the first direction, the first direction intersecting the second direction, the first end portion and the second end portion being oppositely disposed along the second direction, the first end portion being respectively coupled to one end of the main body portion and the first power line portion, the second end portion being respectively coupled to the other end of the main body portion and the first power line portion, and a gap being defined between the first power line portion and the second power line portion; The sub-pixel further includes a sub-pixel driving circuit, the sub-pixel driving circuit includes a storage capacitor, the main body includes a first main portion and a second main portion, the first main portion is close to the first end, the second main portion is close to the second end, the orthographic projection of the second plate of the storage capacitor on the substrate overlaps with the orthographic projection of the first main portion on the substrate, and the second plate of the storage capacitor is coupled to the first main portion through a via provided at the overlapping portion; An orthographic projection of the pore on the substrate does not overlap with an orthographic projection of the second electrode plate of the storage capacitor on the substrate.

2. The display substrate according to claim 1, wherein The plurality of sub-pixels are divided into a plurality of rows of sub-pixels, each row of sub-pixels includes a plurality of sub-pixels sequentially arranged along a first direction; the sub-pixels further include: a first data line pattern and a second data line pattern arranged opposite to each other along a first direction, wherein at least a portion of the first data line pattern and at least a portion of the second data line pattern both extend along the second direction; The orthographic projection of the first data line pattern on the substrate overlaps with the orthographic projection of the first power line portion in the sub-pixel adjacent to the sub-pixel to which it belongs along the first direction on the substrate, and the orthographic projection of the second data line pattern on the substrate overlaps with the orthographic projection of the main body on the substrate.

3. The display substrate according to claim 2, wherein: The orthographic projection of the first data line pattern on the substrate does not overlap with the orthographic projection of the pore on the substrate; and / or the orthographic projection of the second data line pattern on the substrate does not overlap with the orthographic projection of the pore on the substrate.

4. The display substrate according to claim 1, wherein: The sub-pixel further includes a light-emitting control signal line pattern, at least a portion of which extends along the first direction; an orthographic projection of the light-emitting control signal line pattern on the substrate partially overlaps with an orthographic projection of the pore on the substrate.

5. The display substrate according to claim 1, wherein The first power line portion includes a second sub-portion and a first sub-portion for enclosing the aperture, and in a plane parallel to the substrate and along a direction perpendicular to the second direction, a width of the first sub-portion is smaller than a width of the second sub-portion. The display substrate according to claim 1 , wherein: The sub-pixel further includes a light-emitting element, the light-emitting element includes an anode pattern, and an orthographic projection of the anode pattern on the substrate does not overlap with an orthographic projection of the aperture on the substrate.

7. The display substrate according to claim 6, wherein: The orthographic projection of the pore on the substrate is located between the orthographic projection of the first anode pattern on the substrate and the orthographic projection of the second anode pattern on the substrate; the sub-pixel to which the pore belongs includes the first anode pattern, and the next sub-pixel adjacent to the sub-pixel along the first direction includes the second anode pattern.

8. The display substrate according to claim 7, wherein: The plurality of sub-pixels are divided into a plurality of pixel units, each pixel unit including one red sub-pixel, one blue sub-pixel and two green sub-pixels; In pixel units located in the same row along the first direction, the anode patterns included in the red sub-pixels in each pixel unit and the anode patterns included in the blue sub-pixels in each pixel unit are distributed in one row, and the anode patterns included in the green sub-pixels in each pixel unit are distributed in another row; In the pixel units located in the same row along the first direction, the anode patterns included in the red sub-pixels, the anode patterns included in the blue sub-pixels, and the anode patterns included in the green sub-pixels are alternately distributed in sequence; In pixel units located in the same row along the first direction, one of adjacent red sub-pixels and green sub-pixels includes the first anode pattern, and the other of adjacent red sub-pixels and green sub-pixels includes the second anode pattern; In pixel units located in the same row along the first direction, one of adjacent blue sub-pixels and green sub-pixels includes the first anode pattern, and the other of adjacent blue sub-pixels and green sub-pixels includes the second anode pattern.

9. The display substrate according to claim 1, wherein: The sub-pixel further includes a light-emitting element, which includes an anode pattern. A portion of the orthographic projection of the anode pattern on the substrate partially overlaps with a portion of the orthographic projection of the aperture on the substrate.

10. The display substrate according to claim 1, wherein On a plane parallel to the base and in a direction perpendicular to the second direction, the width of the first main body portion is greater than the width of the second main body portion; The sub-pixel driving circuit includes a driving transistor, and the first plate of the storage capacitor is coupled to the gate of the driving transistor.

11. The display substrate according to claim 10, wherein: The orthographic projection of the second electrode plate of the storage capacitor on the substrate does not overlap with the orthographic projection of the pore on the substrate.

12. The display substrate according to claim 1, wherein The sub-pixel further includes a power compensation pattern, at least a portion of which extends along the first direction. The power compensation pattern is respectively coupled to the main body and the first power line portion of the sub-pixel adjacent to the sub-pixel along the first direction.

13. The display substrate according to claim 12, wherein: The sub-pixel further includes: a reset signal line pattern, a gate line pattern, and a light-emitting control signal line pattern sequentially distributed along the second direction; at least a portion of the reset signal line pattern extends along the first direction, at least a portion of the gate line pattern extends along the first direction, and at least a portion of the light-emitting control signal line pattern extends along the first direction; The orthographic projection of the power compensation pattern on the substrate is located between the orthographic projection of the gate line pattern on the substrate and the orthographic projection of the light emitting control signal line pattern on the substrate.

14. The display substrate according to claim 12, wherein: The sub-pixel further includes a light-emission control signal line pattern, at least a portion of which extends along the first direction; the light-emission control signal line pattern includes a first light-emission control portion and a second light-emission control portion, an orthographic projection of the first light-emission control portion on the substrate respectively overlapping with an orthographic projection of the main portion on the substrate, an orthographic projection of the aperture on the substrate, and an orthographic projection of the first power line portion on the substrate; Along the second direction, the orthographic projection of the second light emitting control portion on the substrate is opposite to the orthographic projection of the power compensation pattern on the substrate; On a plane parallel to the substrate, in a direction perpendicular to the first direction, a width of the second light emission control portion is smaller than a width of the first light emission control portion.

15. The display substrate according to claim 12, wherein: The power compensation pattern includes a first part, a second part and a third part; the first part is coupled to the first power line part and one end of the third part respectively, the second part is coupled to the main body and the other end of the third part respectively, and the third part extends along the first direction, and the extension direction of the first part and the extension direction of the second part both intersect with the first direction and both intersect with the second direction.

16. The display substrate according to claim 12, wherein: On a plane parallel to the substrate and in a direction perpendicular to the first direction, an end of the power compensation pattern coupled to the first power line portion has a first width, and the first width gradually increases in a direction approaching the first power line portion.

17. The display substrate according to claim 12, wherein: The sub-pixel further includes a light-emitting element, the light-emitting element includes an anode pattern, and an orthographic projection of the anode pattern on the substrate overlaps with an orthographic projection of the power compensation pattern on the substrate.

18. The display substrate according to claim 1, wherein The sub-pixel further includes: a light-emitting element, an initialization signal line pattern, a reset signal line pattern, a gate line pattern, and a light-emitting control signal line pattern; at least a portion of the initialization signal line pattern, at least a portion of the reset signal line pattern, at least a portion of the gate line pattern, and at least a portion of the light-emitting control signal line pattern all extend along the first direction; The sub-pixel further includes: a first data line pattern and a second data line pattern arranged opposite to each other along a first direction, wherein at least a portion of the first data line pattern and at least a portion of the second data line pattern both extend along a second direction; The sub-pixel driving circuit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor and a storage capacitor; The gate of the third transistor is coupled to the second electrode of the first transistor, the first electrode of the third transistor is coupled to the second electrode of the fifth transistor, and the second electrode of the third transistor is coupled to the first electrode of the first transistor; The gate of the first transistor is coupled to the gate line pattern; The gate of the second transistor is coupled to the reset signal line pattern, the first electrode of the second transistor is coupled to the initialization signal line pattern, and the second electrode of the second transistor is coupled to the gate of the third transistor; The gate of the fourth transistor is coupled to the gate line pattern; the first electrode of the fourth transistor is coupled to the first data line pattern or the second data line pattern, and the second electrode of the fourth transistor is coupled to the first electrode of the third transistor; The gate of the fifth transistor is coupled to the light emitting control signal line pattern, and the first electrode of the fifth transistor is coupled to the power signal line pattern; The gate of the sixth transistor is coupled to the light emitting control signal line pattern, the first electrode of the sixth transistor is coupled to the second electrode of the third transistor, and the second electrode of the sixth transistor is coupled to the light emitting element; The gate of the seventh transistor is coupled to the reset signal line pattern in the next sub-pixel adjacent to the second direction, the first electrode of the seventh transistor is coupled to the initialization signal line pattern in the next sub-pixel adjacent to the second direction, and the second electrode of the seventh transistor is coupled to the light-emitting element; The first plate of the storage capacitor is reused as the gate of the third transistor, and the second plate of the storage capacitor is coupled to the power signal line pattern.

19. A display device comprising the display substrate according to any one of claims 1 to 18.

20. A method for manufacturing a display substrate, comprising: Fabricating a plurality of sub-pixels distributed in an array on a substrate; The steps of manufacturing the sub-pixel specifically include: A power signal line pattern is produced, the power signal line pattern comprising a first power line portion and a second power line portion; at least a portion of the first power line portion extends along a second direction; the second power line portion comprises a main body, a first end, and a second end; the main body and the first power line portion are arranged along the first direction, and the main body and the first power line portion are spaced apart; the first direction intersects the second direction; the first end and the second end are arranged opposite each other along the second direction; the first end is respectively coupled to one end of the main body and the first power line portion; the second end is respectively coupled to the other end of the main body and the first power line portion; and a gap is defined between the first power line portion and the second power line portion; The sub-pixel further includes a sub-pixel driving circuit, the sub-pixel driving circuit includes a storage capacitor, the main body includes a first main portion and a second main portion, the first main portion is close to the first end, the second main portion is close to the second end, the orthographic projection of the second plate of the storage capacitor on the substrate overlaps with the orthographic projection of the first main portion on the substrate, and the second plate of the storage capacitor is coupled to the first main portion through a via provided at the overlapping portion; An orthographic projection of the pore on the substrate does not overlap with an orthographic projection of the second electrode plate of the storage capacitor on the substrate.

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