Flash memory system and flash memory device

Abstract

The present invention discloses a flash memory system and a flash memory device thereof. The flash memory device includes a NAND flash memory and a control circuit. The NAND flash memory includes a cache, a page buffer, and a NAND flash memory array. The NAND flash memory array includes multiple pages, each of which includes multiple sub-pages, each of which has a sub-page length. The page buffer is composed of multiple sub-page buffers, each of which corresponds to different pages in the NAND flash memory array. The cache is composed of multiple sub-buffer areas, each of which corresponds to different pages in the NAND flash memory array. The control circuit is coupled to the NAND flash memory and performs access operations in units of one sub-page.

Description

Technical Field

[0001] The present invention relates to a memory system, and more particularly to a flash memory system and a flash memory device thereof. Background Art

[0002] Flash memory can be mainly divided into two types: NAND flash memory and NOR flash memory. NOR flash memory has the characteristics of being able to read data quickly and randomly, and operates in memory mapping mode to support Direct Memory Access (DMA) operations and eXecute-In-Place (XIP) functions, which are usually required in embedded applications. However, the known NAND flash memory has a large capacity and performs access operations in units of pages, so it requires a long sensing cycle, resulting in excessively high page access latency. In order to improve execution efficiency, the access operations of general NAND flash memory are usually divided into multiple stages. Therefore, NAND flash memory is generally not suitable for random access operations such as in-place execution. However, with the increasing demand for embedded applications, the capacity of traditional NOR flash memory is no longer sufficient, so how to provide a new memory architecture to meet the needs of embedded applications is an important issue. Summary of the Invention

[0003] The present invention provides a flash memory system, which enables NAND flash memory to be suitable for performing random access operations to meet the increasing demands of embedded applications.

[0004] The flash memory device of the present invention includes a NAND flash memory and a control circuit. The NAND flash memory includes a cache, a page buffer, and a NAND flash memory array. The NAND flash memory array includes multiple pages, each of which includes multiple subpages, each of which has a subpage length. The page buffer is composed of multiple subpage buffers, each of which corresponds to different pages in the NAND flash memory array. The cache is composed of multiple subcaches, each of which corresponds to different pages in the NAND flash memory array. The control circuit is coupled to the NAND flash memory and performs access operations in units of one subpage.

[0005] In one embodiment of the present invention, the control circuit pre-fetches data from adjacent pages of a currently read page according to a host request, and stores the pre-fetched data in a page buffer or a cache.

[0006] In one embodiment of the present invention, the data of each sub-page includes a sub-page error correction code, and the control circuit performs error correction on the data of the corresponding sub-page according to the sub-page error correction code.

[0007] In one embodiment of the present invention, the sub-page error correction code has a 1-bit correction capability.

[0008] In one embodiment of the present invention, when the control circuit fails to correct an error on the data of a corresponding sub-page based on a sub-page error correction code, the control circuit rereads the data of the page including the corresponding sub-page through the page buffer, stores the data of the page in a cache, and performs error correction on all data of the page, including the data of the corresponding sub-page, based on the data of the page and its page error correction code.

[0009] In one embodiment of the present invention, the page error correction code has multi-bit correction capability.

[0010] In one embodiment of the present invention, the cache is a multi-level cache, and the multi-level cache performs a cache operation in units of a sub-page.

[0011] In one embodiment of the present invention, the NAND flash memory includes a plurality of memory planes, each memory plane corresponding to a different cache.

[0012] In one embodiment of the present invention, the NAND flash memory includes a plurality of cache memories, and the control circuit performs a cache operation on the plurality of cache memories, selectively moving data between the plurality of cache memories in units of a sub-page.

[0013] In one embodiment of the present invention, the control circuit includes a sub-page selector coupled to the NAND flash memory and controlled by address information in a command output by the host to selectively move data between the page buffer and the cache in units of a sub-page.

[0014] In one embodiment of the present invention, the NAND flash memory includes a tag table, which records sub-page address information of the page buffer and the cache.

[0015] In one embodiment of the present invention, the control circuit reads data of the executed program from multiple sub-pages of the NAND flash memory array, stores the read sub-page data in the corresponding sub-page buffer, selects the sub-page data to be removed from the cache according to a default data replacement algorithm, and moves the read sub-page data stored in the sub-page buffer to the cache.

[0016] In one embodiment of the present invention, when the data of the executed program exists in the cache, the control circuit reads the data from the cache and transmits the data to the host.

[0017] In one embodiment of the present invention, when the data of the executed program does not exist in the cache but exists in the page buffer, the control circuit selects the sub-page data to be removed from the cache according to the default data replacement algorithm and moves the data stored in the page buffer to the cache.

[0018] The present invention also provides a flash memory system, which includes a host and a flash memory device. The host can be used to obtain data. The flash memory device is coupled to the host and is accessed by the host. The flash memory device includes a NAND flash memory and a control circuit. The NAND flash memory includes a cache, a page buffer and a NAND flash memory array. The NAND flash memory array includes multiple pages, each of which includes multiple sub-pages, and each sub-page has a sub-page length. The page buffer is composed of multiple sub-page buffers, and the multiple sub-page buffers correspond to different pages in the NAND flash memory array. The cache is composed of multiple sub-buffer areas, and the multiple sub-buffer areas correspond to different pages in the NAND flash memory array. The control circuit is coupled to the host and the NAND flash memory, and performs access operations in units of one sub-page.

[0019] Based on the above, each page of the NAND flash memory array of the embodiment of the present invention includes multiple sub-pages, each sub-page having a sub-page length. Each sub-page of the page buffer can correspond to a different page in the NAND flash memory array, and each sub-page of the cache can correspond to a different page in the NAND flash memory array. The control circuit can manage the sub-pages of the page buffer and the cache based on a tag table. For example, the tag table can be used to determine the location of the sub-page data corresponding to the access request in the page buffer or cache. If the sub-page data corresponding to the access request is in the page buffer or cache, it can be directly provided to the control circuit without having to read the data from the NAND flash memory array, thereby shortening the access time. In this way, the control circuit can perform access operations in units of one sub-page, making the NAND flash memory suitable for performing random access operations to meet the increasing demands of embedded applications.

[0020] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 is a schematic diagram of a flash memory system according to an embodiment of the present invention.

[0022] Figure 2 Schematic diagram of a NAND flash memory according to an embodiment of the present invention.

[0023] Figure 3 The present invention is a flowchart of a cache operation of a flash memory system according to an embodiment of the present invention.

[0024] Figure 4FIG. 4 is a schematic diagram of a NAND flash memory according to another embodiment of the present invention.

[0025] Figure 5 FIG. 4 is a schematic diagram of a NAND flash memory according to another embodiment of the present invention.

[0026] Figure 6 FIG. 4 is a schematic diagram of a NAND flash memory according to another embodiment of the present invention.

[0027]

Explanation of symbols

[0028] 102: Host

[0029] 104: Flash memory device

[0030] 106: Control circuit

[0031] 108: NAND Flash Memory

[0032] 110, 602, 608: NAND gate flash memory array

[0033] 112, 604, 610: Page buffer

[0034] 114, 606, 612: Cache

[0035] 120: Label table

[0036] 402: Subpage selector

[0037] 404: Input and output ports

[0038] 502: Cache

[0039] P0~Pm:page

[0040] Cnk, Cnk0~Cnk3: sub-pages

[0041] S302 to S318: Steps of cache operation of flash memory system DETAILED DESCRIPTION

[0042] Figure 1 This is a schematic diagram of a flash memory system according to an embodiment of the present invention. Figure 1 The flash memory system includes a host 102 and a flash memory device 104 . The flash memory device 104 may include a control circuit 106 and a NAND flash memory 108 . The control circuit 106 is coupled to the host 102 and the NAND flash memory 108 . The NAND flash memory 108 includes a NAND flash array 110 , a page buffer 112 , and a cache 114 .

[0043] The flash memory device 104 can be controlled by the host 102 to access data. For example, when the host 102 executes a program, the host 102 can control the control circuit 106 of the flash memory device 104 to access the program code required to execute the program, but the present invention is not limited thereto. Figure 2 As shown, it includes multiple pages P0 to Pm. Figure 2 Taking page Pn as an example, each page P0-Pm may include multiple sub-pages Cnk, where n and m are positive integers. Each sub-page Cnk has a sub-page length, which may be, for example, 512 bytes, 256 bytes, or 128 bytes, but is not limited thereto. The control circuit 106 may perform access operations in units of one sub-page. Since the sub-page length of a sub-page is small, the buffered data in the page buffer 112 and the cached data in the cache 114 may include multiple sub-pages from different pages of the NAND flash memory 108, wherein the sub-pages stored in each sub-page buffer area in the page buffer 112 correspond to different pages of the NAND flash memory array at the same sub-page offset (sub-page offset), and the sub-pages stored in each sub-cache area in the cache 114 correspond to different pages of the NAND flash memory array at the same or different sub-page offsets. The cached data in the cache 114 may be completely included in the buffered data in the page buffer 112, but the present invention is not limited thereto. In some embodiments, the cached data in the cache 114 may not overlap with the buffered data in the page buffer 112. Furthermore, the small subpage length of the subpages also helps the control circuit 106 shorten the time required for ECC (Error Correction Code) checking, thereby increasing data access speed.

[0044] Because the subpage length is small, the cached data in cache 114 can cover data from any number of pages in NAND flash array 110, meeting the requirement that data required for program execution is often dispersed across multiple pages. Furthermore, the small subpage length also has the advantage of shortening the time required for ECC checking. Furthermore, NAND flash memory 108 can operate in memory-mapped mode, allowing the host 102 to directly address it via the host system bus and make it visible to the central processing unit or any other component connected to the host system bus. Due to the aforementioned characteristics of NAND flash memory 108, the host 102 can directly access cache 114 through control circuit 106 to obtain the data required for program execution, without having to first store the data required for program execution in another storage device (e.g., random access memory). In other words, NAND flash memory 108 can function as an in-place execution memory, allowing the host 102 to directly execute program code from cache 114. Because access operations are performed within cache 114, the data access speed of the flash memory device 104 of this embodiment can be higher than that of conventional NOR flash memory.

[0045] The control circuit 106 can manage the sub-pages stored in the sub-page buffer of the page buffer 112 and the sub-pages stored in the sub-cache area of ​​the cache 114 based on a tag table 120 maintained and managed by the control circuit 106. The tag table 120 can be composed of address bytes pointing to cached sub-pages. For example, if the access request is a cache hit based on the tag table 120, the control circuit 106 can obtain the location of the sub-page data in the page buffer 112 or the cache 114. If the sub-page data is in the page buffer 112 or the cache 114, the sub-page data can be directly and immediately provided to the control circuit 106 without having to read the data from the NAND flash array 110, thereby shortening access time.

[0046] Furthermore, the cache operation performed by the control circuit 106 may be as follows: Figure 3 As shown. The host 102 can send a request to the control circuit 106 to read the data required by the host 102 to execute the program from the NAND flash memory 108. Figure 3 As shown, the control circuit 106 may first check the tag table 120 to confirm whether the data required by the host 102 to execute the program is in the cache 114 (step S302). If the data required by the host 102 to execute the program is in the cache 114, the control circuit 106 reads the required data from the cache 114 and transmits the read data to the host 102 via the input / output port (step S304). If the data required by the host 102 to execute the program is not in the cache 114, the control circuit 106 may check the tag table 120 to confirm whether the data required to execute the program is in the page buffer 112 (step S306).

[0047] If the data required for executing the program is not in the page buffer 112, the control circuit 106 can read the data required for executing the program from the page of the NAND flash array 110, and store the read data in the page buffer 112 (step S308) and update the tag table 120 accordingly. Figure 4 In the embodiment shown, the control circuit 106 may read data required for executing a program from the sub-page Cnk1 of the page Pn, store the data of the sub-page Cnk1 in the page buffer 112 , and update the tag table 120 .

[0048] It is worth noting that in some embodiments, when reading data required for executing a program, the control circuit 106 may also pre-fetch data from other pages (for example, adjacent pages (for example, the next page) of the page corresponding to the data being read, but not limited to this). In other words, data that will be used by the host 102 in executing a program later is first read and stored in the page buffer 112, so as to further improve the execution efficiency of the flash memory device 104.

[0049] Next, the control circuit 106 may select the sub-page data to be deleted in the cache 114 according to the default data replacement algorithm (step S310), wherein the default data replacement algorithm may be, for example, to select the least recently used (LRU) sub-page data for deletion, but is not limited thereto. For example, the sub-page data to be deleted may also be selected using a first-in-first-out (FIFO) algorithm. After selecting the sub-page data to be deleted, the data required for executing the program stored in the page buffer 112 may be moved to the cache 114 (step S312) to replace the deleted sub-page data. The tag table 120 is modified to reflect the latest temporarily stored sub-page addresses in the page buffer 112 and the cache 114. For example, in Figure 4 In one embodiment, the subpage selector 402 of the control circuit 106 can selectively delete the data of subpage Cnk2 in the cache 114 and store the data of subpage Cnk1 stored in the page buffer 112 in the cache 114 to replace the data of subpage Cnk2 in the cache 114. The subpage selector 402 is coupled to the NAND flash memory 108 and is controlled by the host 102 using information from the tag table 120 (e.g., controlled by address information in instructions output by the host 102) to selectively move subpage data between the page buffer 112 and the cache 114 in units of subpages. In some embodiments, the subpage selector 402 is controlled by the control circuit 106 itself, without the host 102 intervening in the replacement strategy. In addition, if step S306 determines that the data required for program execution is present in the page buffer 112, the process can proceed directly to step S310.

[0050] The control circuit 106 can perform ECC check on the data required for executing the program based on the sub-page error correction code containing the data required for executing the program to perform data error correction (step S314). Since the sub-page length of the data required for executing the program is not large, the number of correctable bits of the sub-page error correction code is also small. It can, for example, use a sub-page error correction code with a 1-bit correction capability to perform error correction, but is not limited to this. The control circuit 106 can determine whether the error correction of the data is successful (step S316). If the error correction of the data is successful, the error correction of the data can enter step S304 and transmit the read data to the host 102 through the input and output port 404. If the error correction of the data fails, the control circuit 106 can perform data error correction based on the page error correction code containing this data (step S318). For example, in Figure 4 In one embodiment, the sub-page Cnk2 may only include a sub-page ECC with a low-bit correction capability (e.g., a sub-page ECC with a 1-bit correction capability). The control circuit 106 may perform error correction on the data of the sub-page Cnk2 in the cache 114 based on the sub-page ECC. Compared to using a sub-page ECC with a multi-bit correction capability (e.g., a sub-page ECC with a 4-bit correction capability), using the sub-page ECC with a low-bit correction capability can complete data error correction more quickly, thereby improving the execution efficiency of the flash memory device 104. If the control circuit 106 fails to correct the error of the data in sub-page Cnk2 in the cache 114, the control circuit 106 can reread the data of the entire page Pn through the page buffer 112, store the data of page Pn in the cache 114, and perform error correction on the data of page Pn, including sub-page Cnk2, in the cache 114 based on the data of page Pn and its included page error correction code (which has multi-bit correction capability, such as 4-bit correction capability). This provides another ECC checking mechanism, which can further ensure the correctness of the data accessed by the control circuit 106 and improve the reliability of the flash memory device 104.

[0051] In some embodiments, when the error correction in step S316 fails, the sub-page selector 402 of the control circuit 106 may first back up the sub-page data (e.g., the data of sub-pages Cnk0, Cnk1, and Cnk3) in the cache 114 to the page buffer 112. After the error correction of the data of sub-page Cnk2 is completed, the data of sub-pages Cnk0, Cnk1, and Cnk3 may be moved back to the cache 114. In other embodiments, the sub-page data in the cache 114 may be directly deleted, and the sub-page data after error correction is completed may be stored in the cache 114. The tag table 120 is updated based on the latest status of the page buffer 112 and the data cache.

[0052] It is worth noting that although the NAND flash memory 108 in the above embodiment is described with the level 1 cache 114 as an example, the number of levels of the cache 114 is not limited to this. Figure 5 As shown in the embodiment, the NAND flash memory 108 includes a cache 502 in addition to the cache 114, thus forming a two-level cache architecture. Similar to the above embodiment, the access to the cache 502 is also performed in units of a sub-page. Since the cache operation of the double-layer cache is similar to the cache operation described above, its implementation details are not repeated here. In addition, in other embodiments, the NAND flash memory 108 may also include multiple memory planes, each memory plane having its corresponding NAND flash memory array, page buffer, and cache, each memory plane corresponding to a different cache, and the caches of different memory planes can transfer data to each other. For example Figure 6 As shown, the NAND flash memory 108 may include memory planes PL0 and PL1, wherein memory plane PL0 includes a NAND flash array 602, a page buffer 604, and a cache 606, and memory plane PL1 includes a NAND flash array 608, a page buffer 610, and a cache 612. The caches of memory planes PL0 and PL1 can transfer data to each other. In this way, the data in the page buffers and caches in each memory plane can not only come from different pages, but also from different memory planes, thereby allowing the cached data in the cache to cover a wider range.

[0053] In summary, each page of the NAND flash memory array of the present invention includes multiple sub-pages, each sub-page has a sub-page length, and the control circuit can perform cache operations of the cache in units of one sub-page, making the NAND flash memory suitable for performing random access operations to meet the increasing needs of embedded applications.

[0054] So far, the embodiments of the present disclosure have been described in detail with reference to the accompanying drawings.

[0055] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above are only specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A flash memory device, wherein: include: A NAND flash memory, including: A NAND flash memory array includes a plurality of pages, wherein each of the pages includes a plurality of sub-pages, and each of the sub-pages has a sub-page length; a cache memory comprising a plurality of sub-cache areas corresponding to different pages in the NAND flash memory array; and a page buffer comprising a plurality of sub-page buffers corresponding to different pages in the NAND flash array, wherein each of the plurality of sub-pages at the same sub-page offset in the page buffer and the cache is from a different page of the NAND flash array; and A control circuit is coupled to the NAND flash memory and performs an access operation based on a sub-page.

2. The flash memory device according to claim 1, wherein The control circuit pre-fetches data of adjacent pages of a currently read page according to a host request, and stores the pre-fetched data in the page buffer or the cache.

3. The flash memory device according to claim 1, wherein The data of each sub-page includes a sub-page error correction code, and the control circuit performs error correction on the data of the corresponding sub-page according to the sub-page error correction code.

4. The flash memory device according to claim 3, wherein The sub-page error correction code has a 1-bit correction capability.

5. The flash memory device according to claim 3, wherein When the control circuit fails to correct the error of the data of the corresponding sub-page based on the sub-page error correction code, the control circuit re-reads the data of a page including the corresponding sub-page through the page buffer, stores the data of the page in the cache, and performs error correction on all data of the page, including the data of the corresponding sub-page, based on the data of the page and its page error correction code. The flash memory device according to claim 5 , wherein: The page error correction code has multi-bit correction capability.

7. The flash memory device according to claim 1, wherein The cache is a multi-level cache, and a cache operation is performed on the multi-level cache using a sub-page as a unit.

8. The flash memory device according to claim 1, wherein The NAND flash memory includes a plurality of memory planes, each of which corresponds to a different high-speed cache.

9. The flash memory device according to claim 1, wherein The NAND flash memory includes: The control circuit performs a cache operation on a plurality of caches and selectively moves data between the caches in units of a sub-page.

10. The flash memory device according to claim 1, wherein The control circuit includes: A sub-page selector is coupled to the NAND flash memory and is controlled by address information in a command output by a host to selectively move data between the page buffer and the cache in units of a sub-page.

11. The flash memory device according to claim 10, wherein The NAND flash memory includes a tag table, which records sub-page address information of the page buffer and the cache.

12. The flash memory device according to claim 1, wherein The control circuit reads data from the sub-pages of the NAND flash memory array, stores the read sub-page data in the page buffer, selects the sub-page data to be overwritten in the cache, and moves the read sub-page data to the cache.

13. The flash memory device according to claim 1, wherein When the control circuit detects that the data exists in the cache, the control circuit transmits the data read from the cache to a host.

14. The flash memory device according to claim 13, wherein When the data does not exist in the cache but exists in the page buffer, the control circuit selects the sub-page data to be overwritten in the cache and moves the data to the cache.

15. A flash memory system, wherein: include: A host, obtains data; A flash memory device is coupled to the host and is accessed by the host. The flash memory device includes: A NAND flash memory, including: A NAND flash memory array includes a plurality of pages, wherein each of the pages includes a plurality of sub-pages, and each of the sub-pages has a sub-page length; a cache memory comprising a plurality of sub-cache areas corresponding to different pages in the NAND flash memory array; and a page buffer comprising a plurality of sub-page buffers corresponding to different pages in the NAND flash array, wherein each of the plurality of sub-pages at the same sub-page offset in the page buffer and the cache is from a different page of the NAND flash array; and A control circuit is coupled to the host and the NAND flash memory and performs an access operation based on a sub-page.

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