Memory System

Abstract

A memory system according to one embodiment of the present invention provides a means for adjusting the trade-off between write throughput and read latency. The memory system according to one embodiment includes a nonvolatile memory and a memory controller. The memory controller is configured to cause the nonvolatile memory to execute a first process for reading data based on a first request from a host device. If the memory controller receives the first request from the host device while the nonvolatile memory is executing a second process, the memory controller is configured to withhold interruption of the second process until a first number of unexecuted first requests held in the memory controller exceeds a first threshold, where the first threshold is an integer greater than or equal to 2.

Description

[0001] Related applications

[0002] This application claims the benefit of priority based on Japanese Patent Application No. 2020-205991 (filing date: December 11, 2020), and the present application incorporates all the contents of the basic application by reference. Technical Field

[0003] Embodiments relate to memory systems. Background Art

[0004] A memory system is known that includes a NAND flash memory as a nonvolatile memory and a memory controller that controls the nonvolatile memory. In the memory system, requirements related to write throughput and read latency are determined. Write throughput is the amount of data that can be written to the nonvolatile memory per unit time. Read latency is the time required to output data read from the nonvolatile memory to the outside of the memory system. Write throughput and read latency can be in a trade-off relationship. Summary of the Invention

[0005] A memory system according to an embodiment of the present invention provides a means to adjust the trade-off between write throughput and read latency.

[0006] A memory system according to an embodiment includes a nonvolatile memory and a memory controller, the memory controller being configured to cause the nonvolatile memory to execute a first process for reading data based on a first request from a host device. If the memory controller receives the first process from the host device while the nonvolatile memory is executing a second process, the memory controller is configured to withhold an interruption of the second process until a first number of unexecuted first requests stored in the memory controller reaches or exceeds a first threshold, the first threshold being an integer greater than or equal to 2. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 This is a block diagram showing the configuration of the information processing system according to the first embodiment.

[0008] Figure 2 This is a block diagram showing an example of signals used in the memory bus according to the first embodiment.

[0009] Figure 3 This is a flowchart showing an example of a series of processes including a program process in the memory system according to the first embodiment.

[0010] Figure 4 This is a flowchart showing an example of a series of processes including a hang determination process in the memory system according to the first embodiment.

[0011] Figure 5 This is a state transition diagram showing the relationship between a plurality of states related to a program process of the memory system according to the first embodiment.

[0012] Figure 6 This is a timing chart showing an example of state transition in a program process accompanied by a hang determination process in the memory system according to the first embodiment.

[0013] Figure 7 This is a block diagram showing the configuration of a memory controller according to a modification of the first embodiment.

[0014] Figure 8 This is a flowchart showing an example of a series of processes including a program process in a memory system according to a modification of the first embodiment.

[0015] Figure 9 This is a flowchart showing an example of a series of processes including a hang determination process in a memory system according to a modification of the first embodiment.

[0016] Figure 10 This is a timing chart showing an example of state transition in a program process accompanied by a hang determination process in a memory system according to a modification of the first embodiment.

[0017] Figure 11 This is a flowchart showing an example of a series of processes including a program process in the memory system according to the second embodiment.

[0018] Figure 12 This is a flowchart showing a series of processes including a first hang determination process in the memory system according to the second embodiment.

[0019] Figure 13 This is a timing chart showing an example of state transition in a program process accompanying a first hang determination process in the memory system according to the second embodiment.

[0020] Figure 14 This is a flowchart showing a series of processes including the second hang determination process in the memory system according to the second embodiment.

[0021] Figure 15 This is a timing chart showing an example of state transition in the programming process accompanying the second hang determination process of the memory system according to the second embodiment.

[0022] Figure 16 This is a flowchart showing a series of processes including a second hang determination process in a memory system according to a modification of the second embodiment.

[0023] Figure 17 This is a timing chart showing an example of state transition in a program process accompanied by a second hang determination process in a memory system according to a modification of the second embodiment.

[0024] Figure 18 This is a block diagram showing an example of the configuration of a nonvolatile memory according to the third embodiment.

[0025] Figure 19 This is a flowchart showing a series of processes including a hang determination process in the memory system according to the third embodiment.

[0026] Figure 20 This is a timing chart showing an example of state transition in a program process accompanied by a hang determination process in the memory system according to the third embodiment.

[0027] Figure 21 This is a flowchart showing a series of processes including a hang determination process in a memory system according to a first modification of the third embodiment.

[0028] Figure 22 This is a timing chart showing an example of state transition in a program process accompanied by a hang determination process in a memory system according to a first modification of the third embodiment.

[0029] Figure 23 This is a flowchart showing a series of processes including a hang determination process in a memory system according to a second modification of the third embodiment.

[0030] Figure 24 This is a timing chart showing an example of state transition in a program process accompanied by a hang determination process in a memory system according to a second modification of the third embodiment.

[0031] Figure 25 This is a flowchart showing an example of a series of processes including a program process in the memory system according to the fourth embodiment.

[0032] Figure 26 This is a flowchart showing a series of processes including a recovery determination process in the memory system according to the fourth embodiment.

[0033] Figure 27 1 is a state transition diagram showing the relationship between a plurality of states related to a program process of the memory system according to the fourth embodiment.

[0034] Figure 28 This is a timing chart showing an example of state transition in a program process accompanied by a restore determination process in the memory system according to the fourth embodiment.

[0035] Figure 29 This is a flowchart showing a series of processes including a recovery determination process in a memory system according to a modification of the fourth embodiment.

[0036] Figure 30 This is a timing chart showing an example of state transition in a program process accompanied by a restore determination process in a memory system according to a modification of the fourth embodiment.

[0037] Figure 31 This is a flowchart showing a series of processes including a recovery determination process in the memory system according to the fifth embodiment.

[0038] Figure 32 1 is a state transition diagram showing the relationship between a plurality of states related to a program process of the memory system according to the fifth embodiment.

[0039] Figure 33 This is a timing chart showing an example of state transition in a program process accompanied by a restore determination process in the memory system according to the fifth embodiment.

[0040] Figure 34 This is a flowchart showing an example of a series of processes including a program process in a memory system according to a modification of the fifth embodiment.

[0041] Figure 35 This is a flowchart showing a series of processes including a recovery determination process in a memory system according to a modification of the fifth embodiment.

[0042] Figure 36 This is a timing chart showing an example of state transition in a program process accompanied by a restore determination process in a memory system according to a modification of the fifth embodiment.

[0043] Figure 37 This is a flowchart showing an example of parameter change processing in the memory system according to the sixth embodiment.

[0044] Figure 38 This is a flowchart showing an example of parameter change processing in a memory system according to a modification of the sixth embodiment.

[0045] Description of Reference Numerals

[0046] 1…Information processing system, 2…Host device, 3…Memory system, 10…Non-volatile memory, 20…Memory controller, 21…Control circuit, 22…Buffer memory, 23…Host I / F, 24…Memory I / F, 25…Command queue, 26…Timer, BUS…Memory bus DETAILED DESCRIPTION

[0047] The following describes the embodiments with reference to the accompanying drawings. In the description, components having substantially the same function and configuration are denoted by the same reference numerals. The embodiments described below illustrate the technical concept. Various modifications may be made to the embodiments.

[0048] 1. First Implementation

[0049] 1.1 Composition

[0050] 1.1.1 Information Processing System

[0051] The configuration of the information processing system according to the first embodiment will be described.

[0052] Figure 1 FIG. 1 is a block diagram showing the configuration of the information processing system according to the first embodiment. Figure 1 As shown, the information processing system 1 includes a host device 2 and a memory system 3 .

[0053] The host device 2 is a data processing apparatus that processes data using the memory system 3. The host device 2 is, for example, a personal computer or a server in a data center.

[0054] The memory system 3 is a storage device connected to the host device 2. The memory system 3 is, for example, an SD TM The memory system 3 executes data programming, reading, and erasing in response to requests (commands) from the host device 2. The memory system 3 may also execute programming, reading, and erasing as internal processing.

[0055] 1.1.2 Memory System

[0056] The internal structure of the memory system according to the first embodiment will be described.

[0057] The memory system 3 includes a nonvolatile memory 10 and a memory controller 20 .

[0058] The nonvolatile memory 10 includes a plurality of memory cell transistors each storing data in a nonvolatile manner. The nonvolatile memory 10 is, for example, a NAND flash memory.

[0059] The memory controller 20 is comprised of, for example, an integrated circuit such as a system-on-a-chip (SoC). The memory controller 20 controls the nonvolatile memory 10 based on requests from the host device 2. Specifically, for example, the memory controller 20 writes write data to the nonvolatile memory 10 based on a write request from the host device 2. Furthermore, the memory controller 20 reads read data from the nonvolatile memory 10 based on a read request from the host device 2. The memory controller 20 then transmits the read data to the host device 2.

[0060] Next, the internal structure of the memory controller 20 is described. The memory controller 20 includes a control circuit 21, a buffer memory 22, a host interface circuit 23, a memory interface circuit 24, and a command queue 25. The functions of each component 21-25 of the memory controller 20 described below can be implemented using hardware or a combination of hardware resources and firmware.

[0061] The control circuit 21 is a circuit that controls the entire memory controller 20. The control circuit 21 includes, for example, a processor such as a CPU (central processing unit) and a ROM (read only memory).

[0062] The buffer memory 22 is a memory for buffering data between the host device 2 and the nonvolatile memory 10. The buffer memory 22 is, for example, an SRAM (static random access memory) and temporarily stores write data and read data.

[0063] The host interface circuit (host I / F) 23 is responsible for the communication between the memory controller 20 and the host device 2. The host interface circuit 23 is connected to the host device 2 via a host bus. The host bus is, for example, compliant with SD TM Interface, SAS (serialattached SCSI (small computer system interface)), SATA (serial ATA (advanced technology attachment)), or PCIe TM (peripheral component interconnect express) bus.

[0064] The memory interface circuit (memory I / F) 24 is responsible for communication between the nonvolatile memory 10 and the memory controller 20. The memory interface circuit 24 is connected to the nonvolatile memory 10 via a memory bus BUS. The memory bus BUS is, for example, a bus compliant with an SDR (single data rate) interface, a switched DDR (double data rate) interface, or ONFI (Open NAND flash interface).

[0065] The command queue 25 is a memory used to queue requests from the host device 2. The command queue 25 is, for example, an SRAM. The command queue 25 is, for example, a prioritized queue. The command queue 25 is configured to store multiple requests, each with a priority. The multiple requests stored in the command queue 25 are executed sequentially according to their respective priorities. Requests in the command queue 25 are deleted from the command queue 25 as the corresponding processes are executed.

[0066] Next, an example of signals exchanged between the nonvolatile memory 10 and the memory controller 20 will be described. Figure 2 This is a block diagram showing an example of signals used in the memory bus according to the first embodiment.

[0067] Signals used in the memory bus BUS include, for example, a chip enable signal CEn, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WEn, a read enable signal REn, a write protect signal WPn, a ready / busy signal RBn, and input / output signals I / O. In this specification, the "n" at the end of a signal name means that the signal is asserted when the signal is at an "L (Low)" level.

[0068] The signal CEn is a signal for enabling the nonvolatile memory 10 .

[0069] The signals CLE and ALE are signals for notifying the nonvolatile memory 10 that the input signal I / O to the nonvolatile memory 10 is a command and an address, respectively.

[0070] The signal WEn is a signal for causing the nonvolatile memory 10 to acquire the input signal I / O.

[0071] The signal REn is a signal for reading the output signal I / O from the nonvolatile memory 10 .

[0072] The signal WPn is a signal for instructing the nonvolatile memory 10 to prohibit writing and erasing of data.

[0073] Signal RBn is a signal indicating whether the nonvolatile memory 10 is in the ready state or the busy state. The ready state indicates that the nonvolatile memory 10 is able to receive commands from the memory controller 20. The busy state indicates that the nonvolatile memory 10 is unable to receive commands from the memory controller 20, except for some commands such as the suspend command instructing execution of the suspend process described later. The "L" level of signal RBn indicates the busy state.

[0074] The input / output signal I / O is, for example, an 8-bit signal. The input / output signal I / O is the entity of data transmitted and received between the nonvolatile memory 10 and the memory controller 20. The input / output signal I / O includes data such as commands, addresses, and write and read data.

[0075] 1.2 Action

[0076] Next, the operation of the memory system according to the first embodiment will be described. 1.2.1

[0078] Programming Processing

[0079] Figure 3 This is a flowchart showing an example of a series of processes including a program process in the memory system according to the first embodiment.

[0080] When a program condition is satisfied (start), the memory controller 20 causes the nonvolatile memory 10 to execute a program process accompanied by a suspend determination process ( S1 ).

[0081] Satisfying the program conditions includes storing a certain amount of write data in the buffer memory 22 in response to a write request from the host device 2. Furthermore, satisfying the program conditions includes satisfying a start condition for a programming process executed in an internal process of the memory controller 20. The internal process includes garbage collection (compaction), refresh, wear leveling, and non-volatile processing of management information of the non-volatile memory 10.

[0082] During programming, the memory controller 20 sends write data from the buffer memory 22 to the nonvolatile memory 10. The nonvolatile memory 10 stores the received write data in a page buffer (not shown) within the nonvolatile memory 10 (data input). Based on the write data stored in the page buffer, the nonvolatile memory 10 executes programming on a memory cell array (not shown) within the nonvolatile memory 10.

[0083] The suspend determination process determines whether to execute a suspend process based on whether a suspend condition is satisfied. The suspend process interrupts the programming process, etc., being executed by the nonvolatile memory 10. By adjusting the timing of executing the suspend process, the memory controller 20 can adjust the trade-off between read latency and write throughput.

[0084] When the programming process, which includes the suspend determination process, is completed, the memory controller 20 causes the nonvolatile memory 10 to execute a status read process (S2). The status read process is a process in which the memory controller 20 reads the status of the nonvolatile memory 10 in order to understand the status of the nonvolatile memory 10. This allows the memory controller 20 to confirm that the programming process of the nonvolatile memory 10 has been completed.

[0085] When the memory controller 20 receives a notification from the nonvolatile memory 10 that the programming process has been completed during the process of S2 , the memory controller 20 ends a series of processes including the programming process (END).

[0086] 1.2.2 Suspend determination processing

[0087] Figure 4 This is a flowchart showing an example of a series of processes including the hang determination process in the memory system of the first embodiment. The series of processes including the hang determination process are executed according to the start conditions of the hang determination process. Figure 4 In the example of FIG. 2 , the start condition of the hang determination process is that the memory controller 20 receives a read request from the host device 2 .

[0088] That is, when receiving a read request from the host device 2 (start), the memory controller 20 determines whether the nonvolatile memory 10 is in programming processing ( S10 ).

[0089] If the program process is not in progress (S10; false), the memory controller 20 causes the nonvolatile memory 10 to execute a read process based on the received read request (S11). When the process of S11 is completed, a series of processes including the hang determination process are completed (end).

[0090] When the program process is in progress ( S10 ; true), the memory controller 20 determines whether a suspend condition is satisfied ( S12 ). Figure 4 The hang condition in the example is that the number of read requests in the command queue 25 is greater than or equal to a threshold value N. The threshold value N is an integer greater than or equal to 2 (N≥2).

[0091] If there are not more than the threshold N read requests in the command queue 25 (S12: False), the memory controller 20 holds the interruption of the program process. That is, the memory controller 20 does not interrupt the program process. Thus, a series of processes including the hang determination process are completed (End).

[0092] When the number of read requests in the command queue 25 is equal to or greater than the threshold value N ( S12 ; true), the memory controller 20 causes the nonvolatile memory 10 to execute a suspend process ( S13 ).

[0093] After interrupting the program process through the suspend process, the memory controller 20 causes the nonvolatile memory 10 to perform a read process based on the read request ( S14 ).

[0094] Every time the process of S14 is completed, the memory controller 20 determines whether or not a read request still exists in the command queue 25 ( S15 ).

[0095] If there are still read requests in the command queue 25 (S15; true), the memory controller 20 causes the nonvolatile memory 10 to execute a read process based on the read request (S14). Thus, the processes of S14 and S15 are repeated until the read processes corresponding to all the read requests in the command queue 25 are executed.

[0096] When there is no read request in the command queue 25 ( S15 ; false), the memory controller 20 causes the nonvolatile memory 10 to execute a restore process ( S16 ).

[0097] When the process of S16 is completed, a series of processes including the hang determination process is completed (END).

[0098] 1.2.3 State Transition of Memory System

[0099] Figure 5 1 is a state transition diagram showing the relationship between a plurality of states related to the programming process of the memory system of the first embodiment. Figure 5 In FIG. 3 , the memory system 3 is shown for Figure 3 as well as Figure 4 The relationships among the various states that a process can assume are shown.

[0100] First, a description will be given of the various states that the memory system 3 can assume.

[0101] like Figure 5As shown, the states of the memory system 3 related to the programming process include a program ready state STS1, a program busy state STS2, and a program suspended state STS3. The program ready state STS1 is a state in which the programming process in the memory system 3 is permitted. The program busy state STS2 is a state in which the memory system 3 is currently executing the programming process. The program suspended state STS3 is a state in which the memory system 3 has suspended the execution of the programming process. In the program busy state STS2, the memory system 3 is prohibited from executing the read process. In the program ready state STS1 and the program suspended state STS3, the memory system 3 is permitted to execute the read process.

[0102] The program ready state STS1 includes a no-waiting-read-request state STS11 and a read-in-progress state STS12. The no-waiting-read-request state STS11 indicates that, in the program ready state STS1, no unexecuted read requests are stored in the command queue 25. The read-in-progress state STS12 indicates that, in the program ready state STS1, the memory system 3 is currently executing a read process.

[0103] The program busy state STS2 includes a no-waiting-read-request state STS21 and a pending-processing-reserved state STS22. The no-waiting-read-request state STS21 is a state in which, in the program busy state STS2, no unexecuted read requests are stored in the command queue 25. The pending-processing-reserved state STS22 is a state in which the memory system 3 is reserving the start of a pending process.

[0104] The program suspension state STS3 includes the suspend processing state STS31, the read processing state STS32, and the resume processing state STS33. The suspend processing state STS31 indicates that the memory system 3 is currently executing the suspend process. The read processing state STS32 indicates that the memory system 3 is currently executing the read process in the program suspension state STS3. The resume processing state STS33 indicates that the memory system 3 is currently executing the resume process. The resume process is a process that resumes the interrupted programming process.

[0105] Next, the events that cause each state transition will be described.

[0106] When a read request is received from the host device 2 in the no-wait-read-request state STS11 (E1), the memory system 3 starts executing a read process and transitions to the read-processing state STS12. When a further read request is received from the host device 2 in the read-processing state STS12 (E2), the memory system 3 maintains the read-processing state STS12 until the read processes corresponding to all the read requests in the command queue 25 are completed. When the read processes corresponding to all the read requests in the command queue 25 are completed (E3), the memory system 3 transitions to the no-wait-read-request state STS11.

[0107] When the program process starts in the no-wait read request state STS11 (E4), the memory system 3 transitions to the no-wait read request state STS21. When the program process is completed in the no-wait read request state STS21 (E5), the memory system 3 transitions to the no-wait read request state STS11. When a read request is received in the no-wait read request state STS21 (E6), the memory system 3 transitions to the process-suspended state STS22.

[0108] If the suspend condition is not satisfied (E7), the memory system 3 remains in the suspend processing state STS22. When the programming process is completed in the suspend processing state STS22 (E8), the memory system 3 transitions to the read processing state STS12. When the suspend condition is satisfied in the suspend processing state STS22 (E9), the memory system 3 transitions to the suspend processing state STS31.

[0109] When the suspend processing is completed in the suspend processing state STS31 (E10), the memory system 3 transitions to the read processing state STS32. When a further read request is received from the host device 2 in the read processing state STS32 (E11), the memory system 3 maintains the read processing state STS32 until the read processing corresponding to all read requests in the command queue 25 is completed. When the read processing corresponding to all read requests in the command queue 25 is completed (E12), the memory system 3 transitions to the resume processing state STS33. When the resume processing is completed (E13), the memory system 3 transitions to the no-waiting-read-request state STS21.

[0110] That is, when the programming process starts in the program ready state STS1 (E4), the memory system 3 transitions to the program busy state STS2. When the programming process is completed in the program busy state STS2 (E5 or E8), the memory system 3 transitions to the program ready state STS1. When the suspend condition is satisfied in the program busy state STS2 (E9), the memory system 3 transitions to the program suspended state STS3. When the resume process is completed in the program suspended state STS3 (E13), the memory system 3 transitions to the program busy state STS2.

[0111] 1.2.4 State Transitions in Programming Processing Accompanied by Suspend Decision Processing

[0112] Figure 6 This is a timing diagram showing an example of state transition in the programming process accompanying the hang determination process of the memory system of the first embodiment. Figure 6 In the example of , the case where the threshold N is 2 is shown. Figure 6 In the example shown in FIG. 2 , before time t10 , the state of the memory system 3 is the no-waiting-read-request state STS11 .

[0113] like Figure 6 As shown, at time t10, the memory controller 20 causes the nonvolatile memory 10 to execute a program process. Accordingly, the state of the memory system 3 enters the no-wait read request state STS21.

[0114] At time t11, the memory controller 20 receives the first read request (first read request). As a result, the number of read requests in the command queue 25 is one less than the threshold value N (=2). Therefore, the state of the memory system 3 enters the pending processing state STS22.

[0115] At time t12, the memory controller 20 receives a second read request (second read request). As a result, the number of read requests in the command queue 25 reaches two, equal to the threshold value N (=2). Consequently, the memory controller 20 causes the nonvolatile memory 10 to execute a suspend process. Consequently, the memory system 3 enters the suspend process state STS31.

[0116] At time t13, the suspend process ends. Then, the memory controller 20 causes the nonvolatile memory 10 to execute a read process (first read process) based on the first read request. As a result, the state of the memory system 3 changes to the read-in-progress state STS32.

[0117] At time t14, the first read process ends. Then, the memory controller 20 causes the nonvolatile memory 10 to execute a read process (second read process) based on the second read request. The memory system 3 maintains the read-in-progress state STS32.

[0118] At time t15, the second read process ends. After confirming that the number of read requests in the command queue 25 is 0, the memory controller 20 causes the nonvolatile memory 10 to execute the recovery process. Accordingly, the state of the memory system 3 enters the recovery process state STS33.

[0119] At time t16, the recovery process ends. Then, the memory controller 20 restarts the programming process of the nonvolatile memory 10. As a result, the state of the memory system 3 enters the no-wait read request state STS21.

[0120] At time t17, the programming process ends. Thereafter, the memory controller 20 confirms, through a status read process, that the data has been written without any problems into the nonvolatile memory 10. As a result, the state of the memory system 3 returns to the no-wait read request state STS11.

[0121] 1.3 Effects of the First Implementation

[0122] According to the first embodiment, the memory controller 20 retains the suspended processing until the number of read requests in the command queue 25 reaches or exceeds the threshold value N. Thus, the memory controller 20 can execute at least the threshold value N read processing simultaneously during a programming interruption. Therefore, compared to interrupting the programming process each time a read request is received, the number of suspended and resumed processing can be reduced. Consequently, compared to interrupting the programming process each time a read request is received, the total time required for suspended and resumed processing (cumulative overhead) can be reduced, and a decrease in write throughput can be suppressed.

[0123] Furthermore, according to the first embodiment, the memory controller 20 executes a suspend process when the number of read requests in the command queue 25 exceeds a threshold value N. Thus, if the suspend condition is met, the memory controller 20 can execute a read process without waiting for the completion of the programming process. Consequently, compared to executing the read process after the programming process is completed, the time required from receiving a read request to completing the read process can be shortened. Consequently, compared to executing the read process after the programming process is completed, an increase in read latency can be suppressed.

[0124] Thus, according to the first embodiment, it is possible to achieve both improved write throughput compared to interrupting the programming process each time a read request is received and improved read latency compared to executing the read process after the programming process is completed. Thus, a means of adjusting the trade-off between write throughput and read latency can be provided.

[0125] 1.4 Modification of the First Embodiment

[0126] In the first embodiment described above, the memory controller 20 holds the pending process until the number of unexecuted read requests reaches a threshold value N or more. However, the embodiment is not limited to this. For example, the memory controller 20 may control the duration of the pending process based on the time elapsed since the first read request was received. In the following description, descriptions of the same configurations and operations as those in the first embodiment are omitted, and the description focuses on configurations and operations that differ from those in the first embodiment.

[0127] 1.4.1 Memory Controller Structure

[0128] Figure 7 FIG. 1 is a block diagram showing the configuration of a memory controller according to a modified example of the first embodiment. Figure 7 As shown, the memory controller 20 also includes a timer 26 .

[0129] The timer 26 measures time. For example, the timer 26 starts measuring (start) based on a start instruction from the control circuit 21. The timer 26 temporarily stops measuring (suspend) based on a temporary stop instruction from the control circuit 21. The timer 26 resumes the temporarily stopped measuring (resume) based on a restart instruction from the control circuit 21. The timer 26 stops measuring (stop) based on a stop instruction from the control circuit 21.

[0130] Before and after timer 26 is started, timer 26 is in the stopped state. From the start of measurement to the end of measurement, timer 26 is in the measuring state. In a modified example of the first embodiment, timer 26 measures the elapsed time from the time the memory system 3 enters the pending processing state STS22 upon receipt of a read request.

[0131] The memory controller 20 acquires, for example, a measured value from the start of measurement by the timer 26. This allows the memory controller 20 to grasp the elapsed time from a desired time.

[0132] 1.4.2 Programming Processing

[0133] Figure 8 This is a flowchart showing an example of a series of processes including a program process in a memory system according to a modification of the first embodiment.

[0134] When a program condition is satisfied (start), the memory controller 20 causes the nonvolatile memory 10 to execute a program process accompanied by a suspend determination process ( S1 ).

[0135] When the program processing accompanying the suspend determination processing is completed, the memory controller 20 causes the nonvolatile memory 10 to execute a status read processing ( S2 ).

[0136] When receiving a status indicating that the programming process is completed from the nonvolatile memory 10 in the process of S2 , the memory controller 20 determines whether the timer 26 is in the process of measuring ( S3 ).

[0137] If the timer 26 is measuring (S3; true), the memory controller 20 stops the timer 26 (S4). When the process of S4 is completed, a series of processes including the programming process are completed (end).

[0138] If the timer 26 is not measuring (S3; false), the process of S4 is not executed, and a series of processes including the programming process are completed (End).

[0139] 1.4.3 Suspend Determination Processing

[0140] Figure 9 This is a flowchart showing an example of a series of processes including a hang determination process in a memory system according to a modification of the first embodiment. Figure 9 In the example of , the hang determination process starts when the memory controller 20 receives a read request from the host device 2 or the measured value of the timer 26 becomes equal to or greater than a threshold value T1. The threshold value T1 is a positive real number.

[0141] That is, when a read request is received from the host device 2 or the measured value of the timer 26 becomes equal to or greater than the threshold value T1 (start), the memory controller 20 determines whether or not the program process is in progress ( S20 ).

[0142] If the program process is not in progress (S20; false), the memory controller 20 causes the nonvolatile memory 10 to execute a read process based on the received read request (S21). When the process of S21 is completed, a series of processes including the hang determination process are completed (end).

[0143] When the program process is in progress ( S20 ; true), the memory controller 20 determines whether a suspend condition is satisfied ( S22 ). Figure 9 The hang condition in the example is that the number of read requests in the command queue 25 is greater than or equal to the threshold value N, or the measured value of the timer 26 is greater than or equal to the threshold value T1.

[0144] If the number of read requests in the command queue 25 is less than or equal to the threshold value N and the measured value of the timer 26 is less than the threshold value T1 (S22: False), the memory controller 20 maintains the interruption of the program process. In other words, the memory controller 20 does not interrupt the program process. The memory controller 20 then determines whether there is only one read request in the command queue 25 and whether the timer 26 is currently stopped (S23).

[0145] When there is not one read request in the command queue 25 or the timer 26 is not stopped ( S23 ; false), a series of processes including the hang determination process are completed (End).

[0146] When there is one read request in the command queue 25 and the timer 26 is stopped ( S23 ; true), the memory controller 20 starts the timer 26 ( S24 ).

[0147] When the process of S24 is completed, the timer 26 maintains the measuring state, and a series of processes including the hang determination process are completed (end).

[0148] When the number of read requests in the command queue 25 is equal to or greater than the threshold value N, or when the measured value of the timer 26 is equal to or greater than the threshold value T1 ( S22 ; true), the memory controller 20 stops the timer 26 ( S25 ).

[0149] After stopping the timer 26, the memory controller 20 causes the nonvolatile memory 10 to execute the suspend process (S26).

[0150] After interrupting the program process through the suspend process, the memory controller 20 causes the nonvolatile memory 10 to perform a read process based on the read request ( S27 ).

[0151] Every time the process of S27 is completed, the memory controller 20 determines whether or not a read request still exists in the command queue 25 ( S28 ).

[0152] If there are still read requests in the command queue 25 (S28; true), the memory controller 20 causes the nonvolatile memory 10 to execute a read process based on the read request (S27). Thus, the processes of S27 and S28 are repeated until the read processes corresponding to all the read requests in the command queue 25 are executed.

[0153] When there is no read request in the command queue 25 ( S28 ; false), the memory controller 20 causes the nonvolatile memory 10 to execute a restore process ( S29 ).

[0154] When the process of S29 is completed, the timer 26 maintains the stopped state, and a series of processes including the hang determination process are completed (end).

[0155] 1.4.4 State Transitions in Programming Processing Accompanying Suspend Decision Processing

[0156] Figure 10This is a timing chart showing an example of state transition in a program process accompanied by a hang determination process in a memory system according to a modification of the first embodiment. Figure 10 In the example of FIG, the case where the suspend process is executed when the measured value of the timer 26 reaches the threshold value T1 before the number of read requests in the command queue 25 reaches the threshold value N is shown. Figure 10 In the example shown in FIG. 2 , before time t20 , the state of the memory system 3 is the no-waiting-read-request state STS11 . Also, before time t20 , the timer 26 is in the stopped state.

[0157] like Figure 10 As shown, at time t20, the memory controller 20 causes the nonvolatile memory 10 to execute a program process. Accordingly, the state of the memory system 3 enters the no-wait read request state STS21.

[0158] At time t21, the memory controller 20 receives the first read request. As a result, the number of read requests in the command queue 25 is reduced to one, less than the threshold value N. Consequently, the memory system 3 enters the pending processing state STS22. Furthermore, upon receipt of the first read request, the memory controller 20 starts the timer 26.

[0159] At time t22, the measured value of the timer 26 reaches the threshold value T1. The memory controller 20 stops the timer 26. Thereafter, the memory controller 20 causes the nonvolatile memory 10 to execute the suspend process. Accordingly, the state of the memory system 3 enters the suspend process state STS31.

[0160] At time t23, the memory controller 20 receives the second read request. As a result, the number of read requests in the command queue 25 becomes two. The memory system 3 maintains the pending processing state STS31.

[0161] At time t24, the suspend process ends. Then, the memory controller 20 causes the nonvolatile memory 10 to execute the first read process. As a result, the state of the memory system 3 enters the read-in-progress state STS32.

[0162] At time t25, the first read process ends. Then, the memory controller 20 causes the nonvolatile memory 10 to execute the second read process. The memory system 3 maintains the read-in-progress state STS32.

[0163] At time t26, the second read process ends. After confirming that the number of read requests in the command queue 25 is 0, the memory controller 20 causes the nonvolatile memory 10 to execute the recovery process. Accordingly, the state of the memory system 3 enters the recovery process state STS33.

[0164] At time t27, the recovery process ends. Then, the memory controller 20 restarts the programming process of the nonvolatile memory 10. As a result, the state of the memory system 3 enters the no-wait read request state STS21.

[0165] At time t28, the programming process ends. Thereafter, the memory controller 20 confirms, through a status read process, that the data has been written without any problems into the nonvolatile memory 10. As a result, the state of the memory system 3 returns to the no-wait read request state STS11.

[0166] 1.4.5 Effects of Modifications of the First Embodiment

[0167] According to a variation of the first embodiment, the memory controller 20 activates the timer 26 in response to the first read request being stored in the command queue 25. When the measured value of the timer 26 reaches the threshold value T1, the memory controller 20 executes the suspend process regardless of whether the number of read requests in the command queue 25 is greater than or equal to the threshold value N. Consequently, the memory controller 20, having received a read request, can initiate the suspend process within the period within the threshold value T1. This achieves the effects described in the first embodiment and suppresses increases in read latency when no subsequent read requests are received.

[0168] 2. Second Implementation

[0169] Next, the memory system of the second embodiment will be described. The second embodiment differs from the first embodiment in that the suspend process is prohibited until the value measured by timer 26 reaches a threshold. Specifically, in the second embodiment, timer 26 measures the elapsed time from the start of the program process and the elapsed time from the end of the resume process. In the following description, the same configuration and operations as those of the modified example of the first embodiment will be omitted, and the description will focus on the configuration and operations that differ from those of the modified example of the first embodiment.

[0170] 2.1 Programming Processing

[0171] Figure 11 This is a flowchart showing an example of a series of processes including a program process in the memory system according to the second embodiment.

[0172] When a program condition is satisfied (start), the memory controller 20 starts the timer 26 ( S0 ).

[0173] After starting the measurement of the timer 26, the memory controller 20 causes the nonvolatile memory 10 to execute a program process accompanied by a hang determination process (S1).

[0174] Alternatively, the timing for starting the timer 26 and the timing for starting the programming process accompanied by the hang determination process may be simultaneous. Specifically, the timer 26 may start counting from the start of the programming process accompanied by the hang determination process. Alternatively, the timer 26 may start counting from the start of the data input process to the page buffer within the nonvolatile memory 10. Alternatively, the timer 26 may start counting from the completion of the data input process to the page buffer within the nonvolatile memory 10.

[0175] Processing and reference after S2 Figure 8 The processing of the modified example of the first embodiment described is the same, and therefore the description thereof will be omitted.

[0176] 2.2 First Suspension Determination Process

[0177] First, the first suspend determination process is described. The first suspend determination process is executed before the first suspend process in the programming process.

[0178] Figure 12 This is a flowchart showing an example of a series of processes including the first hang determination process in the memory system of the second embodiment. Figure 12 In the example, the start condition of the first hang determination process is that the memory controller 20 receives a read request from the host device 2 or the measured value of the timer 26 becomes greater than or equal to threshold T2 in the first measurement in the programming process. Threshold T2 is a positive real number.

[0179] Specifically, in the first measurement in the program process, when a read request is received from the host device 2 or the measured value of the timer 26 becomes equal to or greater than the threshold value T2 (start), the memory controller 20 determines whether the first suspend condition is satisfied ( S30 ). Figure 12 The first suspension condition in the example of is that a read request exists in the command queue 25 and the measured value of the timer 26 is greater than or equal to the threshold value T2.

[0180] When a read request exists in the command queue 25 and the measured value of the timer 26 is equal to or greater than the threshold value T2 ( S30 ; true), the memory controller 20 stops the timer 26 ( S31 ).

[0181] After stopping the timer 26, the memory controller 20 causes the nonvolatile memory 10 to perform the first suspend process in the program process (S32).

[0182] After interrupting the program process through the suspend process, the memory controller 20 causes the nonvolatile memory 10 to perform a read process based on the read request ( S33 ).

[0183] Every time the process of S33 is completed, the memory controller 20 determines whether or not a read request still exists in the command queue 25 ( S34 ).

[0184] If there are still read requests in the command queue 25 (S34; true), the memory controller 20 causes the nonvolatile memory 10 to execute a read process based on the read request (S33). Thus, the processes of S33 and S34 are repeated until the read processes corresponding to all the read requests in the command queue 25 are executed.

[0185] When there is no read request in the command queue 25 ( S34 ; false), the memory controller 20 causes the nonvolatile memory 10 to execute a restore process ( S35 ).

[0186] When the restoration process is completed, the memory controller 20 starts the timer 26 ( S36 ).

[0187] When the process of S36 is completed, the timer 26 maintains the measuring state, and a series of processes including the first hang determination process are completed (end).

[0188] If there are no read requests in the command queue 25 or the measured value of the timer 26 is less than T2 (S30; false), the memory controller 20 maintains the interruption of the program process. In other words, the memory controller 20 does not interrupt the program process. Therefore, the timer 26 remains in the measuring state, and the series of processes including the first hang determination process are completed (end).

[0189] 2.3 State Transitions in Programming Processing Accompanying the First Suspend Decision Processing

[0190] Figure 13 1 is a timing chart showing an example of state transition in the programming process accompanying the first hang determination process of the memory system according to the second embodiment. Figure 13 In the example of FIG, a case is shown where, in the first measurement, after a read request is stored in the command queue 25, a suspend process is executed when the measured value of the timer 26 reaches the threshold value T2. Figure 13 In the example shown in FIG. 2 , before time t30 , the state of the memory system 3 is the no-waiting-read-request state STS11 .

[0191] like Figure 13 As shown, at time t30, the memory controller 20 causes the nonvolatile memory 10 to execute a program process. Consequently, the state of the memory system 3 changes to a no-wait read request state STS21. Furthermore, the memory controller 20 starts a timer 26 from the start of the program process.

[0192] At time t31, the memory controller 20 receives the first read request. As a result, the number of read requests in the command queue 25 reaches one. However, because the value measured by the timer 26 is less than the threshold value T2, the memory controller 20 holds the interruption of the program process. Consequently, the state of the memory system 3 enters the pending state STS22.

[0193] At time t32, the memory controller 20 receives the second read request. This brings the number of read requests in the command queue 25 to two. However, since the count value of the timer 26 is less than the threshold value T2, the memory system 3 maintains the pending processing state STS22.

[0194] At time t33, the measured value of the timer 26 reaches the threshold value T2. The memory controller 20 stops the timer 26. Thereafter, the memory controller 20 causes the nonvolatile memory 10 to execute the suspend process. Accordingly, the state of the memory system 3 enters the suspend process state STS31.

[0195] At time t34, the suspend process ends. Then, the memory controller 20 causes the nonvolatile memory 10 to execute a read process (first read process) based on the first read request. As a result, the state of the memory system 3 enters the read-in-progress state STS32.

[0196] At time t35, the first read process ends. Then, the memory controller 20 causes the nonvolatile memory 10 to execute a read process (second read process) based on the second read request. The memory system 3 maintains the read-in-progress state STS32.

[0197] At time t36, the second read process ends. After confirming that the number of read requests in the command queue 25 is 0, the memory controller 20 causes the nonvolatile memory 10 to execute the recovery process. Accordingly, the state of the memory system 3 enters the recovery process state STS33.

[0198] At time t37, the recovery process ends. Then, the memory controller 20 restarts the programming process of the nonvolatile memory 10. In addition, the memory controller 20 starts the timer 26. With this, the state of the memory system 3 enters the no-wait read request state STS21.

[0199] 2.4 Second Suspension Determination Processing

[0200] Next, the second suspend determination process will be described. The second suspend determination process is executed in the second and subsequent suspend processes in the programming process.

[0201] Figure 14This is a flowchart showing an example of a series of processes including the second hang determination process in the memory system of the second embodiment. Figure 14 In the example, the second hang determination process is initiated when the memory controller 20 receives a read request from the host device 2 or the timer 26 counts up to or above a threshold value T3 during the second or subsequent measurements in the programming process. Threshold value T3 is a positive real number. Threshold value T3 may be equal to or different from threshold value T2.

[0202] Specifically, in the second and subsequent measurements in the program process, when a read request is received from the host device 2 or the measured value of the timer 26 becomes equal to or greater than the threshold value T3 (start), the memory controller 20 determines whether the second suspend condition is satisfied ( S40 ). Figure 14 The second suspension condition in the example of is that a read request exists in the command queue 25 and the measured value of the timer 26 is equal to or greater than the threshold value T3.

[0203] When a read request exists in the command queue 25 and the measured value of the timer 26 is equal to or greater than the threshold value T3 ( S40 ; true), the memory controller 20 stops the timer 26 ( S41 ).

[0204] After stopping the timer 26, the memory controller 20 causes the nonvolatile memory 10 to execute the second and subsequent suspend processes in the program process (S42).

[0205] After interrupting the program process through the suspend process, the memory controller 20 causes the nonvolatile memory 10 to perform a read process based on the read request ( S43 ).

[0206] Every time the process of S43 is completed, the memory controller 20 determines whether or not a read request still exists in the command queue 25 ( S44 ).

[0207] If there are still read requests in the command queue 25 (S44; true), the memory controller 20 causes the nonvolatile memory 10 to execute a read process based on the read request (S43). Thus, the processes of S43 and S44 are repeated until the read processes corresponding to all the read requests in the command queue 25 are executed.

[0208] When there is no read request in the command queue 25 ( S44 ; false), the memory controller 20 causes the nonvolatile memory 10 to execute a restore process ( S45 ).

[0209] When the restoration process is completed, the memory controller 20 starts the timer 26 ( S46 ).

[0210] When the process of S46 is completed, the timer 26 maintains the measuring state, and a series of processes including the second hang determination process are completed (end).

[0211] If there are no read requests in the command queue 25 or the timer 26 count value is less than T3 (S40: False), the memory controller 20 maintains the interruption of the program process. In other words, the memory controller 20 does not interrupt the program process. Therefore, the timer 26 remains in the counting state, and the series of processes including the second hang determination process are completed (End).

[0212] 2.5 State Transition in Programming Processing Accompanied by Second Suspend Decision Processing

[0213] Figure 15 1 is a timing chart showing an example of state transition in the programming process accompanying the second hang determination process of the memory system according to the second embodiment. Figure 15 In the example, as Figure 13 An example of processing after time t37 is shown as a continuation of the example of . Figure 15 In the example shown in FIG. 1 , in the second measurement, after the read request is stored in the command queue 25 , the suspend process is executed when the measured value of the timer 26 reaches the threshold value T3 .

[0214] like Figure 15 As shown, at time t38, the memory controller 20 receives the third read request (the third read request) during the programming process. Consequently, the number of read requests in the command queue 25 becomes one. However, since the value measured by the timer 26 is less than the threshold value T3, the memory controller 20 holds the interruption of the programming process. Consequently, the state of the memory system 3 enters the pending state STS22.

[0215] At time t39, the memory controller 20 receives the fourth read request (fourth read request) during the programming process. Consequently, the number of read requests in the command queue 25 becomes two. However, since the count value of the timer 26 is less than the threshold value T3, the memory system 3 remains in the pending processing state STS22.

[0216] At time t40, the measured value of the timer 26 reaches the threshold value T3. The memory controller 20 stops the timer 26. Thereafter, the memory controller 20 causes the nonvolatile memory 10 to execute the suspend process. Accordingly, the state of the memory system 3 enters the suspend process state STS31.

[0217] At time t41, the suspend process ends. Then, the memory controller 20 causes the nonvolatile memory 10 to execute a read process (third read process) based on the third read request. As a result, the state of the memory system 3 changes to the read-in-progress state STS32.

[0218] At time t42, the third read process ends. Then, the memory controller 20 causes the nonvolatile memory 10 to execute a read process based on the fourth read request (fourth read process). The memory system 3 maintains the read-in-progress state STS32.

[0219] At time t43, the fourth read process ends. After confirming that the number of read requests in the command queue 25 is 0, the memory controller 20 causes the nonvolatile memory 10 to execute the recovery process. Accordingly, the state of the memory system 3 enters the recovery process state STS33.

[0220] At time t44, the recovery process ends. Then, the memory controller 20 restarts the programming process of the nonvolatile memory 10. In addition, the memory controller 20 starts the timer 26. With this, the state of the memory system 3 enters the no-wait read request state STS21.

[0221] At time t45, the programming process ends. Thereafter, the memory controller 20 confirms, through a status read process, that the data has been written without any problems into the nonvolatile memory 10. As a result, the state of the memory system 3 returns to the no-wait read request state STS11.

[0222] 2.6 Effects of the Second Implementation

[0223] According to the second embodiment, the memory controller 20 retains the suspended process until the time elapsed since the start of the programming process exceeds threshold value T2. This allows a suspension prohibition period to be set immediately after the start of the programming process. Furthermore, the memory controller 20 retains the suspended process until the time elapsed since the end of the previous resume process exceeds threshold value T3. This allows a suspension prohibition period of at least threshold value T3 to be set between two suspended processes. Therefore, compared to executing the suspended process each time a read request is received, frequent repetition of the suspended process can be suppressed. Consequently, compared to executing the suspended process each time a read request is received, a decrease in write throughput can be suppressed.

[0224] Furthermore, according to the second embodiment, if a read request exists in the command queue 25 and the timer value is greater than or equal to T2, the memory controller 20 executes a suspend process. Thus, if the suspend condition is met, the memory controller 20 can execute the read process without waiting for the completion of the programming process. Consequently, compared to executing the read process after the programming process is completed, the time required from receiving the read request to the completion of the read process can be shortened. Consequently, compared to executing the read process after the programming process is completed, an increase in read latency can be suppressed.

[0225] Thus, according to the second embodiment, it is possible to achieve both improved write throughput compared to interrupting the programming process each time a read request is received and improved read latency compared to executing the read process after the programming process is completed. Thus, similar to the first embodiment, a means of adjusting the trade-off between write throughput and read latency can be provided.

[0226] In addition, in the second embodiment, the case where both the first and second hang determination processes are executed is described, but the embodiment is not limited to this. For example, the memory controller 20 may execute the first hang determination process without executing the second hang determination process. The memory controller 20 may also execute the second hang determination process without executing the first hang determination process.

[0227] 2.7 Modification of the Second Embodiment

[0228] In the second embodiment described above, the memory controller 20 is described as setting a suspend prohibition period, but the embodiment is not limited to this. For example, even during the suspend prohibition period, if the number of read requests in the command queue 25 is greater than a threshold, the memory controller 20 may execute suspend processing. In the following description, the description of the same configurations and operations as those in the second embodiment is omitted, and the description of the configurations and operations that differ from those in the second embodiment will be focused on.

[0229] 2.7.1 Suspend Determination Processing

[0230] Figure 16 This is a flowchart showing an example of a series of processes including the second hang determination process in a memory system according to a modification of the second embodiment. Figure 16 The example shows that in reference Figure 14 The following describes a case where the processes of S40 - 1 and S40 - 2 are executed instead of the process of S40 in a series of processes of the second embodiment.

[0231] When there are a threshold value N or more read requests in the command queue 25 ( S40 - 1 ; true), the memory controller 20 stops the timer 26 ( S41 ).

[0232] If there are not more than the threshold N read requests in the command queue 25 ( S40 - 1 ; false), the memory controller 20 determines whether there is a read request in the command queue 25 and whether the measured value of the timer 26 is greater than or equal to the threshold T3 ( S40 - 2 ).

[0233] When a read request is received in the command queue 25 and the measured value of the timer 26 is equal to or greater than the threshold value T3 ( S40 - 2 ; true), the memory controller 20 stops the timer 26 ( S41 ).

[0234] If there is no read request in the command queue 25 or the measured value of the timer 26 is smaller than the threshold value T3 ( S40 - 2 ; false), the timer 26 maintains the measuring state and a series of processes including the second hang determination process are completed (End).

[0235] Since the processing after S42 is Figure 14 The processing after S42 is the same, so the description is omitted.

[0236] 2.7.2 State Transition in Programming Processing Accompanied by Second Suspend Decision Processing

[0237] Figure 17 1 is a timing chart showing an example of state transition in a program process accompanied by a second hang determination process in a memory system according to a modification of the second embodiment. Figure 17 In the example, Figure 15 Similarly, as an example Figure 13 An example of processing after time t37 is shown as a continuation of the example of . Figure 17 The example of FIG. 1 shows a case where the number of read requests in the command queue 25 reaches the threshold value N (=2) in the second measurement and the suspend process is executed before the measured value of the timer 26 reaches the threshold value T3.

[0238] like Figure 17 As shown, at time t38, the memory controller 20 receives the third read request. As a result, the number of read requests in the command queue 25 becomes one less than the threshold value N. Therefore, the state of the memory system 3 becomes the pending processing state STS22.

[0239] At time t39, the memory controller 20 receives the fourth read request. As a result, the number of read requests in the command queue 25 reaches two. At this point, although the value measured by the timer 26 is less than the threshold value T3, the number of read requests exceeds the threshold value N. Therefore, the memory controller 20 stops the timer 26. The memory controller 20 then suspends the execution of the nonvolatile memory 10. Consequently, the memory system 3 enters the suspended state STS31.

[0240] At time t40, the measured value of the timer 26 reaches the threshold value T3. Figure 15 The same process from time t41 to t45 is performed by advancing the time period ΔT (= t40 - t39). The memory controller 20 then confirms through a status read process that the data has been written to the nonvolatile memory 10 without any problems. As a result, the state of the memory system 3 returns to the no-wait read request state STS11.

[0241] 2.7.3 Effects of Modifications of the Second Embodiment

[0242] According to the modified example of the second embodiment, the memory controller 20 executes the suspend process when the number of read requests in the command queue 25 reaches or exceeds the threshold value N, regardless of whether the value measured by the timer 26 is or exceeds the threshold value T3. This makes it possible to adjust the trade-off between write throughput and read latency while suppressing increases in read latency.

[0243] In addition, in the modified example of the second embodiment, a case is described in which a determination process related to the number of read requests is added to the second suspend determination process in the second embodiment, but the embodiment is not limited to this. For example, a determination process related to the number of read requests may also be added to the first suspend determination process in the second embodiment. In other words, the memory controller 20 may cause the non-volatile memory 10 to execute the suspend process after N or more read requests have accumulated in the command queue 25, regardless of whether the suspend prohibition period starting from the start of the programming process has passed. In this way, even if the timer 26 measures the elapsed time from the start of the programming process, the same effect as the modified example of the second embodiment can be achieved.

[0244] 3. Third Implementation

[0245] Next, a memory system according to a third embodiment will be described. The third embodiment differs from the first and second embodiments in that the execution timing of the suspend process is controlled so that the read process is actively executed in parallel with the nonvolatile memory 10 while the programming process is interrupted. In the following description, the same configurations and operations as those in the first embodiment are omitted, and the configurations and operations that differ from those in the first embodiment are mainly described.

[0246] 3.1 Composition of Non-Volatile Memory

[0247] Figure 18 1 is a block diagram showing an example of the configuration of a nonvolatile memory according to the third embodiment. Figure 18 As shown, the nonvolatile memory 10 includes a plurality of planes PB (PB0, ..., PBm) (m is an integer greater than or equal to 1). Each of the plurality of planes PB includes a plurality of memory cell transistors. The plurality of planes PB can operate in parallel with each other.

[0248] 3.2 Suspend determination processing

[0249] Figure 19 This is a flowchart showing an example of a series of processes including a hang determination process in the memory system of the third embodiment. Figure 4 Similarly, in the example Figure 19 In the example of FIG. 2 , the start condition of the hang determination process is that the memory controller 20 receives a read request from the host device 2 .

[0250] Due to the processing of S50 and S51 Figure 4 The processing of S10 and S11 is the same, so the description is omitted.

[0251] When the program process is in progress ( S50 ; true), the memory controller 20 determines whether a suspend condition is satisfied ( S52 ). Figure 19 In the example, the suspension condition is that there are at least a threshold value L of read requests for M different planes PB in the command queue 25. The number M is an integer greater than or equal to 2 and less than or equal to (m+1) (2≤M≤m+1). The number M may be equal to or different from the number of planes (m+1) included in the nonvolatile memory 10. The threshold value L is an integer greater than or equal to 1 (L≥1).

[0252] If the number of read requests for at least one of the M planes PB in the command queue 25 is less than or equal to the threshold value L (S52: False), the memory controller 20 maintains the interruption of the program process. In other words, the memory controller 20 does not interrupt the program process. This completes the series of processes, including the hang determination process (End).

[0253] When there are more than the threshold value L of read requests for the different M planes PB in the command queue 25 ( S52 ; true), the memory controller 20 causes the nonvolatile memory 10 to execute the suspend process ( S53 ).

[0254] After the program process is interrupted by the suspend process, the memory controller 20 causes the nonvolatile memory 10 to perform a read process based on the read request (S54). The nonvolatile memory 10 performs read processes on different M-planes in parallel.

[0255] Every time the process of S54 is completed, the memory controller 20 determines whether or not a read request still exists in the command queue 25 ( S55 ).

[0256] If there are still read requests in the command queue 25 (S55; true), the memory controller 20 causes the nonvolatile memory 10 to execute a read process based on the read request (S54). If there are read requests for at least two planes PB in the command queue 25, the memory controller 20 may also execute the read process for the two or more planes PB in parallel. If there is only a read request for one plane PB in the command queue 25, the nonvolatile memory 10 may also execute the read process for the one plane PB. Thus, the processes of S54 and S55 are repeated until the read processes corresponding to all read requests in the command queue 25 are executed.

[0257] When there is no read request in the command queue 25 ( S55 ; false), the memory controller 20 causes the nonvolatile memory 10 to execute a restore process ( S56 ).

[0258] When the process of S56 is completed, a series of processes including the hang determination process is completed (END).

[0259] 3.3 State Transitions in Programming Processing Accompanied by Suspend Decision Processing

[0260] Figure 20 1 is a timing chart showing an example of state transition in the programming process accompanied by the hang determination process of the memory system according to the third embodiment. Figure 20 In the example of , the threshold L is 1 and the number M is 2. Figure 20 In the example shown in FIG. 2 , before time t50 , the state of the memory system 3 is the no-waiting read request state STS11 .

[0261] like Figure 20As shown, at time t50, the memory controller 20 executes the program processing in parallel on the planes PB0 and PB1 of the nonvolatile memory 10. Along with this, the state of the memory system 3 enters the no-wait read request state STS21.

[0262] At time t51, the memory controller 20 receives the first read request (PB0) requesting to read from plane PB0. Consequently, the number of read requests in the command queue 25 for plane PB0 reaches the threshold value L (=1). However, the number of read requests in the command queue 25 for plane PB1 is 0, which is less than the threshold value L (=1). Consequently, the memory system 3 enters the pending processing state STS22.

[0263] At time t52, the memory controller 20 receives a second read request (PB1) requesting to read from plane PB1. Consequently, the number of read requests in the command queue 25 reaches the threshold value L (=1) for each of planes PB0 and PB1. Consequently, the memory controller 20 causes the nonvolatile memory 10 to execute a suspend process. Consequently, the memory system 3 enters the suspend process state STS31.

[0264] At time t53, the suspend process ends. The memory controller 20 then causes the nonvolatile memory 10 to execute the first read process (PB0) on plane PB0. Furthermore, the memory controller 20 causes the nonvolatile memory 10 to execute the second read process (PB1) on plane PB1 in parallel with the first read process (PB0). Consequently, the memory system 3 enters the read-in-progress state STS32.

[0265] At time t54, the first read process (PB0) and the second read process (PB1) are completed. After confirming that the number of read requests in the command queue 25 is 0, the memory controller 20 causes the nonvolatile memory 10 to execute the recovery process. Consequently, the memory system 3 enters the recovery process state STS33.

[0266] At time t55, the recovery process ends. Then, the memory controller 20 restarts the parallel programming process for the planes PB0 and PB1 of the nonvolatile memory 10. As a result, the state of the memory system 3 enters the no-wait read request state STS21.

[0267] At time t56, the programming process ends. Thereafter, the memory controller 20 confirms, through a status read process, that the data has been written without any problems into the nonvolatile memory 10. As a result, the state of the memory system 3 returns to the no-wait read request state STS11.

[0268] 3.4 Effects of the Third Implementation

[0269] According to the third embodiment, the memory controller 20 retains suspended processing until the number of read requests for M different plane PBs within the command queue 25 reaches a threshold value L or more. This allows the memory controller 20 to simultaneously execute the threshold value L or more read processing for each of the M plane PBs during a single interruption of programming processing. Consequently, compared to interrupting programming processing each time a read request for a plane PB is received, the number of suspended and resumed processing can be reduced. Consequently, compared to interrupting programming processing each time a read request for a plane PB is received, cumulative overhead can be reduced, and a decrease in write throughput can be suppressed.

[0270] Furthermore, according to the third embodiment, the memory controller 20 executes a suspend process when the number of read requests for M different planes PB within the command queue 25 is greater than or equal to the threshold value L. Thus, if the suspend condition is satisfied, the memory controller 20 can execute the read process without waiting for the completion of the programming process. Consequently, compared to executing the read process after the programming process is completed, the time required from receiving the read request to the completion of the read process can be shortened. Consequently, compared to executing the read process after the programming process is completed, an increase in read latency can be suppressed.

[0271] Thus, according to the third embodiment, it is possible to achieve both improved write throughput compared to interrupting the programming process each time a read request is received, and improved read latency compared to executing the read process after the programming process is completed. Thus, a means of adjusting the trade-off between write throughput and read latency can be provided.

[0272] When programming is interrupted each time a read request is received for a plane PB, the M plane PBs will have two types: one that performs the read process and one that does not. The plane PB that does not perform the read process enters a standby state until the read process for the other plane PBs is completed. This significantly reduces the operating rate of the non-volatile memory 10 and is not preferred. According to the third embodiment, at least L parallel read processes based on the M plane PBs are performed during one interruption of programming. This can suppress a reduction in the operating rate of the non-volatile memory 10.

[0273] 3.5 First Modification of the Third Embodiment

[0274] In the third embodiment described above, the memory controller 20 reserves the suspended processing until a threshold number L or more of read requests are accumulated in the command queue 25 for each of the M planes PB. However, the embodiment is not limited to this. For example, the memory controller 20 may control the period of the reserved suspended processing based on the elapsed time from the receipt of the first read request, as in the modified example of the first embodiment. That is, in the first modified example of the third embodiment, the timer 26 measures the elapsed time from the state of the memory system 3 entering the suspended processing reserved state STS22 upon receipt of the read request. In the following description, the description of the same configuration and operation as in the modified example of the first embodiment and the third embodiment is omitted, and the description of the configuration and operation that differ from the modified example of the first embodiment and the third embodiment will be focused on.

[0275] 3.5.1 Suspend Determination Processing

[0276] Figure 21 This is a flowchart showing an example of a series of processes including a hang determination process in a memory system according to a first modification of the third embodiment. Figure 21 In the example, Figure 9 Similar to the example of , the start condition of the hang determination process is that the memory controller 20 receives a read request from the host device 2 or the measured value of the timer 26 is greater than or equal to the threshold value T1.

[0277] Due to the processing of S60 and S61 Figure 9 The processing of S20 and S21 is the same, so the description is omitted.

[0278] When the program process is in progress ( S60 ; true), the memory controller 20 determines whether a suspend condition is satisfied ( S62 ). Figure 21 The suspension condition in the example is that there are more than a threshold value L of read requests for M different planes PB in the command queue 25, or the measured value of the timer 26 is more than a threshold value T1.

[0279] If the number of read requests received for at least one plane PB is less than the threshold value L and the count value is less than the threshold value T1 (S62: False), the memory controller 20 maintains the interruption of the program process. In other words, the memory controller 20 does not interrupt the program process. The memory controller 20 then determines whether there is only one read request in the command queue 25 and whether the timer 26 is currently stopped (S63).

[0280] When there is one read request in the command queue 25 and the timer 26 is stopped ( S63 ; true), the memory controller 20 starts the timer 26 ( S64 ).

[0281] When the process of S64 is completed, the timer 26 maintains the measuring state, and a series of processes including the hang determination process are completed (end).

[0282] When the number of read requests for the M planes PB is equal to or greater than the threshold value L, or the measured value of the timer 26 is equal to or greater than the threshold value T1 ( S62 ; true), the memory controller 20 stops the timer 26 ( S65 ).

[0283] After stopping the timer 26, the memory controller 20 causes the nonvolatile memory 10 to execute the suspend process (S66).

[0284] After the programming process is interrupted by the suspend process, the memory controller 20 causes the nonvolatile memory 10 to execute a read process based on the read request (S67). If there are read requests for at least two or more planes PB in the command queue 25, the memory controller 20 may execute the read process for the two or more planes PB in parallel. If there is only a read request for one plane PB in the command queue 25, the memory controller 20 may execute the read process for the one plane PB.

[0285] Every time the process of S67 is completed, the memory controller 20 determines whether or not a read request still exists in the command queue 25 ( S68 ).

[0286] If there are still read requests in the command queue 25 (S68; true), the memory controller 20 causes the nonvolatile memory 10 to execute a read process based on the read request (S67). If there are read requests for at least two planes PB in the command queue 25, the memory controller 20 may also execute the read process for the two or more planes PB in parallel. If there is only a read request for one plane PB in the command queue 25, the nonvolatile memory 10 may also execute the read process for the one plane PB. Thus, the processes of S67 and S68 are repeated until the read processes corresponding to all read requests in the command queue 25 are executed.

[0287] When there is no read request in the command queue 25 ( S68 ; false), the memory controller 20 causes the nonvolatile memory 10 to execute a restore process ( S69 ).

[0288] When the process of S69 is completed, the timer 26 maintains the stopped state, and a series of processes including the hang determination process are completed (end).

[0289] 3.5.2 State Transitions in Programming Processing Accompanied by Suspend Decision Processing

[0290] Figure 22This is a timing chart showing an example of state transition in a program process accompanied by a hang determination process in a memory system according to a first modification of the third embodiment. Figure 22 In the example of FIG, the case where the suspend process is executed when the measured value of the timer 26 reaches the threshold value T1 before the number of read requests for each of the M planes PB reaches the threshold value L is shown. Figure 22 In the example of , the threshold L is 1 and the number M is 2. Figure 22 In the example shown in FIG. 2 , before time t60 , the state of the memory system 3 is the no-waiting-read-request state STS11 .

[0291] like Figure 22 As shown, at time t60, the memory controller 20 executes the program processing in parallel on the planes PB0 and PB1 of the nonvolatile memory 10. Along with this, the state of the memory system 3 enters the no-wait read request state STS21.

[0292] At time t61, the memory controller 20 receives the first read request (PB0). Consequently, the number of read requests in the command queue 25 for plane PB0 becomes L (=1). However, the number of read requests in the command queue 25 for plane PB1 is 0, which is less than the threshold value L (=1). Consequently, the state of the memory system 3 enters the pending processing state STS22. In response to receipt of the first read request (PB0), the memory controller 20 starts the timer 26.

[0293] At time t62, the measured value of the timer 26 reaches the threshold value T1. The memory controller 20 stops the timer 26. Thereafter, the memory controller 20 causes the nonvolatile memory 10 to execute the suspend process. Accordingly, the state of the memory system 3 enters the suspend process state STS31.

[0294] At time t63, the suspend process is terminated without receiving a read request for plane PB1. The memory controller 20 then causes the nonvolatile memory 10 to execute the first read process (PB0). Consequently, the memory system 3 enters the read-in-progress state STS32.

[0295] At time t64, the first read process (PB0) ends. After confirming that the number of read requests in the command queue 25 is 0, the memory controller 20 causes the nonvolatile memory 10 to execute the recovery process. As a result, the memory system 3 enters the recovery process state STS33.

[0296] At time t65, the recovery process ends. Then, the memory controller 20 restarts the parallel programming process for the planes PB0 and PB1 of the nonvolatile memory 10. As a result, the state of the memory system 3 enters the no-wait read request state STS21.

[0297] At time t66, the programming process ends. Thereafter, the memory controller 20 confirms, through a status read process, that the data has been written without any problems into the nonvolatile memory 10. As a result, the state of the memory system 3 returns to the no-wait read request state STS11.

[0298] 3.5.3 Effects of the First Modification of the Third Embodiment

[0299] According to the first variation of the third embodiment, the memory controller 20 activates the timer 26 in response to the first read request being stored after the command queue 25 enters the no-waiting-read-request state STS11. When the measured value of the timer 26 reaches the threshold value T1, the memory controller 20 executes the suspend process regardless of whether the number of read requests for each of the M planes PB in the command queue 25 is greater than or equal to the threshold value L. Consequently, the memory controller 20, having received a read request, can execute the suspend process while within the threshold value T1. This achieves the effects described in the third embodiment and suppresses increases in read latency when no subsequent read requests are received.

[0300] 3.6 Second Modification of the Third Embodiment

[0301] The memory controller 20 may also control the duration of the retention suspension process based on the total number of unexecuted read requests, regardless of whether a read request for each of the M planes PB is received. In the following description, the description of the same configuration and operation as the third embodiment is omitted, and the description of the configuration and operation different from the third embodiment is mainly focused on.

[0302] 3.6.1 Suspend determination processing

[0303] Figure 23 This is a flowchart showing an example of a series of processes including a hang determination process in a memory system according to a second modification of the third embodiment. Figure 19 Same as the example, in Figure 23 In the example of FIG. 2 , the start condition of the hang determination process is that the memory controller 20 receives a read request from the host device 2 .

[0304] Due to the processing of S70 and S71 Figure 19 The processing of S50 and S51 is the same, so the description is omitted.

[0305] When the program process is in progress ( S70 ; true), the memory controller 20 determines whether a suspend condition is satisfied ( S72 ). Figure 23 The suspension condition in the example is that there are more than a threshold value L of read requests for different M planes PB in the command queue 25, or there are more than a threshold value N read requests in the command queue 25.

[0306] In addition, although Figure 18 Although not specifically illustrated in the figures, the nonvolatile memory 10 may have multiple chips. In this case, each of the multiple chips includes multiple planes PB0 to PBm. When the nonvolatile memory 10 has multiple chips, the memory controller 20 has a command queue 25 for each chip. Then, in S72, the memory controller 20 determines whether the number of read requests in the command queue 25 corresponding to the chip being determined is greater than or equal to a threshold value N.

[0307] If the number of read requests for at least one of the M planes PB in the command queue 25 is less than or equal to the threshold value L, and the number of read requests in the command queue 25 is less than or equal to the threshold value N (S72: False), the memory controller 20 maintains the interruption of the programming process. In other words, the memory controller 20 does not interrupt the programming process. This completes the series of processes, including the hang determination process (End).

[0308] When there are more than a threshold value L of read requests for M planes PB in the command queue 25, or when there are more than a threshold value N of read requests in the command queue 25 (S72; true), the memory controller 20 causes the nonvolatile memory 10 to perform suspend processing (S73).

[0309] Due to the processing of S74~S76 and Figure 19 The processing of S54 to S56 is the same, so the description is omitted.

[0310] 3.6.2 State Transitions in Programming Processing Accompanied by Suspend Decision Processing

[0311] Figure 24 This is a timing chart showing an example of state transition in the programming process accompanied by the hang determination process of the memory system according to the second modification of the third embodiment. Figure 24 In the example of FIG, the case where the suspend process is executed by the number of read requests in the command queue 25 reaching the threshold value N before the number of read requests for M planes PB reaches the threshold value L respectively. Figure 24 In the example of , the case where the threshold value N is 2 and the threshold value L is 1 is shown. Figure 24 In the example shown in FIG. 2 , before time t70 , the state of the memory system 3 is the no-waiting read request state STS11 .

[0312] like Figure 24 As shown, at time t70, the memory controller 20 executes the program processing in parallel on the planes PB0 and PB1 of the nonvolatile memory 10. Along with this, the state of the memory system 3 enters the no-wait read request state STS21.

[0313] At time t71, the memory controller 20 receives the first read request (PB0). Consequently, the number of read requests in the command queue 25 for plane PB0 becomes L (=1). However, the number of read requests in the command queue 25 for plane PB1 becomes 0, which is less than the threshold value L (=1). Consequently, the memory system 3 enters the pending processing state STS22.

[0314] At time t72, the memory controller 20 receives a second read request (PB0) requesting to read from plane PB0. This brings the total number of read requests in the command queue 25 to the threshold value N (=2). Consequently, the memory controller 20 causes the nonvolatile memory 10 to execute a suspend process. Consequently, the memory system 3 enters the suspend state STS31.

[0315] At time t73, the suspend process ends. Then, the memory controller 20 causes the nonvolatile memory 10 to execute the first read process (PB0). As a result, the state of the memory system 3 changes to the read-in-progress state STS32.

[0316] At time t74, the first read process (PB0) ends. Then, the memory controller 20 causes the nonvolatile memory 10 to execute the second read process (PB0) on the plane PB0. The memory system 3 maintains the read-in-progress state STS32.

[0317] At time t75, the second read process (PB0) ends. After confirming that the number of read requests in the command queue 25 is 0, the memory controller 20 causes the nonvolatile memory 10 to execute the recovery process. As a result, the memory system 3 enters the recovery process state STS33.

[0318] At time t76, the recovery process ends. Then, the memory controller 20 restarts the parallel programming process for the planes PB0 and PB1 of the nonvolatile memory 10. As a result, the state of the memory system 3 enters the no-wait read request state STS21.

[0319] At time t77, the programming process ends. Thereafter, the memory controller 20 confirms, through a status read process, that the data has been written without any problems into the nonvolatile memory 10. As a result, the state of the memory system 3 returns to the no-wait read request state STS11.

[0320] 3.6.3 Effects of the Second Modification of the Third Embodiment

[0321] According to the second variation of the third embodiment, when the number of read requests in the command queue 25 reaches a threshold value N, the memory controller 20 performs a suspend process regardless of whether the number of read requests for each of the M planes PB is greater than or equal to a threshold value L. Thus, the memory controller 20 can perform a suspend process even if read requests for the M planes PB are not received evenly. This achieves the effects described in the third embodiment and suppresses increases in read latency that would otherwise occur if there were variations in the planes PB targeted by the read requests.

[0322] 4. Fourth Implementation

[0323] Next, a memory system according to a fourth embodiment will be described. The fourth embodiment differs from the first through third embodiments in that the timing of executing the resume process is adjusted to reduce the frequency of short interruptions. Specifically, in the fourth embodiment, timer 26 measures the elapsed time since the start or completion of the suspend process. The following description will omit the same configuration and operations as those in the modified example of the first embodiment, and will focus on the configuration and operations that differ from those in the modified example of the first embodiment.

[0324] 4.1 Programming Processing

[0325] Figure 25 This is a flowchart showing an example of a series of processes including a program process in the memory system according to the fourth embodiment.

[0326] When the program conditions are met (start), the memory controller 20 causes the nonvolatile memory 10 to execute a program process accompanied by a resume determination process (S5). The resume determination process determines whether to execute the resume process based on whether the resume conditions are met. By adjusting the timing of executing the resume process, the memory controller 20 can adjust the trade-off between read latency and write throughput.

[0327] When the program process accompanying the recovery determination process is completed, the memory controller 20 causes the nonvolatile memory 10 to execute a status read process ( S6 ).

[0328] When the memory controller 20 receives a status indicating that the programming process has been completed from the nonvolatile memory 10 in the process of S6 , a series of processes including the programming process ends (END).

[0329] 4.2 Recovery determination processing

[0330] Figure 26This is a flowchart showing an example of a series of processes including the recovery determination process in the memory system of the fourth embodiment. The series of processes including the recovery determination process are executed according to the start conditions of the recovery determination process. Figure 26 In the example of , the start condition of the resume determination process is that the suspension condition is satisfied. The suspension condition can be any of the suspension conditions including the examples in the description of the first to third embodiments. In addition, the suspension condition may be unconditional.

[0331] When the suspend condition is satisfied (START), the memory controller 20 starts the timer 26 (S80).

[0332] When the timer 26 starts counting, the memory controller 20 causes the nonvolatile memory 10 to execute the suspend process (S81). Alternatively, the memory controller 20 may start the timer 26 after the suspend process is completed.

[0333] After interrupting the program process through the suspend process, the memory controller 20 causes the nonvolatile memory 10 to perform a read process based on the read request ( S82 ).

[0334] When the read process is completed, the memory controller 20 waits until a new read request is received from the host device 2 or the measured value of the timer 26 becomes equal to or greater than a threshold value T4 ( S83 ). The threshold value T4 is a positive real number.

[0335] When the standby process of S83 is completed, the memory controller 20 determines whether or not there is still a read request in the command queue 25 ( S84 ).

[0336] If there are still read requests in the command queue 25 (S84; true), the memory controller 20 causes the nonvolatile memory 10 to execute a read process based on the read request (S82). Thus, the processes of S82 to S84 are repeated until the read processes corresponding to all the read requests in the command queue 25 are executed.

[0337] If there is no read request in the command queue 25 (S84; false), the memory controller 20 decides to restart the programming process. Then, the memory controller 20 stops the timer 26 (S85). Figure 26 The recovery condition in the example is that the measured value of the timer 26 is greater than or equal to the threshold value T4 and there is no unexecuted read request.

[0338] After stopping the timer 26 , the memory controller 20 causes the nonvolatile memory 10 to execute a recovery process ( S86 ).

[0339] When the process of S86 is completed, a series of processes including the restoration determination process is completed (END).

[0340] 4.3 State Transition of Memory System

[0341] Figure 27 1 is a state transition diagram showing the relationship between a plurality of states related to a program process of the memory system according to the fourth embodiment.

[0342] First, a description will be given of the various states that the memory system 3 can assume.

[0343] like Figure 27 As shown, the states of the memory system 3 related to the programming process include a program ready state STS1, a program busy state STS2, and a program suspended state STS3. Figure 5 The first embodiment described is the same, so the description is omitted.

[0344] The program suspension state STS3 includes a resume processing pending state STS34 in addition to the suspend processing state STS31, the read processing state STS32, and the resume processing state STS33. The resume processing pending state STS34 is a state in which the start of the resume process is pending.

[0345] Next, the events that cause each state transition will be described.

[0346] Regarding the events of E1 to E11 and E13, and reference Figure 5 The first embodiment described is the same, so the description is omitted.

[0347] When the read processing corresponding to all read requests in the command queue 25 is completed (E12A), the memory system 3 transitions to the resume processing state STS34. When a further read request is received from the host device 2 in the resume processing state STS34 (E14), the memory system 3 transitions to the read processing state STS32. If the resume condition is not met (E15), the memory system 3 remains in the resume processing state STS34. If the resume condition is met in the resume processing state STS34 (E16), the memory system 3 transitions to the resume processing state STS33.

[0348] 4.4 State Transitions in Programming Processing Accompanied by Recovery Decision Processing

[0349] Figure 28 1 is a timing chart showing an example of state transition in the programming process accompanied by the recovery determination process of the memory system according to the fourth embodiment. Figure 28The example of FIG. 1 shows a case where a second read request is received after the first read process is completed and before the measured value of the timer 26 reaches the threshold value T4 during the interruption of the programming process.

[0350] like Figure 28 As shown, at time t80, the memory controller 20 receives the first read request, and accordingly, the state of the memory system 3 changes from the no-waiting-read-request state STS21 to the pending-processing-reserved state STS22.

[0351] At time t81, the memory controller 20 activates the timer 26 in response to the suspend condition being met. Furthermore, the memory controller 20 causes the nonvolatile memory 10 to execute the suspend process. Consequently, the memory system 3 enters the suspend process state STS31. Alternatively, the memory controller 20 may activate the timer 26 after the suspend process is completed.

[0352] At time t82, the suspend process ends. The memory controller 20 causes the nonvolatile memory 10 to execute the first read process. As a result, the state of the memory system 3 changes to the read-in-progress state STS32.

[0353] At time t83, the first read process ends, and accordingly, the state of the memory system 3 changes to the recovery process pending state STS34.

[0354] At time t84, the memory controller 20 receives the second read request. At this time, the value measured by the timer 26 is less than the threshold value T4. Therefore, the memory controller 20 causes the nonvolatile memory 10 to execute the second read process. Consequently, the state of the memory system 3 enters the read-in-progress state STS32.

[0355] At time t85, the second read process ends, and accordingly, the state of the memory system 3 changes to the recovery process pending state STS34.

[0356] At time t86, the measured value of the timer 26 reaches the threshold value T4. The memory controller 20 stops the timer 26. Thereafter, the memory controller 20 causes the nonvolatile memory 10 to execute the recovery process. Accordingly, the state of the memory system 3 enters the recovery process state STS33.

[0357] At time t87, the recovery process ends. Then, the memory controller 20 restarts the programming process of the nonvolatile memory 10. As a result, the state of the memory system 3 returns to the no-wait read request state STS21.

[0358] 4.5 Effects of the Fourth Implementation

[0359] According to the fourth embodiment, the memory controller 20 holds the resume process until the time elapsed from the start or completion of the suspend process exceeds threshold value T4, regardless of whether a read request exists in the command queue 25. This allows for a resume prohibition period to be set that prevents the resume process from being executed immediately after a read request disappears from the command queue 25. Consequently, the memory controller 20 can execute a read process during the same interruption period, based on read requests received between the time when no more read requests exist in the command queue 25 and the time when the timer 26 reaches threshold value T4. Thus, according to the fourth embodiment, compared to executing the resume process immediately after a read request disappears from the command queue 25, an increase in the number of interruptions occurring during a single programming process can be suppressed. Consequently, an increase in read latency can be suppressed, primarily for read processes executed the second or later of an interruption in the programming process.

[0360] According to the fourth embodiment, by appropriately setting the threshold T4, the duration of the recovery processing pending state STS34 can be shortened compared to the cumulative overhead of executing the recovery process immediately after the read request disappears from the command queue 25. This can suppress a decrease in write throughput.

[0361] The resume determination process can be executed independently of the suspend determination process. Therefore, the fourth embodiment can be combined with the first to third embodiments. Thus, in addition to the effects of the first to third embodiments, the effects of the fourth embodiment can also be achieved.

[0362] 4.6 Modification of the Fourth Embodiment

[0363] While the fourth embodiment described above describes a case where the memory controller 20 controls the duration of the hold resume process based on the time elapsed since the start or completion of the suspend process, the embodiment is not limited to this. For example, the memory controller 20 may also control the duration of the hold resume process based on the time elapsed since the completion of the read process within the suspend process. Specifically, in a variation of the fourth embodiment, the timer 26 measures the time elapsed since the completion of the read process executed when the memory system 3 is in the program suspend state STS3. In the following description, descriptions of the same configurations and operations as those in the fourth embodiment are omitted, and the description will focus on the configurations and operations that differ from those in the fourth embodiment.

[0364] 4.6.1 Recovery determination process

[0365] Figure 29 This is a flowchart showing an example of a series of processes including a recovery determination process in a memory system according to a modification of the fourth embodiment.

[0366] When the suspend condition is satisfied (start), the memory controller 20 causes the nonvolatile memory 10 to execute a suspend process ( S90 ).

[0367] After interrupting the program process through the suspend process, the memory controller 20 causes the nonvolatile memory 10 to perform a read process based on the read request ( S91 ).

[0368] When the read process is completed, the memory controller 20 starts the timer 26 ( S92 ).

[0369] When the timer 26 starts measuring, the memory controller 20 waits until a new read request is received from the host device 2 or the measured value of the timer 26 becomes equal to or greater than a threshold value T5 ( S93 ). The threshold value T5 is a positive real number.

[0370] When the standby process of S93 is completed, the memory controller 20 determines whether or not there is still a read request in the command queue 25 ( S94 ).

[0371] When a read request still exists in the command queue 25 ( S94 ; true), the memory controller 20 stops the timer 26 ( S95 ).

[0372] After stopping the timer 26, the memory controller 20 causes the nonvolatile memory 10 to execute a read process based on the read request (S91). Thus, the processes of S91 to S95 are repeated until the read processes corresponding to all the read requests in the command queue 25 are executed.

[0373] If there is no read request in the command queue 25 (S94; false), the memory controller 20 decides to restart the programming process. Then, the memory controller 20 stops the timer 26 (S96). Figure 29 The recovery condition in the example is that the measured value of the timer 26 is greater than or equal to the threshold value T5 and there is no unexecuted read request.

[0374] After stopping the timer 26 , the memory controller 20 causes the nonvolatile memory 10 to execute a recovery process ( S97 ).

[0375] When the process of S97 is completed, a series of processes including the restoration determination process is completed (END).

[0376] 4.6.2 State Transitions in Programming Processing Accompanied by Recovery Decision Processing

[0377] Figure 30 1 is a timing chart showing an example of state transition in a program process accompanied by a recovery determination process in a memory system according to a modification of the fourth embodiment. Figure 30The example of FIG. 1 shows a case where a second read request is received after the first read process is completed and before the measured value of the timer 26 reaches the threshold value T5 during the interruption of the programming process.

[0378] like Figure 30 As shown, at time t90, the memory controller 20 receives the first read request, and accordingly, the state of the memory system 3 changes from the no-waiting-read-request state STS21 to the pending-processing-reserved state STS22.

[0379] At time t91, in response to the suspend condition being satisfied, the memory controller 20 causes the nonvolatile memory 10 to execute the suspend process. Accordingly, the state of the memory system 3 enters the suspend-processing state STS31.

[0380] At time t92, the suspend process ends. The memory controller 20 causes the nonvolatile memory 10 to execute the first read process. As a result, the state of the memory system 3 changes to the read-in-progress state STS32.

[0381] At time t93, the first read process ends, and the memory system 3 enters the recovery process hold state STS34. The memory controller 20 starts the timer 26.

[0382] At time t94, the memory controller 20 receives the second read request. At this time, the value measured by the timer 26 is less than the threshold value T5. Therefore, the memory controller 20 stops the timer 26 and then causes the nonvolatile memory 10 to execute the second read process. Consequently, the memory system 3 enters the read-in-progress state STS32.

[0383] At time t95, the second read process ends, and the memory system 3 enters the recovery process hold state STS34. The memory controller 20 restarts the timer 26.

[0384] At time t96, the measured value of the timer 26 reaches the threshold value T5. Therefore, the memory controller 20 stops the timer 26 and then causes the nonvolatile memory 10 to execute the recovery process. Accordingly, the state of the memory system 3 enters the recovery process state STS33.

[0385] At time t97, the recovery process ends. Then, the memory controller 20 restarts the programming process of the nonvolatile memory 10. As a result, the state of the memory system 3 returns to the no-wait read request state STS21.

[0386] 4.6.3 Effects of Modifications of the Fourth Embodiment

[0387] According to a variation of the fourth embodiment, the memory controller 20 holds the resume process until the time elapsed from the completion of the read process executed during the suspend process becomes greater than or equal to threshold value T5, regardless of whether a read request exists in the command queue 25. This allows for a resume prohibition period to be set that prevents the resume process from being executed immediately after the read request disappears from the command queue 25. Consequently, the same effects as those of the fourth embodiment can be achieved.

[0388] 5. Fifth Implementation

[0389] Next, the memory system of the fifth embodiment is described. The difference between the fifth embodiment and the first to fourth embodiments is that the control is performed in a manner such that the recovery process is forcibly executed even when there is a read request in the command queue 25. That is, in the fifth embodiment, the timer 26 measures the elapsed time from the start or completion of the suspend process. In the following description, a distinction is made between the recovery process performed when there is a read request in the command queue 25 and the recovery process performed when there is no read request in the command queue 25. The recovery process performed when there is a read request in the command queue 25 is also referred to as "forced recovery process". In the following description, the description of the same structure and action as in the first to fourth embodiments is omitted, and the description of the structure and action different from the first to fourth embodiments is mainly given.

[0390] 5.1 Recovery determination processing

[0391] Figure 31 1 is a flowchart showing an example of a series of processes including a recovery determination process in the memory system of the fifth embodiment. Figure 31 In the example, Figure 26 The same as the example, the start condition of the resumption determination process is that the suspension condition is satisfied.

[0392] Due to the processing of S100~S102 and Figure 26 The processing of S80 to S82 is the same, so the description is omitted.

[0393] When the read process is completed, the memory controller 20 determines whether or not a read request still exists in the command queue 25 ( S103 ).

[0394] If there is still a read request in the command queue 25 (S103; true), the memory controller 20 determines whether the measured value of the timer 26 is equal to or greater than the threshold value T6 (S104). The threshold value T6 is a positive real number.

[0395] If the value measured by the timer 26 is less than the threshold value T6 (S104; false), the memory controller 20 causes the nonvolatile memory 10 to execute a read process based on the read request (S102). Thus, the read process is executed until the value measured by the timer 26 reaches the threshold value T6 or the read request in the command queue 25 disappears.

[0396] When the measured value of the timer 26 is equal to or greater than the threshold value T6 (S104; true), the memory controller 20 causes the nonvolatile memory 10 to execute a forced recovery process (S105). Figure 31 The forced recovery condition in the example is that there is an unexecuted read request and the measured value of the timer 26 is greater than or equal to the threshold value T6.

[0397] When there is no read request from the command queue 25 (S103; false), the memory controller 20 causes the nonvolatile memory 10 to execute the recovery process (S106). Figure 31 The recovery condition in the example is that there are no unexecuted read requests.

[0398] When the recovery process or the forced recovery process ends, the memory controller 20 stops the timer 26 ( S107 ).

[0399] When the process of S107 is completed, a series of processes including the restoration determination process are completed (END).

[0400] 5.2 State Transition of Memory System

[0401] Figure 32 1 is a state transition diagram showing the relationship between a plurality of states related to a program process of the memory system according to the fifth embodiment.

[0402] First, a description will be given of the various states that the memory system 3 can assume.

[0403] like Figure 32 As shown, the states of the memory system 3 related to the programming process include a program ready state STS1, a program busy state STS2, and a program suspended state STS3. Figure 27 The fourth embodiment described is the same, so the description is omitted.

[0404] The program suspension state STS3 includes a forced resumption state STS35 in addition to the suspension state STS31, read state STS32, resume state STS33, and resume hold state STS34. The forced resumption state STS35 is a state in which forced resumption processing is being executed.

[0405] Next, the events that cause each state transition will be described.

[0406] Regarding the events of E1-E11, E12A, E13-E15, and reference Figure 27 The fourth embodiment described is the same, so the description is omitted.

[0407] When the forced recovery condition is satisfied in the read processing state STS32 ( E17 ), the memory system 3 transitions to the forced recovery processing state STS35 .

[0408] When the forced recovery process is completed in the forced recovery process in progress state STS35 (E18), the storage system 3 transitions to the suspend process holding state STS22.

[0409] That is, when the resume processing or the forced resume processing is completed in the program suspend state STS3 ( E13 or E18 ), the memory system 3 transitions to the program busy state STS2 .

[0410] 5.3 State Transitions in Programming Processing Accompanied by Recovery Decision Processing

[0411] Figure 33 1 is a timing chart showing an example of state transition in the programming process accompanied by the recovery determination process of the memory system according to the fifth embodiment. Figure 33 In the example shown in FIG, during the interruption of programming processing, the measured value of the timer 26 reaches the threshold value T6 during the second read processing. In this case, even if a third read request is received during the second read processing, the third read processing is not executed during the same interruption period, and the forced recovery processing is executed.

[0412] because Figure 33 The processing from time t100 to time t104 is as shown in FIG. Figure 28 The processing during the period from time t80 to time t84 shown is the same, and therefore the description thereof is omitted.

[0413] At time t105, the measured value of the timer 26 reaches the threshold value T6. The memory system 3 maintains the read processing state STS32 of the second read process.

[0414] At time t106, the memory controller 20 receives the third read request. The memory system 3 maintains the read-in-progress state STS32 of the second read process.

[0415] At time t107, the second read process ends. At this point, a third read request exists in command queue 25. However, the value measured by timer 26 is greater than threshold value T6. Therefore, memory controller 20 causes nonvolatile memory 10 to execute forced recovery processing. Consequently, the memory system 3 enters the forced recovery processing state STS35.

[0416] At time t108, the forced recovery process ends. Accordingly, the memory controller 20 stops the timer 26 and then restarts the programming process of the nonvolatile memory 10. As a result, the state of the memory system 3 returns to the suspended state STS22.

[0417] Afterwards, although Figure 33 Although not shown in the figure, if the re-suspend condition is satisfied, the memory controller 20 can execute the third read process during the next interruption period of the programming process.

[0418] 5.4 Effects of the Fifth Implementation

[0419] According to the fifth embodiment, when the time elapsed since the start or completion of the suspend process reaches threshold value T6, the memory controller 20 forcibly executes the resume process even if there are read requests remaining in the command queue 25. This prevents excessive extension of the programming process interruption period when a large number of read requests are received at once. Therefore, the trade-off between write throughput and read latency can be adjusted while suppressing an excessive decrease in write throughput.

[0420] Furthermore, according to the fifth embodiment, it is possible to limit the interruption period of the programming process from exceeding the threshold value T6, thereby suppressing the deterioration of the reliability of the nonvolatile memory 10.

[0421] 5.5 Modification of the Fifth Embodiment

[0422] In the fifth embodiment described above, the memory controller 20 controls the start timing of the forced resume process based on the time elapsed since the start or completion of the suspend process. However, the embodiment is not limited to this. For example, the memory controller 20 may also control the start timing of the forced resume process based on the length of the accumulated interruption period during the programming process. That is, in a variation of the fifth embodiment, the timer 26 measures the accumulated interruption period during the programming process. In the following description, the description of the same structures and operations as the fifth embodiment is omitted, and the description of the structures and operations that differ from the fifth embodiment is mainly focused on.

[0423] 5.5.1 Programming Processing

[0424] Figure 34This is a flowchart showing an example of a series of processes including a program process in a memory system according to a modification of the fifth embodiment.

[0425] Due to the processing of S5 and S6 Figure 25 The processing of S5 and S6 is the same, so the description is omitted.

[0426] When receiving a status indicating that the programming process is completed from the nonvolatile memory 10 in the process of S6 , the memory controller 20 determines whether the timer 26 is in the process of measuring ( S7 ).

[0427] If the timer 26 is in the process of measuring (S7; true), the memory controller 20 stops the timer 26 (S8). When the process of S8 is completed, a series of processes including the programming process are completed (end).

[0428] If the timer 26 is not measuring ( S7 ; false), the process of S8 is not executed, and a series of processes including the programming process are completed (END).

[0429] 5.5.2 Recovery determination process

[0430] Figure 35 This is a flowchart showing an example of a series of processes including a recovery determination process in a memory system according to a modification of the fifth embodiment. Figure 35 In the example of FIG, the start condition of the resume determination process is that the suspend condition is satisfied and the measured value of the timer 26 is less than the threshold value T7. The suspend condition can be any suspend condition including the examples described in the first to third embodiments. In addition, the suspend condition can also be unconditional.

[0431] When the suspend condition is satisfied and the measured value of the timer 26 is smaller than the threshold value T7 (start), the memory controller 20 determines whether the timer 26 is suspended ( S110 ).

[0432] If the timer 26 is not suspended (ie, the timer 26 is stopped) ( S110 ; false), the memory controller 20 starts the timer 26 ( S111 ).

[0433] When the timer 26 is suspended ( S110 ; true), the memory controller 20 resumes the measurement of the timer 26 ( S112 ).

[0434] When the timer 26 is in the measuring state, the memory controller 20 causes the nonvolatile memory 10 to execute the suspend process ( S113 ).

[0435] After interrupting the program process through the suspend process, the memory controller 20 causes the nonvolatile memory 10 to perform a read process based on the read request ( S114 ).

[0436] When the read process is completed, the memory controller 20 determines whether a read request still exists in the command queue 25 ( S115 ).

[0437] If there is still a read request in the command queue 25 (S115; true), the memory controller 20 determines whether the measured value of the timer 26 is equal to or greater than the threshold value T7 (S116). The threshold value T7 is a positive real number.

[0438] If the value measured by the timer 26 is less than the threshold value T7 (S116; false), the memory controller 20 causes the nonvolatile memory 10 to execute a read process based on the read request (S114). Thus, the read process is executed until the value measured by the timer 26 reaches the threshold value T7 or the read request in the command queue 25 disappears.

[0439] When the measured value of the timer 26 is greater than or equal to the threshold value T7 (S116; true), the memory controller 20 causes the nonvolatile memory 10 to execute a forced recovery process (S117). Figure 35 The forced recovery condition in the example is that there is an unexecuted read request and the measured value of the timer 26 is greater than or equal to the threshold value T7.

[0440] When there is no read request in the command queue 25 (S115; false), the memory controller 20 causes the nonvolatile memory 10 to execute the recovery process (S118). Figure 35 The recovery condition in the example is that there are no unexecuted read requests.

[0441] When the recovery process or the forced recovery process ends, the memory controller 20 suspends the timer 26 ( S119 ).

[0442] When the process of S119 is completed, a series of processes including the restoration determination process are completed (END).

[0443] In addition, Figure 35 In the example of , the case where the period of execution of the suspend process and the resume process is included in the measurement period of the timer 26 is described, but the embodiment is not limited to this. For example, the period of execution of both the suspend process and the resume process, or the period of execution of either process may also be included in the measurement period of the timer 26. In this case, Figure 35 The process of S113 can be executed before the process of S110. In addition, the process of S119 can be executed between the process of S114 and the process of S115.

[0444] 5.5.3 State Transitions in Programming Processing Accompanied by Recovery Decision Processing

[0445] Figure 36 1 is a timing chart showing an example of state transition in a program process accompanied by a recovery determination process in a memory system according to a modification of the fifth embodiment. Figure 36 In the example of , the case where both the suspend process and the resume process are included in the measurement period of the timer 26 is shown. Figure 36 The example shows a case where the measured value of the timer 26 reaches the threshold value T7 during the second read process. In this case, even if a third read request is received before the end of the second read process, the third read process will not be executed during the same interruption period, and the forced recovery process will be executed. Figure 36 In the example of , the timer 26 stops at time t110 (ie, the measured value is 0).

[0446] like Figure 36 As shown, at time t110, the memory controller 20 receives the first read request, and accordingly, the state of the memory system 3 changes from the no-waiting-read-request state STS21 to the pending-processing-reserved state STS22.

[0447] At time t111, the suspend condition is satisfied. Since the timer 26 is stopped, the memory controller 20 starts the timer 26. The memory controller 20 also causes the nonvolatile memory 10 to execute the suspend process. As a result, the state of the memory system 3 enters the suspend process state STS31.

[0448] At time t112, the suspend process ends. The memory controller 20 causes the nonvolatile memory 10 to execute the first read process. As a result, the state of the memory system 3 enters the read-in-progress state STS32 of the first read process.

[0449] At time t113, the first read process ends. The memory controller 20 causes the nonvolatile memory 10 to execute a restore process. As a result, the state of the memory system 3 enters the restore process state STS33.

[0450] At time t114, the recovery process ends. The memory controller 20 suspends the measurement of the timer 26. As a result, the measured value of the timer 26 becomes T7_1 (= t114 - t111). In addition, the measured value T7_1 is smaller than the threshold value T7. The state of the memory system 3 becomes the read-no-wait state STS21.

[0451] At time t115, the memory controller 20 receives the second read request, and accordingly, the state of the memory system 3 changes to the pending processing state STS22.

[0452] At time t116, the suspend condition is met again. Since timer 26 is suspended, memory controller 20 restarts timer 26. Furthermore, memory controller 20 causes nonvolatile memory 10 to execute the suspend process. Consequently, the state of memory system 3 enters the suspend process state STS31.

[0453] At time t117, the memory controller 20 receives the third read request. The memory system 3 maintains the pending processing state STS31.

[0454] At time t118, the suspend process ends. The memory controller 20 causes the nonvolatile memory 10 to execute the second read process. As a result, the state of the memory system 3 enters the read-in-progress state STS32 of the second read process.

[0455] At time t119, the measured value of the timer 26 reaches the threshold value T7. The memory system 3 maintains the read processing state STS32 of the second read process.

[0456] At time t120, the second read process ends. At this point, a third read request exists in command queue 25. However, the value measured by timer 26 is greater than threshold value T7. Therefore, memory controller 20 causes nonvolatile memory 10 to execute forced recovery processing. Consequently, the memory system 3 enters the forced recovery processing state STS35.

[0457] At time t121, the forced recovery process ends. Accordingly, the memory controller 20 suspends the measurement of the timer 26 and then restarts the programming process of the nonvolatile memory 10. As a result, the state of the memory system 3 returns to the suspended processing state STS22.

[0458] Afterwards, although Figure 36 Although not shown in the figure, even if the suspend condition is satisfied again, the measured value of the timer 26 exceeds the threshold value T7, and therefore the memory controller 20 does not interrupt the program process in order to execute the third read process.

[0459] 5.5.4 Effects of Modifications of the Fifth Embodiment

[0460] According to a variation of the fifth embodiment, when the cumulative duration of interruptions during a programming process reaches a threshold value T7, the memory controller 20 forcibly executes a recovery process even if read requests remain in the command queue 25. This prevents excessive extension of the interruption period during programming when a large number of read requests are received at once. Consequently, the trade-off between write throughput and read latency can be adjusted while suppressing an excessive decrease in write throughput.

[0461] Furthermore, according to the modification of the fifth embodiment, the accumulated time of the interruption period in the one-shot programming process can be restricted from exceeding the threshold value T7. Therefore, it is possible to suppress the deterioration of the reliability of the nonvolatile memory 10.

[0462] 6. Sixth Implementation

[0463] Next, a memory system according to the sixth embodiment will be described. The sixth embodiment differs from the first through fifth embodiments in that a suspend condition or a resume condition (or a forced resume condition) is dynamically adjusted. In the following description, descriptions of configurations and operations identical to those in the first through fifth embodiments are omitted, and the description will focus on configurations and operations that differ from those in the first through fifth embodiments.

[0464] 6.1 Parameter Change Processing

[0465] Figure 37 This is a flowchart showing an example of parameter change processing in the memory system according to the sixth embodiment.

[0466] like Figure 37 As shown, when the observation condition is satisfied (start), the memory controller 20 observes the workload of the memory system 3 (S121).

[0467] The observation conditions may include, for example, conditions that are regularly satisfied, such as “a predetermined time has arrived.” Alternatively, the observation conditions may include, for example, conditions that are irregularly satisfied, such as “a predetermined process has been completed.”

[0468] The workload characteristics include, for example, the number of read requests in the command queue 25 (queue depth (QD) or outstanding I / O (OIO)), the idle period of the memory system 3, and the amount of write data in the buffer memory 22. The idle period refers to a period during which the memory system 3 does not perform processing such as read processing or programming processing in response to a request from the host device 2.

[0469] Based on the workload observed in the process of S121, the memory controller 20 changes the suspend condition and / or resume condition (S122). Changing the suspend condition includes, for example, changing the thresholds N, M, and L and thresholds T1 to T3 described in the first to third embodiments. Changing the resume condition includes, for example, changing the thresholds T4 to T7 described in the fourth and fifth embodiments.

[0470] More specifically, for example, if the number of QDs in a read request is less than a threshold, if the idle time of the memory system 3 is greater than a threshold, or if the amount of write data in the buffer memory 22 is less than a threshold, the memory controller 20 reduces at least one of thresholds N, M, and L, and / or reduces at least one of thresholds T1 to T3. In this case, threshold N may also be 0 or 1. Threshold L may also be 0. Thresholds T1 to T3 may also be 0. If the number of QDs in a read request is less than a threshold, if the idle time of the memory system 3 is greater than a threshold, or if the amount of write data in the buffer memory 22 is less than a threshold, the memory controller 20 increases at least one of thresholds T4 to T7.

[0471] When the process of S122 is completed, the parameter change process ends (END).

[0472] 6.2 Effects of the Sixth Implementation

[0473] According to the sixth embodiment, the memory controller 20 monitors the workload. For example, if the amount of write data in the buffer memory 22 observed as the workload is small, the write throughput request from the host device 2 is expected to be relatively low. Alternatively, if the number of read requests observed as the workload is small, the host device 2 is expected to request a shorter read latency. By monitoring the workload in this way, the memory controller 20 can determine which of the two should be prioritized and adjust the trade-off between write throughput and read latency.

[0474] If the observation results indicate that read latency is prioritized over write throughput, the memory controller 20 reduces at least one of thresholds N, M, and L, reduces at least one of thresholds T1-T3, and / or increases at least one of thresholds T4-T7. This allows the memory controller 20 to dynamically change operations during the operation of the memory system 3 to prioritize read latency. This allows for greater flexibility in the operation of the memory system 3.

[0475] 6.3 Modification of the Sixth Embodiment

[0476] In the sixth embodiment described above, the memory controller 20 autonomously changes the suspend and / or resume conditions. However, the embodiment is not limited thereto. For example, the memory controller 20 may also change the suspend and / or resume conditions based on a request from the host device 2. In the following description, descriptions of the same configurations and operations as those in the sixth embodiment are omitted, and descriptions of the configurations and operations that differ from those in the sixth embodiment are primarily focused on.

[0477] 6.3.1 Parameter Change Processing

[0478] Figure 38 This is a flowchart showing an example of parameter change processing in a memory system according to a modification of the sixth embodiment.

[0479] like Figure 38 As shown, when a parameter change request is received from the host device 2 (start), the memory controller 20 changes the suspend condition and / or the resume condition based on the received parameter change request (S125).

[0480] When the process of S125 is completed, the parameter change process ends (END).

[0481] 6.3.2 Effects of Modifications of the Sixth Embodiment

[0482] According to the modification of the sixth embodiment, the memory controller 20 changes the suspend condition and / or the resume condition based on a request from the host device 2. This enables an operation that better meets the expectations of the host device 2.

[0483] 7. Others

[0484] Various modifications can be applied to the above-described first to sixth embodiments and modifications of each embodiment.

[0485] For example, in the first to sixth embodiments and their variations, the case of interrupting the programming process is described, but the embodiments and variations are not limited thereto. For example, even when interrupting the erasing process instead of the programming process, the embodiments and variations are also applicable.

[0486] Furthermore, for example, in the fifth embodiment and its variations, the forced recovery condition is defined based on the value measured by the timer 26. However, the embodiments and variations are not limited thereto. For example, the memory controller 20 may define the forced recovery condition based on the number X of read requests executed during programming or the amount Y of read data read from the non-volatile memory 10 during programming. Specifically, if there are unexecuted read requests and the number X or the amount Y is greater than a threshold, the memory controller 20 may cause the non-volatile memory 10 to execute a forced recovery process.

[0487] While several embodiments of the present invention have been described, these embodiments are provided as examples and are not intended to limit the scope of the invention. These novel embodiments may be implemented in various other ways, and various omissions, substitutions, and modifications may be made without departing from the spirit of the invention. These embodiments and their variations are intended to be included within the scope and spirit of the invention, and are intended to be included within the scope of the invention as set forth in the claims and their equivalents.

Claims

1. A memory system comprising: non-volatile memory; and The memory controller is configured to cause the nonvolatile memory to execute a first process of reading data based on a first request from a host device. The memory controller is configured to retain an interruption of the second processing when the first request is received from the host device during the period when the non-volatile memory is executing the second processing until a first number of the first requests that have not been executed in the memory controller becomes greater than a first threshold, where the first threshold is an integer greater than 2.

2. The memory system of claim 1, wherein: The memory controller is further configured to interrupt the second process when a first period during which the interruption of the second process is retained becomes equal to or greater than a second threshold value. The first period is a continuous period in which the first number is one or more.

3. The memory system of claim 1, wherein: The memory controller is further configured to interrupt the second process when a second period during which the interruption of the second process is retained becomes equal to or greater than a third threshold and the first number is equal to or greater than 1. The second period is a continuous period during which the second process is being executed and does not include a period during which the second process is being suspended.

4. The memory system of claim 3, wherein: The starting point of the second period is the start of the second process.

5. The memory system of claim 3, wherein: The second period starts at the time of resuming the second process after interruption.

6. The memory system of claim 1, wherein: The memory controller is further configured to, while the second process is interrupted, hold the resumption of the interrupted second process until the third period becomes equal to or greater than a fourth threshold value. The third period is a continuous period during which the second process is suspended.

7. The memory system of claim 1, wherein: The memory controller is configured to, during the second process interruption period, causing the nonvolatile memory to execute the first process, The resumption of the interrupted second process is held until the fourth period becomes equal to or greater than the fifth threshold value. The fourth period is a continuous period during which the second process is suspended and the first process is not executed.

8. The memory system of claim 1, wherein: The memory controller is further configured to restart the interrupted second process when a fifth period during which the second process is interrupted becomes equal to or greater than a sixth threshold value. The fifth period is a period during which the second process is suspended.

9. The memory system of claim 8, wherein: The fifth period is a continuous period.

10. The memory system of claim 8, wherein: The fifth period is a cumulative period of the intermittent periods during which the second process is interrupted, sandwiched between the periods of the first process.

11. The memory system of claim 1 , wherein: The memory controller is further configured to change the first threshold based on a workload of the memory system or a second request from the host device. The characteristic of the workload includes one of the first amount, an idle time of the memory system, and an amount of data received from the host device and not yet completed for writing to the non-volatile memory.

12. The memory system of claim 2, wherein: The memory controller is further configured to change the second threshold based on a workload of the memory system or a second request from the host device. The characteristic of the workload includes one of the first amount, an idle time of the memory system, and an amount of data received from the host device and not yet completed for writing to the non-volatile memory.

13. The memory system of claim 3, wherein: The memory controller is further configured to change the third threshold based on a workload of the memory system or a second request from the host device. The characteristic of the workload includes one of the first amount, an idle time of the memory system, and an amount of data received from the host device and not yet completed for writing to the non-volatile memory.

14. The memory system of claim 6, wherein: The memory controller is further configured to change the fourth threshold based on a workload of the memory system or a second request from the host device. The characteristic of the workload includes one of the first amount, an idle time of the memory system, and an amount of data received from the host device and not yet completed for writing to the non-volatile memory.

15. The memory system of claim 7, wherein: The memory controller is further configured to change the fifth threshold based on a workload of the memory system or a second request from the host device. The characteristic of the workload includes one of the first amount, an idle time of the memory system, and an amount of data received from the host device and not yet completed for writing to the non-volatile memory.

16. The memory system of claim 8, wherein: The memory controller is further configured to change the sixth threshold based on a workload of the memory system or a second request from the host device. The characteristic of the workload includes one of the first amount, an idle time of the memory system, and an amount of data received from the host device and not yet completed for writing to the non-volatile memory.

17. The memory system of claim 1, wherein: The second process includes a programming process or an erasing process.

18. A memory system comprising: A non-volatile memory comprising a first plane and a second plane; and a memory controller configured to cause the nonvolatile memory to execute a first process of reading data from the first plane and the second plane in parallel based on a first request corresponding to the first plane and a second request corresponding to the second plane from a host device; The memory controller is configured as follows: When the first request or the second request is received from the host device during the period when the non-volatile memory is executing the second process, the interruption of the second process is retained until a first number, which is the number of the first requests that have not been executed in the memory controller, and a second number, which is the number of the second requests that have not been executed in the memory controller, respectively become greater than a first threshold value, where the first threshold value is an integer greater than 1.

19. The memory system of claim 18, wherein: The memory controller is further configured to interrupt the second process when a first period during which the interruption of the second process is retained becomes equal to or greater than a second threshold value. The first period is a continuous period in which the first number or the second number is 1 or more.

20. The memory system of claim 18, wherein: The memory controller is further configured to interrupt the second process when the sum of the first number and the second number becomes equal to or greater than a second threshold value while the interruption of the second process is retained, where the second threshold value is an integer equal to or greater than 2.

21. A memory system comprising: non-volatile memory; and The memory controller is configured to cause the nonvolatile memory to execute a first process of reading data based on a first request from a host device. The memory controller is configured as follows: When the first request is received from the host device while the nonvolatile memory is executing a second process, the second process is interrupted and the nonvolatile memory is executed with the first process. The resumption of the interrupted second process is held until the continuous period during which the second process is interrupted becomes equal to or longer than a threshold value. When the period becomes equal to or longer than the threshold, the interrupted second process is resumed.

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