An area- and power-efficient mechanism for coalescing wakeup store-dependent loads based on store drains

Abstract

The present application relates to an area and power efficient mechanism for waking up storage-related loads based on storage drain coalescing. A computer system includes a storage queue for holding storage entries and a load queue for holding load entries sleeping on the storage entries. A processor detects a storage drain coalescing operation call and generates a pair of storage tags, the pair of storage tags including a first storage tag corresponding to a first storage entry to be drained and a second storage tag corresponding to a second storage entry to be drained. The processor determines the pair of storage tags: an even type storage tag or an odd type storage tag. When an even type storage tag pair is detected, the processor disables the odd storage tag included in the even type storage tag pair, and while disabling the odd storage tag, wakes up a first load entry dependent on the even storage tag and a second load entry dependent on the odd storage tag based on the even storage tag included in the even type storage tag pair.

Description

Technical Field

[0001] Embodiments of the present invention relate generally to computer processing systems and, more particularly, to instruction sequencing in an out-of-order processor. Background Art

[0002] Microprocessors implemented in modern computer processing systems often perform loads and stores out of order to avoid being idle while waiting for the previous instruction to complete. At the same time, the processor can process the next one or more instructions that can run immediately and independently. When data loading and data storage are performed out of order, a dedicated buffer is implemented to track the data dependencies between loads and stores to ensure that loads and stores observe data in the correct program order. In some architectures, data storage will not be written to the cache until the store has been completed in its out-of-order processing, and therefore a different data load that is newer in the program sequence may require the result of the data of the older storage. However, since the data has not yet been written to the cache, accurate data loading processing must be implemented to ensure that the load does not read data from the cache. Summary of the invention

[0003] According to a non-limiting embodiment, a computer-implemented method for performing a store drain merge operation to wake up a load entry that is dormant on a related storage entry is provided. The method includes detecting, by a processor, a call to perform a store drain merge operation, and generating a storage tag pair, the storage tag pair including a first storage tag corresponding to a first storage entry to be drained and a second storage tag corresponding to a second storage entry to be drained. The method further includes determining that the storage tag pair is one of an even-type storage tag and an odd-type storage tag. The even-type storage tag pair includes a first storage tag as an even storage tag and a second storage tag as an odd storage tag, while the odd-type storage tag includes a first storage tag as an odd storage tag and a second storage tag as an even storage tag. The method also includes disabling the odd storage tag included in the even-type storage tag pair in response to determining the even-type storage tag pair, and waking up a first load entry that depends on the even storage tag and a second load entry that depends on the odd storage tag based on the even storage tag included in the even-type storage tag pair while the odd storage tag is disabled.

[0004] According to another non-limiting embodiment, a computer system is configured to perform a store drain coalescing operation to wake up a load entry sleeping on a related store entry. The computer system includes a store queue unit and a load queue unit, the store queue unit being configured to hold at least one store entry to be completed, and the load queue unit being configured to hold at least one load entry sleeping on a store entry included in the store queue unit. A processor is configured to detect a call to perform a store drain coalescing operation and generate a storage tag pair, the storage tag pair including a first storage tag corresponding to a first storage entry to be drained from the storage queue unit and a second storage tag corresponding to a second storage entry to be drained from the storage queue unit. The processor determines that the storage tag pair is one of an even type storage tag and an odd type storage tag. The even type storage tag pair includes a first storage tag as an even storage tag and a second storage tag as an odd storage tag, while the odd type storage tag includes a first storage tag as an odd storage tag and a second storage tag as an even storage tag. The processor disables the odd storage tag included in the even type storage tag pair in response to determining the even type storage tag pair, and the processor wakes up a first load entry dependent on the even storage tag and a second load entry dependent on the odd storage tag based on the even storage tag included in the even type storage tag pair while the odd storage tag is disabled.

[0005] According to yet another non-limiting embodiment, a computer program product is provided for controlling a computer system to perform a storage drain coalescing operation to wake up a load entry that is dormant on a related storage entry. The computer program product includes a computer-readable storage medium having program instructions embodied therewith. The program instructions are executable by an electronic computer processor to control the processor to perform operations including: detecting, by the processor, a call to perform a storage drain coalescing operation; and generating a storage tag pair, the storage tag pair including a first storage tag corresponding to a first storage entry to be drained and a second storage tag corresponding to a second storage entry to be drained. The method further includes determining that the storage tag pair is one of an even-type storage tag and an odd-type storage tag. The even-type storage tag pair includes a first storage tag as an even storage tag and a second storage tag as an odd storage tag, while the odd-type storage tag includes a first storage tag as an odd storage tag and a second storage tag as an even storage tag. The method also includes disabling an odd storage tag included in the even type storage tag pair in response to determining the even type storage tag pair, and waking up a first load entry dependent on the even storage tag and a second load entry dependent on the odd storage tag based on the even storage tag included in the even type storage tag pair while the odd storage tag is disabled.

[0006] Additional technical features and benefits are achieved through the technology of the present invention. Embodiments and aspects of the present invention are described in detail herein, and these embodiments and aspects are considered to be part of the claimed subject matter. For a better understanding, reference is made to the specific implementation and the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The details of the exclusive rights described herein are particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other features and advantages of the embodiments of the present invention are apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0008] Figure 1 is a block diagram of an example computer system for use in conjunction with one or more non-limiting embodiments;

[0009] Figure 2 depicts a block diagram of a load-store unit included in a computer processing system according to a non-limiting embodiment;

[0010] Figure 3 depicts a store queue unit included in a load-store unit according to a non-limiting embodiment;

[0011] Figure 4 depicts a store queue unit operating in a first mode to read out a single 16-byte store queue entry in accordance with a non-limiting embodiment; and

[0012] Figure 5 depicts a store queue unit operating in a second mode to read out a pair of 16-byte store queue entries in accordance with a non-limiting embodiment;

[0013] Fig. 6A , Figure 6B and Figure 6C depicts a flow chart illustrating a method of waking a load that is dormant on an associated memory entry according to a non-limiting embodiment;

[0014] Figure 7 A flowchart depicting a method of performing a storage drain coalescing operation according to an illustration of a non-limiting embodiment; and

[0015] Figure 8 Depicted is a block diagram of a computer system useful for implementing some or all aspects of one or more non-limiting embodiments.

[0016] The figures described herein are illustrative. Without departing from the spirit of the present invention, there may be many variations of the figures or operations described herein. For example, these actions may be performed in different orders, or actions may be added, deleted or modified. Similarly, the term "coupling" and its variants describe a direct connection between two elements with a communication path and do not imply that there is no intermediate element / connection between these elements. All these variations are considered as a part of the specification.

[0017] In the drawings and the following detailed description of the disclosed embodiments, the various elements shown in the drawings are provided with two or three digit reference numerals. In the case of minor exceptions, the leftmost digit of each reference numeral corresponds to the figure in which its element is first shown. DETAILED DESCRIPTION

[0018] As described above, out-of-order execution uses precise data load processing to ensure that the load does not read data from the cache before the data is actually written to the cache. In order to optimize performance, a "hibernation" process can be adopted, in which the load will read data from a buffer (sometimes called a "store queue") that holds pending store data. If there is an address overlap between the load and the store, the store can forward its data to the load. However, there are certain scenarios where the store cannot always forward its data to the load. When this happens, the load must be "hibernated" or temporarily set to "sleep" in the load queue until the store has completed and is written to the cache, so that the load can read the stored data from the cache. This is usually achieved by assigning a "tag" (i.e., "stag") to each load in the processor. A given stag is defined by multiple bits (e.g., 7 bits) and serves as an identifier that is unique to each store in the processor.

[0019] Stores will always be written to the cache in program order. When a store is written to the cache, it will broadcast its store tag to the load queue structure containing one or more loads that are "sleeping" on its associated store. The load queue structure performs a content addressable memory compare to search for all loads waiting on its associated store. When there is a compare match, the load queue commands the corresponding load to "wake up" and access the cache to return the data.

[0020] Typically, the above-mentioned rest process is expensive to implement in hardware and may also consume excessive power. As an alternative, some computing systems have managed "merged" data stores when they are written to the cache by grouping adjacent stores in the memory to be written to the cache in the same processor cycle. If these groupings can be achieved in a single given processor cycle, these groupings are always completed in pairs of two. This allows the data store to achieve twice the write bandwidth to the cache, thereby improving computer processing performance. However, when two stores are written to the cache at the same time, each store has its own unique identification storage tag ("stag"), and in addition, multiple loads can sleep separately on each store. In order to manage the second storage tag associated with the second storage included in the pair, a second dedicated comparison port can be added to a large load queue structure, which can send two storage tags to be compared at once. However, from a hardware field and power perspective, this solution adds significant cost to the computer processing system.

[0021] According to one or more non-limiting embodiments, a computer processing system is provided that implements a store drain coalescing operation that is capable of waking up loads based on their associated stores without adding a second compare port. More specifically, a finite number of store tags are sequentially assigned in a cycle order (sometimes referred to as a "polling order") that matches the program order of the stores. For example, store tag 0 will be assigned to the first store observed by the program, store tag 1 will be observed by the next store, and so on. When store tags are exhausted (i.e., the number of allocated store tags has reached a set limit), the processor will stall until more store tags become available. When a store reaches the limit of its "tag space", the newer store in the program sequence will simply wrap around again to store tag 0 (if it is available). The processor disambiguates the age of the store by maintaining an "oldest store tag" pointer that knows whether this wraparound situation has occurred. With this in mind, a computer processing system according to one or more non-limiting embodiments of the present invention avoids the need to implement a second compare port in the load queue structure by grouping the drained data stores into pairs of even and odd pairs in order to determine which loads to wake up from hibernation. Even stores will be associated with even store tags, and odd stores will be associated with odd store tags. Since all stores are drained in order, when the store associated with tag (n) drains, it is guaranteed that the store associated with store tag (n+1) will drain next. When the computer processing system initiates store drain coalescing, comparison of the least significant bit (LSB) is disabled, which essentially indicates that all loads waiting on store tag (n) and store tag (n+1) will wake up at the same time.

[0022] In some examples, storage drain coalescing may be initiated during a given cycle associated with a situation where the first storage is an odd storage and the second storage is an even storage. Thus, in one or more non-limiting embodiments of the present invention, the storage drain coalescing described herein performs different operations based on whether the first storage is an even storage and the second storage is an odd storage or whether the first storage is an odd storage and the second storage is an even storage.

[0023] For example, when store flush coalescing for writes to cache occurs on odd stores during a given cycle (n), then double flush tag comparisons will be grouped by disabling LSB comparisons for the next processor cycle (n+1), but only if there is an additional flush in the nested cycle (n+1). If there is no flush in that next cycle (n+1), the store tags that were flushed in the previous cycle (n-1) will be added a single store tag and will be woken up in the next immediately following cycle (n+1), thereby waking up the even store tags alone. If double writes occur consecutively on back-to-back boundaries associated with odd store tags, the processor will continue to delay the next single cycle until it finds a "hole" or "catch-up" event in the store write sequence that essentially "catches up". That is, delayed wake-ups can be performed continuously (i.e., delaying wake-ups to the next cycle) until no double store writes (i.e., store flush coalescing operations) are observed for a given cycle in the sequence.

[0024] Now go to Figure 1 , a block diagram of a processing system 100 is generally shown that includes an instruction scheduling unit (ISU) for out-of-order (OoO) processor-wide vector execution in single-threaded mode, in accordance with one or more embodiments of the present invention. Figure 1 The system 100 shown in FIG. 1 includes an instruction fetch unit / instruction decode unit (IFU / IDU) 106 that fetches and decodes instructions for input to a setup block 108, which prepares the decoded instructions for input to a mapper 110 of the ISU. According to one or more embodiments, the IFU / IDU 106 may fetch and decode six instructions from a thread at a time. According to one or more embodiments of the invention, the six instructions sent to the setup block 108 may include six non-branch instructions, five non-branch instructions and one branch instruction, or four non-branch instructions and two branch instructions. According to one or more embodiments, the setup block 108 checks that sufficient resources exist before sending the fetched instructions to the blocks in the ISU, such as entries in the issue queue, completion table, mapper, and register file.

[0025] Figure 1The mapper 110 shown in maps programmer instructions (eg, logical register names) to physical resources of the processor (eg, physical register addresses). Figure 1 Various mappers 110 are shown, including a condition register (CR) mapper; a link / count (LNK / CNT) register mapper; an integer exception register (XER) mapper; a unified mapper (UMapper) for mapping general purpose registers (GPRs) and vector-scalar registers (VSRs); an architectural mapper (ARCH mapper) for mapping GPRs and VSRs; and a floating point status and control register (FPSCR) mapper.

[0026] The output from the setup block 108 is also input to a global completion table (GCT) 112 for tracking instructions currently in the ISU. The output from the setup block 108 is also input to a dispatch unit 114 for dispatching instructions to issue queues. Figure 1 The embodiment of the ISU shown in FIG. 1 includes a CR issue queue CR ISQ 116 that receives and tracks instructions from the CR mapper and issues 120 instructions to an instruction fetch unit (IFU) 124 to execute CR logical instructions and move instructions. Figure 1 Also shown is a branch issue queue, branch ISQ 118, which receives and tracks branch instructions and LNK / CNT physical addresses from the LNK / CNT mapper. If the predicted branch address and / or direction is incorrect, the branch ISQ 118 may issue 122 instructions to the IFU 124 to redirect instruction fetching.

[0027] Instructions output from the dispatch logic and rename registers from the LNK / CNT mapper, XER mapper, UMapper GPR / VSR, ARCH mapper GPR / VSR, and FPSCR mapper are input to the issue queue 102. Figure 1 As shown, the issue queue 102 tracks issued floating point instructions (Fx), load instructions (L), store instructions (S), and vector and scalar unit (VSU) instructions. Figure 1 In the embodiment shown, issue queue 102 is broken down into two sections, ISQ0 1020 and ISQ1 1021, with each section holding 48 instructions.

[0028] When the processor executes in ST mode, issue queue 102 may be used as a single logical issue queue containing both ISQ0 1020 and ISQ1 1021 to process all instructions of a single thread (in this example, all ninety-six instructions). When the processor executes in MT mode, ISQ0 1020 may be used to process forty-eight instructions from a first thread, and ISQ1 1021 may be used to process forty-eight instructions from a second thread, ISQ1 1021.

[0029] like Figure 1 As shown in , issue queue 102 issues instructions to execution units 104 which are divided into two groups of execution units 1040 , 1041 . Figure 1 The two groups of execution units 1040, 1041 shown in the figure include full fixed-point execution units (Full FX0, FullFX1); load execution units (LU0, LU1); simple fixed-point, store data and store address execution units (SIMPLE FX0 / STD0 / STA0, SIMPLE FX1 / STD1 / STA1); and floating point, vector multimedia extension, decimal floating point and store data execution units (FP / VMX / DFP / STD0, FP / VMX / DFP / STD1). LU0, SIMPLE FX0 / STD0 / STA0 and FP / VMX / DFP / STD0 together form a load-store unit (LSU) 1042. Similarly, LU1, SIMPLE FX1 / STD1 / STA1 and FP / VMX / DFP / STD1 form an LSU 1043. Although ISQ 104 is shown as having split execution units 1040 and 1041, it should be understood that a single execution unit may be implemented without departing from the scope of the present invention.

[0030] like Figure 1 As shown, when the processor executes in ST mode, the first group of execution units 1040 executes instructions issued from ISQ0 1020, and the second group of execution units 1041 executes instructions issued from ISQ1 1021. In an alternative embodiment, when the processor executes in ST mode, instructions issued from both ISQ0 1020 and ISQ1 1021 in issue queue 102 may be issued to any execution unit 1040 in the first group of execution units 1040 and the second group of execution units 1041.

[0031] According to one or more embodiments, when the processor executes in MT mode, the first group of execution units 1040 executes instructions of a first thread issued from ISQ0 1020 , and the second group of execution units 1041 executes instructions of a second thread issued from ISQ1 1021 .

[0032] Figure 1 The number of entries and the sizes of other elements (e.g., bus width, queue size) in issue queue 102 shown in are intended to be exemplary in nature, as embodiments of the present invention may be implemented for issue queues and other elements of various sizes. According to one or more embodiments of the present invention, the size may be selectable or programmable.

[0033] Steering Figure 2, an LSU 1042 included in the computer processing system 100 is shown according to a non-limiting embodiment. The depicted LSU 1042 facilitates the execution of a store drain coalescing operation that is capable of waking up loads based on their associated stores without adding a second compare port. However, it should be noted that the embodiments described herein are not limited to such an LSU. The LSU 1042 includes one or more store queue units (STQ) 220 that hold store entries and one or more load queue units (LDQ) 225 that hold load entries. In Figure 2 In an exemplary embodiment of the present invention, the LSU 1042 includes two STQs 220 (STQ0 and STQ1) and two LDQs 225 (LDQ0 and LDQ1). More or fewer STQs 200 and / or LDQs 225 may be implemented in the LSU 1042. The STQs 200 and LDQs 225 may also be designed and configured to have different amounts of entries. In one or more non-limiting embodiments, for example, the LDQ 225 may have sixty-four (64) entries, while the STQ 200 may have forty (40) entries. However, it should be understood that more or fewer load entries and / or store entries may be implemented.

[0034] If an entry in the queue is available, STQ entries and LDQ entries are typically assigned (allocated) in program order at dispatch time (e.g., by a dispatch unit). STQ entries are typically released (deallocated) when a store instruction has been executed and the store has been queued in a processor cache 250 (e.g., an L1 processor cache). LDQ entries are typically released (deallocated) when a load has completed (retired) and has been fully executed within a processor core.

[0035] Now turn to Figure 3 , shows an example of an STQ 300 included in an LSU 1042 according to a non-limiting embodiment. The STQ 300 may include a storage data queue (SDQ) 301 and a storage reorder queue (SRQ) 302. The SDQ 301, which in some embodiments may be integrated as part of the SRQ 302 itself to further save chip area, is configured to store the translated address instructions or data associated with a given storage queue entry.

[0036] SRQ 302 may store control bits for storage entries in SDQ 301. SRQ 302 may also track storage instructions that have been executed, determine which storage instructions are to be completed next, and determine when data is available in SDQ 301. In one or more non-limiting embodiments, SRQ 302 cycles in entry allocation order, in entry drain order, and in entry deallocation order.

[0037] SRQ entries are allocated at dispatch time, where the allocated storage tag (stag) is filled into the correct row. Each stag is defined by a set number of bits and is an index to the SRQ entry. In one or more non-limiting embodiments, each stag is defined by seven (7) bits. However, it should be understood that the stag may include more or fewer bits without departing from the scope of the present invention. Further, SRQ entries are deallocated on storage drain. In one or more examples, the stag array maintains "overflow" dispatches. For example, if the row in the desired SRQ indicates that SRQ entry "x" is still in use, the information is written to the stag array at dispatch time. When SRQ entry "x" is deallocated, its corresponding row in the SRQ overflow stag structure is read out and copied to the main SRQ stag array structure (i.e., the read of the overflow stag structure is gated depending on whether there are any valid entries for a given thread / region in the overflow stag array). When storage is drained and deallocated, SRQ 302 sends the stag to the issue queue ISQ0 / 1.

[0038] Continue to see Figure 3 , together with Figure 4 and Figure 5 , STQ 300 includes a store drain merge control input 303, a stag output 310, and a drain complete output 312. The store drain merge control input 303 is configured to receive a store drain merge control signal 304, which invokes a first mode or a second mode of the STQ 300. The first mode reads out a single 16-byte store queue entry, while the second mode reads out a pair of 16-byte store queue entries. The stag output 310 outputs a single stag corresponding to a single store entry read from the STQ 300 to the LDQ 225 in response to invoking the first mode or a stag pair indicating a pair of adjacent store entries in response to invoking the second mode. The stag pair can be defined as an even type store tag pair (where the first store tag is an even store tag and the second store tag is an odd store tag) or an odd type store tag (where the first store tag is an odd store tag and the second store tag is an even store tag). The drain complete output 312 outputs a drain complete signal (D) to the LDQ 225 indicating completion of a single drain when operating in the first mode or completion of a drain pair when operating in the second mode.

[0039] For example, Figure 4The STQ 300 is depicted operating in a first mode to read out a single 16-byte store queue entry in accordance with a non-limiting embodiment. In response to the system 100 determining that no store entries to be drained have adjacent addresses, the computing system 100 generates a logic 0 control signal 304 (e.g., a 0 bit) applied to the store drain merge control input 303. The logic 0 invokes the first mode, which causes the STQ 300 to read out a single 16-byte store queue entry 306a during a single clock cycle and output a single stag 307a that is delivered to the LDQ 225. Once the store drain entry 306a is completed, the SRQ 300 outputs a drain complete signal (D) to the LDQ 225, which wakes up the dormant loads in the LDQ 225. LDQ 225 matches stag 307a of completed store entry 306a with one or more loads that previously waited for the store entry to complete, and executes each matching load entry to read corresponding data from cache 250 (eg, L1 250).

[0040] Go to Figure 5 , according to a non-limiting embodiment, the STQ 300 is depicted as operating in a second mode to read out a pair of 1-byte store queue entries. In response to the system 100 determining that one or more store entries to be drained have adjacent addresses, the computing system 100 generates a logic 1 control signal 304 (e.g., 1 bit) applied to the store drain coalescing control input 303. The logic 1 invokes a second mode or "store drain coalescing" operation, which causes the STQ 300 to read out a pair of 16-byte store queue entries 306a and 306b during a single clock cycle. In this mode, the STQ 300 also outputs a pair of stags 307a and 307b corresponding to the two adjacent store entry drains 306a and 306b to the LDQ 225. Once the two store drain entries 306a and 306b are completed, the SRQ 300 outputs a drain complete signal (D) to the LDQ 225, which wakes up the dormant loads in the LDQ 225. Thus, LDQ 225 matches the stag of the completed store entry with one or more wakeup loads that previously waited for the store entry to complete, and writes each matching load entry to cache 250 (eg, L1 250).

[0041] As described above, the LDQ receives a stag pair corresponding to a pair of storage drain entries. In the case where the stag pair corresponds to a pair of storage drain entries having directly adjacent addresses (i.e., where the first storage entry is an address and the second storage entry is an odd address), the least significant bit (LSB) of the stag has a difference of 1. For example, an even stag may be associated with the first storage entry, and an odd stag having an LSB difference of "1" may be associated with the second storage entry having the directly adjacent address. Therefore, the LDQ disables the LSB of the odd stag and performs a single comparison on the awakened load entry using a single even stag, rather than performing two separate comparisons in the LDQ 225 using two stags.

[0042] In some instances, storage merging of write caches may occur on odd boundaries. For example, the first storage entry may be an odd address, such that the directly adjacent entry is an even address. In this case, if there is additional draining in the next processor cycle, the system uses comparison logic that allows odd stags and even stags to be grouped by disabling the next processor cycle by LSB comparison. If there is no draining in this cycle, the stag that was drained in the previous cycle will be incremented by one, and a single stag will be awakened in the next cycle, which will awaken the even stag. If double writes occur continuously on back-to-back boundaries aligned with odd storage tags, the processor will continue to delay the sequence until a chance to substantially catch up and balance occurs in the storage write sequence.

[0043] Go to Fig. 6A , Figure 6B and Figure 6C , which shows a flow diagram of comparison logic for waking up a sleeping dependent load until a corresponding store drain entry is written to a cache, according to a non-limiting embodiment. The method starts at operation 600, and a determination is made at operation 602 as to whether to initiate store drain coalescing in the current cycle. In this example, the current cycle is initially the first cycle (e.g., cycle "0") of a plurality of sequential cycles (e.g., 0-9). Figure 6A-6C The term "store drain coalescing" as referenced in refers to "coalescing" data storage by writing a pair of stores having directly adjacent addresses (e.g., even and odd, or odd and even) into the cache in the same processor cycle. When it is determined that there is no directly adjacent store following the store data write command, the store drain coalescing operation will not be invoked at operation 602 and the method proceeds to operation 604 (see Figure 6B ).

[0044] At operation 604, a determination is made as to whether a store drain coalescing operation was performed in the previous cycle. As described above, the current cycle at this stage in the process flow is the first cycle (i.e., cycle "0"). Therefore, no store drain coalescing operation was performed in the previous cycle, and the method proceeds to operation 606 to generate a single stag corresponding to the single store drain entry. At operation 608, the dormant loads in the LDQ 225 are compared to the single stag. At operation 610, the load entry in the LDQ 225 corresponding to the single stag is awakened and the method ends at operation 612.

[0045] Referring back to operation 602 and initiating a storage drain merge in an initial cycle (i.e., there is a pair of storage entries with adjacent addresses at cycle 0), the method proceeds to operation 614 and generates a first stag corresponding to the first storage entry and a second stag corresponding to the second storage entry. At operation 616, a determination is made as to whether the first stag is an even stag (i.e., corresponding to a storage entry with an even address) or an odd stag (i.e., corresponding to a storage entry with an odd address). When the first stag is an even stag, at operation 618, the system determines that the second stag is an odd stag and disables the LSB on the odd stag. At operation 620, a dormant load in LDQ 225 is compared to a unique even stag. At operation 622, loads dormant on both the even stag and the odd stag are woken up based only on the even stag comparison, and the method ends at operation 624.

[0046] Referring back to operation 616, storage drain merging may occur at an odd boundary, i.e., the first stag may correspond to a storage entry having an odd address, and the second stag may correspond to a storage entry having an even address. Thus, the first stag is determined to be an odd stag, and the method proceeds to operation 626 and disables the LSB of the even stag to delay waking up a load that is dormant on an even stag (see Figure 6C At operation 628, dormant loads in LDQ 225 are compared to only odd stags, and at operation 630, loads dormant on odd stags are awakened based only on the odd stag comparison. At operation 632, the current cycle is incremented and the method returns to operation 602.

[0047] Referring again to operation 602, a determination is made as to whether storage drain coalescence is initiated in the current cycle. At this stage of the process flow, the current cycle is the next cycle in the sequence (e.g., cycle "1"). When storage drain coalescence is initiated in the current cycle, the method proceeds to operation 614 and repeats the above operations.

[0048] However, when storage drain coalescing is not initiated (ie, no directly adjacent storage entries are available), the storage drain coalescing operation will not be invoked at operation 602 and the method proceeds to operation 604 (see Figure 6B ).

[0049] At operation 604, a determination is made as to whether a storage drain merge operation was performed in the previous cycle. Unlike the previous scenario, at this stage of the current cycle of the process flow, the current cycle has been incremented from the initial cycle. When a storage drain merge operation was not performed in the previous cycle, the method repeats the above operations 606-612.

[0050] However, when a drain coalescing operation was performed in the previous cycle, the method proceeds to operation 634 to determine whether store drain is invoked in the current cycle. When store drain is not invoked in the current cycle, a "catch up" event is detected, which provides an opportunity to end delayed wakeup of loads based on an even store tag. Therefore, the odd stag from the previous cycle is incremented by "1" at operation 648, thereby calculating a new even stag. At operation 650, one or more loads in LDQ 225 are woken up based on the newly calculated single even stag, and the method ends at operation 652.

[0051] Returning to operation 634, storage flushing may be called in the current cycle. Thus, the method proceeds to operation 636 to determine whether the storage entry to be flushed is an odd storage entry (i.e., a storage entry with an odd address) or an even storage entry (i.e., a storage entry with an even address). When the storage entry is not an odd entry but an even entry, a "catch-up" event is detected, which provides an opportunity to end delayed wake-up of the load according to the even storage tag. Therefore, the method repeats operations 606-612 as described above, which ultimately wakes up the load entry corresponding to a single stag in LDQ 225 at operation 612, and ends delayed wake-up of the load according to the even storage tag.

[0052] However, when the store entry is an odd entry, at operation 638, the system disables the LSB of the corresponding even stag to delay waking up the loads sleeping on the even stag in the LDQ 225. At operation 640, a single odd stag corresponding to the odd store entry to be drained is generated, and at operation 642, the sleeping loads in the LDQ 225 are compared with the single odd stag. At operation 644, the load entry corresponding to the single odd stag in the LDQ 225 is woken up. At operation 646, the current cycle is incremented and the method returns to operation 602.

[0053] Therefore, with Fig. 6A , Figure 6B and Figure 6CThe operations associated with the flowchart shown in FIG. 1 provide a mechanism to delay the wakeup of a load based on an even store tag to the next processor cycle when a call to perform a store drain coalescing operation occurs on an odd boundary. Whether to disable LSB comparison or even wake up the stag alone depends on how many stores are written to the cache in the subsequent cycle. This delayed wakeup to the next cycle can be performed continuously until no two writes are observed for the sequence.

[0054] See now Figure 7 , a method for performing a storage drain coalescing operation in a computing system according to a non-limiting embodiment is shown. The method starts at operation 700 and a storage write instruction is received at operation 702. At operation 704, an address of a storage to be drained from the STQ is determined. At operation 706, a determination is made as to whether the storage entry to be drained has a neighboring address. When there are no neighboring addresses, the computing system initiates a non-storage drain coalescing operation at operation 708. Thus, at operation 710, a single entry is read from the storage queue during a single clock cycle. At operation 712, the single drained entry is written to the cache and the method ends at operation 714.

[0055] However, when one or more adjacent addresses are detected at operation 706, the computing system initiates a store drain merge operation at operation 716. Thus, a pair of adjacent store entries are read from the store queue during a single clock cycle at operation 718. At operation 720, the pair of drained entries are written to the cache in adjacent memory locations, and the method ends at operation 714.

[0056] Additional processes may also be included, and it should be understood that Figure 7 The processes depicted in the present disclosure represent examples, and other processes may be added or existing processes may be removed, modified, or rearranged without departing from the scope and spirit of the present disclosure.

[0057] Now go to Figure 8 , Figure 8800 is a block diagram of a computer system 800 for implementing some or all aspects of one or more embodiments of the present invention. The computer system 800 may be an electronic computer framework that includes and / or employs any number and combination of computing devices and networks utilizing different communication technologies, as described herein. The computer system 800 may be easily upgradeable, scalable, and modular, with the ability to change to different services or reconfigure some features independently of others. The computer system 800 may be, for example, a server, a desktop computer, a laptop computer, a tablet computer, or a smart phone. In some examples, the computer system 800 may be a cloud computing node. The computer system 800 may be described in the general context of computer system executable instructions (such as program modules) executed by the computer system. In general, a program module may include routines, programs, objects, components, logic, data structures, etc. that perform specific tasks or implement specific abstract data types. The computer system 800 may be practiced in a distributed cloud computing environment, where tasks are performed by remote processing devices linked through a communication network. In a distributed cloud computing environment, program modules may be located in both local and remote computer system storage media including memory storage devices.

[0058] like Figure 8 As shown, the computer system 800 has one or more central processing units (CPUs) 801a, 801b, 801c, etc. (collectively or generally referred to as processors 801). The processor 801 may be a single-core processor, a multi-core processor, a computing cluster, or any number of other configurations. The processor 801 (also referred to as a processing circuit) is coupled to a system memory 803 and various other components via a system bus 802. The system memory 803 may include a read-only memory (ROM) 804 and a random access memory (RAM) 805. The ROM 804 is coupled to the system bus 802 and may include a basic input / output system (BIOS), which controls certain basic functions of the computer system 800. The RAM 805 is a read-write memory coupled to the system bus 802 for use by the processor 801. The system memory 803 provides temporary memory space for the operation of the instructions during operation. The system memory 803 may include a random access memory (RAM), a read-only memory, a flash memory, or any other suitable memory system.

[0059] Computer system 800 includes an input / output (I / O) adapter 806 and a communications adapter 807 coupled to system bus 802. I / O adapter 806 may be a small computer system interface (SCSI) adapter that communicates with hard disk 808 and / or any other similar components. I / O adapter 806 and hard disk 808 are collectively referred to herein as mass storage device 810.

[0060] Software 811 for execution on computer system 800 may be stored in mass storage device 810. Mass storage device 810 is an example of a tangible storage medium readable by processor 801, wherein software 811 is stored as instructions for execution by processor 801 to cause computer system 800 to operate, such as described below with respect to the various figures. Examples of computer program products and execution of such instructions are discussed in greater detail herein. Communications adapter 807 interconnects system bus 802 with network 812, which may be an external network, enabling computer system 800 to communicate with other such systems. In one embodiment, system memory 803 and a portion of mass storage device 810 together store an operating system, which may be a computer program product for coordinating the operation of the computer system 800. Figure 8 The functionality of the various components shown in the diagram may be implemented in any suitable operating system.

[0061] Additional input / output devices are shown connected to the system bus 802 via a display adapter 815 and an interface adapter 816. In one embodiment, adapters 806, 807, 815, and 816 may be connected to one or more I / O buses connected to the system bus 802 via an intermediate bus bridge (not shown). A display 819 (e.g., a screen or display monitor) is connected to the system bus 802 via a display adapter 815, which may include a graphics controller and a video controller for improving the performance of graphics-intensive applications. A keyboard 821, a mouse 822, a speaker 823, and the like may be interconnected to the system bus 802 via an interface adapter 816, which may include, for example, a super I / O chip that integrates multiple device adapters into a single integrated circuit. Suitable I / O buses for connecting peripheral devices such as hard disk controllers, network adapters, and graphics adapters typically include common protocols such as the Peripheral Component Interconnect (PCI). Thus, as Figure 8 As constructed in , the computer system 800 includes processing capabilities in the form of a processor 801, as well as storage capabilities including system memory 803 and mass storage devices 810, input devices such as a keyboard 821 and a mouse 822, and output capabilities including speakers 823 and a display 819.

[0062] In some embodiments, the communication adapter 807 can transmit data using any suitable interface or protocol (such as an Internet Small Computer System Interface, etc.). The network 812 can be a cellular network, a radio network, a wide area network (WAN), a local area network (LAN), or the Internet, etc. An external computing device can be connected to the computer system 800 through the network 812. In some examples, the external computing device can be an external web server or a cloud computing node.

[0063] It should be understood that Figure 8The block diagram is not intended to indicate that the computer system 800 will include Figure 8 Instead, the computer system 800 may include all components shown in FIG. Figure 8 800 (e.g., additional memory components, embedded controllers, modules, additional network interfaces, etc.). Further, the embodiments described herein with respect to computer system 800 may be implemented with any appropriate logic, where in different embodiments, the logic as mentioned herein may include any appropriate hardware (e.g., a processor, an embedded controller, or an application specific integrated circuit, etc.), software (e.g., an application, etc.), firmware, or any appropriate combination of hardware, software, and firmware.

[0064] Different embodiments of the present invention are described herein with reference to the relevant drawings. Without departing from the scope of the present invention, alternative embodiments of the present invention may be designed. Various connections and positional relationships (e.g., above, below, adjacent, etc.) between elements are described in the following description and the accompanying drawings. Unless otherwise indicated, these connections and / or positional relationships may be direct or indirect, and the present invention is not intended to be limited in this respect. Thus, the coupling of entities may refer to direct or indirect coupling, and the positional relationship between entities may be direct or indirect positional relationships. In addition, various tasks and process steps described herein may be incorporated into a more comprehensive program or process with additional steps or functions not described in detail herein.

[0065] The following definitions and abbreviations are used to interpret the claims and specification. As used herein, the terms "comprises," "comprising," "having," or "containing" or any other variation thereof are intended to cover a non-exclusive inclusion. For example, a composition, mixture, process, method, article, or apparatus comprising a list of elements is not necessarily limited to only those elements but may include other elements not expressly listed or inherent to such composition, mixture, process, method, article, or apparatus.

[0066] Additionally, the term "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment or design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. The terms "at least one" and "one or more" may be understood to include any integer greater than or equal to one, i.e., one, two, three, four, etc. The term "plurality" may be understood to include any integer greater than or equal to 2, i.e., two, three, four, five, etc. The term "connected" may include both indirect "connections" and direct "connections."

[0067] The terms "about", "substantially", "approximately" and variations thereof are intended to include the degree of error associated with the measurement of a particular quantity based on the equipment available at the time of filing this application. For example, "about" may include a range of ±8% or 5%, or 2% of a given value.

[0068] For the sake of brevity, conventional techniques related to making and using various aspects of the present invention may or may not be described in detail herein. In particular, various aspects of computing systems and specific computer programs for implementing the various technical features described herein are well known. Thus, for the sake of brevity, many conventional implementation details are only briefly mentioned herein, or omitted entirely, without providing well-known system and / or process details.

[0069] The present invention may be a system, method and / or computer program product of any possible integrated technical detail level. The computer program product may include a computer-readable storage medium (or media) having computer-readable program instructions thereon, and the computer-readable program instructions are used to cause a processor to perform various aspects of the present invention.

[0070] Computer readable storage medium can be a tangible device that can retain and store instructions for use by instruction execution devices. Computer readable storage medium can be, for example, but not limited to, electronic storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer readable storage medium includes the following: portable computer disk, hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disk read-only memory (CD-ROM), digital versatile disk (DVD), memory stick, floppy disk, such as punch card or a mechanical encoding device with a raised structure in a groove with instructions recorded thereon, and any suitable combination of the foregoing. Computer readable storage medium as used herein should not be interpreted as a transient signal itself, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagated by a waveguide or other transmission medium (e.g., a light pulse by a fiber optic cable), or an electrical signal transmitted by a wire.

[0071] The computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to a corresponding computing / processing device, or downloaded to an external computer or external storage device via a network (e.g., the Internet, a local area network, a wide area network, and / or a wireless network). The network may include copper transmission cables, optical transmission fibers, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions to be stored in a computer-readable storage medium within the corresponding computing / processing device.

[0072] The computer-readable program instructions for performing the operation of the present invention can be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, state setting data, configuration data of integrated circuits, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​(such as Smalltalk, C++, etc.) and procedural programming languages ​​(such as "C" programming language or similar programming languages). The computer-readable program instructions can be executed completely on the user's computer, partially on the user's computer, executed as an independent software package, partially on the user's computer, partially on a remote computer, or completely on a remote computer or server. In the latter case, the remote computer can be connected to the user's computer through any type of network (including a local area network (LAN) or a wide area network (WAN)), or can be connected to an external computer (for example, by using the Internet of an Internet service provider). In some embodiments, an electronic circuit (including, for example, a programmable logic circuit, a field programmable gate array (FPGA) or a programmable logic array (PLA)) can execute a computer-readable program instruction to personalize the electronic circuit by utilizing the state information of the computer-readable program instructions, so as to perform various aspects of the present invention.

[0073] Various aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, devices (systems) and computer program products according to embodiments of the present invention. It should be understood that each box of the flowchart and / or block diagram and the combination of each box in the flowchart and / or block diagram can be implemented by computer-readable program instructions.

[0074] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device create a device for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium, which can direct the computer, programmable data processing device, and / or other equipment to work in a specific manner, so that the computer-readable storage medium having the instructions stored therein includes an article of manufacture, which includes instructions for implementing various aspects of the functions / actions specified in one or more blocks in the flowchart and / or block diagram.

[0075] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device, so that a series of operating steps are performed on the computer, other programmable apparatus, or other device to produce a computer-implemented process, so that the instructions executed on the computer, other programmable apparatus, or other device implement the functions / actions specified in one or more boxes of the flowchart and / or block diagram.

[0076] The flow chart and block diagram in the accompanying drawings illustrate the possible architecture, function and operation of the system, method and computer program product according to different embodiments of the present invention.To this end, each box in the flow chart or block diagram can represent a part of a module, segment or instruction, which includes one or more executable instructions for realizing the logical function of the specification.In some alternative embodiments, the function marked in the box may not occur in the order marked in the figure.For example, depending on the function involved, the two boxes shown in succession can actually be performed substantially at the same time, or these boxes can sometimes be performed in the opposite order.It will also be noted that each box in the block diagram and / or flow chart and the combination of the boxes in the block diagram and / or flow chart can be realized by a system based on special-purpose hardware, and the system based on special-purpose hardware performs a specified function or action or performs a combination of special-purpose hardware and computer instructions.

[0077] The description of different embodiments of the present invention has been presented for the purpose of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terms used herein are selected to best explain the principles of the embodiments, practical applications, or technical improvements over technologies found in the marketplace, or to enable other persons of ordinary skill in the art to understand the embodiments described herein.

Claims

1. A computer-implemented method for performing a store drain coalescing operation to wake up a load entry sleeping on a related store entry, the method comprising: detecting, by a processor, a call to perform a store drain merge operation; generating a storage tag pair, the storage tag pair comprising a first storage tag corresponding to a first storage entry to be drained and a second storage tag corresponding to a second storage entry to be drained; Determining that the storage tag pair is one of an even-type storage tag and an odd-type storage tag, the even-type storage tag pair including a first storage tag as an even storage tag and a second storage tag as an odd storage tag, and the odd-type storage tag including a first storage tag as an odd storage tag and a second storage tag as an even storage tag; In response to determining the even-type storage tag pair, disabling the odd-numbered storage tags included in the even-type storage tag pair; as well as While the odd-numbered storage tags are disabled, a first load entry dependent on the even-numbered storage tags and a second load entry dependent on the odd-numbered storage tags are awakened based on the even-numbered storage tags included in the even-type storage tag pair.

2. The computer-implemented method of claim 1 , wherein: The first load entry and the second load entry are awakened in a single given clock cycle of the processor.

3. The computer-implemented method of claim 1 , wherein: The even storage tag and the odd storage tag are defined as a plurality of bits.

4. The computer-implemented method of claim 3, wherein: Disabling the odd storage tags includes disabling the least significant bit (LSB) of the odd storage tags.

5. The computer-implemented method of claim 3, wherein: In response to determining an odd-type storage tag pair, a first load entry dependent on the odd storage tag is awakened during a first clock cycle of the processor, and awakening of a second load entry dependent on the even storage tag is delayed until a subsequent clock cycle after the first clock cycle.

6. The computer-implemented method of claim 5, wherein: Delaying the wake-up of the second load entry includes disabling the LSBs of the even-numbered storage tags.

7. The computer implemented method of claim 6, delaying the wakeup of the second load entry until a subsequent clock cycle precludes a call to perform a store drain coalescing operation.

8. A computer system comprising: a storage queue unit configured to hold at least one storage entry to be completed; a load queue unit configured to hold at least one load entry sleeping on a store entry included in the store queue unit; a processor configured to detect a call to perform a store drain coalescing operation and generate a store tag pair including a first store tag corresponding to a first store entry to be drained from a store queue unit and a second store tag corresponding to a second store entry to be drained from the store queue unit, Wherein, the processor determines that the storage tag pair is one of an even type storage tag and an odd type storage tag, the even type storage tag pair includes a first storage tag as an even storage tag and a second storage tag as an odd storage tag, and the odd type storage tag includes a first storage tag as an odd storage tag and a second storage tag as an even storage tag, the processor disables the odd storage tag included in the even type storage tag pair in response to determining the even type storage tag pair; and the processor wakes up a first load entry dependent on the even storage tag and a second load entry dependent on the odd storage tag based on the even storage tag included in the even type storage tag pair while the odd storage tag is disabled.

9. The computer system according to claim 8, wherein: The first load entry and the second load entry are awakened in a single given clock cycle of the processor.

10. The computer system according to claim 8, wherein: The even storage tag and the odd storage tag are defined as a plurality of bits.

11. The computer system according to claim 10, wherein: Disabling the odd storage tags includes disabling the least significant bit (LSB) of the odd storage tags.

12. The computer system according to claim 10, wherein: In response to determining an odd-type storage tag pair, a first load entry dependent on the odd storage tag is awakened during a first clock cycle of the processor, and awakening of a second load entry dependent on the even storage tag is delayed until a subsequent clock cycle after the first clock cycle.

13. The computer system according to claim 12, wherein: Delaying the wake-up of the second load entry includes disabling the LSBs of the even-numbered storage tags.

14. The computer system of claim 13, delaying wakeup of the second load entry until a subsequent clock cycle precludes a call to perform a store drain coalescing operation.

15. A computer program product for controlling a computer system to perform a storage drain merge operation to wake up a load entry that is dormant on a related storage entry, the computer program product comprising a computer-readable storage medium having program instructions embodied therein, the program instructions being executable by an electronic computer processor to control the processor to perform the steps of the method according to any one of claims 1 to 7.

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