Display panel, display panel detection method, and display device

Abstract

The present disclosure relates to a display panel, a detection method for a display panel, and a display device. The display panel includes: a display area and a non-display area, the non-display area having a gate drive circuit and a detection circuit, the detection circuit being used to detect the gate drive circuit, the gate drive circuit including a multi-level drive signal output terminal, the detection circuit including: a test signal line, and a multi-level switching element connected thereto; the multi-level switching element is connected to the multi-level drive signal output terminal in a one-to-one correspondence; the switching element is used to respond to the drive signal of the drive signal output terminal to apply a clock signal to the test signal line. The present disclosure can detect abnormal conditions of the gate drive circuit and obtain the specific number of levels of the abnormal drive signal output terminal.

Description

Technical Field

[0001] The present disclosure belongs to the field of display technology, and particularly relates to a display panel, a detection method for a display panel, and a display device. Background Art

[0002] GDL (Gate Driver-less) technology utilizes the display panel's existing array manufacturing process to fabricate the scan line driver circuitry on the substrate surrounding the display area, replacing the external integrated circuit (IC) to drive the horizontal scan lines. GDL technology reduces the bonding process required for external ICs, potentially increasing production capacity and reducing product costs. It also makes display panels more suitable for narrow-border or borderless display products. Therefore, GDL technology can be used to fabricate the gate driver on the thin-film transistor array substrate, saving space and the cost of the driver IC.

[0003] However, in existing panel designs, when a GDL circuit anomaly occurs, it's difficult to pinpoint the specific circuit level in the GDL. This inability to accurately determine the location makes it difficult to repair the GDL circuit, resulting in wasted production costs and making it difficult for technicians to optimize the GDL circuit from a design perspective. Summary of the Invention

[0004] The purpose of the present disclosure is to provide a display panel, a display panel detection method and a display device, which can detect the output of each level of the GDL circuit to quickly respond to GDL abnormal problems, thereby optimizing the design and improving the GDL driving stability.

[0005] A first aspect of the present disclosure provides a display panel, comprising a display area and a non-display area, wherein the non-display area has a gate drive circuit and a detection circuit, wherein the detection circuit is used to detect the gate drive circuit, and the gate drive circuit includes a multi-level drive signal output terminal, wherein the detection circuit includes: a test signal line, and a multi-level switching element connected thereto; the multi-level switching element is connected to the multi-level drive signal output terminal in a one-to-one correspondence; the switching element is used to respond to the drive signal of the drive signal output terminal to apply a clock signal to the test signal line.

[0006] In an exemplary embodiment of the present disclosure, the switch element includes a first transistor, a control terminal of the first transistor is connected to the drive signal, a first terminal of the first transistor is connected to the clock signal, and a second terminal of the first transistor is connected to the test signal line.

[0007] In an exemplary embodiment of the present disclosure, the switching element further includes a second transistor; a first end of the second transistor is connected to the drive signal, a second end of the second transistor is connected to the control end of the first transistor, and the control end of the second transistor is used to respond to the control signal to apply the drive signal to the control end of the first transistor.

[0008] In an exemplary embodiment of the present disclosure, the control signal is the clock signal, the driving signal or a power signal.

[0009] In an exemplary embodiment of the present disclosure, the first transistor and the second transistor are both N-type transistors; and / or,

[0010] The first transistor and the second transistor are both oxide thin film transistors.

[0011] In an exemplary embodiment of the present disclosure, a packaging structure is further provided in the non-display area, a test pad is provided in the packaging structure, and the test pad is electrically connected to the test signal line.

[0012] In an exemplary embodiment of the present disclosure, the non-display area has two sets of the gate drive circuits and two sets of detection circuits connected to the two respectively; the display area has a first side and a second side relative to each other, the two sets of the gate drive circuits are respectively located on the first side and the second side, and the detection circuit is located between the gate drive circuit and the display area; the display area also has a third side, the third side is located between the first side and the second side, and the packaging structure is located on the third side; the packaging structure includes a plurality of packaging units arranged in sequence, wherein the test pads are provided on the first and last two packaging units, and the two test pads are respectively electrically connected to the test signal lines closest to them.

[0013] A second aspect of the present disclosure provides a method for detecting a display panel, which is applied to the aforementioned display panel, and the method includes: outputting a clock signal, wherein the clock signal includes a high level and a low level at periodic intervals; controlling a multi-level drive signal output terminal to sequentially output the drive signal, and the drive signals of adjacent levels have an interval time period; the output time period of the drive signal at each level corresponds sequentially to the high level output time period of the clock signal, and the interval time period corresponds to the low level output time period of the clock signal; determining the consistency relationship between the output signal of the test signal line and the clock signal, and determining whether the drive signal is normal or abnormal based on the consistency relationship between the two; when an abnormal situation occurs in the drive signal, obtaining the corresponding level number of the drive signal output terminal.

[0014] In an exemplary embodiment of the present disclosure, the normal or abnormal condition of the driving signal is determined based on the consistency relationship between the output signal of the test signal line and the clock signal, including: when the output signal of the test signal line is consistent with the clock signal, determining that the driving signal remains normal; when the output signal of the test signal line is inconsistent with the clock signal, determining that the driving signal is abnormal.

[0015] A third aspect of the present disclosure provides a display device, comprising: the aforementioned display panel, and a backlight module; the display panel is located on the light-emitting side of the backlight module.

[0016] The present disclosure includes at least the following beneficial effects:

[0017] Since the switch element can respond to the drive signal at the drive signal output terminal to apply the clock signal to the test signal line, it is possible to determine whether the output of the drive signal output terminal is abnormal by detecting whether the output signal waveform on the test signal is abnormal. If an abnormality occurs, the number of abnormal drive signal output terminals can be calculated.

[0018] Other features and advantages of the present disclosure will become apparent from the following detailed description, or may be learned in part by practice of the present disclosure.

[0019] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0021] Figure 1 The display panel according to the first embodiment of the present disclosure is shown;

[0022] Figure 2 The first detection circuit in the display panel according to the first embodiment of the present disclosure is shown;

[0023] Figure 3 The second detection circuit in the display panel according to the first embodiment of the present disclosure is shown;

[0024] Figure 4 The third detection circuit in the display panel according to the first embodiment of the present disclosure is shown;

[0025] Figure 5The fourth detection circuit in the display panel according to the first embodiment of the present disclosure is shown;

[0026] Figure 6 Shown Figure 2-Figure 5 Schematic diagram of the driving timing of the detection circuit;

[0027] Figure 7 A flow chart of a method for detecting a display panel according to a second embodiment of the present disclosure is shown.

[0028] Description of reference numerals:

[0029] 10. Display area; 20. Non-display area; 21. Gate drive circuit; 22. Test pad; 23. Test signal line; 24. Package structure; G, drive signal output terminal; G(1), first-stage drive signal output terminal; G(2), second-stage drive signal output terminal; G(n), n-th-stage drive signal output terminal; Q, switch element; Q(1), first-stage switch element; Q(2), second-stage switch element; Q(n), n-th-stage switch element; COF(1), first package unit; COF(2), second package unit; COF(n), n-th package unit; TA, first transistor; TB, second transistor; 30. Display panel. DETAILED DESCRIPTION

[0030] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art.

[0031] In this disclosure, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this disclosure, "plurality" means two or more, unless otherwise specifically specified.

[0032] In addition, the described features, structures or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure can be practiced without one or more of the specific details, or other methods, components, devices, steps, etc. can be adopted. In other cases, well-known methods, devices, implementations or operations are not shown or described in detail to avoid blurring various aspects of the present disclosure.

[0033] Example 1

[0034] An embodiment of the present disclosure provides a display panel 30, including a display area 10 (Active Areax, abbreviated as AA) and a non-display area 20. The non-display area 20 has a gate drive circuit 21 and a detection circuit. The detection circuit is used to detect the gate drive circuit 21. The gate drive circuit 21 includes a multi-level drive signal output terminal G. The detection circuit includes: a test signal line 23 (Testline), and a multi-level switching element Q connected thereto; the multi-level switching element Q is connected to the multi-level drive signal output terminal G in a one-to-one correspondence; the switching element Q is used to respond to the drive signal of the drive signal output terminal G to apply the clock signal T_CLK to the test signal line 23.

[0035] That is, the drive signal at the drive signal output terminal G can control the on and off states of the switching element Q, so that the clock signal T_CLK can be applied to the test signal line 23 when the switching element Q is in the on state. Therefore, if the clock signal T_CLK cannot be applied to the test signal line 23, it means that the switching element Q is in the off state and the drive signal at the drive signal output terminal G is abnormal, thereby detecting an abnormal gate drive circuit 21. Furthermore, the output signal of the test signal line 23 can be compared with the clock signal T_CLK to calculate the level of the abnormal drive signal output terminal G.

[0036] The following will be combined Figure 1-Figure 5 The display panel will be described in detail.

[0037] In this embodiment, the display panel 30 further includes a pixel group, which is located in the display area 10. The gate driving circuit 21 is used to drive the light-emitting elements in the pixel group to emit light.

[0038] In this embodiment, the non-display area 20 has two sets of gate drive circuits 21, and two sets of detection circuits respectively connected to the two; the display area 10 has a first side and a second side relative to each other, the two sets of gate drive circuits 21 are respectively located on the first side and the second side of the display area 10, and the detection circuit is located between the gate drive circuit 21 and the display area 10.

[0039] Each gate drive circuit 21 includes a multi-stage drive signal output terminal G, and each detection circuit includes a multi-stage switch element Q. The first-stage drive signal output terminal G(1) is connected to the first-stage switch element Q(1), the second-stage drive signal output terminal G(2) is connected to the second-stage switch element Q(2), and so on. The n-th-stage drive signal output terminal G(n) is connected to the n-th-stage switch element Q(n). Furthermore, the gate drive circuit 21 can be a GDL drive circuit.

[0040] In this embodiment, the non-display area 20 further includes a packaging structure 24, and a test pad 22 is provided in the packaging structure 24. The test pad 22 is electrically connected to the test signal line 23. Specifically, the display area 10 further includes a third side, which is located between the first side and the second side, and the packaging structure 24 is located on the third side.

[0041] The packaging structure 24 includes a plurality of packaging units arranged in sequence, for example, a first packaging unit COF (1), a second packaging unit COF (2), and an nth packaging unit COF (n) are arranged in sequence. Test pads 22 are provided on the first and last packaging units, and the two test pads 22 are respectively electrically connected to the test signal lines 23 closest to them. In this embodiment, the test pads 22 on the first packaging unit COF (1) are electrically connected to the test signal lines 23 on the left side of the display area 10, and the test pads 22 on the nth packaging unit COF (n) are electrically connected to the test signal lines 23 on the right side of the display area 10.

[0042] The packaging structure 24 may be a Chip on Film (CFO) packaging. A data fanout line may be provided between the packaging structure 24 and the display area 10 .

[0043] The test pad 22 can be connected to a detection device to detect the output signal of the test signal line 23 and further determine whether there is an abnormality in the driving signal of the driving signal output terminal G. The detection device can be an oscilloscope or a driver IC.

[0044] The detection circuit will be described in detail below.

[0045] The detection circuit includes multiple switching elements Q and a test signal line 23 electrically connected to all switching elements Q. Each switching element Q includes at least a first transistor TA. The first transistor TA may be an oxide thin-film transistor. That is, the active layer of the first transistor TA may be made of an oxide, such as an indium zinc oxide (IGZO) or other metal oxide material. Compared to a-Si (amorphous silicon) thin-film transistors, IGZO thin-film transistors have the advantages of high precision, low power consumption, and high touch performance.

[0046] The specific structure of the switching element Q is described below with examples.

[0047] Example 1, reference Figure 2 The switch element Q is a first transistor TA, a control end of the first transistor TA is connected to the drive signal, a first end of the first transistor TA is connected to the clock signal T_CLK, and a second end of the first transistor TA is connected to the test signal line 23.

[0048] In this embodiment, the valid driving signal at the driving signal output terminal G is at a high level, and the invalid driving signal is at a low level, that is, the high level represents that it belongs to a normal end, and the low level represents that it belongs to an abnormal end; accordingly, the first transistor TA is an N-type transistor, so that only when the driving signal output terminal G outputs a high-level valid driving signal can the first transistor TA be turned on to apply the clock signal T_CLK to the test signal line 23. In other embodiments, the valid driving signal at the driving signal output terminal G is at a low level, and the invalid driving signal is at a high level; accordingly, the first transistor TA can also be a P-type transistor, so that only when the driving signal output terminal G outputs a low-level valid driving signal can the first transistor TA be turned on.

[0049] In Examples 2 to 4, in addition to the first transistor TA, the switching element Q further includes a second transistor TB. A first terminal of the second transistor TB is connected to a drive signal, and a second terminal of the second transistor TB is connected to a control terminal of the first transistor TA. The control terminal of the second transistor TB is configured to respond to the control signal to apply the drive signal to the control terminal of the first transistor TA. In this embodiment, the second transistor TB is also an N-type transistor, and the second transistor TB may also be an oxide thin film transistor.

[0050] Specifically, in Example 2, Figure 3 As shown, the control signal of the second transistor TB is the clock signal T_CLK, that is, the control terminal of the second transistor TB is connected to the clock signal T_CLK. The second transistor TB responds to the clock signal T_CLK so that the drive signal is applied to the control terminal of the first transistor TA. In turn, the first transistor TA responds to the drive signal so that the clock signal T_CLK is applied to the test signal line 23.

[0051] Example 4: Figure 4 As shown, the control signal of the second transistor TB is the power supply voltage VDD, that is, the control terminal of the second transistor TB is connected to the power supply voltage VDD. The power supply voltage VDD is a high-voltage DC voltage, which turns on the second transistor TB. The drive signal is applied to the control terminal of the first transistor TA through the second transistor TB. The first transistor TA then responds to the drive signal to apply the clock signal T_CLK to the test signal line 23. In other embodiments, when the second transistor TB is a P-type transistor, the power supply voltage connected to the control terminal of the second transistor TB can be a low-voltage DC voltage, which turns on the second transistor TB.

[0052] Example 4: Figure 5As shown, the control signal of the second transistor TB is a driving signal, that is, the control terminal of the second transistor TB is connected to the drain. The driving signal is applied to the control terminal of the first transistor TA through the second transistor TB, and then the first transistor TA responds to the driving signal to apply the clock signal T_CLK to the test signal line 23.

[0053] Based on the detection circuits in Examples 1 to 4, it can be seen that each switching element Q only requires two transistors at most, so the circuit is very simple and does not occupy much design space.

[0054] Example 2

[0055] like Figure 7 As shown, this embodiment provides a method for detecting a display panel, which can be used to detect the display panel in the first embodiment. The method includes:

[0056] Step S1: outputting a clock signal T_CLK and controlling a multi-stage driving signal output terminal G to output driving signals in sequence.

[0057] The clock signal T_CLK includes a high level and a low level at periodic intervals.

[0058] The driving signals of adjacent stages have interval time periods; the output time periods of the driving signals of each stage correspond to the high level output time periods of the clock signal T_CLK, and the interval time periods correspond to the low level output time periods of the clock signal T_CLK.

[0059] That is, the detection method includes a first time period t1 and a second time period t2. During the first time period t1, the clock signal T_CLK outputs a high level, and the drive signal output terminals G of each stage sequentially output drive signals. That is, during one of the first time periods t1, only the drive signal output terminal G of one stage outputs a drive signal, and the drive signal output terminals G of the other stages stop outputting drive signals. During the second time period t2, the clock signal T_CLK outputs a low level, and all drive signal output terminals G stop outputting drive signals. The second time period t2 is the interval between the drive signals of two adjacent stages.

[0060] Step S2: Determine whether the output signal of the test signal line 23 is consistent with the clock signal T_CLK, and determine whether the drive signal is normal or abnormal based on the consistency between the two. In some embodiments, when the output signal of the test signal line 23 is consistent with the clock signal T_CLK, the drive signal is determined to be normal; when the output signal of the test signal line 23 is inconsistent with the clock signal T_CLK, the drive signal is determined to be abnormal. This step will be described in detail later in conjunction with the specific detection circuit.

[0061] Step S3: when an abnormality occurs in the driving signal, the level of the corresponding driving signal output terminal G is obtained.

[0062] The following combination Figure 6 The working timing diagram of the detection circuit is shown in FIG. Figure 2-Figure 5 The detection method corresponding to the detection circuit in the embodiment is described in detail. It is worth noting that in the following examples, the effective level of the drive signal output terminal G is always high, that is, during the output time period of the drive signal, its output high level indicates that the terminal is normal, and its output low level indicates that the terminal is abnormal.

[0063] Example 1, combined with reference Figure 2 and Figure 6 Under normal circumstances, during the first time period t1, a certain level of the drive signal output terminal G outputs a high level. The first transistor TA is then turned on, the clock signal T_CLK is written to the test signal line 23, and the test pad 22 detects that the clock signal T_CLK is a high level voltage. That is, the waveform output by the test signal line 23 is consistent with the waveform of the clock signal T_CLK, indicating that there is no abnormality in the drive signal output. If the two waveforms do not correspond, it indicates that the drive signal output terminal G is outputting a low level, indicating an abnormal output. The number of levels of the abnormal drive signal output terminal G can be determined by calculating the waveform using an oscilloscope or by monitoring the driver IC to calculate the value n.

[0064] Example 2, combined with reference Figure 3 and Figure 6 Under normal circumstances, during the first time period t1, the clock signal T_CLK is at a high level, turning on the second transistor TB. The high level at the drive signal output terminal G is applied to the control terminal of the first transistor TA through the second transistor TB, thereby writing the clock signal T_CLK to the test signal line 23. The test pad 22 detects that the clock signal T_CLK is at a high level. That is, the waveform output by the test signal line 23 is consistent with the waveform of the clock signal T_CLK, indicating that there is no abnormality in the drive signal output. If the two waveforms do not correspond, it indicates that the output of the drive signal output terminal G is abnormal, and further information needs to be obtained about the level of the abnormal drive signal output terminal G.

[0065] Example 3, combined with reference Figure 4 and Figure 6Under normal circumstances, during the first time period t1, the power supply voltage VDD turns on the second transistor TB. The high level at the drive signal output terminal G is applied to the control terminal of the first transistor TA through the second transistor TB, thereby writing the clock signal T_CLK to the test signal line 23. The test pad 22 detects that the clock signal T_CLK is at a high level. In other words, the waveform output by the test signal line 23 is consistent with the waveform of the clock signal T_CLK, indicating that there is no abnormality in the drive signal output. If the two waveforms do not correspond, it indicates that the output of the drive signal output terminal G is abnormal, and further information is needed to determine the level of the abnormal drive signal output terminal G.

[0066] Example 4, combined with reference Figure 5 and Figure 6 Under normal circumstances, during the first time period t1, the drive signal turns on the second transistor TB, and the high level of the drive signal output terminal G is applied to the control terminal of the first transistor TA through the second transistor TB, thereby writing the clock signal T_CLK to the test signal line 23. The test pad 22 detects that the clock signal T_CLK is a high-level voltage. In other words, the waveform output by the test signal line 23 is consistent with the waveform of the clock signal T_CLK, indicating that there is no abnormality in the drive signal output. If the two waveforms do not correspond, it indicates that the output of the drive signal output terminal G is abnormal, and further information needs to be obtained about the level of the abnormal drive signal output terminal G.

[0067] It should be understood that in other embodiments, if the effective level of the gate drive signal output terminal G is low, that is, during the output period of the drive signal, the output low level represents that the terminal is a normal terminal, and the output high level represents that the terminal is an abnormal terminal; when using Figure 2-Figure 5 When the detection circuit shown is performing detection, within the first time period t1, the output signal of the test signal line 23 is at a low level, that is, the waveform output by the test signal line 23 is inconsistent with the waveform of the clock signal T_CLK, indicating that there is no abnormality in the drive signal output; within the first time period t1, the output signal of the test signal line 23 is at a high level, that is, the waveform output by the test signal line 23 is consistent with the waveform of the clock signal T_CLK, indicating that there is an abnormality in the drive signal output.

[0068] Based on Examples 1 to 4, it can be seen that the drive signal output by the drive signal output terminal G is only used to control the switch element Q so that the clock signal T_CLK can be applied to the test signal line 23 through the switch element Q. The signal ultimately detected on the test signal line 23 is the clock signal T_CLK, not the drive signal itself. The clock signal T_CLK detected on the test signal line 23 is needed to infer whether the drive signal is normal or abnormal. Because the clock signal T_CLK is a square wave signal, it is more convenient to determine, thereby improving the accuracy of the detection.

[0069] In summary, in this embodiment, the waveform of the clock signal T_CLK output on the test signal line 23 is determined to determine whether the output of the drive signal output terminal G is abnormal. If the waveform of the output clock signal T_CLK is abnormal, the level of the corresponding drive signal output terminal G can be determined by calculation. In this way, it is possible to quickly check and determine whether the gate drive circuit 21 is abnormal, which in turn facilitates rapid analysis and repair of the gate drive circuit 21 abnormality and facilitates technical personnel to optimize the circuit design.

[0070] Example 3

[0071] This embodiment provides a display device, including the display panel of the first embodiment and a backlight module (not shown); the display panel is located on the light-emitting side of the backlight module. For the same or similar parts of this embodiment as the previous embodiment, please refer to the detailed description of the previous embodiment.

[0072] Based on this, it can be seen that the display device of this embodiment can be a liquid crystal display (LCD). They have many advantages such as thin body, power saving, and no radiation, and have been widely used. Such as: television, mobile phone, personal digital assistant (PDA), digital camera, computer screen or laptop screen, etc., which dominate the field of flat panel displays. In the description of this specification, the description of reference terms such as "some embodiments" and "exemplarily" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples without contradiction.

[0073] Although the embodiments of the present disclosure have been shown and described above, it is understood that the above embodiments are illustrative and cannot be understood as limitations on the present disclosure. A person skilled in the art may change, modify, replace and modify the above embodiments within the scope of the present disclosure. Therefore, any changes or modifications made in accordance with the claims and description of the present disclosure shall fall within the scope of the patent of the present disclosure.

Claims

1. A display panel comprising a display area and a non-display area, wherein the non-display area comprises a gate drive circuit and a detection circuit, wherein the detection circuit is used to detect the gate drive circuit, and the gate drive circuit comprises a multi-level drive signal output terminal, wherein: The detection circuit comprises: A test signal line and a multi-stage switching element connected thereto; the multi-stage switching element is connected to the multi-stage drive signal output end in a one-to-one correspondence; The switch element is used to respond to the driving signal of the driving signal output terminal to apply a clock signal to the test signal line, compare the output signal of the test signal line with the clock signal, and calculate the level of abnormal driving signal output terminals; The switch element includes a first transistor, a control terminal of the first transistor is connected to the drive signal, a first terminal of the first transistor is connected to the clock signal, and a second terminal of the first transistor is connected to the test signal line; The switching element also includes a second transistor; the first end of the second transistor is connected to the drive signal, the second end of the second transistor is connected to the control end of the first transistor, and the control end of the second transistor is used to respond to the control signal to apply the drive signal to the control end of the first transistor; wherein the control signal is the clock signal or the power signal.

2. The display panel according to claim 1, wherein: The first transistor and the second transistor are both N-type transistors; and / or, The first transistor and the second transistor are both oxide thin film transistors.

3. The display panel according to claim 1, wherein: The non-display area further has a packaging structure, and a test pad is provided in the packaging structure. The test pad is electrically connected to the test signal line.

4. The display panel according to claim 3, wherein: The non-display area has two sets of gate driving circuits and two sets of detection circuits connected to the two sets respectively; The display area has a first side and a second side opposite to each other, the two sets of gate driving circuits are respectively located on the first side and the second side, and the detection circuit is located between the gate driving circuit and the display area; The display area further has a third side, the third side is located between the first side and the second side, and the encapsulation structure is located on the third side; The packaging structure includes a plurality of packaging units arranged in sequence, wherein the first and last two packaging units are provided with the test pads, and the two test pads are respectively electrically connected to the test signal lines closest thereto.

5. A method for detecting a display panel, applied to the display panel according to claim 1, characterized in that: The detection method comprises: Outputting the clock signal, wherein the clock signal includes a high level and a low level at periodic intervals; Controlling the drive signal output terminals of the multiple stages to sequentially output the drive signals, with the drive signals of adjacent stages having interval time periods; the output time periods of the drive signals of each stage sequentially correspond to the high-level output time periods of the clock signal, and the interval time periods correspond to the low-level output time periods of the clock signal; Determining a consistency relationship between the output signal of the test signal line and the clock signal, and determining whether the drive signal is normal or abnormal based on the consistency relationship between the two; When an abnormal situation occurs in the driving signal, the level of the corresponding driving signal output terminal is obtained.

6. The display panel detection method according to claim 5, wherein: Determining whether the driving signal is normal or abnormal based on a consistency relationship between the output signal of the test signal line and the clock signal includes: When the output signal of the test signal line is consistent with the clock signal, determining that the driving signal remains normal; When the output signal of the test signal line is inconsistent with the clock signal, it is determined that an abnormality occurs in the driving signal.

7. A display device, characterized in that: include: The display panel and backlight module according to claims 1-4; The display panel is located on the light-emitting side of the backlight module.

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