Semiconductor memory device and memory system including the same

Abstract

A semiconductor memory device and a memory system including the same are disclosed. The memory system includes a memory controller adapted to generate a first target address by sampling an activation address according to an activation command, provide the activation address together with the activation command, and provide a first target refresh command together with the first target address, and a memory device adapted to generate a second target address by sampling the activation address according to the activation command, perform a target refresh operation on at least one word line corresponding to the first target address according to the first target refresh command, and perform the target refresh operation on at least one word line corresponding to the second target address according to a second target refresh command.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 123695, filed December 10, 2020, and Korean Patent Application No. 10-2021-0007434, filed January 19, 2021, both of which are incorporated herein by reference in their entirety. Technical Field

[0003] Various embodiments of the present invention relate to semiconductor design technology, and more specifically to memory systems including semiconductor memory devices that perform target refresh operations. Background Technology

[0004] A memory cell in a semiconductor memory device includes a transistor that acts as a switch and a capacitor that stores charge (or data). Data is determined to be at a logic high level (logic level 1) or a logic low level (logic level 0) depending on whether there is any charge in the capacitor of the memory cell (i.e., whether the voltage across the capacitor is high or low).

[0005] Data is stored by accumulating charge in capacitors, theoretically eliminating power consumption. However, leakage current can occur due to factors such as PN coupling in transistors, causing the initial amount of charge stored in the capacitors to disappear, resulting in data loss. To prevent this, data in the memory cell should be read before data loss, and the normal amount of charge should be recharged back into the memory cell based on the read data. Data can only be retained by periodically repeating this operation, and the process of recharging the cell charge is called a refresh operation (hereinafter referred to as "normal refresh operation").

[0006] Recently, in addition to normal refresh operations, extra refresh operations (hereinafter referred to as "target refresh operations") are performed on memory cells of specific word lines that may lose data due to row hammering. Row hammering refers to the phenomenon where data in memory cells coupled to a specific word line or located on a word line adjacent to that word line is corrupted due to the high-frequency activation of the corresponding word line. To prevent row hammering, target refresh operations are performed on word lines that have been activated more than a predetermined number of times (hereinafter referred to as "target word lines") and word lines located adjacent to said word lines.

[0007] In order to select the word line to be refreshed during the target refresh operation, the storage device needs to count all addresses entered along with the activation command. The storage device has counting circuitry to count the number of address inputs, and as technology advances and the size of the storage device decreases, the space occupied by the counting circuitry becomes larger. Summary of the Invention

[0008] Embodiments of the present invention relate to a memory system capable of allowing a memory controller and a memory device to cooperatively generate target addresses each for selecting at least one word line to be refreshed during a target refresh operation.

[0009] According to embodiments of the present invention, a memory system includes: a memory controller generating a first target address by sampling an active address according to an active command, providing the active address along with the active command, and providing a first target refresh command along with the first target address; and a memory device adapted to generate a second target address by sampling the active address according to the active command, perform a target refresh operation on at least one word line corresponding to the first target address according to the first target refresh command, and perform the target refresh operation on at least one word line corresponding to the second target address according to a second target refresh command.

[0010] According to embodiments of the present invention, a semiconductor memory device includes: a first latch outputting a first target address by latching an internal address according to a first target refresh command; a second latch outputting an active address by latching the internal address according to an active command; a second random sampling circuit generating a plurality of sampled addresses by randomly sampling the active address; an output control circuit adapted to sequentially output the sampled addresses as second target addresses according to a second target refresh command while masking a current sampled address in response to a comparison signal; and an address selection circuit adapted to output a final target address by selecting any one of the first target address and the second target addresses according to the second target refresh command, and generate the comparison signal when the first target address and the second target address are identical by comparing the first target address and the second target address.

[0011] According to embodiments of the present invention, an operating method of a memory system includes: at a memory controller, generating a first target address by sampling an active address according to an active command; at the memory controller, providing the active address along with the active command; at the memory controller, providing a first target refresh command along with the first target address; at a memory device, performing a target refresh operation on at least one word line corresponding to the first target address according to the first target refresh command; at the memory device, generating a second target address by sampling the active address according to the active command; and at the memory device, performing the target refresh operation on at least one word line corresponding to the second target address according to a second target refresh command.

[0012] According to an embodiment of the present invention, an operation method of a memory device includes: performing a first target refresh operation on a word line corresponding to a first target address in response to a first target refresh command, the first target address and the first target command being received from a memory controller; generating a second target address by sampling an activation address in response to an activation command; determining whether the number of inputs to a normal refresh command has reached a threshold; and performing a second target refresh operation on the word line corresponding to the second target address in response to determining that the number of inputs to the normal refresh command has reached the threshold.

[0013] According to embodiments of the present invention, a memory system can generate a final target address in such a manner that the memory controller generates a first target address with a high number of activations (or frequency), and the memory device generates a second target address using random sampling. Because the memory controller and the memory device cooperate to sample the target address, the memory system can reduce the load on the memory device while improving the accuracy of the target refresh operation.

[0014] According to embodiments of the present invention, the memory device can select a second target address that is different from the first target address provided by the memory controller. Therefore, the memory system can prevent unnecessary target refresh operations based on the same address, thereby improving refresh efficiency.

[0015] According to embodiments of the present invention, the memory controller can predict the frequency of occurrence of the active address by tracking only a small number of bits of the active address, and randomly sample the active addresses based on the prediction results to select a first target address from the sampled active addresses. Therefore, the memory system can maximize address sampling accuracy while reducing the area overhead on the memory controller.

[0016] According to embodiments of the present invention, the random sampling circuit used in the memory device and the random sampling circuit used in the memory controller can be implemented using different sampling algorithms. Therefore, the memory system can eliminate the periodicity of the sampling circuit and further optimize the target address to select at least one word line during the target refresh operation. Attached Figure Description

[0017] Figure 1 This is a block diagram illustrating a memory system according to an embodiment of the present disclosure.

[0018] Figure 2 This illustrates an embodiment according to the present disclosure. Figure 1 The diagram shows a detailed block diagram of the refresh control module of the memory controller.

[0019] Figure 3 This illustrates an embodiment according to the present disclosure. Figure 2 Detailed block diagram of the tracking circuit.

[0020] Figure 4 is a detailed block diagram of a first latch circuit and an address counter of the memory device shown in Figure 3 .

[0021] Figure 5 is a detailed block diagram of a first latch circuit and an address counter of the memory device shown in Figure 4 .

[0022] Figure 6 is a detailed block diagram of a first random sampling circuit of the memory device shown in Figure 3 .

[0023] Figure 7 is a detailed block diagram of a target address generation circuit of the memory device shown in Figure 6 .

[0024] Figure 8 is a detailed block diagram of a memory device according to an embodiment of the present disclosure. Figure 1

[0025] Figure 9 is a detailed block diagram of an address selection circuit of the memory device shown in Figure 8 .

[0026] Figure 10A and 10B are timing diagrams for describing operations of a memory system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0027] Various embodiments of the present disclosure will be described in detail below with reference to the attached drawings. The present disclosure can have various embodiments and should not be understood only as limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be thorough and complete and will fully convey the scope of the application to those skilled in the art. Throughout the present disclosure, the same reference numerals refer to the same parts throughout the various drawings and embodiments of the present disclosure.

[0028] ​It will be understood that when an element is referred to as being "coupled" or "connected" to another element, it can be directly coupled or connected to the other element or coupled or connected to the other element through a further circuit. It will also be understood that, when the term "comprise" or "comprising" is used in this specification, these terms specify the presence of stated features, integers, steps, operations, elements, components and / or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. In the present disclosure, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise.

[0029] Hereinafter, in order to focus on refresh operations, the description of configurations associated with data input / output operations will be omitted. Specifically, for convenience of description, an address used by a memory controller in a memory system can be designated by a reference numeral "_ADD", while an address used in a memory device can be designated by a reference numeral "ADD_".

[0030] Figure 1 is a block diagram illustrating a memory system 10 according to an embodiment of the present disclosure.

[0031] Referring to Figure 1 , the memory system 10 can include a memory controller 100 and a semiconductor memory device 200.

[0032] The memory controller 100 can control general operations of the memory system 10, and can control general data exchange between a host and the semiconductor memory device 200. The memory controller 100 can generate a command / address signal C / A according to a request REQ from the host, and provide the generated command / address signal C / A to the semiconductor memory device 200. The memory controller 100 can provide a clock CK to the semiconductor memory device 200 together with the command / address signal C / A. The memory controller 100 can provide data DQ corresponding to host data HDATA provided from the host to the semiconductor memory device 200 together with a data strobe signal DQS. The memory controller 100 can receive data DQ read from the semiconductor memory device 200 together with the data strobe signal DQS, and provide the data DQ and the data strobe signal DQS to the host as the host data HDATA.

[0033] In detail, the memory controller 100 can include a host interface (host I / F) 110, a processor 120, a refresh control module 130, a command / address (CMD / ADD) generation module 140, a memory interface (memory I / F) 150, and a bus 170.

[0034] The host interface 110 can be configured to communicate with a host connected to the memory system 10 under the control of the processor 120. For example, the host interface 110 can receive a request REQ and host data HDATA from the host, and provide the host data HDATA to the host by receiving data DQ read from the semiconductor memory device 200 via the memory interface 150.

[0035] The processor 120 can perform various types of computing operations and / or other operations for controlling the semiconductor memory device 200, and / or can execute instructions in the form of firmware or other types of software. The processor 120 can receive the request REQ and the host data HDATA provided from the host through the host interface 110. The processor 120 can generate various commands (e.g., an activation command ACT, a read command, a write command) and addresses corresponding to the request REQ to provide the commands to the refresh control module 130 and the command / address generation module 140. The processor 120 can transfer the host data HDATA to the memory interface 150. The address generated together with the activation command ACT can be defined as an activation address ACT_ADD. The processor 120 can control the overall operation of the host interface 110, the refresh control module 130, the command / address generation module 140, and the memory interface 150.

[0036] The refresh control module 130 can generate commands regarding refresh operations, e.g., a normal refresh command REF and a first target refresh command TREF1, based on the activation command ACT provided from the processor 120. The refresh control module 130 can generate the first target refresh command TREF1 after generating a set number of normal refresh commands REF at regular intervals whenever the number of inputs of the activation command ACT reaches a certain number. The refresh control module 130 can generate a first target address TREF1_ADD having a high activation number or a high activation frequency. Details of the refresh control module 130 according to an embodiment will be described in Figures 2 to 7

[0037] The command / address generation module 140 can generate a command / address signal C / A by scheduling the commands and addresses provided from the processor 120 and the refresh control module 130. The command / address generation module 140 can provide the activation address ACT_ADD together with the activation command ACT as the command / address signal C / A, and provide the first target refresh command TREF1 together with the first target address TREF1_ADD as the command / address signal C / A.

[0038] ​The memory interface 150 can communicate with the semiconductor memory device 200 under the control of the processor 120. For example, the memory interface 150 can transmit command / address signals C / A and data DQ to the semiconductor memory device 200, and transmit data DQ read from the semiconductor memory device 200 to the host interface 110.

[0039] Processor 120 can transfer data between host interface 110, refresh control module 130, command / address generation module 140, and memory interface 150 via bus 170. According to an embodiment, host interface 110, refresh control module 130, command / address generation module 140, and memory interface 150 can communicate independently without going through bus 170. For example, refresh control module 130 and host interface 110 can communicate directly without going through bus 170. Refresh control module 130 and memory interface 150 can communicate directly without going through bus 170. Host interface 110 and memory interface 150 can also communicate directly without going through bus 170.

[0040] Semiconductor memory device 200 can perform refresh, write, and read operations based on clock CK, command / address signal C / A, data strobe signal DQS, and / or data DQ provided by memory controller 100. Refresh operations can include normal refresh operations and target refresh operations. In a normal refresh operation, during a normal refresh cycle, semiconductor memory device 200 sequentially refreshes multiple word lines; in a target refresh operation, during a target refresh cycle, one or more adjacent word lines arranged adjacent to a word line having a high activation count (or high activation frequency) are refreshed.

[0041] Semiconductor memory device 200 can generate internal commands by buffering command / address signals C / A. Figure 8 ICMD) and internal address ( Figure 8 The semiconductor memory device 200 generates a second target refresh command (TREF1) by decoding the ICMD command (ICMD), which is related to the row control operation. The activation command ACT, precharge command PCG, normal refresh command REF, and first target refresh command TREF1 are also generated. Whenever the number of inputs to the normal refresh command REF reaches a set number, the semiconductor memory device 200 can generate a second target refresh command (TREF1). Figure 8 TREF2). That is, the first target refresh command TREF1 can be generated and provided from the memory controller 100, while the second target refresh command TREF2 can be generated by the semiconductor memory device 200 itself.

[0042] The semiconductor storage device 200 can perform a normal refresh operation according to a normal refresh command REF and a target refresh operation according to a first target refresh command TREF1 or a second target refresh command TREF2. For reference, the internal address IADD can correspond to an active address ACT_ADD at the time when the active command ACT is generated. According to an embodiment, the internal address IADD can correspond to a first target address TREF1_ADD at the time when the first target refresh command TREF1 is generated. In addition, the semiconductor storage device 200 can additionally generate a command (e.g., a read command or a write command) related to a data input / output operation by decoding the internal command ICMD.

[0043] In detail, the semiconductor storage device 200 can include a memory cell array 210 and a refresh control circuit 230.

[0044] The memory cell array 210 can include a plurality of memory cells coupled to a plurality of word lines and a plurality of bit lines, and can be arranged in the form of an array.

[0045] The refresh control circuit 230 can provide a final target address TADD to select a word line to be refreshed during a target refresh operation among the word lines. The refresh control circuit 230 can generate a second target address (ADD_TREF2) by sampling an active address ACT_ADD according to an active command ACT. The refresh control circuit 230 can output the final target address TADD by selecting one of a first target address TREF1_ADD and the second target address ADD_TREF2 according to a second target refresh command TREF2. The refresh control circuit 230 can select the first target address TREF1_ADD when the second target refresh command TREF2 is not input, and select the second target address ADD_TREF2 different from the first target address TREF1_ADD when the second target refresh command TREF2 is input. Figure 8

[0046] Accordingly, the semiconductor storage device 200 can perform a target refresh operation on a word line corresponding to the first target address TREF1_ADD in response to the first target refresh command TREF1, and perform a target refresh operation on a word line corresponding to the second target address ADD_TREF2 different from the first target address TREF1_ADD in response to the second target refresh command TREF2. This will be described in detail in Figure 8 and 9 The detailed structure of the semiconductor storage device 200 according to an embodiment will be described in detail in

[0047] ​As described above, according to embodiments of the present application, the memory controller 100 can generate the first target address TREF1_ADD with a high number of activations (or a high frequency of activation), and the semiconductor memory device 200 can generate the second target address ADD_TREF2 with random sampling. Because the memory controller and the memory device cooperate to generate the final target address TADD, the memory system 10 can reduce the burden on the semiconductor memory device 200 while improving the accuracy of the target refresh operation.

[0048] Figure 2 is a detailed block diagram of the refresh control module 130 of the memory controller 100 shown in Figure 1 In Figure 2 In order to focus on the characteristics of the embodiments, additional configurations (e.g., the host interface 110 and the memory interface 150) have been omitted in Figure 3 is a detailed block diagram of the tracking circuit 134 of Figure 2

[0049] Referring to Figure 2 The processor 120 can receive a request REQ from a host through the host interface 110. The processor 120 can generate an activation command ACT and an activation address ACT_ADD corresponding to the request REQ.

[0050] The refresh control module 130 can include a refresh command issuing circuit 132 and a tracking circuit 134.

[0051] The refresh command issuing circuit 132 can generate a normal refresh command REF and a first target refresh command TREF1 based on the activation command ACT provided from the processor 120. The refresh command issuing circuit 132 can issue the first target refresh command TREF1 or the normal refresh command REF when the number of inputs of the activation command ACT reaches a certain number.

[0052] For example, the refresh command issuing circuit 132 can include a command counter 1322 and a counter analyzer 1324.

[0053] The command counter 1322 can generate a count value by counting the number of inputs of the activation command ACT. When the count value reaches a certain number, the counter analyzer 1324 can issue a set number of normal refresh commands REF at regular intervals. The counter analyzer 1324 can issue the first target refresh command TREF1 after issuing the set number of normal refresh commands REF. For example, the counter analyzer 1324 can issue at least one first target refresh command TREF1 after issuing 4096 normal refresh commands REF whenever the count value reaches 10. ​

[0054] The tracking circuit 134 can generate the first target address TREF1 ADD by sampling the activation address ACT ADD in response to the activation command ACT. The tracking circuit 134 can output the first target address TREF1 ADD at each issuance of the first target refresh command TREF1.

[0055] Referring to Figure 3 , the tracking circuit 134 can include a partial sampling circuit 310, a first random sampling circuit 320, and a target address generation circuit 330.

[0056] The partial sampling circuit 310 can store a part of bits in the activation address ACT ADD (e.g., ACT ADD<0:m>) as a partial address ACT ADD<0:n> according to the activation command ACT, where n and m are natural numbers, and n is smaller than m. The partial sampling circuit 310 can set a priority address P ADD<0:n> by counting the number of inputs of the partial address ACT ADD<0:n>. The partial sampling circuit 310 can be initialized to reset the priority address P ADD<0:n> at each issuance of the first target refresh command TREF1. The first random sampling circuit 320 can generate a plurality of sampled addresses SAM ADDx<0:m> by randomly sampling the activation address ACT ADD<0:m>, where x is an integer greater than or equal to 0. The target address generation circuit 330 can output any of the sampled addresses SAM ADDx<0:m> that is identical to the priority address P ADD<0:n> as the first target address TREF1 ADD<0:m> in response to the first target refresh command TREF1.

[0057] Referring back to Figure 2 , the command / address generation module 140 can generate the command / address signal C / A by scheduling the activation command ACT and the activation address ACT ADD provided from the processor 120, and the normal refresh command REF, the first target refresh command TREF1, and the first target address TREF1 ADD provided from the refresh control module 130. The command / address generation module 140 can output the activation address ACT ADD together with the activation command ACT as the command / address signal C / A, and provide the normal refresh command REF as the command / address signal C / A, or provide the first target refresh command TREF1 together with the first target address TREF1 ADD as the command / address signal C / A.

[0058] Figure 4 is a detailed block diagram of the partial sampling circuit 310 of the tracking circuit 134 according to an embodiment of the disclosure. Figure 3 is a detailed block diagram of the partial sampling circuit 310 of the tracking circuit 134 according to an embodiment of the disclosure. Figure 5 is a detailed block diagram of the partial sampling circuit 310 of the tracking circuit 134 according to an embodiment of the disclosure.Figure 4 a detailed block diagram of the first latch circuit 312 and the address counter 314.

[0059] Referring to Figure 4 , the partial sampling circuit 310 can include the first latch circuit 312, the address counter 314, the comparison analyzer 316, and a plurality of priority address storages 318_0 to 318_k.

[0060] When the activation command ACT is input, the first latch circuit 312 can store (n+1) bits of the activation address ACT_ADD<0:m> as (n+1) bits of the partial address ACT_ADD<0:n>. For example, the first latch circuit 312 stores the lower 4 bits of the 12-bit activation address ACT_ADD<0:11> as the 4-bit partial address ACT_ADD<0:3>. In an embodiment, the lower 4 bits of the activation address ACT_ADD<0:11> can be used to designate a word line of the memory cell array 210. Referring to Figure 5 , the first latch circuit 312 can include a plurality of latches LAT10 to LAT1k, each of which can store (n+1) bits of the activation address ACT_ADD<0:m> as the partial address ACT_ADD<0:n> in response to the activation command ACT. The first latch circuit 312 can store a plurality of partial addresses ACT_ADD<0:n> as many times as the number of the latches LAT10 to LAT1k.

[0061] Referring back to Figure 4 , the address counter 314 can generate a plurality of count values by counting the number of inputs of the partial address ACT_ADD<0:n> input to each of the latches LAT10 to LAT1k each time the same partial address ACT_ADD<0:n> is stored in the corresponding one of the latches LAT10 to LAT1k in response to the activation command ACT. The address counter 314 can be initialized by the first target refresh command TREF1. That is, the address counter 314 can count the number of inputs of the partial address ACT_ADD<0:n> cumulatively during each period in which the first target refresh command TREF1 is issued. Referring to Figure 5 , the address counter 314 can include a plurality of counters CNT10 to CNT1k corresponding to the latches LAT10 to LAT1k, respectively. Each of the counters CNT10 to CNT1k can increase its count value by +1 each time the same partial address ACT_ADD<0:n> is stored in the corresponding one of the latches LAT10 to LAT1k.

[0062] Referring back to Figure 4 , the comparison analyzer 316 can compare the count values provided from the address counter 314 to arrange the partial addresses ACT_ADD<0:n> stored in the latches LAT10 to LAT1k, respectively, in a priority order of decreasing count values. The comparison analyzer 316 can sequentially store the partial addresses ACT_ADD<0:n> arranged in the priority order into the priority address memories 318_0 to 318_k, respectively. The priority address memories 318_0 to 318_k can output a priority address P_ADD<0:n> having a highest priority among the arranged partial addresses ACT_ADD<0:n> stored therein.

[0063] Figure 6 is a detailed block diagram illustrating a first random sampling circuit 320 of the Figure 3 according to an embodiment of the disclosure. Figure 7 is a detailed block diagram illustrating a target address generation circuit 330 of the Figure 6 according to an embodiment of the disclosure.

[0064] Referring back to Figure 6 , the first random sampling circuit 320 can include a first random signal generator 322 and a second latch circuit 324.

[0065] The first random signal generator 322 can generate a first sampling signal SAM_EN1 that is randomly enabled. The first random signal generator 322 can be implemented with a linear feedback shift register (LFSR) based random pattern generator.

[0066] The second latch circuit 324 can store the active address ACT_ADD<0:m> as a sampling address SAM_ADDx<0:m> according to the first sampling signal SAM_EN1, where x is an integer from 0 to j. For example, the second latch circuit 324 can include a plurality of latches LAT20 to LAT2j that can sequentially store the active address ACT_ADD<0:m> as the sampling address SAM_ADDx<0:m> whenever the first sampling signal SAM_EN1 is enabled. At this time, since each of the latches LAT20 to LAT2j can store all bits (i.e., (m+1) bits) of the active address ACT_ADD<0:m>, the second latch circuit 324 can have a larger size compared to the first latch circuit 312.

[0067] The target address generation circuit 330 can be activated in response to the first target refresh command TREF1. The target address generation circuit 330 can output any of the sample addresses in the sample addresses SAM_ADDx<0:m> that is identical to the priority address P_ADD<0:n> as the first target address TREF1_ADD<0:m> in response to the first target refresh command TREF1.

[0068] Referring to Figure 7 The target address generation circuit 330 can include a plurality of comparison output circuits 332_0 through 332_j and a buffer circuit 334.

[0069] The comparison output circuits 332_0 through 332_j can correspond to the sample addresses SAM_ADDx<0:m>, respectively. Each of the comparison output circuits 332_0 through 332_j can output a corresponding sample address in the sample addresses SAM_ADDx<0:m> by comparing the corresponding sample address with the priority address P_ADD<0:n>. Each of the comparison output circuits 332_0 through 332_j can output the corresponding sample address when a portion of bits in the corresponding sample address (e.g., SAM_ADDx<0:n>) is identical to all bits in the priority address P_ADD<0:n>. The buffer circuit 334 can buffer and output the sample addresses SAM_ADDx<0:m> output from the comparison output circuits 332_0 through 332_j as the first target address TREF1_ADD<0:m> in response to the first target refresh command TREF1. For example, when the priority address P_ADD<0:3> of "0101" is input in a state in which the first sample address SAM_ADD0<0:11> is "110101010101" and the second sample address SAM_ADD1<0:11> is "110101010111", the target address generation circuit 330 can output the first sample address SAM_ADD0<0:11> of which the lower 4 bits are identical to the priority address P_ADD<0:3> of "0101" as the first target address TREF1_ADD<0:11>.

[0070] With Figures 2 to 7With the above structure shown in FIG. 1, the refresh control module 130 can generate the first target address TREF1_ADD having a high number of activations (or a high activation frequency) by counting the number of inputs of the activation address ACT_ADD according to the activation command ACT. The refresh control module 130 can track only a small number of bits of the activation address ACT_ADD to predict the frequency of occurrence of the activation address, and randomly sample the activation address ACT_ADD based on the result of the prediction to select the first target address TREF1_ADD from among the selected activation addresses ACT_ADD. Thus, the memory system 10 can maximize the address sampling accuracy while reducing the area burden on the memory controller 100.

[0071] Figure 8 is a detailed block diagram of the semiconductor memory device 200 shown in FIG. 1, according to an embodiment of the present disclosure. Figure 1 is a detailed block diagram of the semiconductor memory device 200 shown in FIG. 1, according to an embodiment of the present disclosure. Figure 9 is a detailed block diagram of the semiconductor memory device 200 shown in FIG. 1, according to an embodiment of the present disclosure. Figure 8 is a detailed block diagram of the semiconductor memory device 200 shown in FIG. 1, according to an embodiment of the present disclosure.

[0072] Referring to Figure 8 The semiconductor memory device 200 can include a memory cell array 210, a row control circuit 212, a clock buffer 221, a command / address (CA) buffer 222, a command decoder 223, a target command generation circuit 224, and a refresh control circuit 230.

[0073] The memory cell array 210 can include a plurality of memory cells MC coupled to a word line WL and a bit line BL, and can be arranged in the form of an array. The memory cell array 210 can include at least one memory bank. The number of memory banks or the number of memory cells MC can be determined according to the capacity of the semiconductor memory device 200.

[0074] The clock buffer 221 can receive a clock CK from the memory controller 100. The clock buffer 221 can generate an internal clock CLK by buffering the clock CK. According to an embodiment, the memory controller 100 can deliver a system clock CK_t and CK_c to the semiconductor memory device 200 in a differential manner, and the semiconductor memory device 200 can include clock buffers that receive the differential clocks CK_t and CK_c, respectively.

[0075] The CA buffer 222 can receive a command / address signal C / A from the memory controller 100 based on the clock CK. The CA buffer 222 can sample the command / address signal C / A based on the clock CK, and output an internal command ICMD and an internal address IADD. Thus, the semiconductor memory device 200 can be synchronized with the clock CK.

[0076] The command decoder 223 can decode the internal command I CMD output from the CA buffer 222 to generate an activate command ACT, a precharge command PCG, a normal refresh command REF, and a first target refresh command TREF1. Although not shown, the command decoder 223 can additionally generate a read command RD, a write command WT, a mode register command MRS, etc. by decoding the internal command I CMD.

[0077] The target command generation circuit 224 can generate a second target refresh command TREF2 based on the normal refresh command REF. The target command generation circuit 224 can generate the second target refresh command TREF2 whenever the number of inputs of the normal refresh command REF reaches a certain number. In an embodiment, the frequency of the first target refresh command TREF1 issued by the refresh command issue circuit 132 of the memory controller 100 can be set differently from the frequency of the second target refresh command TREF2 issued by the target command generation circuit 224 of the semiconductor memory device 200. For example, the first target refresh command TREF1 can be generated after 4096 normal refresh commands REF are issued, and the second target refresh command TREF2 can be generated after 8092 normal refresh commands REF are issued.

[0078] The refresh control circuit 230 can latch the internal address IADD as a first target address ADD TREF1 according to the first target refresh command TREF1. The refresh control circuit 230 can latch the internal address IADD as an activate address ADD ACT according to the activate command ACT, and randomly sample the activate address ADD ACT to store a plurality of sample addresses ADD SAMy. When the first target address ADD TREF1 is identical to a second target address ADD TREF2, the refresh control circuit 230 can sequentially output the sample addresses ADD SAMy as the second target address ADD TREF2 according to the second target refresh command TREF2, while masking a current sample address and outputting a next sample address as the second target address ADD TREF2. The refresh control circuit 230 can output a final target address TADD by selecting any target address of the first target address ADD TREF1 and the second target address ADD TREF2 according to the second target refresh command TREF2.

[0079] For reference, the sample address SAM ADDx generated by the first random sampling circuit 320 of the memory controller 100 can be defined as a primary sample address, and the sample address ADD SAMy generated by the second random sampling circuit 234 of the semiconductor memory device 200 can be defined as a secondary sample address.

[0080] In detail, the refresh control circuit 230 can include a first latch 231, a second latch 232, a second random sampling circuit 234, an output control circuit 236, and an address selection circuit 238.

[0081] The first latch 231 can output a first target address ADD TREF1 by latching the internal address IADD according to a first target refresh command TREF1. The second latch 232 can output an activation address ADD ACT by latching the internal address IADD according to an activation command ACT.

[0082] The second random sampling circuit 234 can generate a sampling address ADD SAMy by randomly sampling the activation address ADD ACT.

[0083] In detail, the second random sampling circuit 234 can include a second random signal generator 2342 and a third latch circuit 2344.

[0084] The second random signal generator 2342 can generate a second sampling signal SAM EN2 that is randomly shifted or periodically shifted based on an internal clock CLK. The second random signal generator 2342 can be implemented with a random pattern generator based on a pseudo-random binary sequence (PRBS).

[0085] The third latch circuit 2344 can store the activation address ADD ACT as the sampling address ADD SAMy according to the second sampling signal SAM EN2, where y is an integer from 0 to i. For example, the third latch circuit 2344 can include a plurality of latches LAT30 to LAT3i, each of which can sequentially store the activation address ADD ACT as the sampling address ADD SAMy whenever the second sampling signal SAM EN2 is enabled.

[0086] The output control circuit 236 can sequentially output the sampling address ADD SAMy as a second target address ADD TREF2 according to a second target refresh command TREF2. When a comparison signal HIT is enabled, the output control circuit 236 can mask a current sampling address and output a next sampling address as the second target address ADD TREF2.

[0087] The address selection circuit 238 can output a final target address TADD by selecting any one of the first target address ADD TREF1 and the second target address ADD TREF2 according to the second target refresh command TREF2. The address selection circuit 238 can generate the comparison signal HIT by comparing the first target address ADD TREF1 with the second target address ADD TREF2.

[0088] Referring to Figure 9 , the address selection circuit 238 can include a selector 2382 and a comparator 2384.

[0089] The selector 2382 can output a final target address TADD by selecting any one of the first target address ADD TREF1 and the second target address ADD TREF2 according to the second target refresh command TREF2. The comparator 2384 can compare the first target address ADD TREF1 with the second target address ADD TREF2 and enable a hit signal HIT when corresponding bits in the first target address ADD TREF1 are the same as those in the second target address ADD TREF2.

[0090] Referring back to Figure 8 , the row control circuit 212 can activate a word line WL corresponding to the internal address IADD according to the activation command ACT and pre-charge the activated word line WL according to the pre-charge command PCG. To select a word line to be refreshed during a normal refresh operation, a refresh counter (not shown) can be additionally provided for generating a count address sequentially increased according to the normal refresh command REF. The row control circuit 212 can perform a normal refresh operation of sequentially refreshing a plurality of word lines WL corresponding to the count addresses according to the normal refresh command REF. The row control circuit 212 can perform a target refresh operation of refreshing one or more neighboring word lines of a word line WL corresponding to the final target address TADD according to the first target refresh command TREF1 or the second target refresh command TREF2.

[0091] Although not shown, the memory device 200 can further include a column control circuit for selecting a bit line corresponding to a column address among the internal address IADD according to a read command RD or a write command WT. The memory device 200 can output data DQ read from the memory cell array 210 through the bit line to the memory interface 150 of the memory controller 100 along with a data strobe signal DQS under the control of the column control circuit.

[0092] As described above, the semiconductor memory device 200 can perform a target refresh operation on neighboring word lines corresponding to the first target address ADD TREF1 in response to the first target refresh command TREF1 and perform a target refresh operation on neighboring word lines corresponding to the second target address ADD TREF2 different from the first target address ADD TREF1 in response to the second target refresh command TREF2. Thus, the memory system 10 according to the embodiment can prevent unnecessary target refresh operations according to the same address, thereby improving refresh efficiency.

[0093] Further, the second random signal generator 2342 used in the memory device 200 can generate a random sampling signal in a different scheme from the first random signal generator 322 used in the memory controller 100. Thus, the memory system 10 according to the embodiment can compensate for a randomization difficulty due to periodicity of a sampling circuit by a hybrid sampling algorithm, and further optimize a target refresh target selection.

[0094] In various embodiments of the present invention, although an example in which the first random signal generator 322 includes an LFSR-based random pattern generator and the second random signal generator 2342 includes a PRBS-based random pattern generator is described, the present invention is not limited thereto. According to the embodiment, the first random signal generator 322 can be implemented with any one selected from an LFSR-based or PRBS-based random pattern generator, and the second random signal generator 2342 can be implemented with another random pattern generator. That is, according to the embodiment, the first random signal generator 322 can be implemented according to any scheme selected from an LFSR-based or PRBS-based random pattern generation scheme, and the second random signal generator 2342 can be implemented according to another random pattern generation scheme.

[0095] Hereinafter, referring to Figures 1 to 10B , an operation of the memory system will be described.

[0096] Figure 10A and 10B is a timing diagram for describing an operation of the memory system according to an embodiment of the present disclosure.

[0097] Referring to Figure 10A , a case in which the first target address ADD_TREF1 is different from the second target address ADD_TREF2 is shown.

[0098] When the number of inputs of the activation command ACT reaches a certain number, the refresh command issuing circuit 132 of the memory controller 100 can issue the first target refresh command TREF1. The tracking circuit 134 can generate the first target address TREF1_ADD by sampling the activation address ACT_ADD in response to the activation command ACT. The command / address generation module 140 can output the first target refresh command TREF1 together with the first target address TREF1_ADD as a command / address signal C / A.

[0099] The CA buffer 222 of the semiconductor memory device 200 can receive the command / address signal C / A from the memory controller 100 to output an internal command I CMD and an internal address I ADD. The command decoder 223 can decode the internal command I CMD to generate a first target refresh command TREF1. At this time, the internal address I ADD can correspond to a first target address TREF1 ADD. According to the first target refresh command TREF1, the refresh control circuit 230 can output a first target address ADD TREF1 by latching the internal address I ADD at "A", and output a final target address TADD by selecting the first target address ADD TREF1. The row control circuit 212 can perform a target refresh operation of refreshing one or more adjacent word lines of a word line WL corresponding to the final target address TADD according to the first target refresh command TREF1. Specifically, the row control circuit 212 can perform the target refresh operation after a predetermined time from activation of the first target refresh command TREF1.

[0100] Next, the processor 120 can generate an activation command ACT and an activation address ACT ADD corresponding to the request REQ from the host. The command / address generation module 140 can provide the activation address ACT ADD with the activation command ACT as a command / address signal C / A. The semiconductor memory device 200 can output an internal command I CMD and an internal address I ADD according to the command / address signal C / A, and decode the internal command I CMD to generate the activation command ACT. The row control circuit 212 can perform an activation operation of activating a word line WL corresponding to the internal address I ADD according to the activation command ACT. Such an activation operation can be repeatedly performed whenever the activation command ACT is input.

[0101] Whenever the activation command ACT is input, the second latch 232 can output an activation address ADD ACT by latching the internal address I ADD, and the second random sampling circuit 234 can sequentially store the activation address ADD ACT as a sampled address ADD SAMy during an activation section in which the second sampling signal SAM EN2 is enabled. For example, the activation address ADD ACT of "C" can be stored as a first sampled address ADD SAM0 during a first activation section of the second sampling signal SAM EN2. The activation address ADD ACT of "E" can be stored as a second sampled address ADD SAM1 during a second activation section of the second sampling signal SAM EN2.

[0102] Thereafter, when the number of inputs of normal refresh commands REF reaches a certain number, the target command generation circuit 224 can generate a second target refresh command TREF2. The output control circuit 236 can output the first sample address ADD SAM0 of "C" as the second target address ADD TREF2 according to the second target refresh command TREF2. At this time, because the first target address ADD TREF1 of "A" is different from the second target address ADD TREF2 of "C", the address selection circuit 238 can disable the comparison signal HIT. The address selection circuit 238 can output the final target address TADD by selecting the second target address ADD TREF2 of "C" according to the second target refresh command TREF2. The row control circuit 212 can perform a target refresh operation of refreshing one or more neighboring word lines of the word line WL corresponding to the final target address TADD according to the second target refresh command TREF2. Specifically, the row control circuit 212 can perform the target refresh operation after a predetermined time from activation of the second target refresh command TREF2.

[0103] Reference Figure 10B , a case where the first target address ADD TREF1 is the same as the second target address ADD TREF2 is shown. In Figure 10B , the active address ADD ACT of "A" can be stored as the first sample address ADD SAM0 during the first active section of the second sample signal SAM EN2, and the active address ADD ACT of "E" can be stored as the second sample address ADD SAM1 during the second active section of the second sample signal SAM EN2.

[0104] The output control circuit 236 can output the first sample address ADD SAM0 of "A" as the second target address ADD TREF2 according to the second target refresh command TREF2. At this time, because the first target address ADD TREF1 of "A" is the same as the second target address ADD TREF2 of "A", the address selection circuit 238 can enable the comparison signal HIT. Thus, the output control circuit 236 can mask the first sample address ADD SAM0 of "A" while outputting the second sample address ADD SAM1 of "E" as the second target address ADD TREF2. The address selection circuit 238 can output the final target address TADD by selecting the second target address ADD TREF2 of "E" according to the second target refresh command TREF2. The row control circuit 212 can perform a target refresh operation of refreshing one or more neighboring word lines of the word line WL corresponding to the final target address TADD according to the second target refresh command TREF2. Specifically, the row control circuit 212 can perform the target refresh operation after a predetermined time from activation of the second target refresh command TREF2.

[0105] As described above, the memory device 200 can perform a target refresh operation according to a second target address ADD TREF2 different from a first target address ADD TREF1 corresponding to a most recently refreshed word line. Thus, the memory system 10 can prevent unnecessary target refresh operations according to the same address, thereby improving refresh efficiency.

[0106] Various embodiments of the present disclosure have been described in the drawings and the specification. Although specific terms are used herein, these terms are used only for the purpose of describing the embodiments of the present disclosure. Accordingly, the present disclosure is not limited to the above-described embodiments, and many variations are possible within the spirit and scope of the present disclosure. It will be apparent to those skilled in the art that various modifications can be made based on the technical idea of the present disclosure, in addition to the embodiments disclosed herein. The embodiments can be combined to form additional embodiments.

[0107] It should be noted that, although the technical spirit of the present disclosure has been described in connection with the embodiments of the present disclosure, this is only for the purpose of description and should not be construed as limiting. It will be understood by those skilled in the art that various changes can be made without departing from the technical spirit of the present disclosure and the appended claims.

[0108] For example, for the logic gates and transistors provided as examples in the above-described embodiments, different positions and types can be implemented according to the polarity of the input signal.

Claims

1. A memory system comprising: a memory controller adapted to: generate a first target address by sampling an activation address according to an activation command, provide the activation address together with the activation command, and provide a first target refresh command together with the first target address; and a memory device adapted to: generate a second target address by randomly sampling the activation address according to the activation command, perform a target refresh operation on at least one word line corresponding to the first target address according to the first target refresh command, and perform the target refresh operation on at least one word line corresponding to the second target address according to a second target refresh command.

2. The memory system of claim 1, wherein, the memory controller generates the first target address based on a priority address and a plurality of primary sample addresses, wherein the memory controller is further adapted to: generate the priority address by counting a number of inputs of a partial address corresponding to a partial bit of the activation address, and generate the primary sample addresses by randomly sampling the activation address, wherein the memory device generates the second target address based on a plurality of secondary sample addresses, and wherein the memory device further generates the plurality of secondary sample addresses by randomly sampling the activation address.

3. The memory system of claim 2, wherein the memory controller includes one of a random pattern generator based on a linear feedback shift register and a random pattern generator based on a pseudo-random binary sequence, and wherein the memory controller includes the other of the random pattern generators.

4. The memory system of claim 2, wherein the memory controller further generates the first target refresh command after generating a set number of normal refresh commands at regular intervals each time a number of inputs of the activation command reaches a certain number, and wherein the memory device further generates the second target refresh command each time a number of inputs of the normal refresh command reaches a set number.

5. The memory system of claim 1, wherein, the memory controller includes: a refresh command issuing circuit that issues the first target refresh command when a number of inputs of the activation command reaches a certain number; a partial sampling circuit adapted to: store a partial bit of the activation address as a partial address according to the activation command, and set a priority address by counting a number of inputs of the partial address; a first random sampling circuit that generates a plurality of primary sample addresses by randomly sampling the activation address; and a target address generation circuit that outputs any of the primary sample addresses that is identical to the priority address as the first target address in response to the first target refresh command.

6. The memory system of claim 5, wherein, the refresh command issuing circuit includes: a command counter that generates a count value by counting a number of inputs of the activation command; and a priority address generation circuit that sets the priority address by counting a number of inputs of the partial address. a counter analyzer which issues the first target refresh command after generating a set number of normal refresh commands at regular intervals when the count value reaches the certain number.

7. The memory system of claim 5, wherein, The partial sampling circuit includes: a first latch circuit including a plurality of latches each storing the partial bits in the active address as the partial address in response to the activation command; an address counter generating a plurality of count values by counting a number of inputs of the same partial address input to each of the latches during each cycle of issuance of the first target refresh command; a comparison analyzer arranging the partial addresses stored in the latches according to a priority by comparing the count values; and a plurality of priority address storages sequentially storing respective partial addresses arranged according to the priority therein, and outputting the priority address having the highest priority among the arranged partial addresses stored therein.

8. The memory system of claim 5, wherein, The first random sampling circuit includes: a first random signal generator generating a first sampling signal randomly enabled; and a second latch circuit sequentially storing the active address as the primary sampling addresses into a plurality of latches according to the first sampling signal.

9. The memory system of claim 5, wherein, The target address generating circuit includes: a plurality of comparison output circuits each adapted to output a corresponding primary sampling address among the primary sampling addresses when the corresponding primary sampling address is identical to the priority address by comparing the corresponding primary sampling address with the priority address; and a buffer circuit outputting the primary sampling address output from the comparison output circuit as the first target address in response to the first target refresh command.

10. The memory system of claim 1, wherein, The memory device includes: a second random sampling circuit generating a plurality of secondary sampling addresses by randomly sampling the active address; an output control circuit adapted to sequentially output the secondary sampling addresses as the second target addresses according to the second target refresh command, and to mask a current secondary sampling address in response to a comparison signal; and an address selection circuit adapted to output a final target address by selecting any target address among the first target address and the second target address according to the second target refresh command, and to generate the comparison signal when the first target address is identical to the second target address by comparing the first target address with the second target address.

11. The memory system of claim 10, wherein, The second random sampling circuit includes: a second random signal generator generating a second sampling signal randomly enabled; and a third latch circuit sequentially storing the active address as the secondary sampling addresses into a plurality of latches according to the second sampling signal.

12. The memory system of claim 10, wherein, The memory device further includes a row control circuit performing the target refresh operation on the word line corresponding to the final target address according to the first target refresh command or the second target refresh command.

13. A semiconductor memory device, comprising: a first latch which outputs a first target address by latching an internal address according to a first target refresh command; a second latch which outputs an activation address by latching the internal address according to an activation command; a second random sampling circuit which generates a plurality of sample addresses by randomly sampling the activation address; an output control circuit adapted to sequentially output the sample addresses as second target addresses according to a second target refresh command, and to mask a current sample address in response to a comparison signal; and an address selection circuit adapted to output a final target address by selecting any of the first target address and the second target address according to the second target refresh command, and to generate the comparison signal when the first target address and the second target address are identical by comparing the first target address with the second target address.

14. The semiconductor memory device of claim 13, further comprising a row control circuit which performs a target refresh operation on at least one word line corresponding to the final target address according to the first target refresh command or the second target refresh command. the second random sampling circuit includes:

15. The semiconductor memory device according to claim 13, wherein, a random signal generator which generates a sampling signal which is randomly enabled; and a latch circuit which sequentially stores the activation address as the sample addresses into a plurality of latches according to the sampling signal. the address selection circuit includes:

16. The semiconductor memory device according to claim 13, wherein, a selector which outputs the final target address by selecting any of the first target address and the second target address according to the second target refresh command; and a comparator which compares the first target address with the second target address, and generates the comparison signal when the first target address and the second target address are identical.

17. The semiconductor memory device of claim 13, further comprising: a command decoder which decodes a command to generate a normal refresh command, the first target refresh command, and the activation command; and a target command generation circuit which generates the second target refresh command when a number of inputs of the normal refresh command reaches a certain number.

18. An operating method of a memory system, comprising: generating, at a memory controller, a first target address by sampling an activation address according to an activation command; providing, at the memory controller, the activation address together with the activation command; providing, at the memory controller, a first target refresh command together with the first target address; performing, at a memory device, a target refresh operation on at least one word line corresponding to the first target address according to the first target refresh command; generating, at the memory device, a second target address by randomly sampling the activation address according to the activation command; and performing, at the memory device, the target refresh operation on at least one word line corresponding to the second target address according to a second target refresh command. the generating a first target address includes: storing part bits of the activation address as a part address according to the activation command; ​ 19. The method of operation of claim 18, wherein, ​ ​ setting a priority address by counting a number of inputs to the partial address; generating a plurality of primary sample addresses by randomly sampling the active addresses; and outputting, in response to the first target refresh command, any of the primary sample addresses that is identical to the priority address as the first target address.

20. The operating method of claim 19, wherein the generating the first target address includes sampling the active addresses according to a random pattern generation scheme selected from among a linear feedback shift register based random pattern generation scheme and a pseudo-random binary sequence based random pattern generation scheme, and wherein the generating the second target address includes sampling the active addresses according to another random pattern generation scheme.

21. The method of operating of claim 18, wherein, the generating the second target address includes: generating a plurality of secondary sample addresses by randomly sampling the active addresses; sequentially outputting the secondary sample addresses as the second target addresses according to the second target refresh command; when the first target address is identical to the second target address, masking a current secondary sample address and outputting a next secondary sample address; and outputting a final target address by selecting any of the first target address and the second target address according to the second target refresh command.

22. The operating method of claim 18, further comprising: at the memory controller, generating the first target refresh command after generating a set number of normal refresh commands at regular intervals whenever a number of inputs of the active command reaches a certain number; and at the memory device, whenever a number of inputs of the normal refresh command reaches a set number, the memory device generates the second target refresh command.

23. An operating method of a memory device, the operating method comprising: performing a first target refresh operation on a word line corresponding to a first target address in response to a first target refresh command, the first target address and the first target refresh command being received from a memory controller; generating a second target address by randomly sampling active addresses in response to an active command; determining whether a number of inputs of a normal refresh command reaches a threshold value; and performing a second target refresh operation on a word line corresponding to the second target address in response to determining that the number of inputs of the normal refresh command reaches the threshold value. ​

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