A single-bit differential SRAM memory and computing integrated array and device

Abstract

The present invention relates to a single-bit differential SRAM memory and computing integrated array and device. The array includes: a plurality of memory and computing integrated units, a first capacitor, and a second capacitor; each memory and computing integrated unit includes: a 6T-SRAM memory cell, a first inverter, a second inverter, a transistor TL3, and a transistor TR3; the first inverter is respectively connected to the memory cell and the drain of TL3, the gate of TL3 is used to input data IN, the source of TL3 is connected to one end of the first capacitor, and the other end of the first capacitor is grounded; the second inverter is respectively connected to the memory cell and the drain of TR3, the gate of TR3 is used to input data IN, the source of TR3 is connected to one end of the second capacitor, and the other end of the second capacitor is grounded. The memory and computing integrated array of the present invention simultaneously calculates a whole column of memory and computing integrated units during the calculation process, which has no influence on the weight value. This decoupling operation completely eliminates the read-write interference.

Description

Technical Field

[0001] The present invention relates to the technical field of in-memory computing, and in particular to a single-bit differential SRAM in-memory computing array and device. Background Art

[0002] The unprecedented growth in the scale of deep neural networks (DNNs) has led to a large amount of data needing to be moved from off-chip memory to on-chip processing cores in modern machine learning (ML) accelerators. Currently, the industry is exploring designs for performing analog DNN computations in memory arrays, and has developed in-memory computing (CIM) and processing-in-memory (PIM) methods to reduce the energy consumption of DNN processors by implementing parallel data processing in memory. CIM allows MAC operations to be performed in each column by activating multiple rows, rather than accessing the original data row by row as in traditional memory. This greatly reduces the amount of intermediate data generated and facilitates highly parallel computing.

[0003] The traditional method of calculating single-bit input multiplied by single-bit weight is inefficient, and since the weight is connected to the source and drain of the transistor, it will cause interference to the weight value when the bit-line voltage swing is too large during the calculation process; moreover, when performing multi-unit calculations, because the quantization range of the bit-line voltage is too small, a very precise quantization comparator is required to implement analog-to-digital conversion, and the design of a high-precision ADC is not easy. Otherwise, quantization errors will occur, and at the same time, a high-speed and high-precision ADC will bring a relatively large proportion of energy consumption, which is not conducive to optimizing the energy efficiency parameters. At the same time, during the multiply-accumulate calculation process, for the multiplication calculation with an input of 0, it actually has no impact on the calculation result. However, if the input multiplied by the weight is an asymmetric operation, its calculation result will have an unexpected impact. Summary of the Invention

[0004] The purpose of the present invention is to provide a single-bit differential SRAM in-memory computing array and device to achieve an enlarged quantization margin and no read / write interference.

[0005] To achieve the above object, the present invention provides a single-bit differential SRAM in-memory computing array, the array comprising:

[0006] M in-memory computing units, a first capacitor, and a second capacitor, where M is a positive integer greater than or equal to 1;

[0007] Each of the memory - in - computing units includes: a 6T - SRAM memory cell, a first inverter, a second inverter, transistor TL3, and transistor TR3; the input terminal of the first inverter is connected to the Q point of the 6T - SRAM memory cell, the output terminal of the first inverter is connected to the drain of transistor TL3, the gate of transistor TL3 is used to input data IN, the source of transistor TL3 is connected to one end of the first capacitor, and the other end of the first capacitor is grounded; the input terminal of the second inverter is connected to the QB point of the 6T - SRAM memory cell, the output terminal of the second inverter is connected to the drain of transistor TR3, the gate of transistor TR3 is used to input data IN, the source of transistor TR3 is connected to one end of the second capacitor, and the other end of the second capacitor is grounded; differential weight values are respectively stored at the Q point and the QB point;

[0008] The array further includes:

[0009] A differential quantizer, which is respectively connected to one end of the first capacitor and one end of the second capacitor, and is used to output a voltage difference.

[0010] Optionally, the 6T - SRAM memory cell includes:

[0011] Transistors TP1, TP2, TN1, TN2, TN3, and TN4;

[0012] The sources of transistor TP1 and transistor TP2 are both connected to the power supply VDD, the gates of transistor TP1, transistor TN1, the drain of transistor TP2, and the drain of transistor TN2 are all connected, and the connection point is called the QB point, the gates of transistor TP2, transistor TN2, the drain of transistor TP1, and the drain of transistor TN1 are all connected, and the connection point is called the Q point, the sources of transistor TN1 and transistor TN2 are both connected to the common terminal VSS, the gates of transistor TN3 and transistor TN4 are both connected to the word line, the drain of transistor TN3 is connected to the Q point, the source of transistor TN3 is connected to the bit line, the drain of transistor TN4 is connected to the anti - bit line, and the source of transistor TN4 is connected to the QB point.

[0013] Optionally, the first inverter includes transistors TL1 and TL2; the source of transistor TL1 is connected to the power supply VDD, the gates of transistor TL1 and transistor TL2 are both connected to the Q point, the drains of transistor TL1 and transistor TL2 are both connected to the drain of transistor TL3, and the source of transistor TL2 is grounded.

[0014] Optionally, the second inverter includes a transistor TR1 and a transistor TR2; the source of the transistor TR1 is connected to the power supply VDD, the gates of the transistor TR1 and the transistor TR2 are both connected to the QB point, the drains of the transistor TR1 and the transistor TR2 are both connected to the drain of the transistor TR3, and the source of the transistor TR2 is grounded.

[0015] The present invention also provides a single-bit differential SRAM computing-in-memory device, which includes:

[0016] N of the above computing-in-memory arrays, an input driving module, a bit line driving module, and a word line driving module, where N is a positive integer greater than or equal to 1;

[0017] The input driving module includes M data output terminals, and the data output terminals are used to output data IN;

[0018] The bit line driving module includes N bit line output terminals and N inverted bit line output terminals. The bit line output terminals are used to output bit lines, and the inverted bit line output terminals are used to output inverted bit lines;

[0019] The word line driving module includes M word line output terminals, and the word line output terminals are used to output word lines;

[0020] Each computing-in-memory unit in the i-th row is respectively connected to the i-th data output terminal of the input driving module, each computing-in-memory unit in the i-th row is respectively connected to the i-th word line output terminal of the word line driving module, each computing-in-memory unit in the j-th column is respectively connected to the j-th bit line output terminal of the bit line driving module, and each computing-in-memory unit in the j-th column is respectively connected to the j-th inverted bit line output terminal of the bit line driving module, where i is a positive integer greater than or equal to 1 and less than or equal to M, and j is a positive integer greater than or equal to 1 and less than or equal to N.

[0021] Optionally, N is 64 and M is 128.

[0022] According to the specific embodiments provided by the present invention, the following technical effects of the present invention are disclosed:

[0023] The present invention relates to a single-bit differential SRAM computing-in-memory array and device. The array includes: a plurality of computing-in-memory units, a first capacitor, and a second capacitor; each computing-in-memory unit includes: a 6T-SRAM storage unit, a first inverter, a second inverter, a transistor TL3, and a transistor TR3; the first inverter is respectively connected to the storage unit and the drain of TL3, the gate of TL3 is used to input data IN, the source of TL3 is connected to one end of the first capacitor, and the other end of the first capacitor is grounded; the second inverter is respectively connected to the storage unit and the drain of TR3, the gate of TR3 is used to input data IN, the source of TR3 is connected to one end of the second capacitor, and the other end of the second capacitor is grounded. The computing-in-memory array of the present invention performs simultaneous calculations on a whole column of computing-in-memory units during the calculation process, has no influence on the weight value. This decoupling operation completely eliminates read-write interference and expands the quantization margin. Description of the Drawings

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0025] Figure 1 Structural diagram of the single-bit differential SRAM computing-in-memory array of the present invention;

[0026] Figure 2 Structural diagram of the 6T-SRAM of the present invention;

[0027] Figure 3 Working schematic diagram of the present invention for calculating 1 × (-1) = -1;

[0028] Figure 4 Working schematic diagram of the present invention for calculating 1 × (+1) = +1;

[0029] Figure 5 Working schematic diagram of the present invention for calculating 0 × (+1 / -1) = 0;

[0030] Figure 6 Structural diagram of the single-bit differential SRAM computing-in-memory device of the present invention;

[0031] Symbol Explanation:

[0032] 1 - Input driving module, 2 - Bit line driving module, 3 - Word line driving module, 4 - Computing-in-memory array, 5 - Computing-in-memory unit, 6 - Differential quantizer, 7 - First inverter, 8 - Second inverter. Detailed Embodiments

[0033] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0034] The object of the present invention is to provide a single-bit differential SRAM memory-computation integrated array and device to achieve an enlarged quantization margin and no read-write interference.

[0035] To make the above objects, features, and advantages of the present invention more obvious and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0036] Embodiment 1

[0037] The present invention provides a single-bit differential SRAM memory-computation integrated array, and the array includes: M memory-computation integrated units 5 (i.e., Cells), a first capacitor C1, and a second capacitor C2, where M is a positive integer greater than or equal to 1. Taking 1 memory-computation integrated unit 5 as an example for discussion, as Figure 1 shown. Each of the memory-computation integrated units 5 includes: a 6T-SRAM storage unit, a first inverter 7, a second inverter 8, a transistor TL3, and a transistor TR3; the input end of the first inverter 7 is connected to the Q point of the 6T-SRAM storage unit, the output end of the first inverter 7 is connected to the drain of the transistor TL3, the gate of the transistor TL3 is used to input data IN, the source of the transistor TL3 is connected to one end of the first capacitor C1, and the other end of the first capacitor C1 is grounded; the input end of the second inverter 8 is connected to the QB point of the 6T-SRAM storage unit, the output end of the second inverter 8 is connected to the drain of the transistor TR3, the gate of the transistor TR3 is used to input data IN, the source of the transistor TR3 is connected to one end of the second capacitor C2, and the other end of the second capacitor C2 is grounded.

[0038] As an optional implementation manner, the array of the present invention further includes: a differential quantizer 6, which is respectively connected to one end of the first capacitor C1 and one end of the second capacitor C2, and is used to output a voltage difference OUT[4:0]. The voltage difference OUT[4:0] refers to the difference between the left read bit line (abbreviated as RBLL) and the right read bit line (abbreviated as RBLR). Figure 1The in-memory computing array consists of a 6T-SRAM cell for storing weights and multiply-accumulate (MAC) computing logic units on both the left and right sides. The MAC computing logic on the left side consists of a first inverter, transistor TL3, and coupling capacitor C1, and the MAC computing logic on the right side consists of a second inverter, transistor TR3, and coupling capacitor C2. In this embodiment, both transistor TL3 and transistor TR3 are NMOS transistors. Transistor TL3 and transistor TR3 are both controlled by the input data IN. When the input data IN = 1, the switch is turned on; otherwise, the switch is turned off.

[0039] As Figure 2 shown, the 6T-SRAM memory cell of the present invention includes: transistor TP1, transistor TP2, transistor TN1, transistor TN2, transistor TN3, and transistor TN4.

[0040] The source of transistor TP1 and the source of transistor TP2 are both connected to the power supply VDD. The gate of transistor TP1, the gate of transistor TN1, the drain of transistor TP2, and the drain of transistor TN2 are all connected to point QB. The gate of transistor TP2, the gate of transistor TN2, the drain of transistor TP1, and the drain of transistor TN1 are all connected to point Q. The source of transistor TN1 and the source of transistor TN2 are both connected to the common terminal VSS. The gate of transistor TN3 and the gate of transistor TN4 are both connected to the word line WL. The drain of transistor TN3 is connected to point Q. The source of transistor TN3 is connected to the bit line BL. The drain of transistor TN4 is connected to the complementary bit line BLB. The source of transistor TN4 is connected to point QB.

[0041] In this embodiment, transistor TP1, transistor TP2, transistor TN1, transistor TN2, transistor TN3, and transistor TN4 form a classic 6T-SRAM memory cell for storing weight values. Among them, the differential weight values are stored at point Q and point QB respectively. The word line ( W ord L ine, abbreviated as WL) is connected to the gates of transistor TN3 and transistor TN4 to control the on / off of transistor TN3 and transistor TN4. The bit line ( B it L ine, abbreviated as BL) is connected to the source of transistor TN3. The complementary bit line ( B it L ine BConnect the drain of transistor TN4 to it (abbreviated as BLB), pre-charge the bit line BL of the current column to a high level, then the anti-bit line BLB is at a low level. After setting the word line WL of the current row to a high level, transistors TN3 and TN4 are turned on, then the bit line BL will conduct with point Q, and point Q is charged to a high level. And after passing through the inverter composed of transistors TP2 and TN2, the value of point QB becomes a low level. At the same time, since the anti-bit line is at a low level, it also accelerates the discharge speed of point QB. This process completes the writing of a high level at point Q and a low level at point QB. In this embodiment, Q = 1, QB = 0 represents the weight W = +1, while Q = 0, QB = 1 represents the weight W = -1. (Note: Since BL, BLB, and WL related to the 6T-SRAM memory cell are only related to the weight writing and do not participate in the calculation process, for the sake of simplicity, Figure 1 、 Figure 3 and Figure 5 omit BL, BLB, and WL).

[0042] As Figure 1 shown, the first inverter 7 includes transistors TL1 and TL2; the source of transistor TL1 is connected to the power supply VDD, the gates of transistor TL1 and transistor TL2 are both connected to point Q, the drains of transistor TL1 and transistor TL2 are both connected to the drain of transistor TL3, and the source of transistor TL2 is grounded. The second inverter 8 includes transistors TR1 and TR2; the source of transistor TR1 is connected to the power supply VDD, the gates of transistor TR1 and transistor TR2 are both connected to point QB, the drains of transistor TR1 and transistor TR2 are both connected to the drain of transistor TR3, and the source of transistor TR2 is grounded. In this embodiment, both transistor TL2 and transistor TR2 are NMOS transistors, and both transistor TL1 and transistor TR1 are PMOS transistors.

[0043] In Figure 1 the left PMOS transistor TL1 and the NMOS transistor TL2 of the 6T-SRAM memory cell form the first inverter 7, and the Q value of the 6T-SRAM is connected to the gates of transistors TL1 and TL2. The source of transistor TL1 is connected to VDD, the source of transistor TL2 is connected to VSS, and the drains of transistors TL1 and TL2 are commonly connected to the right endpoint of the NMOS transistor TL3 (i.e., the drain of transistor TL3). The left end of TL3 is the left read bit line ( R ead B it L ine LOn the left (abbreviated as RBLL), RBLL is connected to the upper endpoint of capacitor C1 and also to the first input terminal of the differential quantizer. Similarly, on the right side of the 6T-SRAM memory cell, PMOS transistor TR1 and NMOS transistor TR2 form the second inverter 8, and the QB value of the 6T-SRAM memory cell is connected to the gates of transistor TR1 and transistor TR2. The source of transistor TR1 is connected to VDD, the source of transistor TR2 is connected to VSS, and the drains of transistor TR1 and transistor TR2 are commonly connected to the left endpoint of NMOS transistor TR3 (i.e., the drain of transistor TR3). The right end of TR3 is the right read bit line ( R ead B it L ine R ight, abbreviated as RBLR), RBLR is connected to the upper endpoint of capacitor C2 and also to the second input terminal of the differential quantizer.

[0044] The final calculation result is obtained by calculating the voltage difference between the two upper endpoints RBLL and RBLR of the coupling capacitors C1 and C2 in the differential quantizer 6. The specific truth table and calculation logic are as follows:

[0045] The calculation logic truth table is shown in Table 1:

[0046] Table 1 Calculation Logic Truth Table

[0047]

[0048] As described in the calculation logic of Table 1, the first column is the input value Input, where a high level indicates an input of 1 and a low level indicates an input of 0; the second column is the weight Weight. When Q = 1 and QB = 0, it means the weight Weight = +1, and when Q = 0 and QB = 1, it means the weight Weight = -1; the third column is the calculation result, that is, the input weight product (Input Weight Product, abbreviated as IWP). When the voltage on RBLR minus the voltage on RBLL is positive, it means IPW = +1, and when the voltage on RBLR minus the voltage on RBLL is negative, it means IPW = -1. The specific calculation process is as follows:

[0049] Take Figure 1 the array in as an example, and pre-charge the coupling capacitor voltage to 0.6V.

[0050] The schematic diagram of calculating 1 × (-1) = -1 is as shown in Figure 3 (in the figure, the light-colored part of the circuit indicates non-conduction and non-operation, the dark color is conduction and operation, and the arrow direction is the current flow direction). The working process is as follows:

[0051] If the input data is 1, both transistor TL3 and transistor TR3 are in the conducting state, the weight value W = -1, then Q = 0. So in the MAC calculation logic on the left side of the 6T - SRAM memory cell, TL1 is conducting with VDD, and transistor TL2 is in the cut-off state. The upper endpoint RBLL of the coupling capacitor C1 will be charged by VDD through the conducting TL1 and TL3. Eventually, there will be an increase in voltage of +ΔV on RBLL. At the same time, QB = 1. So in the MAC calculation logic on the right side of the 6T - SRAM memory cell, transistor TR2 is conducting with VSS, and transistor TR1 is in the cut-off state. The upper endpoint RBLR of the coupling capacitor C2 will be discharged by VSS through the conducting transistor TR2 and transistor TR3. Eventually, there will be a decrease of -ΔV on RBLR. The voltage difference V RBLR -V RBLL = (-ΔV) - (+ΔV) = -2ΔV. This design stipulates that a negative voltage difference is the logical negative value -1. So in this process, IN = 1, W = -1, and IWP = 1×(-1) = -1.

[0052] The schematic diagram of calculating 1 × (+1) = +1 is as Figure 4 shown. (In the figure, the lightly shaded part of the circuit represents non-conducting and non-operating, the dark part is conducting and operating, and the arrow direction is the current flow direction). The working process is as follows:

[0053] If the input data is 1, both transistor TL3 and transistor TR3 are in the conducting state, the weight value W = +1, then Q = 1. So in the MAC calculation logic on the left side of the 6T - SRAM memory cell, transistor TL2 is conducting with VSS, and transistor TL1 is in the cut-off state. The upper endpoint RBLL of the coupling capacitor C1 will be discharged by VSS through the conducting transistor TL3 and transistor TL2. Eventually, there will be a decrease in voltage of -ΔV on RBLL. At the same time, QB = 0. So in the MAC calculation logic on the right side of the 6T - SRAM memory cell, transistor TR1 is conducting with VDD, and transistor TR2 is in the cut-off state. The upper endpoint RBLR of the coupling capacitor C2 will be charged by VDD through the conducting transistor TR1 and transistor TR3. Eventually, there will be an increase of +ΔV on RBLR. The voltage difference V RBLR -V RBLL = (+ΔV) - (-ΔV) = +2ΔV. This design stipulates that a positive voltage difference is the logical positive value +1. So in this process, IN = 1, W = +1, and IWP = 1×(+1) = +1.

[0054] The schematic diagram of calculating 0 × (+1 / -1) = 0 is as Figure 5 shown. (In the figure, the lightly shaded part of the circuit represents non-conducting and non-operating, the dark part is conducting and operating, and the arrow direction is the current flow direction). The working process is as follows:

[0055] If the input data is 0, then both the transistor TL3 and the transistor TR3 in the MAC calculation logic circuit are in the cut-off region. Whether the weight W = +1 or W = -1, there is no path between the coupling capacitors C1, C2 and VDD, or VSS. Therefore, there is no voltage fluctuation on RBLL and RBLR, so V RBLR -V RBLL = 0, indicating that IN = 0, W = +1 / -1, and IWP = 0.

[0056] The above three calculations are the multiplication calculation results that each Cell may have due to different inputs and weights. In this design, the accumulation of the multiplication results is achieved by connecting the bit lines in the same column. The calculation results of each cell are accumulated on RBLL and RBLR in the form of analog voltages respectively, and finally, the voltage difference is obtained through a differential quantizer and quantized into a 5-bit digital value.

[0057] Embodiment 2

[0058] The present invention also provides a single-bit differential SRAM memory and computing integrated device, and the device includes:

[0059] N memory and computing integrated arrays 4, an input driving module 1, a bit line driving module 2, and a word line driving module 3 in Embodiment 1, where N is a positive integer greater than or equal to 1; the input driving module 1 includes M data output terminals, and the data output terminals are used to output data IN; the bit line driving module 2 includes N bit line output terminals and N anti-bit line output terminals, the bit line output terminals are used to output bit lines, and the anti-bit line output terminals are used to output anti-bit lines; the word line driving module 3 includes M word line output terminals, and the word line output terminals are used to output word lines; each memory and computing integrated unit 5 in the i-th row is respectively connected to the i-th data output terminal of the input driving module 1, each memory and computing integrated unit 5 in the i-th row is respectively connected to the i-th word line output terminal of the word line driving module 3, each memory and computing integrated unit 5 in the j-th column is respectively connected to the j-th bit line output terminal of the bit line driving module 2, and each memory and computing integrated unit 5 in the j-th column is respectively connected to the j-th anti-bit line output terminal of the bit line driving module 2, where i is a positive integer greater than or equal to 1 and less than or equal to M, and j is a positive integer greater than or equal to 1 and less than or equal to N.

[0060] In this embodiment, taking N as 64 and M as 128 as an example, the device structure diagram is as Figure 6 shown, including 64 memory and computing integrated arrays 4, and each memory and computing integrated array 4 includes 128 memory and computing integrated units 5 (i.e., Cells).

[0061] The input driving module 1 includes 128 data output terminals, which are used to output 128 data, namely IN0 - IN127.

[0062] The bit line driving module 2 includes 64 bit line terminals and 64 complementary bit line terminals; the 64 bit line terminals are used to output 64 bit lines, namely BL0 - BL63 respectively; the 64 complementary bit line terminals are used to output 64 complementary bit lines, namely BLB0 - BLB63 respectively.

[0063] The word line driving module 3 includes 128 word line terminals, which are used to output 128 word lines, namely WL0 - WL127 respectively.

[0064] The in-memory computing unit 5 at the i-th row and j-th column is respectively connected to the i-th data output terminal of the input driving module 1, the i-th word line output terminal of the word line driving module 3, the j-th bit line output terminal and the j-th complementary bit line output terminal of the bit line driving module 2. The left read bit lines of each in-memory computing array are represented by RBLL0 - RBLL63, the right read bit lines are represented by RBLR0 - RBLR63, and the outputs of 64 differential quantizers 6 are represented by OUT0[4:0] - OUT64[4:0].

[0065] A single-bit differential SRAM (Static Random Access Memory) in-memory computing array and device with enlarged quantization margin and no read-write interference disclosed by the present invention. The in-memory computing array and device are composed of multiple in-memory computing units. The in-memory computing unit 5 (Cell) is composed of 1 6T-SRAM weight storage unit and 2 computing circuits. The computing circuits are symmetrically distributed on both sides of the weight unit, and can realize hardware acceleration for neural networks with 1-bit input and 1-bit weight. The product sum of the input and the weight is represented by the charge and discharge of the load capacitor, and the quantization result is determined by the voltage difference between the load capacitors on both sides after the calculation. The final analog calculation result is quantized into a 5-bit digital value and output through a differential quantizer. This in-memory computing device can complete the multiply-accumulation calculation of 128 single-bit data and 128 single-bit weights by column at one time, and realize fully parallel vector matrix multiplication within a single cycle.

[0066] The solution disclosed by the present invention has the following advantages:

[0067] The in-memory computing unit 5 designed by the present invention uses a classic 6T-SRAM storage unit to store weight values, and controls the gates of transistors TL1, TL2, TR1 and TR2 with the weight values. During the calculation process, a whole column of in-memory computing units can be calculated simultaneously without affecting the weight values. This decoupling operation completely eliminates read-write interference.

[0068] In the operation part of the in-memory computing unit designed by the present invention, the amount of half multiply-accumulate operations is simplified. There are four types of multiplication combinations in traditional in-memory computing, namely 1×1 = 1, 1×0 = 0, 0×1 = 0, and 0×0 = 0. In the present invention, the input data IN is used to control the transistor TL3 and the transistor TR3. Only when the input data IN = 1, the circuit conducts to perform charge and discharge operations. When the input data IN = 0, the circuit does not conduct, and the charge and discharge circuits are both in a holding state, eliminating the invalid part where the input data 0 is multiplied by the weight to be 0, saving half of the amount of operations, and greatly improving both power consumption and computing speed.

[0069] In the present invention, the weight is represented by a binary value, that is, W = -1 or W = +1. When the input data IN = 1, the total voltage accumulation effects of the calculation paths on both sides of the calculation cell always present opposite results. The calculation result obtained by finally taking the voltage difference has a larger quantization range than the single-sided charge and discharge, and at the same time, the requirement for the quantization accuracy of the differential quantizer is reduced, which will reduce the design complexity of the quantization circuit.

[0070] The multiplication calculation effect of a single cell in the present invention is twice that of the conventional single-sided calculation voltage difference, which will reduce the quantization pressure of the analog-to-digital conversion, making it easier for the differential quantizer to quantize the multiply-accumulate result.

[0071] This design uses a shared coupling capacitor and a differential quantizer for each column, instead of the traditional design where each calculation capacitor is mounted with a small capacitor, reducing a certain area in the later layout design implementation, and indirectly reducing the problem of capacitor leakage.

[0072] In this specification, each embodiment is described in a progressive manner. The key point of each embodiment is to illustrate the differences from other embodiments. The same or similar parts among the embodiments can be referred to each other.

[0073] In this article, specific examples are used to elaborate on the principle and implementation manner of the present invention. The descriptions of the above embodiments are only used to help understand the method and its core idea of the present invention; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present invention.

Claims

1. A single-bit differential SRAM computing-in-memory array, characterized in that, the array includes: M computing-in-memory units, a first capacitor and a second capacitor, where M is a positive integer greater than or equal to 1; each of the computing-in-memory units includes: a 6T-SRAM memory cell, a first inverter, a second inverter, transistor TL3 and transistor TR3; the input terminal of the first inverter is connected to the Q point of the 6T-SRAM memory cell, the output terminal of the first inverter is connected to the drain of transistor TL3, the gate of transistor TL3 is used to input data IN, the source of transistor TL3 is connected to one end of the first capacitor, and the other end of the first capacitor is grounded; the input terminal of the second inverter is connected to the QB point of the 6T-SRAM memory cell, the output terminal of the second inverter is connected to the drain of transistor TR3, the gate of transistor TR3 is used to input data IN, the source of transistor TR3 is connected to one end of the second capacitor, and the other end of the second capacitor is grounded; the differential weight values are respectively stored at the Q point and the QB point; the array further includes: a differential quantizer, connected to one end of the first capacitor and one end of the second capacitor respectively, for outputting a voltage difference.

2. The single-bit differential SRAM computing-in-memory array according to claim 1, characterized in that, the 6T-SRAM memory cell includes: transistors TP1, TP2, TN1, TN2, TN3 and TN4; the sources of transistor TP1 and transistor TP2 are both connected to the power supply VDD, the gates of transistor TP1, the gate of transistor TN1, the drains of transistor TP2 and transistor TN2 are all connected, and the connection point is called the QB point, the gates of transistor TP2, the gate of transistor TN2, the drains of transistor TP1 and transistor TN1 are all connected, and the connection point is called the Q point, the sources of transistor TN1 and transistor TN2 are both connected to the common terminal VSS, the gates of transistor TN3 and transistor TN4 are both connected to the word line, the drain of transistor TN3 is connected to the Q point, the source of transistor TN3 is connected to the bit line, the drain of transistor TN4 is connected to the anti-bit line, and the source of transistor TN4 is connected to the QB point.

3. The single-bit differential SRAM computing-in-memory array according to claim 2, characterized in that, the first inverter includes transistors TL1 and TL2; the source of transistor TL1 is connected to the power supply VDD, the gates of transistor TL1 and transistor TL2 are both connected to the Q point, the drains of transistor TL1 and transistor TL2 are both connected to the drain of transistor TL3, and the source of transistor TL2 is grounded.

4. The single-bit differential SRAM computing-in-memory array according to claim 3, characterized in that, The second inverter includes a transistor TR1 and a transistor TR2; the source of the transistor TR1 is connected to the power supply VDD, the gates of the transistor TR1 and the transistor TR2 are both connected to the QB point, the drains of the transistor TR1 and the transistor TR2 are both connected to the drain of the transistor TR3, and the source of the transistor TR2 is grounded.

5. A single-bit differential SRAM memory and computing integrated device, characterized in that the device includes: N memory and computing integrated arrays according to any one of claims 1-4, an input driving module, a bit line driving module, and a word line driving module, where N is a positive integer greater than or equal to 1; the input driving module includes M data output terminals, and the data output terminals are used to output data IN; the bit line driving module includes N bit line output terminals and N anti-bit line output terminals, the bit line output terminals are used to output bit lines, and the anti-bit line output terminals are used to output anti-bit lines; the word line driving module includes M word line output terminals, and the word line output terminals are used to output word lines; Each memory and computing unit in the i-th row is respectively connected to the i-th data output terminal of the input driving module, each memory and computing unit in the i-th row is respectively connected to the i-th word line output terminal of the word line driving module, each memory and computing unit in the j-th column is respectively connected to the j-th bit line output terminal of the bit line driving module, and each memory and computing unit in the j-th column is respectively connected to the j-th anti-bit line output terminal of the bit line driving module, where i is a positive integer greater than or equal to 1 and less than or equal to M, and j is a positive integer greater than or equal to 1 and less than or equal to N.

6. The single-bit differential SRAM memory and computing integrated device according to claim 5, characterized in that N is 64 and M is 128.

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