Semiconductor memory device and test system including semiconductor memory device

Abstract

Disclosed are a semiconductor memory device and a test system including the same. The semiconductor memory device includes a test mode data storage configured to store test write pattern data in response to a register write command and a register address during a test operation, and to output test read pattern data in response to a test read command and a test mode data selection signal; a memory cell array including a plurality of memory cells and configured to generate read data; a read path unit configured to generate n read data by serializing the read data; and a test read data generation unit configured to generate n test read data by comparing the test read pattern data with each of the n read data generated at a first data rate during the test operation, and to generate the n test read data at a second data rate lower than the first data rate.

Description

[0001] Korean Patent Application No. 10-2020-0174328, entitled "Semiconductor Memory Device and Test System Including Semiconductor Memory Device", filed on December 14, 2020 with the Korean Intellectual Property Office, is incorporated herein by reference in its entirety. Technical Field

[0002] The embodiments relate to semiconductor memory devices and test systems including semiconductor memory devices. Background Technology

[0003] Once a semiconductor memory device is manufactured, the manufacturer can use test equipment to perform tests (e.g., parallel bit test) to test whether the semiconductor memory device is functioning correctly. Summary of the Invention

[0004] The embodiment relates to a semiconductor memory device, the semiconductor memory device comprising: a test mode data storage device configured to, during a test operation, store test write mode data having a first predetermined number of bits in response to a register write command and a register address, and output test read mode data having a first predetermined number of bits in response to a test read command and a test mode data selection signal; a row decoder configured to generate a plurality of word line selection signals by decoding a row address; a column decoder configured to generate a plurality of column selection signals by decoding a column address; and a memory cell array including a plurality of memory cells and configured to generate test read mode data from one of the plurality of word line selection signals and the plurality of column selection signals. The memory cell selected by one of the selection signals generates read data with multiple bits; the read path unit is configured to generate n read data, each having a first predetermined number of bits, by serializing the read data with the multiple bits; and the test read data generation unit is configured to, during a test operation, generate n test read data, each having a third predetermined number of bits, by comparing test read mode data with the first predetermined number of bits generated at a first data rate with each of the n read data with the first predetermined number of bits, by a second predetermined number of bits, and generate the n test read data with the third predetermined number of bits at a second data rate lower than the first data rate.

[0005] The embodiments also relate to a semiconductor memory, the semiconductor memory comprising: a command and address generator configured to, during a test operation, generate a register address and a register write command, generate a row address and a test activation command, or generate a column address and a test write command, or generate a column address and a test mode data selection signal and a test read command by receiving and decoding test commands / addresses in response to a test clock signal; and a test mode data storage device configured to, during a test operation, generate a register address and a register write command, generate a row address and a test activation command, or generate a column address and a test write command, or generate a column address and a test mode data selection signal and a test read command by receiving and decoding test commands / addresses and dedicated signals in response to a test clock signal; and a test mode data storage device configured to, during a test operation, respond to register write commands and addresses and dedicated signals... The system includes a memory address for storing test write mode data having a first predetermined number of bits, and outputs test read mode data having a first predetermined number of bits in response to a test read command and a test mode data selection signal; a row decoder configured to generate multiple word line selection signals by decoding the row address; a column decoder configured to generate multiple column selection signals by decoding the column address; and a memory cell array comprising multiple memory cells and configured to store write data having multiple bits in a memory cell selected by one of the multiple word line selection signals and one of the multiple column selection signals, or from a selected memory cell. The test write data generation unit is configured to, during a test operation, in response to a test write clock signal, copy each of n test write data having a second predetermined number of bits applied at a first data rate, or invert and copy n test write data having a second predetermined number of bits applied at a first data rate, and generate n write data each having a first predetermined number of bits at a second data rate higher than the first data rate; a write path unit is configured to generate write data having multiple bits by parallelizing the n write data each having a first predetermined number of bits; and a read path unit is configured to generate write data having multiple bits. The path unit is configured to generate n read data having a first predetermined number of bits by serializing read data having multiple bits; and the test read data generation unit is configured to, during a test operation, generate n test read data each having a fourth predetermined number of bits by comparing test read pattern data having a first predetermined number of bits with each of the n read data having a first predetermined number of bits generated at a first data rate, and generate the n test read data each having a fourth predetermined number of bits at a third data rate lower than the first data rate.

[0006] The embodiment also relates to a test system, the test system comprising: a test device configured to: apply a test command / address in response to a test clock signal, send test data or test write mode data having a first predetermined number of bits in response to a test write clock signal, and receive test data; and a semiconductor memory device comprising: a test mode data storage device configured to, during a test operation, store test write mode data having a first predetermined number of bits in response to a register address when the test command / address is a register write command and a register address, and output test read mode data having a first predetermined number of bits in response to a test read command and a test mode data selection signal when the test command / address is a test read command and a test mode data selection signal; a row decoder configured to generate a plurality of word line selection signals by decoding the row address; and a column decoder configured to... To generate multiple column select signals by decoding column addresses, a memory cell array, comprising multiple memory cells and configured to generate read data having multiple bits from a memory cell selected by one of the multiple word line select signals and one of the multiple column select signals, a read path unit configured to generate n read data, each having a first predetermined number of bits, by serializing the read data having the multiple bits, and a test read data generation unit configured to, during a test operation, generate n test read data, each having a third predetermined number of bits, by comparing test read mode data having a first predetermined number of bits with each of the n read data having a first predetermined number of bits generated at a first data rate, and generate the n test read data each having a third predetermined number of bits at a second data rate lower than the first data rate. Attached Figure Description

[0007] The features will become clear to those skilled in the art from a detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0008] Figure 1 This is a block diagram illustrating a test system according to an example embodiment.

[0009] Figure 2A and Figure 2B This is a block diagram illustrating a semiconductor memory device according to an example embodiment.

[0010] Figure 3 This is a block diagram illustrating a command and address generation unit according to an example embodiment.

[0011] Figure 4 This is a diagram illustrating the truth table of commands and addresses applied from a test device according to an example embodiment.

[0012] Figure 5AThis is a diagram illustrating a test mode data storage device according to an example embodiment, and Figure 5B This is a diagram illustrating a test mode data storage device according to an example embodiment.

[0013] Figure 6 This is a reference timing diagram used to describe register write operations according to an example embodiment.

[0014] Figure 7 This is a diagram illustrating the configuration of the test write data generation unit according to an example embodiment.

[0015] Figure 8 This is a timing diagram used to describe a test write operation according to an example embodiment.

[0016] Figure 9 This is a diagram illustrating the configuration of a test read data generation unit according to an example embodiment.

[0017] Figure 10 This is a timing diagram used to describe a test read operation according to an example embodiment. Detailed Implementation

[0018] Figure 1 This is a block diagram illustrating a test system according to an example embodiment.

[0019] Reference Figure 1 The test system 1000 may include a test device 100 and a semiconductor memory device 200.

[0020] Test device 100 can send test clock signal TCK, test command / address TCA, test clock enable signal TCKE, test command / address bus inversion signal TCABI and test reset signal TRESET to semiconductor memory device 200, and can send and receive test data TDQ.

[0021] The semiconductor memory device 200 can receive a test clock signal TCK, a test command / address TCA, a test clock enable signal TCKE, a test command / address bus inversion signal TCABI, and a test reset signal TRESET, and can send and receive test data TDQ.

[0022] The test clock signal TCK can be applied via the clock signal terminal CKP. The test command / address signal TCA can be applied via the command / address terminal CAP. The test clock enable signal TCKE can be applied via the clock enable terminal CKEP. The test command / address bus inversion signal TCABI can be applied via the command / address bus inversion signal terminal CABIP. The test reset signal TRESET can be applied via the reset signal terminal RESETP. Test data TDQ can be input and output via the data terminal DQP.

[0023] The test device 100 can apply a test command / address TCA on the rising and falling edges of the test clock signal TCK, can send test data TDQ or test write mode data TPDQ at a first data rate (e.g., single data rate (SDR)) in response to the rising edge of the test write clock signal TWCK during a test write operation, and can receive test data TDQ sent at a second data rate equal to or lower than the first data rate during a test read operation.

[0024] Semiconductor memory device 200 may be a semiconductor memory device that operates at a third data rate (e.g., double data rate (DDR)) during normal operation, and may be, for example, a DDR, low power DDR (LPDDR), or graphics DDR (GDDR) device.

[0025] During a test write operation, the semiconductor memory device 200 can receive test data TDQ input at a first data rate and can internally generate test write data at a third data rate higher than the first data rate.

[0026] The semiconductor memory device 200 can generate test read data by comparing internally pre-stored test mode data with read data generated internally at a third data rate, and generate test read data as test data TDQ at a second data rate during the test read operation.

[0027] The test clock enable signal TCKE, the test command / address bus inversion signal TCABI, and the test reset signal TRESET can be used as test mode data selection signals during test read operations. However, during normal operation, the clock enable signal CKE (applied via the clock enable signal terminal CKEP) can be used to deactivate the internal clock signal (not shown), data input unit (not shown), and data output unit (not shown) in the semiconductor memory device 200; the command / address bus inversion signal CABI (applied via the command / address bus inversion signal terminal CABIP) can be used to invert the command / address bus; and the reset signal RESET (applied via the reset signal terminal RESETP) can be used to reset the semiconductor memory device 200. In other words, the test clock enable signal TCKE, the test command / address bus inversion signal TCABI, and the test reset signal TRESET can be dedicated signals used for special purposes during normal operation.

[0028] When the Test Clock Enable signal TCKE, Test Command / Address Bus Invert signal TCABI, and Test Reset signal TRESET are at a "low" level, this indicates that the signals are activated. When these signals are at a "high" level, this indicates that the signals are deactivated.

[0029] Figure 2A and Figure 2B This is a block diagram illustrating a semiconductor memory device according to an example embodiment.

[0030] Reference Figure 2A and Figure 2B The semiconductor memory device 200 may include a power-on signal generator 20, an initialization unit 22, a command and address generation unit 24, a mode setting register 26, an internal clock signal generator 28, a delay controller 30, a test mode data storage device 32, a row decoder 34, a column decoder 36, a memory cell array 38, a read path unit 40, a test read data generation unit 42, a data output unit 44, a write path unit 46, a test write data generation unit 48, a data input unit 50, and a first switch SW1 to a sixth switch SW6.

[0031] The following will describe Figure 2A and Figure 2B The function of the block shown in the image.

[0032] The power-on signal generator 20 can detect the level of the memory voltage EV and generate a power-on signal pup when the memory voltage EV reaches the target voltage level.

[0033] The initialization unit 22 can generate an initialization signal init in response to the power-on signal pup and the test reset signal TRESET during test operation, or generate an initialization signal init in response to the power-on signal pup and the reset signal RESET during normal operation.

[0034] Command and address generation unit 24 can generate mode setting code OPC and mode setting command MRS by decoding test command / address TCA in response to test clock signal TCK. Mode setting code OPC may include information related to test mode enable signal TMRSEN, test write mode control signal TWRP, write delay WL, read delay RL and / or burst length BL.

[0035] When the test mode enable signal TMRSEN is activated, or when both the test mode enable signal TMRSEN and the initialization signal init are activated, the command and address generation unit 24 can generate the register address REGADD and the register write command REGWR by decoding the test command / address TCA in response to the test clock signal TCK.

[0036] Furthermore, when the test mode enable signal TMRSEN is activated, the command and address generation unit 24 can decode the applied test command / address TCA in response to the test clock signal TCK to generate the test activation command TACT and row address RADD, and generate the test write command TWR and column address CADD.

[0037] Furthermore, when the test mode enable signal TMRSEN is activated, the command and address generation unit 24 can use the test command / address TCA, the test clock enable signal TCKE, the test command / address inversion signal TCABI, and the test reset signal TRESET applied in response to the test clock signal TCK to generate the test read command TRD, the column address CADD, and the test mode data selection signal OTFPS.

[0038] During normal operation, the command and address generation unit 24 can decode the command and address CA in response to the clock signal CK and the clock enable signal CKE to generate the row address RADD and the activation command ACT, generate the column address CADD and the write command WR or the read command RD, and generate the mode setting code OPC and the mode setting command MRS.

[0039] The mode setting register 26 can set the write delay WL, read delay RL, burst length BL, test mode enable signal TMRSEN, and test write mode control signal TWRP by using the mode setting code OPC applied together with the mode setting command MRS.

[0040] During test operation, the internal clock signal generator 28 can receive the test clock signal TCK and the test write clock signal TWCK, and generate the internal clock signal ICK and the internal write clock signals IWCK and IWCK'. During normal operation, the internal clock signal generator 28 can receive the clock signal CK and the write clock signal TWCK, and generate the internal clock signal ICK and the internal write clock signal IWCK.

[0041] During test or normal operation, the delay controller 30 may generate a write delay signal WLC in response to a test write command TWR or a write command WR and an internal clock signal ICK (the write delay signal WLC is activated after a period corresponding to the write delay WL and deactivated after a period corresponding to the burst length BL), and the delay controller 30 may generate a read delay signal RLC in response to a test read command TRD or a read command RD and an internal clock signal ICK (the read delay signal RLC is activated after a period corresponding to the read delay RL and deactivated after a period corresponding to the burst length BL).

[0042] The test mode data storage device 32 may include multiple registers (not shown). During test operation, the test mode data storage device 32 may store test write mode data TPDQ in a register selected from multiple registers in response to the register write command REGWR and the register address REGADD, and output test read mode data tpd in a register selected from multiple registers in response to the test read command TRD and the test mode data selection signal OTFPS.

[0043] During test or normal operation, the line decoder 34 can generate multiple word line selection signals wl by decoding the line address RADD.

[0044] During test or normal operation, column decoder 36 can generate multiple column selection signals csl by decoding column address CADD.

[0045] The memory cell array 38 may include a plurality of memory cells (not shown). The memory cell array 38 may store write data DI into a memory cell selected by a plurality of word line selection signals wl and a plurality of column selection signals csl, or output read data DO from a memory cell selected by a plurality of word line selection signals wl and a plurality of column selection signals csl. For example, each of the write data DI and the read data DO may be y bits of data, and y bits may be 256 bits.

[0046] During test read operations and normal read operations, read path unit 40 can generate n m-bit read data do (here referred to as n read data) by serializing read data DO (for example, each of n and m can be an integer greater than 4). For example, read path unit 40 can generate 16 16-bit read data do in DDR 1-bit order by serializing 256-bit read data DO.

[0047] When the first switch SW1 is closed in response to the test read command TRD, the test read data generation unit 42 can generate n (m / L) bit test read data tdo (which may be referred to herein as n test read data) by comparing each of the n m-bit read data do with the m-bit test read mode data tpd in L-bit increments, and serialize each of the n (m / L) bit test read data tdo at a second data rate in 1-bit increments in response to the read delay signal RLC and the internal test write clock signal IWCK' (e.g., L can be an integer greater than 2). For example, the test read data generation unit 42 can generate 16 8-bit, 4-bit, 2-bit, or 1-bit test read data tdo by comparing each of the 16 16-bit read data do with the 16-bit test read mode data tpd in 2-bit, 4-bit, 8-bit, or 16-bit increments, and serialize each of the 16 8-bit, 4-bit, 2-bit, or 1-bit test read data tdo sequentially in 1-bit increments.

[0048] When the second switch SW2 is closed in response to the test read command TRD, the data output unit 44 can drive each of the n (m / L) bits of test read data tdo at a second data rate of 1 bit to generate n test data TDQs. When the third switch SW3 is closed in response to the read command RD, the data output unit 44 can drive each of the n m-bit normal read data ndo at a third data rate of 1 bit to generate n data DQs. For example, during a test read operation, the data output unit 44 can generate 16 8-bit, 4-bit, 2-bit, or 1-bit test read data tdos by driving each of the 16 8-bit, 4-bit, 2-bit, or 1-bit test read data tdos sequentially at a second data rate of 1 bit, while during a normal read operation, the data output unit 44 can generate 16 16-bit data DQs by driving each of the 16 16-bit normal read data ndos sequentially at a third data rate of 1 bit.

[0049] During test write operations and normal write operations, write path unit 46 can generate y-bit write data DI by parallelizing n m-bit write data di. For example, write path unit 46 can generate 256-bit write data DI by parallelizing 16 16-bit write data di.

[0050] During the test write operation, when the fourth switch SW4 and the fifth switch SW5 are closed, the test write data generation unit 48 can receive n x-bit test write data tdi applied at a first data rate in response to the internal write clock signal IWCK, and generate n m-bit write data di at a third data rate. For example, the test write data generation unit 48 can receive 16 8-bit, 4-bit, 2-bit, or 1-bit test write data tdi applied at SDR in response to the rising edge of the test write clock signal TWCK, and generate 16 16-bit write data di at DDR in response to the rising and falling edges of the internal write clock signal IWCK (which has the same frequency as the test write clock signal TWCK).

[0051] During a test write operation, when the fifth switch SW5 is closed, the data input unit 50 can receive and buffer each of the n test data TDQ input at the second data rate in 1-bit increments in response to the test write clock signal TWCK, and generate n x-bit test write data tdi. During a normal write operation, when the sixth switch SW6 is closed, the data input unit 50 can receive and buffer each of the n data TQ input at the third data rate in 1-bit increments in response to the write clock signal WCK, and generate n m-bit normal write data ndi at the third data rate.

[0052] Figure 3 This is a block diagram illustrating a command and address generation unit according to an example embodiment.

[0053] Reference Figure 3 The command and address generation unit 24 may include a test command and address generator 24-2 and a normal command and address generator 24-4.

[0054] The following will describe Figure 3 The function of the block shown in the image.

[0055] When the test mode enable signal TMRSEN is activated, the test command and address generator 24-2 can decode the test command / address TCA in response to the test clock signal TCK, and can generate the register write command REGWR and register address REGADD, generate the mode set code OPC and mode set command MRS, generate the row address RADD and test activation command TACT, or generate the column address CADD and test write command TWR.

[0056] Furthermore, when the test mode enable signal TMRSEN is activated, the test command and address generator 24-2 can use the test clock enable signal TCKE, the test command / address bus inversion signal TCABI, the test reset signal TRESET, and the test command / address TCA applied in response to the test clock signal TCK to generate the test read command TRD, the column address CADD, and the test mode data selection signal OTFPS. In one example, the test command and address generator 24-2 can generate the column address CADD, the test mode data selection signal OTFPS, and the test read command TRD by receiving and decoding at least one of the test clock enable signal TCKE, the test command / address bus inversion signal TCABI, and the test reset signal TRESET, as well as the test command / address TCA, in response to the test clock signal TCK.

[0057] The Test Mode Data Select (OTFPS) signal can be a predetermined number of bits of data. For example, the Test Mode Data Select (OTFPS) signal can consist of at least one of the Test Clock Enable (TCKE), Test Command / Address Bus Invert (TCABI), and Test Reset (TRESET), as well as data generated from at least one address signal in the Test Command / Address (TCA) that is not used to indicate the Test Read Command (TRD) and Column Address (CADD) (or is not used to indicate the Column Address).

[0058] During normal operation, the normal command and address generator 24-4 can decode the command and address CA in response to the clock signal CK and the clock enable signal CKE, and can generate the row address RADD and the activation command ACT, generate the column address CADD and the write command WR or the read command RD, and generate the mode setting code OPC and the mode setting command MRS.

[0059] Figure 4 This is a diagram illustrating the truth table of commands and addresses applied from a test device according to an example embodiment.

[0060] Reference Figure 4 The mode setting command MRS can be indicated when the command signals TCA9 and TCA8 included in the test command / address TCA are at a "high" level H and a "low" level L respectively on the rising edge (R) of the test clock signal TCK, and when the command signals TCA9 and TCA8 included in the test command / address TCA are at a "high" level H and a "low" level L respectively on the falling edge (F) of the test clock signal TCK. Figure 4 The address signal in shaded area I indicates the address of mode setting register 26, and Figure 4 The address signal in shaded area II indicates the mode setting code OPC.

[0061] The register write command REGWR can be indicated when both command signals TCA9 and TCA8 included in the test command / address TCA are at a "high" level H on the rising edge of the test clock signal TCK, and when command signals TCA9, TCA8, TCA7, and TCA6 included in the test command / address TCA are at a "high" level H, a "low" level L, a "high" level H, and a "low" level L, respectively, on the falling edge of the test clock signal TCK. Figure 4 The address signal in shaded area III indicates the register address REGADD of test mode data storage device 32.

[0062] and Figure 4 Unlike the case shown, the area marked with "X" can also be used to indicate the register address REGADD of the test mode data storage device 32.

[0063] The test activation command TACT can be indicated when the command signal TCA9, included in the test command / address TCA, is at a "low" level L on the rising edge of the test clock signal TCK. Figure 4 The address signal in the shaded area IV can indicate the memory address. Figure 4 The address signal in the shaded area V indicates the row address RADD.

[0064] The test write command TWR can be indicated when both command signals TCA9 and TCA8 included in the test command / address TCA are at a "high" level H on the rising edge of the test clock signal TCK, and when all of the command signals TCA9 to TCA6 included in the test command / address TCA are at a "low" level L on the falling edge of the test clock signal TCK. Figure 4 The address signal in the shaded region IV indicates the memory address. Figure 4 The address signal in the shaded area VI indicates the column address CADD. "V" represents a "high" level H or a "low" level L (defined logic level).

[0065] The test read command TRD can be indicated when both command signals TCA9 and TCA8 included in the test command / address TCA are at a "high" level H on the rising edge of the test clock signal TCK, and when command signals TCA9, TCA8, TCA7, and TCA6 included in the test command / address TCA are at a "low" level L, a "high" level H, a "low" level L, and a "low" level L, respectively, on the falling edge of the test clock signal TCK. Figure 4 The address signal in the shaded area IV can indicate the memory address. Figure 4 The address signal in the shaded area VI indicates the column address CADD.

[0066] In addition, the test clock enable signal TCKE, the test command / address bus inversion signal TCABI, and the test reset signal TRESET applied at the rising and falling edges of the test clock signal TCK, as well as the address signals TCA5 and TCA3 (which are not used to indicate column addresses) applied at the falling edge of the test clock signal TCK, can indicate the test mode data selection signal OTFPS.

[0067] Figure 5A This is a diagram illustrating a test mode data storage device according to an example embodiment.

[0068] Reference Figure 5A The test mode data storage device 32 may include an address decoder 32-2, a register unit 32-4, and an input / output unit 32-6.

[0069] Address decoder 32-2 can decode register address REGADD in response to register write command REGWR to activate one of k register select signals rsel1 to rselk (k can be an integer greater than 2). Address decoder 32-2 can decode test mode data select signal OTFPS in response to test read command TRD to activate one of k register select signals rsel1 to rselk.

[0070] Register unit 32-4 may include k registers REG1 to REGk. The k registers REG1 to REGk may store or output m-bit test mode data TPD in response to k selection signals rsel1 to rselk.

[0071] Input / output unit 32-6 can respond to the register write command REGWR and output m-bit test write mode data TPDQ as m-bit test mode data TPD. Input / output unit 32-6 can respond to the test read command TRD and output m-bit test mode data TPD as m-bit test read mode data tpd.

[0072] Figure 5B This is a diagram illustrating a test mode data storage device according to an example embodiment.

[0073] Reference Figure 5B The test mode data storage device 32' may include an address decoder 32-2', a register unit 32-4', and a selector 32-6'.

[0074] Address decoder 32-2' can decode register address REGADD in response to register write command REGWR, activating one of k register select signals rsel1 to rselk.

[0075] Register unit 32-4' may include k registers REG1 to REGk. The k registers REG1 to REGk may store m bits of test mode data TPD in response to k selection signals rsel1 to rselk, and output k m bits of test mode data TPD in response to the test read command TRD.

[0076] Selector 32-6' can respond to the test read command TRD and the test mode data selection signal OTFPS to select one of k m-bit test mode data TPDs and output the selected m-bit test mode data TPD as m-bit test read mode data tpd.

[0077] Figure 6 This is a reference timing diagram used to describe register write operations according to an example embodiment.

[0078] Reference Figure 6 Test commands / addresses TCA_F11 and TCA_S11 can be applied at the rising and falling edges of the test clock signal TCK, respectively, and m-bit test mode data TPD1 can be applied as test write mode data TPDQ in response to the test write clock signal TWCK. The command COM included in test commands / addresses TCA_F11 and TCA_S11 indicates the register write command REGWR. The address ADD included in test commands / addresses TCA_F11 and TCA_S11 indicates the register address REGADD1. A register select signal rsel1 corresponding to the register address REGADD1 can be generated in response to the register write command REGWR. Figure 5A The test mode data storage device 32 can store m-bit test mode data TPD1 in register REG1 in response to the register selection signal rsel1.

[0079] When the register address REGADD changes from REGADD2 to REGADDk and the test mode data TPD changes from TPD2 to TPDk, the above operation can be repeated to store different (k-1) m-bit test mode data TPD2 to TPDk in (k-1) registers REG2 to REGk respectively.

[0080] Figure 7 This is a diagram illustrating the configuration of the test write data generation unit according to an example embodiment.

[0081] Reference Figure 7 The test write data generation unit 48 may include a copy circuit 48-2 and a copy and reverse circuit 48-4. Figure 7The configuration of a test write data generator corresponding to one of the n data terminals DQP1 to DQPn is shown. For example, when there are 16 data terminals, the test write data generation unit 48 may include 16 test write data generators.

[0082] The replication circuit 48-2 can send test write data tdi as write data di in response to the "high" level of the internal write clock signal IWCK.

[0083] The copy and reverse circuit 48-4 can send test write data tdi as write data di in response to a "low" level of the internal write clock signal IWCK, or send inverted test write data as write data di.

[0084] For example, when the test write mode control signal TWRP is at a "low" level, the copy and reverse circuit 48-4 can send test write data tdi as write data di, and when the test write mode control signal TWRP is at a "high" level, the copy and reverse circuit 48-4 can reverse the test write data tdi and send the reversed test write data as write data di.

[0085] Figure 8 This is a timing diagram used to describe a test write operation according to an example embodiment.

[0086] Before performing a test write operation, a mode setting operation can be performed in response to the mode setting command MRS to activate the test mode enable signal TMRSEN, set the write latency WL to 3, set the burst length BL to 16, and set the test write mode control signal TWRP. Then, the line address RADD1 can be applied in response to the test activation command TACT.

[0087] Figure 8 This is based on the assumption that continuous test write operations are performed after row address RADD1 is applied together with the test activation command TACT.

[0088] Reference Figure 8 Test commands / addresses TCA_F21 and TCA_S21 can be applied in response to the rising and falling edges of the test clock signal TCA_K, respectively. The command COM included in test commands / addresses TCA_F21 and TCA_S21 can instruct the test write command TWR. The address ADD included in test commands / addresses TCA_F21 and TCA_S21 can include the column address CADD1.

[0089] Reference Figure 2B and Figure 8Row decoder 34 can decode row address RADD1 to select one of a plurality of word line select signals wl (e.g., wl1 (not shown)), and column decoder 36 can decode column address CADD1 to select one of a plurality of column select signals csl (e.g., csl1 (not shown)). Memory cells of memory cell array 38 can be selected by one of the plurality of word line select signals wl and one of the plurality of column select signals csl.

[0090] Reference Figure 8 Three cycles after the test clock cycle TCK from the application of the test command and address TCA_F21, the test data TDQ "01010101" is applied in SDR in response to the test write clock signal TWCK.

[0091] Reference Figure 2B and Figure 7 When the test write mode control signal TWRP is at a "low" level, the test write data generator of the test write data generation unit 48 can copy the test write data "01010101" applied through the data input unit 50, and generate write data di "0011001100110011" in DDR mode in response to the internal write clock signal IWCK (which has the same frequency as the test write clock signal TWCK). Alternatively, when the test write mode control signal TWRP is at a "high" level, the test write data generator of the test write data generation unit 48 can copy and invert the test write data tdi "01010101" applied through the data input unit 50, and generate write data di "0110011001100110" in DDR mode in response to the internal write clock signal IWCK. The test write data generation unit 48 can generate each of the 16 16-bit write data di in 1-bit sequential order. The write path unit 46 can receive 16 16-bit write data di, parallelize the 16 16-bit write data di, and output 256-bit write data DI to the selected memory unit.

[0092] Subsequently, the write data di "00000000000000000" or "0101010101010101" can be stored in the memory cell selected by row address RADD1 and column address CADD2 by performing the above operations. Furthermore, the write data di "1111111111111111" or "1010101010101010" can then be stored in the memory cell selected by row address RADD1 and column address CADD3.

[0093] In the above test write operation, even because Figure 1Due to the operating speed limitations of the test equipment 100 shown, test data TDQ is applied in SDR in response to the test write clock signal TWCK. The semiconductor memory device 200 can also generate test write data tdi internally in DDR in response to the internal write clock signal IWCK.

[0094] Figure 9 This is a diagram illustrating the configuration of a test read data generator included in a test read data generation unit according to an example embodiment.

[0095] Reference Figure 9 The test read data generator 42' may include a comparison unit 42” and a register 42-5. The comparison unit 42” includes a first comparator 42-1 to a fourth comparator 42-4.

[0096] Figure 9 Based on the following assumptions: the 16-bit test read mode data tpd is tpd15 to tpd0, and the serially applied 16-bit read data do is do15 to do0.

[0097] Figure 9 The configuration of a test read data generator 42' corresponding to one of the n data terminals DQP1 to DQPn is shown. For example, when there are 16 data terminals, the test read data generation unit 42 may include 16 test read data generators 42'.

[0098] Reference Figure 9 The first comparator 42-1 compares the 4-bit test read mode data tpd15 to tpd12 with the 4-bit read data do15 to do12. When the 4-bit test read mode data tpd15 to tpd12 matches the 4-bit read data do15 to do12, the first comparator 42-1 generates the data "0"; otherwise, the first comparator 42-1 generates the data "1".

[0099] The second comparator 42-2 compares the 4-bit test read mode data tpd11 to tpd8 with the 4-bit read data do11 to do8. When the 4-bit test read mode data tpd11 to tpd8 match the 4-bit read data do11 to do8, the second comparator 42-2 generates the data "0"; otherwise, the second comparator 42-2 generates the data "1".

[0100] Similarly, each of the third comparator 42-3 and the fourth comparator 42-4 can generate the data "0" or "1" by comparing different 4-bit data.

[0101] Register 42-5 stores the data output from the first comparator 42-1 to the fourth comparator 42-4 as 4-bit test read data tdo3 to tdo0, and generates the test read data tdo3 to tdo0 sequentially, one bit at a time, in response to the internal write clock signal IWCK'. For example, the internal write clock signal IWCK' is a signal with a frequency four times lower than the internal write clock signal IWCK, and may have the same frequency as the test clock signal TCK. The test read data tdo3 to tdo0 may be generated in response to the rising edge of a clock signal with a frequency equal to or lower than the frequency of the test write clock signal TWCK.

[0102] Figure 10 This is a timing diagram used to describe a test read operation according to an example embodiment.

[0103] Before performing a test read operation, a mode setup operation can be performed in response to the mode setup command MRS to activate the test mode enable signal TMRSEN, set the read latency RL to 3, and set the burst length BL to 16. Then, the line address RADD1 can be applied in response to the test activation command TACT.

[0104] Figure 10 This is based on the assumption that continuous test read operations are performed after row address RADD1 is applied together with the test activation command TACT.

[0105] Reference Figure 10 Test commands / addresses TCA_F31 and TCA_S31 can be applied respectively in response to the rising and falling edges of the test clock signal TCK. (See reference...) Figure 4 The command COM included in test command / address TCA_F31 and test command / address TCA_S31 may instruct the test read command TRD, and the address ADD included in test command / address TCA_F31 and test command / address TCA_S31 may include the column address CADD1.

[0106] Reference Figure 2B and Figure 10Row decoder 34 can decode row address RADD1 to select one of a plurality of word line select signals wl (e.g., wl1 (not shown)), and column decoder 36 can decode column address CADD1 to select one of a plurality of column select signals csl (e.g., csl1 (not shown)). Memory cells of memory cell array 38 can be selected by one of the plurality of word line select signals wl and one of the plurality of column select signals csl, and generate y-bit read data DO. Read path unit 40 can generate n m-bit read data do "1011001100110011" by serializing the y-bit read data DO.

[0107] Reference Figure 4 and Figure 10 The addresses included in test command / address TCA_F31 and test command / address TCA_S31 can indicate the portion of the test mode data select signal OTFPS that is set to "0" (e.g., the least significant bit (LSB)), and the test clock enable signal TCKE, test reset signal TRESET, and test command / address bus inversion signal TCABI can indicate the remaining portion of the test mode data select signal OTFPS that is set to "000000" (e.g., the high 6 bits). In other words, the test mode data select signal OTFPS can be "0000000".

[0108] Reference Figure 2A , Figure 5A , Figure 5B and Figure 9 The test mode data storage device 32, in response to the test mode data selection signal OTFPS, outputs the test mode data TPD1 "0011001100110011" stored in register REG1 of register unit 32-4 or 32-4' as test read mode data tpd. The test read data generator of the test read data generation unit 42 compares the 16-bit read data do "1011001100110011" with the 16-bit test read mode data tpd "0011001100110011" in 4-bit increments, and generates 4-bit test read data tdo "1000" sequentially bit by bit in response to the internal write clock signal IWCK'. When the 16-bit read data do and the 16-bit test read mode data tpd are completely matched, 4-bit test read data tdo "0000" can be generated. The data output unit 44 can serially generate each of n 4-bit test read data tdo as test data TDQ.

[0109] Although the test read data generator of the test read data generation unit 42 has been described in the above example embodiment as generating 4-bit test read data tdo serially, the test read data generator may be configured to include two comparators and thus generate 2-bit test read data tdo serially, may be configured to include eight comparators and thus generate 8-bit test read data tdo serially, or may be configured to include 16 comparators and thus generate 16-bit test read data tdo.

[0110] In the aforementioned test read operation, the semiconductor memory device 200 can internally compare the m-bit test mode data with the m-bit read data bit by bit (m / k) (where k is an integer less than m and greater than 2) to generate test read data that is k bits less than m bits, and then send the test read data to the test device 100. Therefore, the semiconductor memory device 200 can send the test data TDQ to the test device 100 at a data rate equal to or lower than the SDR. Thus, although the operating speed of the test device 100 is limited, the test time is not increased.

[0111] By summarizing and reviewing, the test equipment can perform test operations at the same operating speed as the semiconductor memory device performing normal operations using the control unit (e.g., central processing unit (CPU) or graphics processing unit (GPU)) in the actual memory system. However, the operating speed of the test equipment has not increased accordingly compared to the ever-increasing operating speeds of semiconductor memory devices; therefore, the operating speed of the semiconductor memory device precedes the operating speed of the test equipment. For example, while a semiconductor memory device may be able to send and receive data at a rate of 16 gigabits per second (GB), the test equipment may only be able to send and receive data at a rate of 8 GB per second. Therefore, it takes longer to test the semiconductor memory device.

[0112] As described above, the embodiments may provide a semiconductor memory device that reduces test time, and a test system including the semiconductor memory device.

[0113] According to the example embodiment, even when the operating speed of the test equipment is lower than the operating speed of the semiconductor memory device, the semiconductor memory device can internally generate test read data by comparing test mode data with read data generated at a third data rate, and output the test read data at a second data rate lower than the first data rate. Therefore, the test time is not increased.

[0114] Example embodiments have been disclosed herein. Although specific terminology has been used, it is used in a general and descriptive sense only and will be interpreted in a way that is not intended to be limiting. In some instances, as will be apparent to those skilled in the art, unless otherwise expressly indicated, features, characteristics, and / or elements described in connection with particular embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, as at the time of filing of this application. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A semiconductor memory device, comprising: Test mode data storage device, the test mode data storage device is configured to: Test write mode data is stored in response to a register write command and a register address, wherein each test write mode data has a first predetermined number of bits, and In response to a test read command and a test mode data selection signal, test read mode data is output, wherein each test read mode data has a first predetermined number of bits; The line decoder generates word line selection signals by decoding the line address; The column decoder generates the column selection signal by decoding the column address; The memory cell array outputs data from memory cells selected by word line select signals and column select signals; A read path unit is configured to generate n read data at a first data rate by serializing data from a memory cell array, wherein each of the n read data has a first predetermined number of bits, where n is an integer greater than 4; and The test read data generation unit is configured to perform the following during the test operation: n test read data are generated by comparing the test read pattern data with each of the n read data, wherein each of the n test read data has a third predetermined number of bits, and wherein the comparison is performed based on a second predetermined number of bits. The n test read data are generated at a second data rate, wherein the second data rate is lower than the first data rate.

2. The semiconductor memory device according to claim 1, further comprising: Command and address generators are configured to run during test operations: By receiving and decoding test commands / addresses in response to a test clock signal, register addresses and register write commands are generated, row addresses and test activation commands are generated, or column addresses and test write commands are generated, or... The test command / address and dedicated signals are received and decoded in response to the test clock signal to generate column address, test mode data selection signal and test read command.

3. The semiconductor memory device of claim 2, wherein, The test mode data selection signal uses an address that is not used to indicate the column address, which is included in the address signal in the test command / address, and is generated using a dedicated signal.

4. The semiconductor memory device according to claim 3, wherein, Specialized signals include at least one of the following: a test clock enable signal, a test command and address bus inversion signal, and a test reset signal used for special purposes during normal operation.

5. The semiconductor memory device according to claim 2, wherein, The test mode data storage device includes a register unit, which contains multiple registers. The test mode data storage device is configured to: store test mode data in one of the plurality of registers in response to a register address, or output test mode data from one of the plurality of registers in response to a test mode data selection signal. The test mode data storage device is also configured as follows: In response to the register write command and the register address, test write mode data is sent as test mode data, and In response to the test read command and the test mode data selection signal, the test mode data is sent as the test read mode data.

6. The semiconductor memory device according to any one of claims 2 to 5, wherein, The test read data generation unit includes n test read data generators. Each of the n test read data generators includes a comparison unit configured to generate test read data by comparing test read pattern data with read data.

7. The semiconductor memory device according to claim 6, further comprising: The test write data generation unit is configured as follows: Copy each of the n test writes at a third data rate, or copy and reverse each of the n test writes at a third data rate, each test write having a fourth predetermined number of bits, and n write data are generated at a first data rate, each write data having a first predetermined number of bits. The first data rate is higher than the third data rate, and the second data rate is equal to or lower than the third data rate.

8. The semiconductor memory device according to claim 7, wherein, The test command / address is applied in response to the rising and falling edges of the test clock signal. Each of the n test write data is applied in response to the rising edge of a test write clock signal with a higher frequency than the test clock signal, and Each of the n test read data is generated in response to the rising edge of a clock signal having a frequency equal to or lower than that of the test write clock signal.

9. A semiconductor memory device, comprising: Command and address generators are configured to run during test operations: By receiving and decoding test commands / addresses in response to a test clock signal, register addresses and register write commands are generated, row addresses and test activation commands are generated, or column addresses and test write commands are generated, or... By receiving and decoding test commands / addresses and dedicated signals in response to the test clock signal, column addresses, test mode data selection signals, and test read commands are generated. Test mode data storage device, the test mode data storage device is configured to: Test write mode data is stored in response to a register write command and a register address, wherein each test write mode data has a first predetermined number of bits, and In response to a test read command and a test mode data selection signal, test read mode data is output, wherein each test read mode data has a first predetermined number of bits; The line decoder generates word line selection signals by decoding the line address; The column decoder generates the column selection signal by decoding the column address; The memory cell array outputs data from memory cells selected by word line select signals and column select signals; The test write data generation unit is configured to perform the following during the test operation: In response to a test write clock signal, n test write data are copied at a first data rate, or n test write data are copied and reversed at the first data rate, wherein each test write data has a second predetermined number of bits, where n is an integer greater than 4. n write data are generated at a second data rate, wherein the second data rate is higher than the first data rate, and each write data has a first predetermined number of bits; A write path unit is configured to parallelize the n write data; A read path unit, configured to serialize data output from a memory cell array to generate n read data, each of the n read data having a first predetermined number of bits; and The test read data generation unit is configured to perform the following during the test operation: n test read data are generated by comparing the test read pattern data with each of the n read data generated at a second data rate, wherein the comparison is performed based on a third predetermined number of bits, and wherein each of the n test read data has a fourth predetermined number of bits. The n test read data are generated at a third data rate, wherein the third data rate is lower than the first data rate.

10. The semiconductor memory device according to claim 9, wherein, The test mode data selection signal uses an address that is not used to indicate the column address, which is included in the address signal in the test command / address, and is generated using a dedicated signal.

11. The semiconductor memory device of claim 10, wherein, Specialized signals include at least one of the following: a test clock enable signal, a test command and address bus inversion signal, and a test reset signal used for special purposes during normal operation.

12. The semiconductor memory device according to any one of claims 9 to 11, wherein, The test read data generation unit includes n test read data generators. Each of the n test read data generators includes a comparison unit configured to generate test read data by comparing test read pattern data with read data.

13. The semiconductor memory device according to claim 12, wherein, The test command / address is applied in response to the rising and falling edges of the test clock signal. Each of the n test write data is applied on the rising edge of the test write clock signal. Each of the n test read data is generated in response to the rising edge of a clock signal having a frequency equal to or lower than that of the test write clock signal.

14. A testing system, comprising: The test equipment is configured as follows: Apply test commands / addresses in response to the test clock signal. In response to the test write clock signal, test data or test write mode data with a first predetermined number of bits is sent, and Receive test data; as well as Semiconductor memory devices, the semiconductor memory devices include: Test mode data storage device, the test mode data storage device is configured to: When the test command / address is a register write command and a register address, test write mode data is stored in response to the register address, wherein each test write mode data has a first predetermined number of bits, and When the test command / address is a test read command and a test mode data selection signal, test read mode data is output in response to the test mode data selection signal, wherein each test read mode data has a first predetermined number of bits. The line decoder generates word line selection signals by decoding the line address. The column decoder generates the column selection signal by decoding the column address. The memory cell array outputs data from memory cells selected via word line select signals and column select signals. A read path unit is configured to serialize data output from a memory cell array to generate n read data items, each of the n read data items having a first predetermined number of bits, where n is an integer greater than 4. The test read data generation unit is configured to perform the following during the test operation: n test read data are generated by comparing the test read pattern data with each of the n read data generated at a first data rate, wherein the comparison is performed based on a second predetermined number of bits, and wherein each of the n test read data has a third predetermined number of bits. The n test read data are generated at a second data rate, wherein the second data rate is lower than the first data rate.

15. The testing system according to claim 14, wherein, The semiconductor memory device also includes a command and address generator, which is configured to: By receiving and decoding test commands / addresses in response to a test clock signal, register addresses and register write commands are generated, row addresses and test activation commands are generated, or column addresses and test write commands are generated, or... The test command / address and dedicated signals are received and decoded in response to the test clock signal to generate column address, test mode data selection signal and test read command.

16. The testing system according to claim 15, wherein, The test mode data selection signal uses an address that is not used to indicate the column address, which is included in the address signal in the test command / address, and is generated using a dedicated signal.

17. The testing system according to claim 16, wherein, Specialized signals include at least one of the following: a test clock enable signal, a test command and address bus inversion signal, and a test reset signal used for special purposes during normal operation.

18. The testing system according to claim 15, wherein, The test mode data storage device includes a register unit, which contains multiple registers. The test mode data storage device is configured to: store test mode data in one of the plurality of registers in response to a register address, or output test mode data from one of the plurality of registers in response to a test mode data selection signal. The test mode data storage device is also configured as follows: In response to the register write command and the register address, test write mode data is sent as test mode data, and In response to the test read command and the test mode data selection signal, the test mode data is sent as the test read mode data.

19. The test system according to any one of claims 15 to 18, wherein, The test read data generation unit includes n test read data generators. Each of the n test read data generators includes a comparison unit configured to generate test read data by comparing test read pattern data with read data.

20. The testing system according to claim 19, wherein, The semiconductor memory device also includes a test write data generation unit, which is configured to: Copy each of the n test write data at a third data rate, or copy and reverse each of the n test write data at a third data rate, wherein the third data rate is lower than the first data rate or equal to or higher than the second data rate, wherein each test write data has a fourth predetermined number of bits, and n write data are generated at a first data rate, wherein each write data has a first predetermined number of bits. The test command / address is applied in response to the rising and falling edges of the test clock signal. Each of the n test write data is applied in response to the rising edge of a test write clock signal with a higher frequency than the test clock signal, and Each of the n test read data is generated in response to the rising edge of a clock signal having a frequency equal to or lower than that of the test write clock signal.

Images