Chip screening method, system, computer device and storage medium

Abstract

The present invention discloses a chip screening method, system, computer equipment and storage medium. The chip screening method includes: obtaining a scanning defect map of a wafer, the scanning defect map is obtained by scanning at least one chip on the wafer in a preset scanning mode, and the scanning defect map includes a test structure and a pseudo-bad chip connected to the test structure; obtaining a standard image map with a single graphic repeating unit; using a preset graphic repeating unit menu program according to the scanning defect map to generate at least one mask image map, the mask image map has a one-to-one correspondence with the graphic repeating unit, and the graphic repeating unit has at least one chip; judging whether the pseudo-bad chip is a qualified chip based on the comparison result between the standard image map and each mask image map, effectively filtering the cutting path test structure, avoiding the false bad chips without defects from being mistakenly caught, and greatly improving the product shipment yield.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a chip screening method, system, computer equipment and storage medium. Background Art

[0002] In existing semiconductor manufacturing technology, after the preparation of a semiconductor wafer is completed, the chips need to be cut into multiple chips. The cutting process is performed in a cutting street area.

[0003] When sawing a wafer into multiple chips, the area to be scanned must be selected to detect chipping defects along the saw path. Under the machine's scanning lens, chipping along the saw path appears as a black defect. When a black chipping touches the die seal ring, it will be detected as a black defect. Furthermore, if a black test key for wafer acceptance testing is provided on the saw path and is connected to chips on opposite sides of the test key, the test key will also be mistakenly detected as a chipping defect, resulting in the capture of qualified chips.

[0004] The traditional approach is to set a fixed size to filter out test structures to reduce the probability of being mistakenly caught as chipping. However, there are cases where chipping of the same fixed size will be filtered out, resulting in chips with chipping not being caught, reducing the product shipment yield. Summary of the Invention

[0005] Based on this, it is necessary to provide a chip screening method, system, computer equipment and storage medium to address the problems in the above-mentioned background technology, which can accurately screen out chips connected to the test structure, and at the same time accurately identify other defective chips other than those connected to the test structure, thereby improving product shipment yield.

[0006] To solve the above technical problems, the first aspect of the present application proposes a chip screening method, comprising:

[0007] Obtaining a scan defect map of a wafer, wherein the scan defect map is obtained by scanning at least one chip on the wafer in a preset scanning mode, and the scan defect map includes a test structure and pseudo defective chips connected to the test structure;

[0008] Obtain a standard image diagram with a single schematic repeating unit;

[0009] Generate at least one mask image image using a preset diagram repeating unit menu program according to the scanned defect image, wherein the mask image image corresponds to the diagram repeating unit in a one-to-one manner, and the diagram repeating unit has at least one chip;

[0010] According to the comparison result between the standard image and each of the mask images, it is determined whether the pseudo defective chip is a qualified chip.

[0011] In the chip screening method provided in the above embodiment, a scanning defect map of the wafer is obtained, and the scanning defect map is obtained by scanning at least one chip on the wafer in a preset scanning mode. The scanning defect map includes pseudo defective chips connected to the test structure, so that the pseudo defective chips connected to the test structure and the defective chips are captured together; a standard image map with a single graphic repeating unit is obtained; according to the scanning defect map, a preset graphic repeating unit menu program is used to generate at least one mask image map, the mask image map corresponds one-to-one to the graphic repeating unit, and there is at least one chip in the graphic repeating unit; according to the comparison result between the standard image map and each mask image map, it is judged whether the pseudo defective chip is a qualified chip, effectively filtering the cutting path test structure, avoiding defective pseudo defective chips from being mistakenly captured, and greatly improving the product shipment yield.

[0012] In one embodiment, judging whether the pseudo defective chip is a qualified chip based on the comparison result between the standard image and each of the mask images includes:

[0013] Determining whether the standard image is identical to each of the mask images;

[0014] If they are the same, the pseudo defective chip and the remaining chips except the pseudo defective chip in the illustrated repeating unit are all determined as the qualified chips;

[0015] Otherwise, it is determined that there is a defect in the illustrated repeating unit, and the chip with the defect is determined as a bad chip.

[0016] In one embodiment, it further includes:

[0017] A wafer coding map is obtained, where the wafer coding map includes a code of each qualified chip and a code of each defective chip.

[0018] In one embodiment, the areas of the test structures in adjacent repeating units are the same.

[0019] In one embodiment, the test structure is located on a wafer dicing street, and the dummy defective chips are located on opposite sides of the test structure.

[0020] In one embodiment, the width of the test structure is greater than the width of the wafer dicing street.

[0021] A second aspect of the present application provides a chip screening system, comprising:

[0022] A scanning defect map acquisition module is used to acquire a scanning defect map of a wafer, wherein the scanning defect map is acquired by scanning at least one chip on the wafer in a preset scanning mode, and the scanning defect map includes a test structure and pseudo defective chips connected to the test structure;

[0023] A standard image acquisition module, used for acquiring a standard image with a single graphical repeating unit;

[0024] a mask image generating module, configured to generate at least one mask image according to the scanned defect image using a preset diagram repeating unit menu program, wherein the mask image corresponds to the diagram repeating unit in a one-to-one manner, and the diagram repeating unit contains at least one chip;

[0025] A comparison module is configured to determine the pseudo defective chip as a qualified chip based on a comparison result between the standard image and each of the mask images.

[0026] In the chip screening system provided in the above embodiment, a scanning defect map acquisition module, a standard image map acquisition module, a mask image map generation module and a comparison module are set, wherein the scanning defect map acquisition module is used to acquire a scanning defect map of the wafer, and the scanning defect map is acquired by scanning at least one chip on the wafer in a preset scanning mode. The scanning defect map includes pseudo defective chips connected to the test structure, so as to capture the pseudo defective chips connected to the test structure and the chips with defects together; the standard image map acquisition module is used to acquire a standard image map with a single graphic repeating unit; the mask image map generation module is used to generate at least one mask image map according to the scanning defect map using a preset graphic repeating unit menu program, the mask image map corresponds one-to-one to the graphic repeating unit, and there is at least one chip in the graphic repeating unit; based on the comparison result between the standard image map and each mask image map, it is judged whether the pseudo defective chip is a qualified chip, effectively filtering the cutting road test structure, avoiding the false defective chips without defects from being mistakenly captured, and greatly improving the product shipment yield.

[0027] In one embodiment, the comparison module includes:

[0028] a judging unit, configured to judge whether the standard image is identical to each of the mask images;

[0029] a qualified chip determining unit, configured to determine the pseudo defective chips and the remaining chips except the pseudo defective chips in the image repetition unit as qualified chips when the standard image is identical to each of the mask image;

[0030] The defective chip determining unit is used to determine that there are defects in the image repetition unit when the standard image is different from each of the mask image images, and determine the chip with the defect as a defective chip.

[0031] A third aspect of the present application provides a computer device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the above method when executing the computer program.

[0032] A fourth aspect of the present application provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program implements the steps of the above method when executed by a processor.

[0033] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention and implement it according to the contents of the specification, the following is a detailed description of the preferred embodiments of the present invention with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, without paying any creative work, they can also obtain drawings of other embodiments based on these drawings.

[0035] Figure 1 This is a schematic diagram of a chip screening method provided in one embodiment of the present application;

[0036] Figure 2 A schematic diagram of a test structure provided in an embodiment of the present application;

[0037] Figure 3 A schematic diagram of a scan defect map provided in one embodiment of the present application;

[0038] Figure 4 A schematic diagram of a mask image provided in one embodiment of the present application;

[0039] Figure 5 This is a partial flow chart of a chip screening method provided in one embodiment of the present application;

[0040] Figure 6 A schematic diagram of a wafer after a pseudo-bad chip is determined to be a qualified chip provided in one embodiment of the present application;

[0041] Figure 7 This is a schematic structural diagram of a chip screening system provided in one embodiment of the present application;

[0042] Figure 8 This is a structural diagram of a computer device provided in one embodiment of the present application.

[0043] Description of reference numerals: 10, wafer; 11, chip; 20, test structure; 30, dicing street; 40, illustrated repeating unit;

[0044] 100. Chip screening system; 101. Scanning defect map acquisition module; 102. Standard influence map acquisition module; 103. Mask processing module; 104. Comparison module. DETAILED DESCRIPTION

[0045] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings illustrate preferred embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the disclosure of the present application.

[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0047] In the case of using “including,” “having,” and “comprising” described herein, another component may be added unless a clear limiting term such as “only,” “consisting of,” etc. is used. Unless mentioned otherwise, a term in the singular form may include a plural form and should not be understood as having one number.

[0048] It should be understood that although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of this application.

[0049] In this application, unless otherwise specified or limited, the terms "connected" and "connection" should be understood in a broad sense. For example, they can refer to direct connection or indirect connection through an intermediate medium, internal communication between two elements, or interaction between two elements. Those skilled in the art will understand the specific meanings of the above terms in this application based on specific circumstances.

[0050] In order to illustrate the above technical solutions of the present application, specific embodiments are provided below.

[0051] In a chip screening method provided in one embodiment of the present application, Figure 1 As shown, the chip screening method includes the following steps:

[0052] Step S10: Obtaining a scan defect map of the wafer, wherein the scan defect map is obtained by scanning at least one chip on the wafer in a preset scanning mode, and the scan defect map includes pseudo defective chips connected to the test structure;

[0053] Step S20: obtaining a standard image with a single graphical repeating unit;

[0054] Step S30: generating at least one mask image according to the scanned defect image using a preset diagram repeating unit menu program, wherein the mask image corresponds to the diagram repeating unit in a one-to-one manner, and the diagram repeating unit contains at least one chip;

[0055] Step S40 : determining whether the pseudo defective chip is a qualified chip based on the comparison result between the standard image and each mask image.

[0056] In the chip screening method provided in the above embodiment, a scanning defect map of the wafer is obtained, and the scanning defect map is obtained by scanning at least one chip on the wafer in a preset scanning mode. The scanning defect map includes pseudo defective chips connected to the test structure, so that the pseudo defective chips connected to the test structure and the defective chips are captured together; a standard image map with a single graphic repeating unit is obtained; according to the scanning defect map, a preset graphic repeating unit menu program is used to generate at least one mask image map, the mask image map corresponds one-to-one to the graphic repeating unit, and there is at least one chip in the graphic repeating unit; according to the comparison result between the standard image map and each mask image map, it is judged whether the pseudo defective chip is a qualified chip, effectively filtering the cutting path test structure, avoiding defective pseudo defective chips from being mistakenly captured, and greatly improving the product shipment yield.

[0057] In one embodiment, the number of test structures in the standard image is the same as the number of test structures in the mask image, and the positions of the test structures in the standard image are the same as the positions of the test structures in the mask image. During the comparison process, the test structures in the standard image correspond to the test structures in the mask image to prevent false positive chips from being mistakenly detected.

[0058] In one embodiment of the present application, Figure 2 As shown, the wafer 10 is divided into a plurality of chips 11 with the dicing street 30 as the boundary, and the test structure 20 is located on the dicing street 30. The width of the test structure 20 is greater than the width of the wafer dicing street 30. Part of the test structure 20 covers the chips 11 on opposite sides of the test structure and is electrically connected to the chips 11 on opposite sides. The chip electrically connected to the test structure 20 is a pseudo defective chip S (such as Figure 3 and Figure 4 shown).

[0059] In one embodiment of the present application, Figure 3 As shown, the scanned defect image of the wafer 11 in step S10 is composed of a scanned image of at least one chip 11; the standard image image with a single illustrated repeating unit obtained in step S20 has no defects and has pseudo defective chips connected to the test structure. The number of chips in a single illustrated repeating unit can be single or multiple.

[0060] As an example, Figure 3 A represents a qualified chip. In this application, a qualified chip A is a chip that is not connected to the test structure 20 and does not have a black defect. B represents a defective chip. A defective chip B has a black defect. Figure 3 For example, Figure 3 The black defects in FIG are circular defects, and this application does not limit the shape of the black defects.

[0061] As an example, the black defect may be a chipping defect in the cutting path.

[0062] As an example, the preset scanning method in step S10 is the scanning method of a traditional machine, which can scan the chips sequentially along the horizontal or vertical direction of the wafer, and this application will not go into details.

[0063] In one embodiment of the present application, in step S20, a standard image diagram having a single graphical repetitive unit is obtained. When the machine initially establishes a recipe, the standard image diagram of a single graphical repetitive unit of the corresponding product wafer provided directly by the customer can be pre-stored in the machine menu.

[0064] It should be noted that the size of the illustrated repeating unit is related to the size of the wafer 10 to ensure that the multiple illustrated repeating units evenly divide the multiple chips in the wafer 10.

[0065] In one embodiment of the present application, Figure 4 As shown, in step S30, a preset illustrated repeating unit menu program is used, and the illustrated repeating unit 40 equally divides the multiple chips 11 on the wafer 10, that is, the number of chips 11 in each illustrated repeating unit 40 is the same, and all have a test structure 20 and a pseudo defective chip S connected to the test structure 20, wherein the pseudo defective chip S is located on opposite sides of the test structure 20.

[0066] As an example, the mask image corresponds to the illustrated repeating unit one-to-one, and the number of chips in the mask image is the same as the number of chips in the illustrated repeating unit; multiple illustrated repeating units are defined by a preset illustrated repeating unit menu program, and multiple mask images are generated by scanning the wafer 10.

[0067] As an example, the number of chips in the standard image is the same as the number of chips in the mask image. Figure 4 For example, the chips in each repeating unit 40 are arranged in 2 rows and 3 columns with equal spacing, and the number is 6. This application does not limit this. Multiple repeating units 40 shown in the figure divide all the chips 11 on the wafer 11 into equal parts.

[0068] As an example, the preset graphical repetitive unit menu program may be a menu program pre-established by an engineer at the machine operation terminal according to customer requirements.

[0069] In one embodiment, please refer to Figure 4 Adjacent repeating units 40 evenly divide the test structure 20 located on the cutting path 30, and the areas of the test structures 20 in adjacent repeating units 40 are the same, so as to ensure that the structure in each repeating unit 40 is the same, ensure the accuracy of the comparison results between the standard image and multiple mask images, and improve the product shipment yield.

[0070] In one embodiment of the present application, Figure 5 As shown, step S40: judging whether the pseudo defective chip is a qualified chip based on the comparison result of the standard image and the plurality of mask images, includes the following steps:

[0071] Step S41: determining whether the standard image is identical to each mask image;

[0072] Step S42: If they are the same, the pseudo defective chip in the illustrated repeating unit and the remaining chips except the pseudo defective chip are determined as qualified chips;

[0073] Step S43: Otherwise, it is determined that there are defects in the repeating unit shown in the figure, and the chip with defects is determined as a bad chip, such as Figure 6 shown.

[0074] In the above embodiment, it is determined whether the standard image is identical to a plurality of mask image images corresponding one to one with the illustrated repeating units. If the two images are identical, the pseudo-bad chips in the illustrated repeating units are determined to be qualified chips, and at this time, there are no defects on the pseudo-bad chips. If the two images are different, it is determined that the chips other than the pseudo-bad chips have black defects, and such chips with black defects are bad chips. While automatically filtering the test structure, the chips with defects in the illustrated repeating units are accurately determined, thereby improving the wafer shipment yield.

[0075] In one embodiment, Figure 6 A represents a qualified chip, and B represents a defective bad chip; wherein the bad chip B may include a pseudo bad chip S with defects.

[0076] In one embodiment of the present application, the chip screening method further comprises the following steps:

[0077] Step S50: Obtain a wafer coding map, where the wafer coding map includes the codes of each qualified chip and the codes of each defective chip.

[0078] Specifically, because a single pair of wafers uses a preset graphical repetitive unit menu program, it is impossible to obtain a wafer coding map. In order to obtain a high-yield wafer with qualified chip A, this application combines a preset scanning method to obtain a scanning defect map and a preset graphical repetitive unit menu program. The qualified chip A and the defective chip determined by the above-mentioned chip screening method are encoded to obtain a wafer coding map (not shown in the figure), which satisfies the requirement of providing a wafer coding map to customers when the wafers are shipped. At the same time, it can effectively filter the test structure, avoid misgrabbing, and improve the product shipment yield.

[0079] As an example, it can be binary encoding or decimal encoding. This application does not limit the counting method of the encoding.

[0080] In one embodiment of the present application, Figure 7 As shown, a chip screening system 100 is also provided, including a scanning defect image acquisition module 101 , a standard image image acquisition module 102 , a mask image generation module 103 and a comparison module 104 .

[0081] Specifically, the scanning defect map acquisition module 101 is used to obtain a scanning defect map of the wafer, and the scanning defect map is obtained by scanning at least one chip on the wafer in a preset scanning mode, and the scanning defect map includes a pseudo defective chip connected to the test structure; the standard image map acquisition module 102 is used to obtain a standard image map with a single graphic repetition unit; the mask image map generation module 103 is used to generate at least one mask image map according to the scanning defect map using a preset graphic repetition unit menu program, and the mask image map corresponds one-to-one to the graphic repetition unit; there is at least one chip in the graphic repetition unit; the comparison module 104 is used to determine whether the pseudo defective chip is a qualified chip based on the comparison result of the standard image map and each mask image map.

[0082] In the chip screening system provided in the above embodiment, a scanning defect map acquisition module, a standard image map acquisition module, a mask image map generation module and a comparison module are set, wherein the scanning defect map acquisition module is used to acquire a scanning defect map of the wafer, and the scanning defect map is acquired by scanning at least one chip on the wafer in a preset scanning mode, and the scanning defect map includes pseudo defective chips connected to the test structure, so as to capture the pseudo defective chips connected to the test structure and the chips with defects together; the standard image map acquisition module is used to acquire a standard image map with a single graphic repetition unit; the mask image map generation module is used to generate at least one mask image map according to the scanning defect map using a preset graphic repetition unit menu program, and the mask image map corresponds one-to-one to the graphic repetition unit; there is at least one chip in the graphic repetition unit; based on the comparison result between the standard image map and each mask image map, it is judged whether the pseudo defective chip is a qualified chip, effectively filtering the cutting road test structure, avoiding the false defective chips without defects from being mistakenly captured, and greatly improving the product shipment yield.

[0083] In one embodiment of the present application, the comparison module 104 includes a judgment unit, a qualified chip determination unit, and a defective chip determination unit.

[0084] Specifically, the judgment unit is used to judge whether the standard image image is the same as each mask image image; the qualified chip determination unit is used to determine that the pseudo defective chips in the illustrated repetitive unit and the remaining chips except the pseudo defective chips are qualified chips when the standard image image is the same as each mask image image; the defective chip determination unit is used to determine that there are defects in the illustrated repetitive unit when the standard image image is different from each mask image image, and determine the chips with defects as defective chips.

[0085] In one embodiment of the present application, a computer device is further provided, including a memory and a processor. The memory stores a computer program, and when the computer program is executed by the processor, the steps of the above method are implemented.

[0086] Those skilled in the art will understand that Figure 8 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than shown in the figure, or combine certain components, or have a different component arrangement.

[0087] In one embodiment of the present application, a storage medium is further provided, on which a computer program is stored. When the computer program is executed by a processor, the steps of the above method are implemented.

[0088] It should be understood that, unless otherwise expressly stated herein, there is no strict order restriction for the execution of the steps, and the steps may be executed in other orders. Furthermore, at least a portion of the steps may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but may be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but may be executed in rotation or alternation with other steps or at least a portion of the sub-steps or stages of other steps.

[0089] Those skilled in the art will appreciate that all or part of the processes in the above-mentioned embodiment methods can be implemented by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application may include at least one of non-volatile and volatile memory. Non-volatile memory may include read-only memory (ROM), magnetic tape, floppy disk, flash memory or optical memory, etc. Volatile memory may include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM).

[0090] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0091] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art could make various modifications and improvements without departing from the spirit of the present application, all of which fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A chip screening method, characterized in that: include: Obtaining a scanned defect map of a wafer, wherein the scanned defect map is obtained by scanning at least one chip on the wafer in a preset scanning mode, the scanned defect map including a test structure and pseudo defective chips connected to the test structure, wherein the test structure is located on a dicing street of the wafer; Obtaining a standard image having a single repeating unit, wherein the multiple repeating units evenly divide all chips on the wafer, the number of chips in each repeating unit is the same, the number of test structures in the standard image is the same as the number of test structures in the mask image, and the positions of the test structures in the standard image are the same as the positions of the test structures in the mask image; Generate at least one mask image image using a preset diagram repeating unit menu program according to the scanned defect image, wherein the mask image image corresponds to the diagram repeating unit in a one-to-one manner, and the diagram repeating unit has at least one chip; According to the comparison result between the standard image and each of the mask images, it is determined whether the pseudo defective chip is a qualified chip.

2. The chip screening method according to claim 1, characterized in that The step of determining whether the pseudo defective chip is a qualified chip based on the comparison result between the standard image and each of the mask images includes: Determining whether the standard image is identical to each of the mask images; If they are the same, the pseudo defective chip and the remaining chips except the pseudo defective chip in the illustrated repeating unit are all determined as the qualified chips; Otherwise, it is determined that there is a defect in the illustrated repeating unit, and the chip with the defect is determined as a bad chip.

3. The chip screening method according to claim 2, characterized in that Also includes: A wafer coding map is obtained, where the wafer coding map includes a code of each qualified chip and a code of each defective chip.

4. The chip screening method according to any one of claims 1 to 3, characterized in that: The areas of the test structures in adjacent repeating units shown in the figure are the same.

5. The chip screening method according to any one of claims 1 to 3, characterized in that: The test structure is located on a wafer dicing street, and the pseudo defective chips are located on two opposite sides of the test structure.

6. The chip screening method according to claim 5, characterized in that The width of the test structure is greater than the width of the wafer dicing street.

7. A chip screening system, characterized in that: include: a scanning defect map acquisition module, configured to acquire a scanning defect map of a wafer, wherein the scanning defect map is acquired by scanning at least one chip on the wafer in a preset scanning mode, the scanning defect map including a test structure and pseudo defective chips connected to the test structure, wherein the test structure is located on a dicing path of the wafer; a standard image acquisition module, configured to acquire a standard image having a single image repeating unit; the multiple image repeating units evenly divide all chips on the wafer, the number of chips in each image repeating unit being the same, the number of test structures in the standard image being the same as the number of test structures in the mask image, and the positions of the test structures in the standard image being the same as the positions of the test structures in the mask image; a mask image generating module, configured to generate at least one mask image according to the scanned defect image using a preset diagram repeating unit menu program, wherein the mask image corresponds to the diagram repeating unit in a one-to-one manner, and the diagram repeating unit contains at least one chip; A comparison module is configured to determine the pseudo defective chip as a qualified chip based on a comparison result between the standard image and each of the mask images.

8. The chip screening system according to claim 7, characterized in that: The comparison module includes: a judging unit, configured to judge whether the standard image is identical to each of the mask images; a qualified chip determining unit, configured to determine the pseudo defective chips and the remaining chips except the pseudo defective chips in the image repetition unit as qualified chips when the standard image is identical to each of the mask image; The defective chip determining unit is used to determine that there are defects in the image repetition unit when the standard image is different from each of the mask image images, and determine the chip with the defect as a defective chip.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 6 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

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