Source / drain regions and their formation methods

Abstract

This disclosure relates to source / drain regions and methods for forming them. One method includes: etching a first recess adjacent to a first dummy gate stack and a first fin; etching a second recess adjacent to a second dummy gate stack and a second fin; and epitaxially growing a first epitaxial region in the first recess. The method further includes: depositing a first metallized mask over the first dummy gate stack, over the second dummy gate stack, over the first epitaxial region in the first recess, and in the second recess; patterning the first metallized mask to expose the first dummy gate stack and the first epitaxial region; epitaxially growing a second epitaxial region in the first recess, over the first epitaxial region; and removing the remainder of the first metallized mask after epitaxially growing the second epitaxial region.

Description

Technical Field

[0001] This disclosure generally relates to source / drain regions and methods for forming them. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material on a semiconductor substrate, and then using photolithography to pattern the various material layers to form circuit components and elements thereon.

[0003] The semiconductor industry continuously improves the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by constantly reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, other problems arise that need to be addressed. Summary of the Invention

[0004] According to one embodiment of this disclosure, a method of forming a semiconductor device is provided, comprising: etching a first recess adjacent to a first dummy gate stack and a first fin; etching a second recess adjacent to a second dummy gate stack and a second fin; epitaxially growing a first epitaxial region in the first recess; depositing a first metal-containing mask over the first dummy gate stack, over the second dummy gate stack, over the first epitaxial region in the first recess, and in the second recess; patterning the first metal-containing mask to expose the first dummy gate stack and the first epitaxial region; epitaxially growing a second epitaxial region in the first recess over the first epitaxial region; and removing the remaining portion of the first metal-containing mask after epitaxially growing the second epitaxial region.

[0005] According to another embodiment of this disclosure, a method for forming a semiconductor device is provided, comprising: etching a first recess in a first fin, wherein the first fin includes a first plurality of semiconductor layers; etching a second recess in a second fin, wherein the second fin includes a second plurality of semiconductor layers; depositing a first aluminum oxide layer on the bottom surface and sidewalls of the first recess and the second recess; removing the first aluminum oxide layer from the first recess; epitaxially growing a first epitaxial region in the first recess while the first aluminum oxide layer covers the second recess; and removing the first aluminum oxide layer from the second recess.

[0006] According to another embodiment of this disclosure, a semiconductor device is provided, comprising: a first fin; a shallow trench isolation region adjacent to the first fin; a first epitaxial source / drain region extending into the first fin, wherein the first epitaxial source / drain region includes: a first epitaxial region; and a second epitaxial region located above the first epitaxial region, wherein the second epitaxial region includes a material different from the first epitaxial region; a first metal residue located between the first epitaxial source / drain region and the shallow trench isolation region; and a gate located above the first fin. Attached Figure Description

[0007] Various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily enlarged or reduced.

[0008] Figure 1 An example of a nanostructured field-effect transistor (nano-FET) according to some embodiments is shown in a three-dimensional view.

[0009] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figure 8A Figure 8B Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 11A , Figure 11B , Figure 11C , Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16 , Figure 17A , Figure 17B , Figure 17C , Figure 18 , Figure 19 Figure 20 Figure 21 , Figure 22 , Figure 23A , Figure 23B , Figure 23C , Figure 24 , Figure 25A , Figure 25B , Figure 25C , Figure 26A , Figure 26B , Figure 27A , Figure 27B , Figure 28A , Figure 28B , Figure 29A , Figure 29B , Figure 30A , Figure 30B , Figure 30C , Figure 31A , Figure 31B , Figure 31C , Figure 32A , Figure 32B and Figure 32C This is a cross-sectional view of an intermediate stage in the fabrication of a nanostructured FET according to some embodiments. Detailed Implementation

[0010] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples throughout this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0011] In addition, spatially related terms (e.g., "below," "below," "lower than," "above," "upper") may be used herein to facilitate the description of the relationship of one element or feature shown in the figure relative to another element(s) or feature(s). These spatially related terms are intended to cover different orientations of the device in use or operation other than those shown in the figure. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein shall be interpreted accordingly.

[0012] Various embodiments provide a metal-containing mask during source / drain epitaxial processes for forming source / drain regions in n-type and p-type device regions of a semiconductor die. The metal-containing mask protects the structure in the n-type or p-type device region of the die when growing source / drain regions for another type of device. In some embodiments, the metal-containing mask includes alumina, hafnium oxide, aluminum nitride, etc. It has been observed that metal oxides may be less likely to absorb precursors flowing during source / drain epitaxy. For example, the initial nucleation reaction between the metal-containing mask and the precursor can provide relatively high-energy bonding between the metal-containing mask and the precursor. As a result, the precursor may remain on the surface of the metal-containing mask rather than be absorbed into the metal oxide mask, making precursor residues easier to remove during wet cleaning processes for removing the metal-containing mask and reducing defects in the resulting device. The source / drain processing window can also be advantageously improved. Furthermore, the use of a metal-containing mask allows for more bottom-up source / drain growth because the metal-containing mask can leave residue along the sidewalls of the STI region, which helps suppress growth along the surface. <100> Epitaxial growth of crystal planes.

[0013] The embodiments are described below in the specific context of a die including a nanostructured FET. However, various embodiments may be applied to dies that replace or incorporate other types of transistors (e.g., FinFETs, planar transistors, etc.) in conjunction with nanostructured FETs.

[0014] Figure 1 An example of a nanostructured FET (e.g., nanowire FET, nanosheet FET, etc.) according to some embodiments is shown in a three-dimensional view. The nanostructured FET includes a nanostructure 55 (e.g., nanosheet, nanowire, etc.) on fins 66 on a substrate 50 (e.g., a semiconductor substrate), wherein the nanostructure 55 serves as a channel region for the nanostructured FET. The nanostructure 55 may include p-type nanostructures, n-type nanostructures, or combinations thereof. Isolation regions 68 are disposed between adjacent fins 66, which may protrude above and from between adjacent isolation regions 68. Although the isolation regions 68 are shown / described as separate from the substrate 50, as used herein, the term "substrate" may refer to a single semiconductor substrate or a combination of a semiconductor substrate and an isolation region. Furthermore, although the bottom portion of the fin 66 is shown as a single continuous material with respect to the substrate 50, the bottom portion of the fin 66 and / or the substrate 50 may comprise a single material or multiple materials. In this context, fin 66 refers to the portion extending between adjacent isolation regions 68.

[0015] A gate dielectric layer 96 is located above the top surface of fin 66 and extends along the top, sidewalls, and bottom surface of nanostructure 55. A gate electrode 98 is located above the gate dielectric layer 96. Epitaxial source / drain regions 90 are disposed on fin 66 on opposite sides of the gate dielectric layer 96 and the gate electrode 98.

[0016] Figure 1 The reference cross sections used in the following figures are further illustrated. Cross section A-A' is along the longitudinal axis of the gate electrode 98 and in a direction perpendicular to, for example, the direction of current flow between the epitaxial source / drain regions 90 of the nanostructure FET. Cross section B-B' is perpendicular to cross section A-A' and parallel to the longitudinal axis of the fin 66 of the nanostructure FET, and in, for example, the direction of current flow between the epitaxial source / drain regions 90 of the nanostructure FET. Cross section C-C' is parallel to cross section A-A' and extends through the epitaxial source / drain regions of the nanostructure FET. For clarity, the following figures refer to these reference cross sections.

[0017] Some embodiments discussed herein are discussed in the context of nanostructured FETs formed using a post-gate process. In other embodiments, a pre-gate process may be used. Furthermore, some embodiments are contemplated for use in planar devices (e.g., planar FETs) or in FinFETs.

[0018] Figures 2 to 32C This is a cross-sectional view of an intermediate stage in the fabrication of a nanostructured FET according to some embodiments. Figures 2 to 5 , Figure 6A , Figure 25A , Figure 26A , Figure 27A , Figure 28A , Figure 29A , Figure 30A , Figure 31A and Figure 32A It shows Figure 1 The reference section A-A' is shown. Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11B , Figure 11C , Figure 12 , Figure 13 , Figure 14 Figure 15 Figure 16 , Figure 17A , Figure 18 , Figure 19 , Figure 20 , Figure 21 , Figure 22 , Figure 23A , Figure 24 , Figure 25B , Figure 26B , Figure 27B , Figure 28B , Figure 29B , Figure 30B , Figure 31B and Figure 32B It shows Figure 1 The reference section B-B' is shown. Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 17B , Figure 17C , Figure 23B , Figure 23C , Figure 25C , Figure 30C , Figure 31C and Figure 32C It shows Figure 1 The reference section C-C' is shown.

[0019] exist Figure 2 In this embodiment, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which may be doped (e.g., with p-type or n-type dopants) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on a substrate, which is typically a silicon substrate or a glass substrate. Other substrates may also be used, such as multilayer substrates or gradient substrates. In some embodiments, the semiconductor material of the substrate 50 may include: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium arsenide phosphide; or combinations thereof.

[0020] Substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form an n-type device, such as an NMOS transistor, like an n-type nanostructure FET, and the p-type region 50P can be used to form a p-type device, such as a PMOS transistor, like a p-type nanostructure FET. The n-type region 50N can be physically separated from the p-type region 50P (as shown by separator 20), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be provided between the n-type region 50N and the p-type region 50P. Although one n-type region 50N and one p-type region 50P are shown, any number of n-type regions 50N and p-type regions 50P can be provided.

[0021] Further in Figure 2In this process, a multilayer stack 64 is formed on a substrate 50. The multilayer stack 64 includes alternating layers of first semiconductor layers 51A-C (collectively referred to as first semiconductor layers 51) and second semiconductor layers 53A-C (collectively referred to as second semiconductor layers 53). For illustrative purposes and as discussed in more detail below, the second semiconductor layer 53 is removed and the first semiconductor layer 51 is patterned to form a channel region of a nanostructured FET in a p-type region 50P. Alternatively, the first semiconductor layer 51 is removed and the second semiconductor layer 53 is patterned to form a channel region of a nanostructured FET in an n-type region 50N. However, in some embodiments, the first semiconductor layer 51 may be removed and the second semiconductor layer 53 may be patterned to form a channel region of a nanostructured FET in an n-type region 50N, and the second semiconductor layer 53 may be removed and the first semiconductor layer 51 may be patterned to form a channel region of a nanostructured FET in a p-type region 50P. In other embodiments, the first semiconductor layer 51 may be removed and the second semiconductor layer 53 may be patterned to form the channel region of the nanostructured FET in both the n-type region 50N and the p-type region 50P.

[0022] For illustrative purposes, the multilayer stack 64 is shown as comprising three layers each of a first semiconductor layer 51 and a second semiconductor layer 53. In some embodiments, the multilayer stack 64 may include any number of first semiconductor layers 51 and second semiconductor layers 53. Each layer of the multilayer stack 64 may be epitaxially grown using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), etc. In various embodiments, the first semiconductor layer 51 may be formed of a first semiconductor material suitable for p-type nanostructure FETs, such as silicon germanium, etc., and the second semiconductor layer 53 may be formed of a second semiconductor material suitable for n-type nanostructure FETs, such as silicon, silicon carbon, etc. For illustrative purposes, the multilayer stack 64 is shown as having a bottom semiconductor layer suitable for p-type nanostructure FETs. In some embodiments, the multilayer stack 64 may be formed such that the bottom layer is a semiconductor layer suitable for n-type nanostructure FETs.

[0023] The first semiconductor material and the second semiconductor material can be materials with high etch selectivity relative to each other. This allows the first semiconductor layer 51 of the first semiconductor material to be removed without significantly removing the second semiconductor layer 53 of the second semiconductor material in the n-type region 50N, thereby allowing the second semiconductor layer 53 to be patterned to form the channel region of the n-type NSFETS. Similarly, the second semiconductor layer 53 of the second semiconductor material can be removed without significantly removing the first semiconductor layer 51 of the first semiconductor material in the p-type region 50P, thereby allowing the first semiconductor layer 51 to be patterned to form the channel region of the p-type NSFETS.

[0024] Now for reference Figure 3 According to some embodiments, fins 66 are formed in substrate 50, and nanostructures 55 are formed in multilayer stack 64. In some embodiments, nanostructures 55 and fins 66 can be formed in multilayer stack 64 and substrate 50, respectively, by etching trenches in multilayer stack 64 and substrate 50. Etching can be any acceptable etching, such as reactive ion etching (RIE), neutral beam etching (NBE), or combinations thereof. Etching can be anisotropic. Forming nanostructures 55 by etching multilayer stack 64 can further define first nanostructures 52A-C (collectively referred to as first nanostructures 52) from first semiconductor layer 51 and second nanostructures 54A-C (collectively referred to as second nanostructures 54) from second semiconductor layer 53. First nanostructures 52 and second nanostructures 54 can be further collectively referred to as nanostructure 55.

[0025] The fin 66 and nanostructure 55 can be patterned using any suitable method. For example, one or more photolithography processes can be used to pattern the fin 66 and nanostructure 55, including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing the creation of patterns with, for example, smaller pitches than that achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fin 66.

[0026] For illustrative purposes, Figure 3The fins 66 in the n-type region 50N and the p-type region 50P are shown to have substantially equal widths. In some embodiments, the width of the fin 66 in the n-type region 50N may be larger or thinner than the width of the fin 66 in the p-type region 50P. Furthermore, while each of the fins 66 and nanostructures 55 is shown to always have a consistent width, in other embodiments, the fins 66 and / or nanostructures 55 may have tapered sidewalls such that the width of each of the fins 66 and / or nanostructures 55 increases continuously in the direction toward the substrate 50. In such embodiments, each nanostructure 55 may have a different width and be trapezoidal.

[0027] exist Figure 4 In the nanostructure 55, a shallow trench isolation (STI) region 68 is formed adjacent to the fin 66. The STI region 68 can be formed by depositing an insulating material on the substrate 50, the fin 66, and the nanostructure 55 and between adjacent fins 66. The insulating material can be an oxide (e.g., silicon oxide), a nitride, or a combination thereof, and can be formed by high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), or a combination thereof. Other insulating materials formed by any acceptable process can be used. In the illustrated embodiment, the insulating material is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process can be performed. In the embodiment, the insulating material is formed such that an excess of insulating material covers the nanostructure 55. Although the insulating material is shown as a single layer, some embodiments may employ multiple layers. For example, in some embodiments, a liner (not shown separately) can be formed first along the surfaces of the substrate 50, the fin 66, and the nanostructure 55. Subsequently, a filler material such as described above can be formed on the liner.

[0028] Then, a removal process is applied to the insulating material to remove excess insulating material above the nanostructure 55. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), etch-back process, or a combination thereof may be employed. This planarization process exposes the nanostructure 55 such that, after the planarization process is completed, the top surface of the nanostructure 55 and the insulating material are flush.

[0029] The insulating material is then recessed to form STI regions 68. The insulating material is recessed such that the upper portions of fins 66 in regions 50N and 50P protrude between adjacent STI regions 68. Furthermore, the top surface of the STI regions 68 can have a flat surface (as shown), a convex surface, a concave surface (e.g., dish-shaped), or a combination thereof. The top surface of the STI regions 68 can be formed as flat, convex, and / or concave by appropriate etching. The STI regions 68 can be recessed using an acceptable etching process, such as an etching process selective for the material of the insulating material (e.g., etching the material of the insulating material at a faster rate than the material of fins 66 and nanostructures 55). For example, it can be removed using an oxide employing, for example, diluted hydrofluoric acid (dHF).

[0030] The above about Figures 2 to 4 The described process is merely one example of how the fins 66 and nanostructures 55 can be formed. In some embodiments, the fins 66 and / or nanostructures 55 can be formed using masking and epitaxial growth processes. For example, a dielectric layer can be formed over the top surface of the substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. Epitaxial structures can be epitaxially grown in the trenches, and the dielectric layer can be recessed such that the epitaxial structure protrudes from the dielectric layer to form the fins 66 and / or nanostructures 55. The epitaxial structure may include alternating semiconductor materials as described above, such as a first semiconductor material and a second semiconductor material. In some embodiments in which the epitaxial structure is epitaxially grown, the epitaxially grown material may be in-situ doped during growth, which may avoid prior and / or subsequent implantation, but in-situ doping and implantation doping may be used together.

[0031] Furthermore, for illustrative purposes only, the first semiconductor layer 51 (and the resulting nanostructure 52) and the second semiconductor layer 53 (and the resulting nanostructure 54) are shown and discussed herein as comprising the same material in the p-type region 50P and the n-type region 50N. Thus, in some embodiments, one or both of the first semiconductor layer 51 and the second semiconductor layer 53 may be different materials in the p-type region 50P and the n-type region 50N, or may be formed in a different order.

[0032] Further in Figure 4In this process, suitable wells (not shown separately) can be formed in fins 66, nanostructures 55, and / or STI regions 68. In embodiments with different well types, different implantation steps for n-type regions 50N and p-type regions 50P can be implemented using photoresist or other masks (not shown separately). For example, photoresist can be formed over fins 66 and STI regions 68 in n-type regions 50N and p-type regions 50P. The photoresist is patterned to expose p-type regions 50P. The photoresist can be formed using spin coating techniques and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, n-type impurity implantation is performed in p-type regions 50P, and the photoresist can be used as a mask to substantially prevent n-type impurities from being implanted into n-type regions 50N. The n-type impurities can be phosphorus, arsenic, antimony, etc., implanted into the region at a concentration of about 10. 13 atoms / cm 3 To about 10 14 atoms / cm 3 Within the specified range. After injection, the photoresist is removed, for example, through an acceptable ashing process.

[0033] After or before implantation of the p-type region 50P, a photoresist or other mask (not shown separately) is formed over the fins 66, nanostructures 55, and STI regions 68 in both the p-type region 50P and the n-type region 50N. The photoresist is patterned to expose the n-type region 50N. The photoresist can be formed using spin coating and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, p-type impurity implantation can be performed in the n-type region 50N, and the photoresist can be used as a mask to substantially prevent p-type impurities from being implanted into the p-type region 50P. The p-type impurities can be boron, boron fluoride, indium, etc., implanted into the region at a concentration of approximately 10. 13 atoms / cm 3 To about 10 14 atoms / cm 3 Within the specified range. After injection, the photoresist can be removed, for example, by an acceptable ashing process.

[0034] Following implantation into the n-type region 50N and the p-type region 50P, annealing can be performed to repair implantation damage and activate the implanted p-type and / or n-type impurities. In some embodiments, the growth material of the epitaxial fins can be in-situ doped during growth, which can avoid implantation, but in-situ doping and implantation doping can be used together.

[0035] exist Figure 5In this process, a dummy dielectric layer 70 is formed on the fin 66 and / or nanostructure 55. The dummy dielectric layer 70 can be, for example, silicon oxide, silicon nitride, a combination thereof, etc., and can be deposited or thermally grown according to acceptable techniques. A dummy gate layer 72 is formed on the dummy dielectric layer 70, and a mask layer 74 is formed on the dummy gate layer 72. The dummy gate layer 72 can be deposited on the dummy dielectric layer 70 and then planarized, for example, by CMP. The mask layer 74 can be deposited on the dummy gate layer 72. The dummy gate layer 72 can be a conductive or non-conductive material, and can be selected from the group consisting of amorphous silicon, polysilicon, poly-SiGe, metal nitrides, metal silicides, metal oxides, and metals. The dummy gate layer 72 can be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques for depositing the selected material. The dummy gate layer 72 can be made of other materials that have high etch selectivity relative to the etching of the isolation region. The mask layer 74 can include, for example, silicon nitride, silicon oxynitride, etc. In this example, a single dummy gate layer 72 and a single mask layer 74 are formed across the n-type region 50N and the p-type region 50P. Note that, for illustrative purposes only, the dummy dielectric layer 70 is shown to cover only the fin 66 and the nanostructure 55. In some embodiments, the dummy dielectric layer 70 may be deposited such that the dummy dielectric layer 70 covers the STI region 68, such that the dummy dielectric layer 70 extends between the dummy gate layer 72 and the STI region 68.

[0036] Figures 6A to 11C Various additional steps in manufacturing the embodiment device are shown. Figure 7A Figure 8A Figure 9A , Figure 10A and Figure 11A Features of either region 50N or region 50P are shown. Figure 6A and Figure 6B In this process, acceptable photolithography and etching techniques can be used to pattern the mask layer 74 (see [link]). Figure 5 A mask 78 is formed. The pattern of the mask 78 can then be transferred to the dummy gate layer 72 and the dummy dielectric layer 70 to form dummy gate 76 and dummy gate dielectric 71, respectively. The dummy gate 76 covers the corresponding channel region of the fin 66. The pattern of the mask 78 can be used to separate each dummy gate 76 from the adjacent dummy gate 76 entities. The dummy gate 76 may also have a length direction substantially perpendicular to the length direction of the corresponding fin 66.

[0037] exist Figure 7A and Figure 7B In, respectively in Figure 6A and Figure 6BA first spacer layer 80 and a second spacer layer 82 are formed on top of the structure shown. The first spacer layer 80 and the second spacer layer 82 will then be patterned to act as spacers for forming self-aligned source / drain regions. Figure 7A and Figure 7B In this configuration, a first spacer layer 80 is formed on the top surface of the STI region 68; on the top surface and sidewalls of the fin 66, nanostructure 55, and mask 78; and on the sidewalls of the dummy gate 76 and dummy gate dielectric 71. A second spacer layer 82 is deposited on the first spacer layer 80. The first spacer layer 80 can be formed from silicon oxide, silicon nitride, silicon oxynitride, etc., using techniques such as thermal oxidation, or deposited by CVD, ALD, etc. The second spacer layer 82 can be formed from a material having a different etch rate than the material of the first spacer layer 80, such as silicon oxide, silicon nitride, silicon oxynitride, etc., and can be deposited by CVD, ALD, etc.

[0038] Implantation for lightly doped source / drain (LDD) regions (not shown separately) can be performed after the formation of the first spacer layer 80 and before the formation of the second spacer layer 82. In embodiments with different device types, similar to the above... Figure 4 The implantation discussed earlier can involve forming a mask, such as a photoresist, on the n-type region 50N while exposing the p-type region 50P. An impurity of an appropriate type (e.g., p-type) can then be implanted into the exposed fins 66 and nanostructures 55 in the p-type region 50P. The mask can then be removed. The n-type impurity can be any of the previously discussed n-type impurities, and the p-type impurity can be any of the previously discussed p-type impurities. The lightly doped source / drain regions can have approximately 1 × 10⁻⁶. 15 atoms / cm 3 To approximately 1×10 19 atoms / cm 3 The impurity concentration is within a certain range. Annealing can be used to repair injection damage and reactivate the injected impurities.

[0039] exist Figure 8A and Figure 8BIn this process, a first spacer layer 80 and a second spacer layer 82 are etched to form a first spacer 81 and a second spacer 83. As will be discussed in more detail below, the first spacer 81 and the second spacer 83 are used for self-alignment of the subsequently formed source / drain regions and to protect the sidewalls of the fin 66 and / or nanostructure 55 during subsequent processing. The first spacer layer 80 and the second spacer layer 82 can be etched using a suitable etching process, such as an isotropic etching process (e.g., wet etching process), anisotropic etching process (e.g., dry etching process), etc. In some embodiments, the material of the second spacer layer 82 has a different etch rate than the material of the first spacer layer 80, such that the first spacer layer 80 can be used as an etch stop layer when patterning the second spacer layer 82, and that the second spacer layer 82 can be used as a mask when patterning the first spacer layer 80. For example, the second spacer layer 82 can be etched using an anisotropic etching process, wherein the first spacer layer 80 serves as an etch stop layer, and the remaining portion of the second spacer layer 82 forms the second spacer 83, such as... Figure 8A As shown. Subsequently, the second spacer 83 serves as a mask during the etching of the exposed portion of the first spacer layer 80, thereby forming the first spacer 81, as... Figure 8A As shown.

[0040] like Figure 8A As shown, the first spacer 81 and the second spacer 83 are disposed on the sidewalls of the fin 66 and / or the nanostructure 55. Figure 8B As shown, in some embodiments, the second spacer layer 82 can be removed from the first spacer layer 80 adjacent to the mask 78, dummy gate 76, and dummy gate dielectric 71, and the first spacer 81 is disposed on the sidewalls of the mask 78, dummy gate 76, and dummy gate dielectric 71. In other embodiments, a portion of the second spacer layer 82 may remain on the first spacer layer 80 adjacent to the mask 78, dummy gate 76, and dummy gate dielectric 71.

[0041] Note that the above disclosure generally describes the process for forming spacers and LDD regions. Other processes and sequences can be used. For example, fewer or additional spacers can be used, different step sequences can be used (e.g., the first spacer 81 can be patterned before depositing the second spacer layer 82), additional spacers can be formed and removed, etc. Furthermore, different structures and steps can be used to form n-type devices and p-type devices.

[0042] exist Figure 9A and Figure 9BIn some embodiments, a first recess 86 is formed in the fin 66, nanostructure 55, and substrate 50. An epitaxial source / drain region is then formed in the first recess 86. The first recess 86 may extend through the first nanostructure 52 and the second nanostructure 54, and into the substrate 50. Figure 9A As shown, the top surface of the STI region 68 may be higher than or flush with the bottom surface of the first recess 86. In various embodiments, the fin 66 may be etched such that the bottom surface of the first recess 86 is disposed below the top surface of the STI region 68; and so on. The first recess 86 may be formed by etching the fin 66, nanostructure 55, and substrate 50 using anisotropic etching processes such as RIE, NBE, etc. The first spacer 81, the second spacer 83, and the mask 78 mask portions of the fin 66, nanostructure 55, and substrate 50 during the etching process for forming the first recess 86. Each layer of the nanostructure 55 and / or the fin 66 may be etched using a single etching process or multiple etching processes. A timed etching process may be used to stop etching the first recess 86 after it has reached a desired depth.

[0043] exist Figure 10A and Figure 10B In the process, the sidewalls of the layers of the multilayer stack 64 formed of a first semiconductor material (e.g., a first nanostructure 52) exposed by the first recess 86 are etched to form a sidewall recess 88 in an n-type region 50N, and the sidewalls of the layers of the multilayer stack 64 formed of a second semiconductor material (e.g., a second nanostructure 54) exposed by the first recess 86 are etched to form a sidewall recess 88 in a p-type region 50P. Although in Figure 10BThe sidewalls of the first nanostructure 52 and the second nanostructure 54 in the recess 88 are shown as straight, but these sidewalls can be concave or convex. Isotropic etching processes, such as wet etching, can be used to etch the sidewalls. A mask (not shown) can be used to protect the p-type region 50P while an etchant selective for the first semiconductor material is used to etch the first nanostructure 52, such that in the n-type region 50N, the second nanostructure 54 and the substrate 50 remain relatively unetched compared to the first nanostructure 52. Similarly, a mask (not shown) can be used to protect the n-type region 50N while an etchant selective for the second semiconductor material is used to etch the second nanostructure 54, such that in the p-type region 50P, the first nanostructure 52 and the substrate 50 remain relatively unetched compared to the second nanostructure 54. In embodiments in which the first nanostructure 52 comprises, for example, SiGe and the second nanostructure 54 comprises, for example, Si or SiC, the sidewalls of the first nanostructure 52 in the n-type region 50N can be etched using a dry etching process utilizing tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc., and the sidewalls of the second nanostructure 54 in the p-type region 50P can be etched using a dry etching process utilizing hydrogen fluoride, another fluorine-based etchant, etc.

[0044] exist Figures 11A-11C In the middle, a first internal spacer 90 is formed in the sidewall recess 88. This can be achieved by... Figure 10A and Figure 10B An internal spacer layer (not shown separately) is deposited on the structure shown to form a first internal spacer 90. The first internal spacer 90 serves as an isolation feature between the subsequently formed source / drain regions and the gate structure. As will be discussed in more detail below, the source / drain regions will be formed in the recess 86, and the first nanostructure 52 in the n-type region 50N and the second nanostructure 54 in the p-type region 50P will be replaced with corresponding gate structures.

[0045] The internal spacer layer can be deposited using conformal deposition processes such as CVD or ALD. The internal spacer layer may comprise materials such as silicon nitride or silicon oxynitride, but any suitable material can be used, for example, a low-k material with a k-value less than about 3.5. The internal spacer layer can then be anisotropically etched to form a first internal spacer 90. Although the outer walls of the first internal spacer 90 are shown flush with the sidewalls of the second nanostructure 54 in the n-type region 50N and the first nanostructure 52 in the p-type region 50P, the outer walls of the first internal spacer 90 may extend beyond the sidewalls of the second nanostructure 54 and / or the first nanostructure 52, respectively, or be recessed equivalent to the sidewalls of the second nanostructure 54 and / or the first nanostructure 52.

[0046] Furthermore, despite Figure 11B The outer wall of the first internal spacer 90 is shown as straight, but the outer wall of the first internal spacer 90 can be concave or convex. For example, Figure 11C An embodiment is shown in which, in the n-type region 50N, the sidewalls of the first nanostructure 52 are concave, the outer sidewalls of the first internal spacer 90 are concave, and the first internal spacer corresponds to the concave sidewalls of the second nanostructure 54. An embodiment is also shown in which, in the p-type region 50P, the sidewalls of the second nanostructure 54 are concave, the outer sidewalls of the first internal spacer 90 are concave, and the first internal spacer corresponds to the concave sidewalls of the first nanostructure 52. The internal spacer layer can be etched using anisotropic etching processes such as RIE, NBE, etc. The first internal spacer 90 can be used to prevent subsequent etching processes (e.g., etching processes for forming the gate structure) from damaging the subsequently formed source / drain regions (e.g., the epitaxial source / drain regions 92 and 93 discussed below).

[0047] exist Figure 12 In the p-type region 50P, a first epitaxial region 92A is formed in a first recess 86, and a first epitaxial region 93A is formed in a first recess 86 in an n-type region 50N. The first epitaxial regions 92A and 93A may comprise silicon-cobalt-nickel alloy (SiCoNi), undoped silicon, lightly doped silicon, etc. The first epitaxial regions 92A and 93A can be grown using any suitable epitaxial process to partially fill the first recess 86. For example, the top surfaces of the first epitaxial regions 92A and 93A may be below or flush with the bottom nanostructure of the multilayer stack 64 (e.g., the first nanostructure 52A). In other embodiments, the top surfaces of the first epitaxial regions 92A and 93A may be set at different levels relative to the multilayer stack 64.

[0048] The first epitaxial regions 92A and 93A may be implanted with dopants, similar to the previously discussed process for forming lightly doped source / drain regions, followed by annealing. The impurities implanted into the p-type region 50P and the n-type region 50N may be the same or different, and may be any of the previously discussed impurities. In some embodiments, the first epitaxial regions 92A and 93A may be doped in situ during growth. The first epitaxial regions 92A and 93A may be buffer layers, lightly doped to interact with subsequently formed epitaxial regions (e.g., epitaxial regions 92B and 93B, see [link to relevant documentation]) grown on the first epitaxial regions 92A and 93A. Figure 24 Compared to the substrate 50, the epitaxial regions 92A and 93A have a crystal structure more similar to that of the substrate 50. Thus, the first epitaxial regions 92A and 93A can serve as transition regions, reducing the size of the lower substrate 50 and the upper epitaxial regions (e.g., epitaxial regions 92B and 93B, see [link]). Figure 24Crystal mismatch between )

[0049] exist Figure 13 In this process, a mask layer 84 is deposited in the n-type region 50N and the p-type region 50P. The mask layer 84 may be a conformal layer deposited along the sidewalls and bottom surface of the recess 86, for example, along the sidewalls of the first nanostructure 52, the second nanostructure 54, and the internal spacer 90, and along the upper surfaces of the first epitaxial regions 92A and 93A. The mask layer 84 may be further deposited to cover the top surface and sidewalls of the mask 78, the dummy gate 76, and the dummy gate dielectric 71. The mask layer 84 may be a metal-containing mask layer and may include aluminum oxide, aluminum nitride, hafnium oxide, etc. The mask layer 84 may be deposited using a suitable process such as PVD, CVD, ALD, etc. For example, the deposition of the mask layer 84 may be an ALD process performed as follows: a temperature in the range of about -150°C to about 320°C; a pressure in the range of about 1 Torr to about 10 Torr; and a pulse time in the range of 50 ms to 200 ms. Furthermore, in embodiments where the mask layer 84 comprises aluminum oxide, trimethylaluminum and water can be flowed during the ALD deposition process as precursors. In embodiments where the mask layer 84 comprises aluminum nitride, trimethylaluminum and a nitrogen source (e.g., NH3, N2H4, etc.) can be flowed during the ALD deposition process as precursors. In embodiments where the mask layer 84 comprises hafnium oxide, trimethylhafnium and water can be flowed during the ALD deposition process as precursors. The mask layer 84 may have a width W1 in the range of about 1 nm to about 5 nm.

[0050] exist Figure 14 In this process, photoresist 85 is deposited and patterned. For example, photoresist 85 can be formed using a spin coating technique and can be patterned using an acceptable photolithography technique. Photoresist 85 can be patterned to expose p-type regions 50P while covering n-type regions 50N. Although photoresist 85 is illustrated as a single unit, it should be understood that photoresist 85 can have a multilayer structure. In some embodiments, photoresist 85 can be or can include a back-side antireflective coating (BARC) material.

[0051] exist Figure 15In this process, an etching process is applied to remove the mask layer 84 in the p-type region 50P. The etching process can be a wet etching process using a suitable etchant such as diluted hydrogen fluoride (dHF). As a result of this etching process, the sidewalls of the multilayer stack 64 and the top surface of the first epitaxial region 92A are exposed in the p-type region 50P. However, the remainder of the mask layer 84 may cover the multilayer stack 64, the first epitaxial region 93A, and the dummy gate 76 in the n-type region 50N. As a result of this etching process, metal residue 99 from the mask layer 84 may remain in the p-type region 50P (see [link to relevant documentation]). Figure 17B and Figure 17C Metal residue 99 may be located, for example, on the first epitaxial region 92A and along the sidewalls of the STI region 68. After patterning the mask layer 84, the photoresist 85 may be removed using, for example, cleaning and / or ashing processes. Figure 16 The resulting structure is shown.

[0052] exist Figures 17A-17C In this embodiment, the remaining portion of the epitaxial source / drain region 92 is formed in the p-type region 50P. The epitaxial source / drain region 92 may include one or more semiconductor material layers. For example, the epitaxial source / drain region 92 may include a first epitaxial region 92A and a second epitaxial region 92B located above the first epitaxial region 92A. The first semiconductor material layer 92A and the second semiconductor material layer 92B may be formed of different semiconductor materials and may be doped with different dopant concentrations. In some embodiments, the first semiconductor material layer 92A may have a lower dopant concentration than the second semiconductor material layer 92B. Any number of semiconductor material layers may be used for the epitaxial source / drain region 92. For example, in some embodiments, the epitaxial source / drain region 92 may include additional epitaxial regions grown above the second epitaxial region 92B. In such embodiments, these additional epitaxial regions may include materials different from the first epitaxial region 92A and / or the second epitaxial region 92B and / or have different dopant concentrations.

[0053] In some embodiments, the second epitaxial region 92B can apply stress to the first nanostructure 52 in the p-type region 50P, thereby improving performance. For example... Figure 17A As shown, a second epitaxial region 92B is formed in the first recess 86 such that each dummy gate 76 is disposed between corresponding adjacent pairs of the second epitaxial regions 92B. In some embodiments, a first spacer 81 is used to separate the second epitaxial region 92B from the dummy gate 76 by an appropriate lateral distance, and a first internal spacer 90 is used to separate the second epitaxial region 92B from the second nanostructure 54 by an appropriate lateral distance, such that the epitaxial source / drain region 92 does not short-circuit with the subsequently formed gate of the resulting nanostructure FET.

[0054] The second epitaxial region 92B may include any acceptable material suitable for a p-type nanostructure FET. For example, if the first nanostructure 52 is silicon-germanium, the second epitaxial region 92B may include a material on which compressive strain is applied to the first nanostructure 52, such as silicon-germanium, boron-doped silicon-germanium, germanium, germanium-tin, etc. The epitaxial source / drain region 92 may also have a surface protruding from the corresponding surface of the multilayer stack 64 and may have a facet.

[0055] The epitaxial source / drain region 92, the first nanostructure 52, the second nanostructure 54, and / or the substrate 50 can be implanted with dopants to form the source / drain region, similar to the previously discussed process for forming lightly doped source / drain regions, followed by annealing. The impurity concentration of the source / drain region 92 can be approximately 1 × 10⁻⁶. 19 atoms / cm 3 1×10 21 atoms / cm 3 Between. The p-type impurity used for the source / drain region 92 can be any of the previously discussed impurities. In some embodiments, the epitaxial source / drain region 92 can be doped in situ during growth. In embodiments in which the epitaxial source / drain region 92 includes additional layers located above the second epitaxial region 92B, the doping concentration of these additional layers can be different from (e.g., less than) that of the second epitaxial region 92B.

[0056] like Figure 17B and Figure 17C As shown, as a result of the epitaxial process used to form the epitaxial source / drain regions 92, the upper surface of the epitaxial source / drain regions 92 has facets that extend laterally outward beyond the sidewalls of the nanostructure 55. In some embodiments, these facets cause adjacent epitaxial source / drain regions 92 of the same NSFET to merge, such as... Figure 17B As shown. In other embodiments, adjacent source / drain regions 92 remain separated after the epitaxial process is completed, as... Figure 17C As shown. In Figure 17B and Figure 17C In the illustrated embodiment, a first spacer 81 may be formed on the top surface of the STI region 68 to prevent epitaxial growth. In some other embodiments, the first spacer 81 may cover portions of the sidewalls of the nanostructure 55 to further prevent epitaxial growth. In some other embodiments, the spacer etching used to form the first spacer 81 may be adjusted to remove spacer material to allow the epitaxial growth region to extend to the surface of the STI region 68.

[0057] During the growth of the second epitaxial region 92B, a mask layer 84 covers the n-type region 50N. Advantages are achieved because the mask layer 84 comprises a metal. For example, during the epitaxial growth of the second epitaxial region 92B, a hydrogen-containing precursor (e.g., SiH4, Si2H6, SiH2C2, etc.) can flow into a deposition chamber located in the recess 86 and above the mask layer 84. In embodiments where the mask layer 84 comprises alumina, the hydrogen component of the precursor can form relatively high-energy bonds with the oxygen atoms of the mask layer 84. As a result, the precursor can be retained on the surface of the mask layer 84, reducing precursor absorption into the mask layer 84, and undesirable precursor residues (e.g., nodule defects) can be more easily removed using the mask layer 84. By removing precursor residues, the subsequent epitaxial growth in the n-type region 50N (e.g., epitaxial source / drain regions 93, see...) can be advantageously increased. Figure 23A ) process window.

[0058] Further as Figure 17B and Figure 17C As shown, the deposition and removal of the mask layer 84 can result in the formation of a metal residue 99 on the sidewalls of the first epitaxial region 92A and the STI region 68. When a second epitaxial region 92B is formed over the first epitaxial region 92A, the residue 99 can be disposed between the first epitaxial region 92A and the second epitaxial region 92B along the bottom corner of the second epitaxial region 92B. The residue 99 can be further disposed between the epitaxial source / drain region 92 and the STI region 68. In some embodiments, the metal residue 99 can be confined along... <100> Planar epitaxial growth is used to improve the bottom-up growth of the second epitaxial region 92B. In some embodiments, the concentration of metal elements (e.g., aluminum, hafnium, etc.) in the metal residue 99 in region 202 may be greater than about 10. 19 at / cm 3 Region 202 may refer to a region having a width W2, the lateral boundary of which extends through the adjacent fin 66. In some embodiments, the width W2 may be in the range of about 10 nm to about 100 nm.

[0059] exist Figure 18 In this process, the mask layer 84 is removed from the n-type region 50N by, for example, an etching process. This etching process can be a wet etching using dHF acid, H2SO4, NH4OH, H2O2, or combinations thereof as etchants. Since the precursor flowing during the growth of the second epitaxial region 92B remains bonded to the surface of the mask layer 84, this etching process can easily remove the residual precursor using the mask layer 84. As a result, precursor residue in the finished device can be reduced, and the processing window for forming the epitaxial source / drain regions in the n-type region 50N can be increased.

[0060] exist Figure 19 In this process, a mask layer 87 is deposited in the n-type region 50N and the p-type region 50P. The mask layer 87 may be a conformal layer deposited along the sidewalls and bottom surface of the recess 86 in the n-type region 50N (e.g., along the sidewalls of the first nanostructure 52, the second nanostructure 54, and the internal spacer 90, and along the upper surface of the first epitaxial region 93A). The mask layer 87 may be further deposited to cover the top surface and sidewalls of the mask 78, the dummy gate 76, and the dummy gate dielectric 71, and the top surface of the epitaxial source / drain region 92 in the p-type region 50P. The mask layer 87 may be formed from a similar material and using a similar process to that used for the mask layer 84. For example, in some embodiments, the mask layer 87 may be a metal-containing mask layer and may include aluminum oxide, aluminum nitride, hafnium oxide, etc. The mask layer 87 may have a width W1 ranging from about 1 nm to about 5 nm.

[0061] exist Figure 20 In this process, photoresist 89 is deposited and patterned. For example, photoresist 89 can be formed using spin coating and can be patterned using acceptable photolithography techniques. Photoresist 89 is patterned to expose n-type regions 50N while covering p-type regions 50P. Although photoresist 89 is illustrated as a single unit, it should be understood that photoresist 89 may have a multilayer structure. In some embodiments, photoresist 89 may be or may include a BARC material.

[0062] exist Figure 21 In this process, an etching process is applied to remove the mask layer 87 in the n-type region 50N. The etching process can be a wet etching process using a suitable etchant such as dHF acid. As a result of this etching process, the sidewalls of the multilayer stack 64 and the top surface of the first epitaxial region 93A are exposed in the n-type region 50N. However, the remainder of the mask layer 87 may cover the multilayer stack 64, the epitaxial source / drain regions 92, and the dummy gate 76 in the p-type region 50P. As a result of this etching process, metal residue 101 from the mask layer 87 may remain in the n-type region 50N (e.g., see...). Figure 23B and Figure 23C Metal residue 101 may be located, for example, on the top surface of the first epitaxial region 93A and / or on the sidewalls of the STI region 68. After patterning the mask layer 87, the photoresist 89 may be removed using, for example, cleaning and / or ashing processes. Figure 22 The resulting structure is shown.

[0063] exist Figures 23A-23CIn this context, the remaining portion of the epitaxial source / drain region 93 is formed within the n-type region 50N. The epitaxial source / drain region 93 may include one or more semiconductor material layers. For example, the epitaxial source / drain region 93 may include a first epitaxial region 93A and a second epitaxial region 93B located above the first epitaxial region 93A. The first semiconductor material layer 93A and the second semiconductor material layer 93B may be formed of different semiconductor materials and may be doped with different dopant concentrations. In some embodiments, the first semiconductor material layer 93A may have a lower dopant concentration than the second semiconductor material layer 93B. Any number of semiconductor material layers may be used for the epitaxial source / drain region 93. For example, in some embodiments, the epitaxial source / drain region 93 may include additional epitaxial regions grown above the second epitaxial region 93B. In such embodiments, these additional epitaxial regions may include materials different from the first epitaxial region 93A and / or the second epitaxial region 93B and / or have different doping concentrations.

[0064] In some embodiments, the second epitaxial region 93B can apply stress to the second nanostructure 54 in the n-type region 50N, thereby improving performance. The second epitaxial region 93B is formed in the first recess 86 such that each dummy gate 76 is disposed between corresponding adjacent pairs of the second epitaxial regions 93B. In some embodiments, a first spacer 81 is used to separate the second epitaxial region 93B from the dummy gate 76 by an appropriate lateral distance, and a first internal spacer 90 is used to separate the second epitaxial region 93B from the first nanostructure 52 by an appropriate lateral distance, such that the epitaxial source / drain region 93 does not short-circuit with the subsequently formed gate of the resulting nanostructure FET.

[0065] The second epitaxial region 93B may comprise any acceptable material suitable for an n-type nanostructure FET. For example, if the second nanostructure 54 is silicon, the second epitaxial region 93B may comprise a material on which tensile strain is applied, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, etc. The epitaxial source / drain region 93 may also have a surface protruding from a corresponding surface of the multilayer stack 64 and may have a facet.

[0066] The epitaxial source / drain region 93, the first nanostructure 52, the second nanostructure 54, and / or the substrate 50 can be implanted with dopants to form the source / drain region, similar to the previously discussed process for forming lightly doped source / drain regions, followed by annealing. The impurity concentration of the source / drain region 93 can be approximately 1 × 10⁻⁶. 19 atoms / cm 3 1×10 21 atoms / cm 3Between. The n-type impurity used for the source / drain region 93 can be any of the previously discussed impurities. In some embodiments, the epitaxial source / drain region 93 can be doped in situ during growth. In embodiments in which the epitaxial source / drain region 93 includes additional layers located above the second epitaxial region 93B, the doping concentration of these additional layers can be different from (e.g., less than) that of the second epitaxial region 93B.

[0067] like Figure 23B and Figure 23C As shown, as a result of the epitaxial process used to form the epitaxial source / drain regions 93, the upper surface of the epitaxial source / drain regions 93 has small facets that extend laterally outward beyond the sidewalls of the nanostructure 55. In some embodiments, these facets cause adjacent epitaxial source / drain regions 93 of the same NSFET to merge, such as... Figure 23B As shown. In other embodiments, adjacent source / drain regions 93 remain separated after the epitaxial process is completed, as... Figure 23C As shown. In Figure 23B and Figure 23C In the illustrated embodiment, the first spacer 81 may be formed on the top surface of the STI region 68 to prevent epitaxial growth. In some other embodiments, the first spacer 81 may cover portions of the sidewalls of the nanostructure 55 to further prevent epitaxial growth.

[0068] During the growth of the second epitaxial region 93B, the mask layer 87 covers the p-type region 50P. Advantages are achieved because the mask layer 87 comprises a metal. For example, during the epitaxial growth of the second epitaxial region 93B, a hydrogen-containing precursor (e.g., SiH4, Si2H6, SiH2C2, etc.) can flow into a deposition chamber located in the recess 86 and above the mask layer 87. In embodiments where the mask layer 87 comprises alumina, the hydrogen component of the precursor can form relatively high-energy bonds with the oxygen atoms of the mask layer 87. As a result, the precursor can be retained on the surface of the mask layer 87, precursor absorption into the mask layer 87 can be reduced, and unwanted precursor residues (e.g., nodule defects) can be more easily removed using the mask layer 87.

[0069] Further as Figure 23B and Figure 23CAs shown, the deposition and removal of mask layer 87 can result in metal residues remaining on the sidewalls of the first epitaxial region 93A and the STI region 68. When the second epitaxial region 93B is formed over the first epitaxial region 92A, the residue 101 can be disposed between the first epitaxial region 93A and the second epitaxial region 93B along the bottom corner of the second epitaxial region 93B. The residue 101 can be further disposed between the epitaxial source / drain region 93 and the STI region 68. In some embodiments, the concentration of the metal element (e.g., aluminum, hafnium, etc.) in the metal residue 101 in region 204 can be greater than about 10. 19 at / cm 3 Region 204 may refer to a region having a width W4, the lateral boundary of which extends through the adjacent fin 66. In some embodiments, the width W4 may be in the range of about 10 nm to about 100 nm.

[0070] exist Figure 24 In this process, the mask layer 87 is removed from the n-type region 50N by, for example, an etching process. This etching process can be a wet etching using dHF acid, H2SO4, NH4OH, H2O2, or combinations thereof as etchants. Since the precursor flowing during the growth of the second epitaxial region 93B remains bonded to the surface of the mask layer 87, this etching process can easily remove residual precursors using the mask layer 87. As a result, precursor residues in the finished device can be reduced.

[0071] Therefore, epitaxial source / drain regions 92 and 93 are formed in the p-type region 50P and the n-type region 50N, respectively. For ease of discussion only, the above figures depict the epitaxial source / drain region 92 in the p-type region 50P being formed prior to the epitaxial source / drain region 93 in the n-type region 50N. It should be understood that in other embodiments, the epitaxial source / drain region in the n-type region 50N may be formed prior to the formation of the epitaxial source / drain region in the p-type region 50P.

[0072] exist Figures 25A-25C In, respectively in Figure 6A , Figure 24 The first interlayer dielectric (ILD) 96 is deposited on the structure shown. Figures 7A-24 The process will not change. Figure 6A(See the cross-section shown). The first ILD 96 can be formed of a dielectric material and can be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL) 94 is disposed between the first ILD 96 and the epitaxial source / drain region 92, mask 78, and first spacer 81. CESL 94 may include a dielectric material having an etch rate different from that of the overlying first ILD 96, such as silicon nitride, silicon oxide, silicon oxynitride, etc.

[0073] exist Figures 26A-26B In this process, a planarization process such as CMP can be performed to make the top surface of the first ILD 96 flush with the top surface of the dummy gate 76 or the mask 78. This planarization process may also remove the mask 78 on the dummy gate 76, as well as a portion of the first spacer 81 along the sidewall of the mask 78. After this planarization process, the top surfaces of the dummy gate 76, the first spacer 81, and the first ILD 96 are flush within the process variation. Therefore, the top surface of the dummy gate 76 is exposed through the first ILD 96. In some embodiments, the mask 78 may be retained, in which case the planarization process makes the top surface of the first ILD 96 flush with the top surfaces of the mask 78 and the first spacer 81.

[0074] exist Figure 27A and Figure 27B In one or more etching steps, the dummy gate 76 and mask 78 (if present) are removed to form the second recess 98. A portion of the dummy gate dielectric 71 in the second recess 98 is also removed. In some embodiments, the dummy gate 76 and dummy gate dielectric 71 are removed by an anisotropic dry etching process. For example, this etching process may include a dry etching process using one or more reactive gases that selectively etch the dummy gate 76 at a faster rate than the first ILD 96 or the first spacer 81. Each second recess 98 exposes and / or overlays a portion of the nanostructure 55 that serves as a channel region in the subsequently completed nanostructure FET. The portion of the nanostructure 55 serving as a channel region is disposed between adjacent pairs of epitaxial source / drain regions 92. During removal, the dummy gate dielectric 71 can be used as an etch stop layer as the dummy gate 76 is etched. The dummy gate dielectric 71 can then be removed after the removal of the dummy gate 76.

[0075] exist Figure 28A and Figure 28B In this process, the first nanostructure 52 in the n-type region 50N and the second nanostructure 54 in the p-type region 50P are removed, extending the second recess 98. The first nanostructure 52 can be removed by forming a mask (not shown) over the p-type region 50P and performing an isotropic etching process, such as wet etching, using an etchant selective for the material of the first nanostructure 52, while the second nanostructure 54, the substrate 50, and the STI region 68 remain relatively unetched compared to the first nanostructure 52. In embodiments where the first nanostructure 52 comprises, for example, SiGe and the second nanostructures 54A-54C comprise, for example, Si or SiC, the first nanostructure 52 in the n-type region 50N can be removed using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like.

[0076] The second nanostructure 54 in the p-type region 50P can be removed by forming a mask (not shown) over the n-type region 50N and performing an isotropic etching process, such as wet etching, using an etchant selective for the material of the second nanostructure 54, while the first nanostructure 52, substrate 50, and STI region 68 remain relatively unetched compared to the second nanostructure 54. In embodiments where the second nanostructure 54 comprises, for example, SiGe and the first nanostructure 52 comprises, for example, Si or SiC, hydrogen fluoride, another fluorine-based etchant, etc., can be used to remove the second nanostructure 54 in the p-type region 50P.

[0077] exist Figure 29A and Figure 29B In this process, a gate dielectric layer 100 and a gate electrode 102 are formed to replace the gate. The gate dielectric layer 100 is conformally deposited in the second recess 98. In the n-type region 50N, the gate dielectric layer 100 may be formed on the top surface and sidewalls of the substrate 50, as well as on the top surface, sidewalls, and bottom surface of the second nanostructure 54, and in the p-type region 50P, the gate dielectric layer 100 may be formed on the top surface and sidewalls of the substrate 50, as well as on the top surface, sidewalls, and bottom surface of the first nanostructure 52. The gate dielectric layer 100 may also be deposited on the top surface of the first ILD 96, CESL 94, the first spacer 81, and the STI region 68.

[0078] According to some embodiments, the gate dielectric layer 100 includes one or more dielectric layers, such as oxides, metal oxides, etc., or combinations thereof. For example, in some embodiments, the gate dielectric may include a silicon oxide layer and a metal oxide layer situated on top of the silicon oxide layer. In some embodiments, the gate dielectric layer 100 includes a high-k dielectric material, and in these embodiments, the gate dielectric layer 100 may have a k value greater than about 7.0, and may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The structure of the gate dielectric layer 100 may be the same or different in the n-type region 50N and the p-type region 50P. Methods for forming the gate dielectric layer 100 may include molecular beam deposition (MBD), ALD, PECVD, etc.

[0079] Gate electrodes 102 are deposited on the gate dielectric layer 100 and fill the remainder of the second recess 98. Gate electrodes 102 may comprise a metallic material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiples thereof. For example, although in Figure 17A and Figure 17B A single-layer gate electrode 102 is shown, but the gate electrode 102 may include any number of liner layers, any number of work function adjustment layers, and filler material. Any combination of layers constituting the gate electrode 102 may be deposited in the n-type region 50N between adjacent second nanostructures 54 and between the second nanostructure 54A and the substrate 50, and may be deposited in the p-type region 50P between adjacent first nanostructures 52.

[0080] The formation of the gate dielectric layer 100 in the n-type region 50N and the p-type region 50P can occur simultaneously, such that the gate dielectric layer 100 in each region is formed of the same material, and the formation of the gate electrode 102 can occur simultaneously, such that the gate electrode 102 in each region is formed of the same material. In some embodiments, the gate dielectric layer 100 in each region can be formed by different processes, such that the gate dielectric layer 100 can be made of different materials and / or have different numbers of layers, and / or the gate electrode 102 in each region can be formed by different processes, such that the gate electrode 102 can be made of different materials and / or have different numbers of layers. When using different processes, various masking steps can be used to mask and expose appropriate regions.

[0081] After filling the second recess 98, a planarization process such as CMP can be performed to remove material from the gate electrode 102 and excess portions of the gate dielectric layer 100 above the top surface of the first ILD 96. The remaining material of the gate electrode 102 and the gate dielectric layer 100 thus form the replacement gate structure of the resulting nanostructured FET. The gate electrode 102 and the gate dielectric layer 100 can be collectively referred to as the “gate structure”.

[0082] exist Figures 30A-30C In this process, the gate structure (including the gate dielectric layer 100 and the corresponding upper gate electrode 102) is recessed, such that a recess is formed between the gate structure directly above and the opposite portion of the first spacer 81. A gate mask 104 comprising one or more layers of dielectric material (e.g., silicon nitride, silicon oxynitride, etc.) is filled into the recess, and then a planarization process is performed to remove excess dielectric material extending above the first ILD 96. The gate contacts subsequently formed (e.g., referred to below) Figure 32A and Figure 32B The gate contact 114 discussed here passes through the gate mask 104 and contacts the top surface of the recessed gate electrode 102.

[0083] like Figures 30A-30C As further shown, the second ILD 106 is deposited over the first ILD 96 and the gate mask 104. In some embodiments, the second ILD 106 is a flowable film formed by FCVD. In some embodiments, the second ILD 106 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., and can be deposited by any suitable method such as CVD, PECVD, etc.

[0084] exist Figures 31A-31CIn this process, the second ILD 106, the first ILD 96, CESL 94, and the gate mask 104 are etched to form a third recess 108, which exposes the surface of the epitaxial source / drain regions 92 and 93 and / or the gate structure. The third recess 108 can be formed by etching using an anisotropic etching process (e.g., RIE, NBE, etc.). In some embodiments, the third recess 108 can be etched through the second ILD 106 and the first ILD 96 using a first etching process; it can be etched through the gate mask 104 using a second etching process; and it can then be etched through the CESL 94 using a third etching process. A mask (e.g., photoresist) can be formed on and patterned over the second ILD 106 to mask portions of the second ILD 106 from the first and second etching processes. In some embodiments, the etching process may over-etch, so the third recess 108 extends into the epitaxial source / drain regions 92 and 93 and / or the gate structure, and the bottom of the third recess 108 may be flush with (e.g., at the same level, or having the same distance from the substrate) or below (e.g., closer to the substrate) the epitaxial source / drain regions 92 and 93 and / or the gate structure. Although Figure 31B The third recess 108 is shown as exposing the epitaxial source / drain regions 92 and 93 and the gate structure in the same cross section. However, in various embodiments, the epitaxial source / drain regions 92 and 93 and the gate structure may be exposed in different cross sections, thereby reducing the risk of short-circuiting the subsequently formed contacts. After forming the third recess 108, a silicide region 110 is formed over the epitaxial source / drain regions 92. In some embodiments, the silicide region 110 is formed as follows: first, a metal (not shown), such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals, or alloys thereof, capable of reacting with the semiconductor material (e.g., silicon, silicon-germanium, germanium) of the underlying epitaxial source / drain regions 92 and 93 to form a silicide region or germanide region, is deposited over the exposed portion of the epitaxial source / drain regions 92 and 93; then, a thermal annealing process is performed to form the silicide region 110. Unreacted portions of the deposited metal are then removed, for example, by an etching process. Although the silicide region 110 is referred to as a silicide region, it can also be a germanide region or a silicon-germanide region (e.g., a region comprising both silicide and germanide). In an embodiment, the silicide region 110 comprises TiSi and has a thickness in the range of about 2 nm to about 10 nm.

[0085] Next, in Figures 32A-32CIn the third recess 108, contacts 112 and 114 (also referred to as contact plugs) are formed. Contacts 112 and 114 may each include one or more layers, such as a barrier layer, a diffusion layer, and a filler material. For example, in some embodiments, contacts 112 and 114 each include a barrier layer and a conductive material, and are electrically coupled to underlying conductive features (e.g., gate structure 102 and / or silicide region 110 in the illustrated embodiment). Contact 114 is electrically coupled to gate structure 102 and may be referred to as a gate contact, and contact 112 is electrically coupled to silicide region 110 and may be referred to as a source / drain contact. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process such as CMP may be performed to remove excess material from the surface of the second ILD 106.

[0086] although Figures 32A-32C The diagram shows contact 112 extending to each epitaxial source / drain region 92 and 93, but contact 112 may be omitted from some epitaxial source / drain regions 92 and 93. For example, as will be explained in more detail below, conductive features (e.g., power rails) may subsequently be attached via the back side of one or more epitaxial source / drain regions 92 and 93. For these specific epitaxial source / drain regions 92 and 93, source / drain contact 112 may be omitted, or may be an unconnected conductive line (e.g., conductive line features, see below) Figure 21 () a virtual contact.

[0087] Various embodiments provide a metal-containing mask during source / drain epitaxial processes for forming source / drain regions in n-type and p-type device regions of a semiconductor die. The metal-containing mask protects the structure in the n-type or p-type device region of the die when growing source / drain regions for another type of device. In some embodiments, the metal-containing mask includes aluminum oxide, hafnium oxide, aluminum nitride, etc. It has been observed that metal oxides may be less likely to absorb precursors flowing during source / drain epitaxy. As a result, precursors may remain on the surface of the metal-containing mask, making it easier to remove precursor residues during a wet cleaning process for removing the metal-containing mask, and potentially reducing defects in the resulting device. The source / drain processing window can also be advantageously improved. Furthermore, the use of a metal-containing mask can allow for more bottom-up source / drain growth because the metal-containing mask can leave residues along the sidewalls of the STI region, which helps suppress the growth of precursors along the surface of the device. <100> Epitaxial growth of crystal planes.

[0088] In one embodiment, a method includes: etching a first recess adjacent to a first dummy gate stack and a first fin; etching a second recess adjacent to a second dummy gate stack and a second fin; epitaxially growing a first epitaxial region in the first recess; depositing a first metallized mask over the first dummy gate stack, over the second dummy gate stack, over the first epitaxial region in the first recess, and in the second recess; patterning the first metallized mask to expose the first dummy gate stack and the first epitaxial region; epitaxially growing a second epitaxial region in the first recess over the first epitaxial region; and removing the remainder of the first metallized mask after epitaxially growing the second epitaxial region. Optionally, in some embodiments, the first metallized mask includes aluminum oxide, aluminum nitride, or hafnium oxide. Optionally, in some embodiments, the method further includes: growing a first epitaxial region in a first recess while growing a third epitaxial region in a second recess; depositing a second metal-containing mask over a first dummy gate stack, a second dummy gate stack, the second epitaxial region, and the third epitaxial region in the second recess; patterning the second metal-containing mask to expose the second dummy gate stack and the third epitaxial region; epitaxially growing a fourth epitaxial region over the third epitaxial region in the second recess; and removing the remainder of the second metal-containing mask after epitaxially growing the fourth epitaxial region. Optionally, in some embodiments, the first and second epitaxial regions provide a first source / drain region of a first transistor, wherein the third and fourth epitaxial regions provide a second source / drain region of a second transistor, and wherein the second transistor is of a different type from the first transistor. Optionally, in some embodiments, after patterning the first metal-containing mask, metal residues of the first metal-containing mask remain on the first epitaxial region. Optionally, in some embodiments, epitaxially growing the second epitaxial region includes: flowing a hydrogen-containing precursor in a first recess and over a first metal-containing mask, and wherein removing the remainder of the first metal-containing mask includes: removing precursor residues of the hydrogen-containing precursor together with the remainder of the first metal-containing mask. Optionally, in some embodiments, the precursor residues are bonded to the surface of the first metal-containing mask. Optionally, in some embodiments, the hydrogen-containing precursor is SiH4, Si2H6, or SiH2C2.

[0089] In one embodiment, a method includes: etching a first recess in a first fin, wherein the first fin includes a first plurality of semiconductor layers; etching a second recess in a second fin, wherein the second fin includes a second plurality of semiconductor layers; depositing a first alumina layer on the bottom surface and sidewalls of the first and second recesses; removing the first alumina layer from the first recess; epitaxially growing a first epitaxial region in the first recess while the first alumina layer covers the second recess; and removing the first alumina layer from the second recess. Optionally, in some embodiments, the method further includes: depositing a second alumina layer on the first epitaxial region and on the bottom surface and sidewalls of the second recess; removing the second alumina layer from the second recess; epitaxially growing a second epitaxial region in the second recess while the second alumina layer covers the first epitaxial region; and removing the second alumina layer from the first epitaxial region. Optionally, in some embodiments, epitaxially growing the first epitaxial region includes: allowing a hydrogen-containing precursor to flow on the first alumina layer, and wherein residues of the hydrogen-containing precursor are bonded to the surface of the first alumina layer. Optionally, in some embodiments, removing the first alumina layer from the second recess includes removing hydrogen-containing precursors bonded to the surface of the first alumina layer. Optionally, in some embodiments, the method further includes epitaxially growing a third epitaxial region in the first recess and simultaneously epitaxially growing a fourth epitaxial region in the second recess before depositing the first alumina layer.

[0090] In one embodiment, a device includes: a first fin; a shallow trench isolation region adjacent to the first fin; a first epitaxial source / drain region extending into the first fin, wherein the first epitaxial source / drain region includes: a first epitaxial region; and a second epitaxial region located above the first epitaxial region, wherein the second epitaxial region includes a material different from the first epitaxial region; a first metal residue located between the first epitaxial source / drain region and the shallow trench isolation region; and a gate located above the first fin. Optionally, in some embodiments, the first metal residue is disposed between the first epitaxial region and the second epitaxial region. Optionally, in some embodiments, the device further includes: a second fin, wherein the shallow trench isolation region is located between the first fin and the second fin; a second epitaxial source / drain region extending into the second fin; and a second metal residue located between the second epitaxial source / drain region and the shallow trench isolation region. Optionally, in some embodiments, the second metal residue and the first metal residue each include aluminum. Optionally, in some embodiments, the aluminum concentration in the first region is greater than 10%. 19 at / cm 3The first region has a first lateral boundary extending through the first fin and a second lateral boundary extending through the second fin. Optionally, in some embodiments, the first fin includes a plurality of nanostructures, and a gate structure is disposed around each of the plurality of nanostructures. Optionally, in some embodiments, the first metal residue includes hafnium.

[0091] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0092] Example 1 is a method of forming a semiconductor device, comprising: etching a first recess adjacent to a first dummy gate stack and a first fin; etching a second recess adjacent to a second dummy gate stack and a second fin; epitaxially growing a first epitaxial region in the first recess; depositing a first metal-containing mask over the first dummy gate stack, over the second dummy gate stack, over the first epitaxial region in the first recess, and in the second recess; patterning the first metal-containing mask to expose the first dummy gate stack and the first epitaxial region; epitaxially growing a second epitaxial region in the first recess over the first epitaxial region; and removing the remainder of the first metal-containing mask after epitaxially growing the second epitaxial region.

[0093] Example 2 is the method described in Example 1, wherein the first metal-containing mask comprises aluminum oxide, aluminum nitride, or hafnium oxide.

[0094] Example 3 is the method of Example 1, further comprising: growing a first epitaxial region in the first recess while growing a third epitaxial region in the second recess; depositing a second metal-containing mask over the first dummy gate stack, the second dummy gate stack, the second epitaxial region, and the third epitaxial region in the second recess; patterning the second metal-containing mask to expose the second dummy gate stack and the third epitaxial region; epitaxially growing a fourth epitaxial region over the third epitaxial region in the second recess; and removing the remaining portion of the second metal-containing mask after epitaxially growing the fourth epitaxial region.

[0095] Example 4 is the method described in Example 3, wherein the first epitaxial region and the second epitaxial region provide a first source / drain region of the first transistor, wherein the third epitaxial region and the fourth epitaxial region provide a second source / drain region of the second transistor, and wherein the second transistor is of a different type from the first transistor.

[0096] Example 5 is the method described in Example 1, wherein, after patterning the first metal-containing mask, metal residues of the first metal-containing mask remain on the first epitaxial region.

[0097] Example 6 is the method of Example 1, wherein epitaxially growing the second epitaxial region includes: flowing a hydrogen-containing precursor in the first recess and over the first metal-containing mask, and wherein removing the remainder of the first metal-containing mask includes: removing precursor residues of the hydrogen-containing precursor together with the remainder of the first metal-containing mask.

[0098] Example 7 is the method described in Example 6, wherein the precursor residue is bonded to the surface of the first metal-containing mask.

[0099] Example 8 is the method described in Example 6, wherein the hydrogen-containing precursor is SiH4, Si2H6, or SiH2C2.

[0100] Example 9 is a method of forming a semiconductor device, comprising: etching a first recess in a first fin, wherein the first fin includes a first plurality of semiconductor layers; etching a second recess in a second fin, wherein the second fin includes a second plurality of semiconductor layers; depositing a first aluminum oxide layer on the bottom surface and sidewalls of the first recess and the second recess; removing the first aluminum oxide layer from the first recess; epitaxially growing a first epitaxial region in the first recess while the first aluminum oxide layer covers the second recess; and removing the first aluminum oxide layer from the second recess.

[0101] Example 10 is the method of Example 9, further comprising: depositing a second alumina layer on the first epitaxial region and on the bottom surface and sidewalls of the second recess; removing the second alumina layer from the second recess; epitaxially growing a second epitaxial region in the second recess while the second alumina layer covers the first epitaxial region; and removing the second alumina layer from the first epitaxial region.

[0102] Example 11 is the method of Example 9, wherein epitaxial growth of the first epitaxial region includes: flowing a hydrogen-containing precursor over the first alumina layer, and wherein a residue of the hydrogen-containing precursor is bonded to the surface of the first alumina layer.

[0103] Example 12 is the method of Example 11, wherein removing the first alumina layer from the second recess includes: removing the hydrogen-containing precursor bonded to the surface of the first alumina layer.

[0104] Example 13 is the method of Example 9, further comprising: epitaxially growing a third epitaxial region in the first recess and simultaneously epitaxially growing a fourth epitaxial region in the second recess before depositing the first alumina layer.

[0105] Example 14 is a semiconductor device comprising: a first fin; a shallow trench isolation region adjacent to the first fin; a first epitaxial source / drain region extending into the first fin, wherein the first epitaxial source / drain region comprises: a first epitaxial region; and a second epitaxial region located above the first epitaxial region, wherein the second epitaxial region comprises a material different from the first epitaxial region; a first metal residue located between the first epitaxial source / drain region and the shallow trench isolation region; and a gate located above the first fin.

[0106] Example 15 is the device described in Example 14, wherein the first metal residue is disposed between the first epitaxial region and the second epitaxial region.

[0107] Example 16 is the device described in Example 14, further comprising: a second fin, wherein the shallow trench isolation region is located between the first fin and the second fin; a second epitaxial source / drain region extending into the second fin; and a second metal residue located between the second epitaxial source / drain region and the shallow trench isolation region.

[0108] Example 17 is the device described in Example 16, wherein the second metal residue and the first metal residue each comprise aluminum.

[0109] Example 18 is the device described in Example 17, wherein the aluminum concentration in the first region is greater than 10. 19 at / cm 3 The first region has a first lateral boundary extending through the first fin and a second lateral boundary extending through the second fin.

[0110] Example 19 is the device described in Example 14, wherein the first fin comprises a plurality of nanostructures, and wherein a gate structure is disposed around each of the plurality of nanostructures.

[0111] Example 20 is the device described in Example 14, wherein the first metal residue comprises hafnium.

Claims

1. A method for forming a semiconductor device, comprising: Etch a first recess, which is adjacent to a first dummy gate stack and a first fin; Etch a second recess, which is adjacent to a second dummy gate stack and a second fin; A first epitaxial region is grown epitaxially in the first recess; A first metal-containing mask is deposited on the first dummy gate stack, on the second dummy gate stack, on the first epitaxial region in the first recess, and in the second recess. The first metal-containing mask is patterned to expose the first dummy gate stack and the first epitaxial region; In the first recess, a second epitaxial region is epitaxially grown above the first epitaxial region; as well as After the second epitaxial region is epitaxially grown, the remaining portion of the first metal-containing mask is removed.

2. The method according to claim 1, wherein, The first metal-containing mask includes aluminum oxide, aluminum nitride, or hafnium oxide.

3. The method according to claim 1, further comprising: While the first epitaxial region is grown in the first recess, the third epitaxial region is grown in the second recess; A second metal-containing mask is deposited on the first dummy gate stack, the second dummy gate stack, the second epitaxial region, and the third epitaxial region in the second recess; The second metal-containing mask is patterned to expose the second dummy gate stack and the third epitaxial region; In the second recess, a fourth epitaxial region is epitaxially grown over the third epitaxial region; as well as After the fourth epitaxial region is epitaxially grown, the remaining portion of the second metal-containing mask is removed.

4. The method according to claim 3, wherein, The first epitaxial region and the second epitaxial region provide a first source / drain region for a first transistor, wherein the third epitaxial region and the fourth epitaxial region provide a second source / drain region for a second transistor, and wherein the second transistor is of a different type from the first transistor.

5. The method according to claim 1, wherein, After the first metal-containing mask is patterned, the metal residue of the first metal-containing mask remains on the first epitaxial region.

6. The method according to claim 1, wherein, Epitaxial growth of the second epitaxial region includes: flowing a hydrogen-containing precursor in the first recess and over the first metal-containing mask, wherein removing the remainder of the first metal-containing mask includes: removing precursor residues of the hydrogen-containing precursor together with the remainder of the first metal-containing mask.

7. The method according to claim 6, wherein, The precursor residue is bonded to the surface of the first metal-containing mask.

8. The method according to claim 6, wherein, The hydrogen-containing precursor is SiH4, Si2H6, or SiH2C2.

9. A method for forming a semiconductor device, comprising: A first recess is etched in the first fin, wherein the first fin includes a first plurality of semiconductor layers; A second recess is etched in the second fin, wherein the second fin includes a second plurality of semiconductor layers; A first aluminum oxide layer is deposited on the bottom surface and sidewall of the first and second recesses; Remove the first aluminum oxide layer from the first recess; While the first alumina layer covers the second recess, a first epitaxial region is epitaxially grown in the first recess; and Remove the first aluminum oxide layer from the second recess.

10. The method of claim 9, further comprising: A second alumina layer is deposited on the first epitaxial region and on the bottom surface and sidewalls of the second recess; Remove the second aluminum oxide layer from the second recess; While the second alumina layer covers the first epitaxial region, a second epitaxial region is epitaxially grown in the second recess; as well as Remove the second alumina layer from the first epitaxial region.

11. The method according to claim 9, wherein, Epitaxial growth of the first epitaxial region includes: flowing a hydrogen-containing precursor over the first alumina layer, wherein a residue of the hydrogen-containing precursor is bonded to the surface of the first alumina layer.

12. The method according to claim 11, wherein, Removing the first alumina layer from the second recess includes removing the hydrogen-containing precursor bonded to the surface of the first alumina layer.

13. The method of claim 9, further comprising: Before depositing the first alumina layer, a third epitaxial region is epitaxially grown in the first recess, and a fourth epitaxial region is epitaxially grown in the second recess.

14. A semiconductor device, comprising: First fin; The shallow trench isolation area is adjacent to the first fin; A first epitaxial source / drain region extends into the first fin, wherein the first epitaxial source / drain region includes: The first extended region; and A second epitaxial region is located above the first epitaxial region, wherein the second epitaxial region comprises a material different from that of the first epitaxial region; A first metal residue is located between the first epitaxial source / drain region and the shallow trench isolation region; and The gate is located above the first fin. The first metal residue is disposed between the first epitaxial region and the second epitaxial region.

15. The device according to claim 14, further comprising: The second fin, wherein the shallow groove isolation area is located between the first fin and the second fin; The second epitaxial source / drain region extends into the second fin; The second metal residue is located between the second epitaxial source / drain region and the shallow trench isolation region.

16. The device according to claim 15, wherein, The second metal residue and the first metal residue each comprise aluminum.

17. The device according to claim 16, wherein, The aluminum concentration in the first metal residue area is greater than 10. 19 at / cm 3 The first metal residue region has a first lateral boundary extending through the first fin and a second lateral boundary extending through the second fin.

18. The device according to claim 14, wherein, The first fin comprises a plurality of nanostructures, wherein a gate structure is disposed around each of the plurality of nanostructures.

19. The device according to claim 14, wherein, The first metal residue includes hafnium.

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