Integrated circuit (IC) structure with body contact to well containing multiple diode junctions

Abstract

The present disclosure provides an integrated circuit (IC) structure with a body contact to a well containing multiple diode junctions. A first doped well is located in a substrate. A transistor is located on the first doped well. A trench isolation (TI) is adjacent to a portion of the first doped well. A second doped well within the substrate has a bottom surface located below a bottom surface of the first doped well. A sidewall of the TI abuts the second doped well in a horizontal direction. A first diode junction is located between the second doped well and the first doped well. A second diode junction is located between the second doped well and the substrate. A body contact is located on the second doped well.

Description

Technical Field

[0001] The embodiments of this disclosure generally relate to integrated circuit (IC) structures. More specifically, various embodiments of this disclosure provide IC structures having a body contact to a well containing multiple diode junctions. Background Technology

[0002] In the microelectronics industry, and other industries involving the construction of microstructures, there has always been a desire to reduce the size of structural features and microelectronic devices and / or to provide more circuitry for a given chip size. Miniaturization typically allows for improved performance (more processing per clock cycle and less heat generation) at lower power levels and lower costs. Current techniques involve atomically scaling certain microdevices such as logic gates, FETs, and capacitors. Circuit chips with millions of such devices are commonplace.

[0003] Circuit manufacturers are currently striving to reduce the two-dimensional area occupied by device components, for example, to reduce 2D area and power consumption. One problem with the miniaturization of digital circuits characterized by field-effect transistors (FETs) is the electrical bias of the transistor body terminals (i.e., the electrically active regions beneath the source, drain, channel, and gate of the FET). The FET body bias can affect the linearity of the expected input-output voltage function and / or voltage gain in the circuit components. In conventional designs, effective biasing of the FET body may require forming several (i.e., three or more) distinct wells. This approach uses a considerable area and may not be feasible in many device or technology settings. Furthermore, in some technology settings, such transistor structures often fail to provide sufficient voltage gain or reliable electrical operation. Summary of the Invention

[0004] Some aspects of this disclosure provide an integrated circuit (IC) structure including: a first doped well located within a substrate, the first doped well having a first doping type; a transistor structure located on the first doped well; a trench isolation (TI) adjacent to a portion of the first doped well; and a second doped well located within the substrate and coupled to a body contact, the second doped well having a second doping type opposite to the first doping type, wherein the sidewalls of the TI are adjacent to the second doped well in a horizontal direction, a vertical boundary between the second doped well and the first doped well defines a first diode junction, and a vertical boundary between the second doped well and the substrate defines a second diode junction.

[0005] Other aspects of this disclosure provide an integrated circuit (IC) structure comprising: a first doped well located within a substrate, the first doped well having a first doping type; a transistor structure located on the first doped well; a trench isolation (TI) adjacent to a portion of the first doped well; a second doped well located within the substrate, the second doped well having a second doping type opposite to the first doping type, wherein the second doped well includes: a first portion located below the first doped well, wherein a vertical boundary between the first portion of the second doped well and the first doped well defines a first diode junction, and a vertical boundary between the first portion of the second doped well and the substrate defines a second diode junction; and a second portion coupled to a body contact and having a bottom surface substantially coplanar with the bottom surface of the first portion, wherein the second portion includes a sidewall adjacent to the first portion of the second doped well and adjacent to the TI.

[0006] Another aspect of this disclosure provides a method for forming an integrated circuit (IC) structure, the method comprising: forming a first doped well of a first doping type in a substrate; forming a trench isolation (TI) in the substrate adjacent to a sidewall of the first doped well; forming a second doped well of a second doping type in the substrate, wherein a vertical boundary between a first portion of the second doped well and the first doped well defines a first diode junction, and a vertical boundary between the first portion of the second doped well and the substrate defines a second diode junction; forming a transistor structure on the first doped well; and forming a body contact to a second portion of the second doped well. Attached Figure Description

[0007] These and other features of this disclosure will be more readily understood through a detailed description of various aspects thereof, taken in conjunction with the accompanying drawings, which illustrate various embodiments of this disclosure, wherein:

[0008] Figure 1 A cross-sectional view is provided of the formation of a first doped well and trench isolation (TI) in a substrate according to the method of this disclosure.

[0009] Figure 2 A cross-sectional view is provided of the first portion of the second doped well formed in the method according to this disclosure.

[0010] Figure 3 Cross-sectional views of dopant extension regions formed in a first doped well and a second doped well according to embodiments of the present disclosure are provided.

[0011] Figure 4Cross-sectional views of alternative processes for forming dopant extension regions in a first doped well and a second doped well according to embodiments of the present disclosure are provided.

[0012] Figure 5 A cross-sectional view of a second portion and optional resistive region forming a second doped well according to an embodiment of the present disclosure is provided.

[0013] Figure 6 A cross-sectional view of a transistor structure formed according to an embodiment of the present disclosure is provided.

[0014] Figure 7 A cross-sectional view of an IC structure having a body contact to a second doped well according to an embodiment of the present disclosure is provided.

[0015] Figure 8 A plan view of an IC structure having a body contact to a second doped well according to an embodiment of the present disclosure is provided.

[0016] Figure 9 Cross-sectional views of an IC structure according to another embodiment of the present disclosure are provided.

[0017] Figure 10 Plan views of IC structures according to other embodiments of this disclosure are provided.

[0018] Figure 11 Cross-sectional views of IC structures according to other embodiments of this disclosure are provided.

[0019] Figure 12 A plan view of an IC structure according to an additional embodiment of the present disclosure is provided.

[0020] Figure 13 A plan view of an IC structure according to a further embodiment of the present disclosure is provided.

[0021] It should be noted that the accompanying drawings of this disclosure are not necessarily drawn to scale. The drawings are intended to depict typical aspects of this disclosure and should therefore not be considered as limiting the scope of this disclosure. In the drawings, similar reference numerals indicate similar elements between the figures. Detailed Implementation

[0022] In this description, reference is made to the accompanying drawings, which form part of the specification and are illustrated by way of specific exemplary embodiments in which the teachings may be practiced. These embodiments have been described in sufficient detail to enable those skilled in the art to practice the teachings, and it should be understood that other embodiments may be used and changes may be made within the scope of the teachings. Therefore, the description herein is merely illustrative.

[0023] Embodiments of this disclosure provide an integrated circuit (IC) structure having a body contact to a doped well, the doped well having a plurality of diode junctions. The IC structure can be formed on a substrate, for example, on a bulk region of a semiconductor material. The substrate may have a first doped well of a first doping type, wherein the top surface of the first doped well is substantially coplanar (e.g., flush) with the top surface of the substrate. A transistor may be located on the first doped well and may include a source region, a drain region, and a channel region located within the first doped well. One or more trench isolation (TI) regions may be located within the first doped well. A second doped well, also within the substrate, may have a second doping type opposite to the first doping type. The bottom surface of the second doped well may be located below the bottom surface of the first doped well. A vertical boundary between the first and second doped wells defines a first diode junction, while a vertical boundary between the second doped well and the substrate defines a second diode junction. The body contact coupled to the second doped well allows electrical biasing of the first doped well below the transistor through the diode junctions. Embodiments of this disclosure also include a method of forming an IC structure having a body contact to a second doped well having a diode junction.

[0024] refer to Figure 1 A cross-sectional view of an initial structure 100 according to an embodiment of the present disclosure is shown. In various methods according to embodiments of the present disclosure, the initial structure 100 can be adapted to form various IC structures, and various processing methods are discussed herein. The initial structure 100 may have a substrate 102, which includes, for example, one or more semiconductor materials. The substrate 102 may include any semiconductor material now known or hereafter developed, including but not limited to silicon, germanium, silicon carbide, and materials substantially composed of one or more III-V compound semiconductors having the chemical formula Al X1 Ga X2 In X3 As Y1 P Y2 N Y3 Sb Y4 The composition is defined, where X1, X2, X3, Y1, Y2, Y3, and Y4 represent relative proportions that are each greater than or equal to zero, and X1 + X2 + X3 + Y1 + Y2 + Y3 + Y4 = 1 (where 1 is the total relative molar amount). Other suitable substrates include those with the composition Zn. A1 Cd A2 Se B1 Te B2The substrate 102 is a II-VI compound semiconductor, wherein A1, A2, B1, and B2 are relative proportions greater than or equal to zero, and A1 + A2 + B1 + B2 = 1 (where 1 is the total molar amount). Strain may occur in the entire substrate 102 or a portion thereof. The substrate 102 may include a bulk silicon layer, but in other embodiments, it may take the form of a semiconductor-on-insulator (SOI) substrate, semiconductor fins, and / or other types of substrates. The substrate 102 may have a top surface S on which subsequent components (e.g., masks, contacts, transistors, etc.) are formed.

[0025] One or more trench isolations (TI) 104 may be formed in selected regions of substrate 102 to define electrical boundaries between various subsequently formed elements. The TI 104 may be provided in the form of shallow trench isolation or deep trench isolation; that is, in some embodiments, the TI 104 may have varying depths within substrate 102. The TI 104 may be provided by forming trenches within selected portions of substrate 102 and filling the trenches with an insulating material such as an oxide to isolate one region of the substrate from adjacent regions of the substrate. Figure 1 One or more of the TI 104 shown may be part of a single region of the TI 104 material, having a ring-shaped geometry (e.g., a ring, a hollow polygon, etc.). In this case, the TI 104 may be formed circumferentially around the first doped well 106 (e.g., as shown in the diagram). Figure 7 (As shown and discussed elsewhere in this document). TI 104 may have a top surface that is substantially coplanar with the top surface S of substrate 102, for example, by planarizing it after the TI 104 material is formed. Figure 1 Two regions of TI 104 are shown as examples; possible additional regions of TI 104 are shown in dashed lines. Each TI 104 can be formed from any material now known or later developed for providing electrical insulation, and may include, for example: silicon nitride (Si3N4), silicon oxide (SiO2), fluorinated SiO2 (FSG), hydrogenated carbon silicon oxide (SiCOH), porous SiCOH, borophosphosilicate glass (BPSG), silsesquioxane, carbon (C) doped oxides (i.e., organosilicones) including atoms of silicon (Si), carbon (C), oxygen (O) and / or hydrogen (H), thermosetting polyarylene ethers, spin-coated silicon-carbon polymer materials, near-frictionless carbon (NFC), or multilayers thereof.

[0026] The method according to this disclosure may include introducing a dopant into a semiconductor material to form one or more doped regions within a substrate 102, taking the form of a first doped well 106 having a first doping type. "Dopant" refers to an element introduced into a semiconductor to establish p-type (acceptor) or n-type (donor) conductivity. Typically, in doping, the dopant, dose, and energy level are specified and / or the resulting doping level may be specified. The dose may be expressed in centimeters per square centimeter (cm²). 2 The number of atoms and energy levels (specified in keV) are specified, thus producing per cubic centimeter (cm²) 3 The doping level (concentration in the substrate) refers to the number of atoms. The number of atoms is usually specified in exponential notation, where a number like "3E15" represents 3 multiplied by 10 to the power of 15, or "3" followed by 15 zeros (3,000,000,000,000,000). An example of doping is approximately 1E12 to 1E13 atoms / cm³. 2 Boron (B) was implanted at doses between 1E17 and 1E18 atoms / cm² at energies of approximately 40 to 80 keV to produce a yield of 1E17 to 1E18 atoms / cm². 3 The doping levels between these parameters. The doped portion of the substrate may be referred to in the art as a "well". A well typically refers to an implanted / diffused region in a semiconductor wafer required to realize a complementary metal-oxide-semiconductor (CMOS) element. A "deep well" refers to doped semiconductor material located beneath active device components and / or other wells. Depending on the properties of the device to be fabricated, the first doped well 106 may be P-type or N-type doped.

[0027] According to one example, the first doping type can be P-type doping, so the first doped well 106 can be referred to as a "P-well". When referring to dopants, P-type dopants are elements introduced into semiconductor materials to generate free holes by "accepting" electrons from semiconductor atoms and thus "releasing" holes. The acceptor atom must have one less valence electron than the matrix semiconductor. P-type dopants suitable for substrate 102 can include, but are not limited to: boron (B), indium (In), and gallium (Ga). Boron (B) is the most common acceptor in silicon technology. Other alternatives include In and Ga. Ga has a high diffusivity in silicon dioxide (SiO2), so the oxide cannot be used as a mask during Ga diffusion. The first doped well 106 can be formed in substrate 102, for example, by vertical ion implantation at a target location (e.g., between regions forming TI 104). Since the first doped well 106 can be formed by doping a portion of substrate 102, it can have a top surface coplanar with the top surface S of substrate 102. In some cases, substrate 102 may also include a dopant, which may be of the same doping type as the first doped well 106, or may not be of the same doping type as the first doped well 106. In this case, the first doped well 106 may have the same doping type as substrate 102, but has a higher doping concentration of the first doping type (e.g., p-type doping) than substrate 102. Therefore, even if the first doped well 106 and substrate 102 have the same doping type, the first doped well 106 and substrate 102 can be distinguished at least in part based on their doping concentration, dopant material, etc. Substrate 102 may include other doped wells having the same or different doping types, and this is only for clarity. Figure 1 Such a trap is omitted in the text.

[0028] Turn Figure 2 Subsequent processing may include forming additional doped wells within substrate 102. A mask 108 may be formed over the initial structure 100. Mask 108 may include any mask material now known or developed later. Common mask materials are photoresists (photoresists) and nitrides. Nitrides are generally classified as “hard masks.” Mask 108 may include a developable organic planarization layer (OPL) on substrate 102, a developable antireflective coating (ARC) on the developable OPL, and / or a “photoresist mask” layer on the developable ARC layer. Mask 108 includes an opening M. Opening M exposes the area within substrate 102 above the first doped well 106 and TI 104. Mask 108 may cover other portions of substrate 102 (or other TI 104, if applicable) to protect these portions from receiving dopants and / or being otherwise processed.

[0029] The method disclosed herein may include forming a second doped well 110 beneath the TI 104 and the first doped well 106. The second doped well 110 may have a second doping type opposite to that of the first doped well 110, for example, N-type doping if the first doped well 106 is P-type doped. The second doped well 110 may be formed by introducing an N-type dopant into the substrate 102 and / or the precursor semiconductor material using any now-known or later-developed technique for doping material beneath the first doped well 106, e.g., ion implantation. An N-type dopant is an element introduced into a semiconductor material to generate free electrons, for example, by “donating” electrons to the semiconductor. An N-type dopant must have one more valence electron than the semiconductor. Common N-type donors in silicon (Si) include, for example, phosphorus (P), arsenic (As), and / or antimony (Sb). The process for forming the second doped well 110 may have substantially no effect on the doping and / or composition of the overlying material, including the TI 104 and the first doped well 106 (e.g., the first doped well 106 may continue to have the first doping type after the formation of the second doped well 110). A first portion 110a of the second doped well may be located below the TI 104. Other portions of the second doped well 110 may be formed by other processes described herein. The first portion 110a of the second doped well 110 may be located below and in direct contact with the bottom surface of the TI 104 and the first doped well 106 above it.

[0030] Now for reference Figure 3 Embodiments of this disclosure may optionally include adjusting the dopant concentration in the target portion of the first doped well 106 and / or the second doped well 110 to control the position of the diode junction. A diode junction is a physical interface between two oppositely doped regions of semiconductor material. The diode effect is modulated by changing the doping levels on both sides of the junction. According to an example, mask 108 ( Figure 2 The dopant mask 108 can be removed (e.g., by stripping and / or other mask removal processes) and subsequently replaced with a dopant-adjusting mask 112. The dopant-adjusting mask 112 can include components relative to mask 108. Figure 2The opening M within the first doped well 106 is narrower in width or otherwise has an opening N of a different size. The size of the opening N can allow additional dopants to be introduced into the first doped well 106 and / or the second doped well 110, for example, to create a first dopant extension region 114 in the first doped well 106 and a second dopant extension region 116 in the second doped well 110. The first dopant extension region 114 can have the same doping type as the first doped well 106, and the second dopant extension region 116 can have the same doping type as the second doped well 110. The dopant extension regions 114, 116 can be distinguished from other portions of the doped wells 106, 110 by having a significantly higher dopant concentration therein. In this case, a low-leakage junction diode is formed between the first doped well 106 and the second doped well 110. In some cases, the dopant extension regions 114, 116 may not be formed in only one of the respective doped wells 106, 110. For example, either of the dopant extension regions 114, 116 may horizontally overlap with the other of the dopant extension regions 114, 116 within one or both of the doped wells 106, 110. Similarly, the dopant extension regions 114, 116 may extend into the upper portion of the doped well 106 and / or gate structure 126, thus being closer to the location of a set of source / drain regions 127. In some embodiments, the formation of the dopant extension regions 114, 116 may be omitted (e.g., by adjusting the dopant mask 112). The nested arrangement of the doped wells 106, 110 in the substrate 102 (possibly with the addition of the dopant extension regions 114, 116) can define a set of diode junctions in the final IC structure. The location and polarity of such diode junctions are discussed in more detail elsewhere herein (e.g., regarding...). Figure 6 ).

[0031] Figure 4 An alternative arrangement is shown, in which the first part 110a (e.g., using) Figure 2 The mask 108 and the bottom surface of the first doped well 106 are very lightly doped. In this case, another mask 112A can be used to heavily dope the uncovered first portion 110a and a portion of the bottom surface of the first doped well 106. This process leaves very lightly doped dopant extension regions 114, 116 and creates a diode with high reverse leakage current. Therefore, compared to other configurations, the dopant extension regions 114, 16 can have a significantly lower dopant concentration than the adjacent portions of the doped wells 106, 110.

[0032] Figure 5 The additional doping of substrate 102 and the formation of additional materials to control the electrical bias of the final IC structure are shown. Here, mask 112 ( Figure 3 ) can be replaced with trap mask 118 (e.g., having the same characteristics as mask 108). Figure 2(The composition is the same as or similar to that of 112). The well mask 118 may include one or more openings J located above the position adjacent to the TI 104. In some cases, the openings J may be horizontally surrounding the TI 104. In the case of forming multiple TI 104s, the openings J may be above a portion of the substrate 102, which is horizontally located between the multiple TI 104s. An additional dopant of a second doping type (e.g., N-type doping) may be introduced into the substrate 102 in a manner similar to that of the first portion 110a of the second doped well 110, or introduced by any other suitable technique. Introducing the dopant into the substrate 102 below the openings J of the well mask 118 may form one or more second portions 110b of the second doped well 110. The second portions 110b may extend vertically from the top surface S of the substrate 102 or from the resistive region 120 to the bottom surface T within the substrate 102. In this case, the bottom surface T is substantially coplanar with the bottom surface of the first portion 110a. In this configuration, the second portion 110b may have a sidewall U that is horizontally adjacent to the first portion 110a of the second doped well 110 and the STI 104 above it. As will be discussed in further detail herein, the sidewall U of the second portion may be horizontally surrounding the first portion 110a and / or the TI 104.

[0033] Continue to refer to Figure 5 Embodiments of this disclosure may include forming a resistive material within a second portion 110b of the second doped well 110. Using a mask 118 or another structure, a portion of the semiconductor material within the second portion 110b may be intentionally damaged to increase resistance in the damaged region. When implemented, such intentional damage to the second portion 110b may include introducing argon (Ar), xenon (Xe), and / or other molecules (e.g., by implantation) to transform a sub-portion of the second portion 110b into a resistive region 120. The resistive region 120 may include various types of damaged silicon, such as argon-implanted silicon or xenon-implanted silicon, and / or may include other semiconductor materials with a greater resistance than the remainder of the second doped well 110. The material and / or damage type used to form the resistive region 120 may be controlled such that the resistive region 120 has a desired resistance, for example, from about twenty kiloohms (kΩ) to about one hundred megaohms (MΩ) or greater. The second portion 110b of the second doped well 110 located below the resistive region 120 may act as a conductive region. Forming a resistive region 120 in the second portion 110b of the second doped well 110 can allow subsequently formed contacts to the second doped well 110 (as discussed elsewhere herein) to exhibit lower electrical bias sensitivity and / or greater control over the behavior of the transistor structure formed on the first doped well 106.

[0034] Turn Figure 6The next step may include forming active device elements on various doped materials in the substrate 102. Figure 6 This illustrates the formation of a transistor mask 122 on the upper surface S of substrate 102. Based on the process sequence for forming various wells and insulating materials in substrate 102, the transistor mask 122 can replace the well mask 118. Figure 5 Or any other masking material discussed herein. The transistor mask 122 may cover a portion of the substrate 102, TI 104, and / or the second region 110b of the second doped well 110 (including the resistive region 120 where applicable). The transistor mask 122 may have an opening P above the first doped well 106, such that various materials can be formed thereon.

[0035] The method disclosed herein may include forming a gate dielectric layer 124 on the upper surface S of the substrate 102, above the first doped well 106. The gate dielectric layer 124 may include a high-k dielectric, such as, but not limited to: metal oxides, such as tantalum oxide (Ta₂O₅), barium titanium oxide (BaTiO₃), hafnium oxide (HfO₂), zirconium oxide (ZrO₂), aluminum oxide (Al₂O₃); or metal silicates, such as hafnium silicate (HfO₂). A1 Si A2 O A3 ) or hafnium oxynitride silicate (Hf A1 Si A2 O A3 N A4), where A1, A2, A3 and A4 represent relative proportions, which are greater than or equal to zero and A1+A2+A3+A4 (1 is the total relative molar amount). The gate dielectric layer 124 may include any conceivable insulating material, such as, but not limited to: silicon nitride (Si3N4); silicon oxide (SiO2); fluorinated SiO2 (FSG); hydrogenated carbon silicon oxide (SiCOH); porous SiCOH; borosilicate glass (BPSG); silsesquioxane; carbon (C) doped oxides (i.e., organosilicones) comprising atoms of silicon (Si), carbon (C), oxygen (O) and / or hydrogen (H); thermosetting polyarylene ether; SiLK (a polyarylene ether available from Dow Chemical Corporation); spin-coated silicon-carbon-containing polymer materials available from JSR Corporation; hydrogenated carbon silicon oxide (SiCOH); porous SiCOH; porous methylsilsesquioxane (MSQ); porous hydrogen silsesquioxane (HSQ); octamethylcyclotetrasiloxane (OMCTS)[(CH3)2SiO]4 available from Air Liquide. 2.7, or other low dielectric constant (k<3.9) materials, or combinations thereof. The gate dielectric layer 124 may also include high-k dielectric materials, such as, but not limited to, hafnium silicate (HfSiO), zirconium silicate (ZrSiOx), silicon oxynitride (SiON), or any combination thereof.

[0036] The method of this disclosure may further include forming a gate structure 126 over a gate dielectric layer 124 on the first doped well 106. Additional dopant may be formed in a region adjacent to the gate dielectric layer 124 within the first doped well 106 to form a set of source / drain (S / D) regions 127 in the first doped well 106. The gate dielectric layer 124, gate structure 126, and S / D regions 127 together define a transistor structure 128 on the first doped well 106. The S / D regions 127 may be formed by introducing a selected type of dopant (e.g., a P-type dopant) into the substrate 102 using any techniques now known or developed hereafter (as discussed herein with respect to the formation of the first doped well 106 and / or the second doped well 110). In some cases, the S / D regions 127 may be formed by doping with the aid of various additional masks (not shown). The S / D regions 127 may have a depth D1 below the upper surface, which is significantly smaller than the total depth D2 of the first doped well 106. In some cases, D1 can be at most about one-tenth of the total depth D2 of the first doped well 106 (e.g., D1 is at most about five nanometers (nm) below the upper surface S). The transistor structure 128 can take the form of a field-effect transistor (FET) or a similar device architecture.

[0037] During operation, the gate structure 126 can be used to apply a voltage across the gate dielectric 124 to the first doped well 106, thereby putting the transistor structure 128 into an operational state, for example, allowing charge carriers to flow between the S / D regions 127. Those skilled in the art will understand that the gate structure 126 may include one or more layers, potentially forming a gate stack. According to one example, the gate structure 126 may be formed of doped or undoped polysilicon (poly-Si). In another example, the gate structure 126 may include materials such as, but not limited to, aluminum (Al), zinc (Zn), indium (In), copper (Cu), indium copper (InCu), tin (Sn), tantalum (Ta), tantalum nitride (TaN), tantalum carbide (TaC), titanium (Ti), titanium nitride (TiN), titanium carbide (TiC), tungsten (W), tungsten nitride (WN), tungsten carbide (WC), and / or combinations thereof. Various insulating materials (e.g., spacers) may be included within and / or formed on the sidewalls of the gate structure 126, but for clarity only, such materials are not described. Figure 6 omitted.

[0038] Turn Figure 7 Embodiments of this disclosure may include additional material forming electrical couplings for other structures used in transistor structure 128 and other device structures. At this stage, transistor mask 122 may be removed. Figure 6 And / or any other remaining masking material. Subsequent processing may include forming an interlayer dielectric (ILD) 130 over the substrate 102, transistor structure 128, and other components described herein. The ILD 130 may be formed using other techniques, such as deposition or forming an insulating material on the structure. The ILD 130 may include the same insulating material as TI 104, or it may include a different electrically insulating material. In any case, the ILD 130 and TI 104 constitute different components, for example, because TI 104 is formed within a trench in the substrate 102 rather than on it. Additional metallization layers (not shown) may be formed on the ILD 130 during mid-process and / or back-processing.

[0039] To electrically couple the transistor structure 128 to this metallization layer, a set of S / D contacts 132 can be formed on the S / D region 127 and within the ILD 130. Similarly, gate contacts 134 can be formed on the gate structure 126 and within the ILD 130. Additionally, one or more body contacts 136 can be formed within the ILD 130 to the second portion 110b of the second doped well 110 (e.g., on the resistive region 120 therein). In some cases, substrate contacts 138 can also be formed to the substrate 102, for example, to connect the substrate 102 to ground or a different bias voltage. Contacts 132, 134, 136, and 138 can be formed within a predetermined portion of the ILD 130 by performing a controlled vertical etching to form openings to one or more contact sites, and then filling the openings with a conductor. Contacts 132, 134, 136, and 138 can comprise any known or later-developed conductive material configured for electrical contact, such as copper (Cu), aluminum (Al), gold (Au), etc. Contacts 132, 134, 136, and 138 may additionally include a refractory metal liner (not shown) positioned alongside ILD 130 to prevent electromigration degradation, short circuits with other components, etc. Additionally, selected portions of the second doped well 110, resistive region 120, gate structure 126, and / or S / D region 127 may include silicide regions, i.e., semiconductor portions annealed in the presence of an overlying conductor to increase the conductivity of the semiconductor regions of contacts 132, 134, 136, and 138.

[0040] Embodiments of this disclosure provide an IC structure 140 that can be manufactured by one or more example methods described herein. The IC structure 140 includes two doped wells (a first doped well 106 and a second doped well 110), wherein a body contact 136 operatively biases the first doped well 106 located below a transistor structure 128. The IC structure 140 includes, for example, a substrate 102 and a first doped well 106 of a first doping type within the substrate 102, wherein the substrate 102 and the first doped well 106 each have substantially coplanar top surfaces (e.g., along the top surface S of the substrate 102). The transistor structure 128 is located on the first doped well 106, for example, wherein an S / D region is formed in the first doped well 106 to a first depth D1 below the top surface S. Figure 1 The TI 104 may be located within the first doped well 106 and, in some cases, may be adjacent to the transistor structure 128 in the horizontal direction. In some cases, the TI 104 may have the same depth as the first doped well 106, or may extend below the upper surface S to a depth less than the total depth D2 of the first doped well 106. Figure 6 The depth of such implementation is described elsewhere in this document.

[0041] IC structure 140 may include a second doped well 110 of the opposite doping type to the first doped well 106, located within substrate 102 and below the bottom surface of the first doped well 106 (i.e., below total depth D2). A first portion 110a of the second doped well 110 may be completely below the first doped well 106, while a second portion 110b of the second doped well may be transverse to the first portion 110a, the first doped well 106, and TI 104 (e.g., at sidewall U). The vertical boundary between the first doped well 106 and the second doped well 110 (e.g., at its first portion 110a) may define a first diode junction 142. The first diode junction 142 may be generated by opposite P-type and N-type doping within the doped wells 106, 110, as discussed herein, and / or may be further defined by the location of dopant extension regions 114, 116. The first diode junction 142 allows current to flow in only one direction (e.g., from the first doped wells 106, 110) to allow electrical biasing of the first doped well 106 through the first diode 142. The IC structure 140 may also include a second diode junction 144 located between the substrate 102 and the second doped well 110. The second diode junction 144 is similarly generated by the second doped well 110 having a doping type opposite to that of the substrate 102, and in some cases, a dopant extension region 116 is present. Similar to the first diode junction 142, the second diode junction 144 allows current to flow in only one direction between the substrate 102 and the second doped well 110 to prevent any unwanted electrical signals from the substrate 102 from reaching the transistor structure 128 for stronger biasing of the first doped well 106 through the second doped well 110.

[0042] To electrically bias the body of transistor structure 128 (i.e., the first doped well 106), IC structure 140 may include a body contact 136 to the second doped well 110. The body contact 136 may be coupled directly and / or via a resistive region 120 thereon to a second portion 110b of the second doped well 110. By electrically biasing the first doped well 106 using the second doped well 110, an operator of IC structure 140 can influence the electrical gain and / or linearity of transistor structure 128 during operation. Applying a reverse (i.e., positive voltage) bias to the second doped well 110 via the body contact 136, relative to the case where no body bias is applied to the second doped well 110, can increase the voltage gain (i.e., the ratio of gate voltage to source / drain voltage) of transistor structure 128. Conversely, applying a positive (i.e., negative voltage) bias to the second doped well 110 via the body contact 136 can cause the voltage gain of transistor structure 128 to exhibit a relatively linear curve relative to a changing gate voltage. This behavior differs from transistor structures with a configuration that does not include doped wells 106, 110 and the body contact 136 to the second doped well 110.

[0043] refer to Figure 7 and Figure 8 ,in Figure 7 It shows along Figure 8 The view shown in view line 7-7 is a cross-sectional view of the IC structure 140. Embodiments of the IC structure 140 can be arranged such that the main bias element (e.g., the second doped well 110) and / or the accompanying insulating element (e.g., TI 104) horizontally surround the transistor structure 128. For example, the IC structure 140 may include a ring-shaped TI 104 that horizontally surrounds and thus encloses the transistor structure 128. In this case, some portions of the second doped well 110 may horizontally surround and thus enclose the TI 104. In this case, the second doped well 110 may be substantially cup-shaped (i.e., having a boat-shaped geometry), which is easily identifiable from... Figure 7 Cross-sectional view and Figure 8 As can be seen in the plan view. For further isolation between the second doped well 110 and the substrate 102, another TI 104 can be horizontally surrounded and thus enclose a portion of the second doped well 110. While the TI 104 and the second doped region 110 are in... Figure 8 The figure is shown as having a rectangular outline in the XY plane, but in other embodiments, any conceivable geometry (e.g., a circular outline and / or various polygonal outlines) is possible.

[0044] Another configuration of IC structure 140 is in Figure 9 As shown in the image. (The part about omitting the reference is missing.) Figure 9 Redundancy explanation of the various components of the IC structure 140 shown. Figure 9 The cross-section of the IC structure 140 shown depicts the first doped well 106 extending below the bottom surface C of the TI 104, such that a portion of the first doped well 106 is located vertically between the second doped well 110 and the TI 104. Figure 9 As shown in the configuration, limiting the depth and / or size of TI 104 can increase the physical interface between the first doped well 106 and the second doped well 110, thereby increasing the size of the first diode junction 142 between them. In another case, if the depth of TI 104 is less than the depth of the high-resistance region 120, a junction diode 142A will appear in parallel with the existing first diode 142. The junction diode 142A is formed between the damaged second doped well and the first doped well 106. Such a configuration is desirable, for example, when a stronger bias of the first doped well 106 is required through the second doped well 110 and the body contact 136. In all other respects, IC structure 140 can be constructed similarly or identically to other configurations of IC structure 140 described herein.

[0045] The IC structure 140 is further configured in another way. Figure 10 and Figure 11 As shown in the figure, Figure 11 Provided along Figure 10 The cross-sectional view taken by view line 11-11. (Details omitted.) Figure 10 , Figure 11 Redundancy explanation of various components in the illustrated IC structure 140. In some device configurations (e.g., IC floorplans, which include floorplans with different dopant distributions and / or other design configurations), the second doped well 110 may not horizontally surround TI 104 and / or the first doped well 106. Figure 10 As shown, the second doped well 110 can extend horizontally across TI 104 between the two inner sidewalls K of the substrate 102. In this case, the second portion 110b of the second doped well 110 can be horizontally away from the transistor structure 128 in the IC structure 140. However, as Figure 11 As shown, the first portion 110a can extend horizontally outward from the second portion 110b (e.g., along the X-axis) and lie below the first doped well 106, thereby forming diode junctions 142, 144 at the physical interfaces between the substrate 102, the first doped well 106, and the second doped well 110. In this case, a portion of TI 104 can have a larger horizontal width than in other embodiments of IC structure 140 because there is no additional material for the second doped well 110 at these locations.

[0046] Brief reference Figure 12 and Figure 13 A plan view of an IC structure 140 according to another embodiment is provided. Figure 12 and Figure 13 The additional examples provided are substantially similar to other implementations discussed in this paper (e.g., Figure 10 and Figure 11 The embodiments shown are illustrated, and are discussed as examples to indicate other possible modifications to one or more elements of the IC structure 140. For example, Figure 12 An embodiment is shown in which a second portion 110b of the second doped well 110 extends from left to right along the X-axis between the two inner sidewalls K of the substrate 102. In this case, the second doped well 110 may further include a portion located at the first doped well 106 ( Figures 1 to 7 , Figure 9 , Figure 11 The first part below 110a ( Figures 1 to 7 , Figure 9 , Figure 11 The method is similar to that discussed in this article. Figure 11 The cross-section. In Figure 13In another example shown, the second portion 110b of the second doped well 110 can be formed in an island-shaped region within the TI 104, such that the TI 104 horizontally surrounds the second portion 110b. The island-shaped region can be placed anywhere within the TI 104 (perpendicular, parallel, or diagonally to the gate structure 126). Here, the second doped well 110 does not horizontally adjoin any portion of the substrate 102 (e.g., as shown). Figure 10 and Figure 11 (As shown). However, similar to other embodiments discussed herein, the second doped well 110 may have a first portion 110a extending horizontally below the transistor structure 128 to electrically bias the first doped well 106. (Not considered) Figure 12 and Figure 13 Despite the apparent differences in the plan view shown, IC structure 140 can operate in a manner substantially similar to or identical to other embodiments discussed herein. Furthermore, in such an embodiment, resistive region 120 ( Figures 3 to 7 , Figure 9 , Figure 11 It can still be formed anywhere desired in the second part 110b of the second doped well 110.

[0047] The embodiments disclosed herein can provide several technical and commercial advantages, some of which are discussed herein. The ability to form a floating body (i.e., the first doped well 106) beneath the transistor structure 128 and to have only one other doped region (i.e., the second doped well 110) in the substrate 12 allows embodiments of the IC structure 140 to have adjustable voltage gain and linearity based on whether a forward or reverse bias is applied to the second doped well 110. These characteristics can be valuable in several technical applications. For example, in low-noise amplifier (LNA) or power amplifier (PA) circuits, different transistors in the circuit may require the highest possible voltage gain or linearity during operation to ensure low noise and sufficient amplification. In such applications, embodiments of the IC structure 140 can be used to provide a plurality of transistors, each of which may have different forward or reverse biases to achieve the desired characteristics. Another technical application of the IC structure 140 may include, for example, radio frequency (RF) switches, where highly controllable resistance is required to ensure RF signal isolation. In this case, the presence of the resistor region 120 allows the desired resistance to be integrated relatively easily into the transistor structure while still allowing a forward or reverse voltage bias to be applied to the transistor body during operation.

[0048] The methods described above are used in the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in the form of raw wafers (i.e., as a single wafer with multiple unpackaged chips), as bare dies, or in packages. In the latter case, the chips are mounted in single-chip packages (e.g., plastic carriers with leads attached to a motherboard or other higher-level carriers) or multi-chip packages (e.g., ceramic carriers with surface interconnects and / or buried interconnects). In any case, the chips are then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (e.g., a motherboard) or (b) a final product. The final product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units.

[0049] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It will be further understood that, when used in this specification, the terms “comprising” and / or “including” specify the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. “Optional” or “optionally” indicates that an event or condition subsequently described may or may not occur, and the description includes cases where the event occurs and cases where the event does not occur.

[0050] The approximate language used throughout the specification and claims can be used to modify any quantitative expression that allows for variation without causing a change in its associated essential function. Therefore, values ​​modified by one or more terms such as “about,” “approximate,” and “substantially” are not limited to the specified exact values. In at least some cases, approximate language may correspond to the precision of the instrument used to measure the value. In this document and throughout the specification and claims, range limitations can be combined and / or interchanged, such ranges being identified and including all subranges contained therein, unless the context or language indicates otherwise. The term “approximate” applied to a specific value within a range applies to both values ​​and, unless otherwise dependent on the precision of the instrument used to measure the value, may indicate + / - 10% of said value.

[0051] All the means or steps plus functional elements in the following claims are intended to include any structure, material, action, and equivalent that performs the function in combination with other claimed elements of the specific claim. The present disclosure has been described for purposes of illustration and description, but such description is not intended to be exhaustive or to limit the disclosure to the forms disclosed. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the disclosure. The embodiments were chosen and described in order to best explain the principles and practical application of the disclosure and to enable others skilled in the art to understand the various embodiments of the disclosure with various modifications suitable for the particular intended use.

Claims

1. An integrated circuit (IC) structure, comprising: A first doped well located within a substrate, the first doped well having a first doping type; Transistor structure located on the first doped well; A first dopant extension region located within the first doped well, the first dopant extension region having a higher concentration of the first doping type than the adjacent portion of the first doped well; Trench isolation TI adjacent to a portion of the first doped well; as well as A second doped well located within the substrate and coupled to a body contact, the second doped well having a second doping type opposite to the first doping type, wherein the sidewall of the TI is adjacent to the second doped well in a horizontal direction, the vertical boundary between the second doped well and the first doped well defines a first diode junction, and the vertical boundary between the second doped well and the substrate defines a second diode junction.

2. The IC structure according to claim 1, wherein the second doped well comprises: A resistive region located below the body contact to the second doped well and having a sidewall adjacent to the TI in the horizontal direction; as well as A conductive region located below the resistive region.

3. The IC structure according to claim 1, wherein the adjacent portion of the first doped well is located in the vertical direction between the bottom surface of the TI and the portion of the second doped well below the first doped well.

4. The IC structure of claim 1, wherein the TI surrounds the first doped well in a horizontal direction, and a portion of the second doped well surrounds the TI in a horizontal direction.

5. The IC structure of claim 1, wherein the transistor structure includes a set of source / drain regions located within the first doped well, and wherein the depth of the set of source / drain regions within the first doped well is at most one-tenth of the depth of the first doped well relative to the top surface of the substrate.

6. The IC structure according to claim 1, wherein the first dopant extension region is adjacent to the first diode junction.

7. The IC structure of claim 1, wherein the second doped well includes a second dopant extension region adjacent to the first diode junction, the second dopant extension region having a second doping type with a concentration different from that of the adjacent portion of the second doped well.

8. An integrated circuit (IC) structure, comprising: A first doped well located within a substrate, the first doped well having a first doping type; Transistor structure located on the first doped well; A first dopant extension region located within the first doped well, the first dopant extension region having a higher concentration of the first doping type than the adjacent portion of the first doped well; Trench isolation TI adjacent to a portion of the first doped well; A second doped well located within the substrate, the second doped well having a second doping type opposite to the first doping type, wherein the second doped well comprises: A first portion located below the first doped well, wherein the vertical boundary between the first portion of the second doped well and the first doped well defines a first diode junction, and the vertical boundary between the first portion of the second doped well and the substrate defines a second diode junction; as well as A second portion coupled to the body contact and having a bottom surface substantially coplanar with the bottom surface of the first portion, wherein the second portion includes a sidewall adjacent to the first portion of the second doped well and adjacent to the TI.

9. The IC structure of claim 8, wherein the second portion of the second doped well comprises: A resistive region located below the body contact to the second doped well; as well as A conductive region located below the resistive region.

10. The IC structure of claim 8, wherein the adjacent portion of the first doped well is located in the vertical direction between the bottom surface of the TI and the first portion of the second doped well.

11. The IC structure of claim 8, wherein the TI surrounds the first doped well in a horizontal direction, and the second portion of the second doped well surrounds the TI in a horizontal direction.

12. The IC structure of claim 8, wherein the transistor structure includes a set of source / drain regions located within the first doped well, and wherein the depth of the set of source / drain regions within the first doped well is at most one-tenth of the depth of the first doped well relative to the top surface of the substrate.

13. The IC structure according to claim 8, wherein the first dopant extension region is adjacent to the first diode junction.

14. The IC structure of claim 8, wherein the second doped well includes a second dopant extension region adjacent to the first diode junction, the second dopant extension region having a second doping type with a concentration different from that of the adjacent portion of the second doped well.

15. A method for forming an integrated circuit (IC) structure, the method comprising: A first doped well of the first doping type is formed within the substrate; A first dopant extension region is formed within the first doped well, the first dopant extension region having a higher concentration of the first doping type than the adjacent portion of the first doped well; A trench isolation TI is formed adjacent to the sidewall of the first doped well; A second doped well of a second doping type is formed within the substrate, wherein a vertical boundary between a first portion of the second doped well and the first doped well defines a first diode junction, and a vertical boundary between the first portion of the second doped well and the substrate defines a second diode junction. A transistor structure is formed on the first doped well; as well as A body contact is formed in the second portion of the second doped well.

16. The method of claim 15, further comprising forming a resistive region within the second doped well, wherein the body contact is formed such that the body contact is coupled to the resistive region within the second doped well.

17. The method of claim 15, wherein forming the TI comprises forming the TI circumferentially around the first doped well.

18. The method of claim 15, wherein forming the transistor structure comprises forming a set of source / drain regions within the first doped well to a depth of at most one-tenth the depth of the first doped well relative to the top surface of the substrate.

19. The method of claim 15, further comprising forming a second dopant extension region within the second doped well, the second dopant extension region having a higher concentration of the second doping type than the adjacent portion of the second doped well.

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