Display device

Abstract

A display device includes a display area having a plurality of sub-pixels, a plurality of pad electrodes in a peripheral area outside the display area, a first organic insulating layer including an opening overlapping the plurality of pad electrodes, and an integrated circuit overlapping the plurality of pad electrodes and electrically connected to the plurality of pad electrodes, wherein a distance between an edge of the first organic insulating layer defining the opening and an edge of the integrated circuit is 40 micrometers (μm) or more.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2020-0173682, filed on December 11, 2020, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0003] Aspects of one or more embodiments relate to a display apparatus. BACKGROUND

[0004] Recently, display panels have been used for various purposes. Also, as the thickness and weight of display panels have been reduced, the range of application of display panels has increased.

[0005] As the area occupied by a display area in a display panel increases, elements can be positioned in a relatively narrow peripheral area. When cracks occur according to the arrangement of the elements, the reliability of the display apparatus can be reduced, or display quality deterioration can occur due to the cracks.

[0006] The above information disclosed in this Background section is only for enhancement of understanding of the background of the disclosure, and therefore it can not necessarily constitute the prior art. SUMMARY

[0007] Aspects of one or more embodiments include a display apparatus having relatively improved reliability and relatively improved display quality.

[0008] Additional aspects will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following description, or can be learned by practice of the provided embodiments.

[0009] According to one or more embodiments, a display apparatus includes a display area having a plurality of sub-pixels, a plurality of pad electrodes located in a peripheral area outside the display area, a first organic insulating layer including an opening overlapping the plurality of pad electrodes, and an integrated circuit overlapping the plurality of pad electrodes and electrically connected to the plurality of pad electrodes, wherein a distance between an edge of the first organic insulating layer defining the opening and an edge of the integrated circuit is about 40 µm or more.

[0010] According to some embodiments, the display apparatus can further include a second organic insulating layer located on the first organic insulating layer, wherein the second organic insulating layer extends beyond the edge of the first organic insulating layer to overlap a portion of the integrated circuit.

[0011] According to some embodiments, the second organic insulating layer can include a first portion overlapping the first organic insulating layer, and a second portion extending beyond the edge of the first organic insulating layer to overlap the portion of the integrated circuit, wherein a thickness of the second portion is less than a thickness of the first portion.

[0012] According to some embodiments, the second organic insulating layer can include a connecting portion between the first portion and the second portion, the connecting portion of the second organic insulating layer including a stepped portion, wherein the stepped portion can be located on a top surface of the first organic insulating layer.

[0013] According to some embodiments, the distance can be in a range from about 40 µm to about 80 µm.

[0014] According to some embodiments, the display device can further include a plurality of data lines passing through the display area, and a plurality of connection lines electrically connecting the plurality of data lines to the plurality of pad electrodes.

[0015] According to some embodiments, some of the plurality of connection lines can overlap the opening of the first organic insulating layer.

[0016] According to some embodiments, the display device can further include a touch input layer including a plurality of touch electrodes and a touch insulating layer located in the display area, wherein the touch insulating layer overlaps the second organic insulating layer.

[0017] According to some embodiments, the touch insulating layer can overlap the second portion of the second organic insulating layer.

[0018] According to some embodiments, the touch insulating layer can include at least one of an organic insulating material and an inorganic insulating material.

[0019] According to some embodiments, the plurality of sub-pixels can emit light by using light emitting diodes located on a substrate, wherein a portion of the first organic insulating layer is located between the substrate and the light emitting diodes.

[0020] According to one or more embodiments, a display device includes a display area having a plurality of sub-pixels, a plurality of signal lines in the display area, a plurality of pad electrodes in a peripheral area outside the display area and electrically connected to the plurality of signal lines, a first organic insulating layer including an opening overlapping the plurality of pad electrodes, a second organic insulating layer on the first organic insulating layer, and an integrated circuit overlapping and electrically connected to the plurality of pad electrodes, wherein an edge of the first organic insulating layer defining the opening is outside the integrated circuit to be spaced apart from an edge of the integrated circuit.

[0021] According to some embodiments, a distance between the edge of the first organic insulating layer and the edge of the integrated circuit can be in a range from about 40 μm to about 80 μm.

[0022] According to some embodiments, the second organic insulating layer can extend beyond the edge of the first organic insulating layer to overlap a portion of the integrated circuit.

[0023] According to some embodiments, the second organic insulating layer includes a first portion overlapping the first organic insulating layer and a second portion extending beyond the edge of the first organic insulating layer to overlap a portion of the integrated circuit, wherein a thickness of the second portion is less than a thickness of the first portion.

[0024] According to some embodiments, the second organic insulating layer can include a connection portion between the first portion and the second portion, the connection portion of the second organic insulating layer including a stepped portion, wherein the stepped portion is opposite the edge of the integrated circuit, the edge of the first organic insulating layer being between the stepped portion and the edge of the integrated circuit.

[0025] According to some embodiments, the display device can further include a plurality of connection lines electrically connecting data lines of the display area to the plurality of pad electrodes of the peripheral area, wherein the plurality of connection lines are under the first organic insulating layer.

[0026] According to some embodiments, some of the plurality of connection lines can overlap the opening of the first organic insulating layer.

[0027] According to some embodiments, the plurality of sub-pixels can emit light by using light emitting diodes on a substrate, wherein each of a portion of the first organic insulating layer and a portion of the second organic insulating layer is between the substrate and the light emitting diodes.

[0028] According to some embodiments, the display device can further include a touch input layer including a plurality of touch electrodes and a touch insulating layer positioned in the display area, wherein the touch insulating layer overlaps the first organic insulating layer and the second organic insulating layer.

[0029] Other features and characteristics of embodiments according to the present disclosure will become more apparent from the drawings, the claims, and the detailed description. BRIEF DESCRIPTION OF DRAWINGS

[0030] The above and other aspects, features, and characteristics of certain embodiments will become more apparent from the following description with reference to the drawings, in which:

[0031] Figure 1A and Figure 1B is a perspective view illustrating a display device according to some embodiments;

[0032] Figure 2 is a plan view illustrating a display panel according to some embodiments;

[0033] Figure 3 is an equivalent circuit diagram illustrating a sub-pixel circuit electrically connected to a light emitting diode provided in a display device according to some embodiments;

[0034] Figure 4 is a cross-sectional view illustrating a portion of a display device according to some embodiments;

[0035] Figure 5A is a plan view illustrating an arrangement of a pad electrode and a first organic insulating layer positioned in a peripheral area of a display device according to some embodiments;

[0036] Figure 5B is a plan view illustrating an integrated circuit positioned on a pad electrode of Figure 5A according to some embodiments;

[0037] Figure 6 is an image illustrating stress induced in a display device during bonding of an integrated circuit according to some embodiments;

[0038] Figure 7 is an enlarged plan view illustrating a portion VII of Figure 5B according to some embodiments;

[0039] Figure 8 is a cross-sectional view taken along line A-A' and line B-B' of Figure 7 according to some embodiments; and

[0040] Figure 9 is a cross-sectional view taken along line C-C' of Figure 7 according to some embodiments. DETAILED DESCRIPTION

[0041] Reference will now be made in detail to aspects of some embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. In this regard, the present embodiments can take on a variety of different forms and should not be limited by the description herein. Accordingly, the embodiments are described below, by way of example only, with reference to the accompanying drawings. As used in this document, the terms "and / or" and "at least one of" include any and all combinations of one or more of the associated listed items. Throughout this document, the expression "at least one of a, b, and c," means "a alone, b alone, c alone, a and b together, a and c together, b and c together, all of a, b, and c, or variations thereof."

[0042] As the present disclosure allows various changes and numerous embodiments, specific embodiments will be shown in the drawings and described in detail in the detailed description. Effects and features of the present disclosure and methods for achieving the effects and features of the present disclosure will be clarified with reference to embodiments described below in greater detail with reference to the accompanying drawings. However, the present disclosure is not limited to the following embodiments and the present disclosure can be implemented in various forms.

[0043] Hereinafter, aspects of some embodiments will be described in greater detail with reference to the accompanying drawings, in which like or corresponding elements are denoted by like reference numerals and repetitive description thereof is omitted.

[0044] Although the terms "first", "second", and the like can be used to describe various elements, the elements should not be limited by these terms. The terms are only used to distinguish one element from another.

[0045] As used in this document, the singular forms "a", "an" and "the" include plural references unless the context clearly dictates otherwise.

[0046] It will also be understood that the terms "comprises", "has", and "includes" are intended to mean that there is existence of the described features or elements, and that the possibility of additional features or elements is not excluded.

[0047] It will also be understood that when a layer, region, or component is referred to as being "on" another layer, region, or component, it can be directly on the other layer, region, or component, or intervening layers, regions, or components can be present.

[0048] The size of each element shown in the drawings can be exaggerated or reduced, for convenience in description. For example, since the size and thickness of each element shown in the drawings are arbitrarily shown for convenience in description, the present disclosure is not limited thereto.

[0049] When a specific embodiment can be implemented differently, a specific process sequence can be different from the described sequence. For example, two consecutively described processes can be performed substantially simultaneously, or in an order opposite to the described sequence.

[0050] It will be understood that when a layer, region or element is referred to as being "connected" to another layer, region or element, it can be directly connected to the other layer, region or element or intervening layers, regions or elements can be connected. For example, when a layer, region or element is referred to as being "electrically connected" to another layer, region or element, it can be electrically connected directly to the other layer, region or element, or electrically connected to the other layer, region or element with intervening layers, regions or elements therebetween.

[0051] "A and / or B" is used herein to mean "A or B or both A and B."

[0052] Figure 1A and Figure 1B is a perspective view showing a display device according to some embodiments.

[0053] Referring to Figure 1A and Figure 1B , the display device 1, which is a device for displaying a moving image (e.g., a video image) or a still image (e.g., a static image), can be a portable electronic device such as a mobile phone, a smart phone, a tablet personal computer (PC), a mobile communication terminal, an electronic organizer, an electronic book, a portable multimedia player (PMP), a navigation device, or an ultra-mobile PC (UMPC). Alternatively, the display device 1 can be used as a display screen of any one of various products such as a television, a notebook computer, a monitor, an advertisement board, or an Internet of Things (IoT) device. Also, the display device 1 according to some embodiments can be used in a wearable device such as a smart watch, a watch phone, a glasses-type display, or a head-mounted display (HMD). Also, the display device 1 according to some embodiments can be used as a central information display (CID) positioned on an instrument panel, a center panel, or a cluster of a vehicle, an interior mirror display instead of a side mirror of a vehicle, or a display positioned at the back of a front seat for entertainment of a rear seat of a vehicle. For convenience in description, the display device 1 according to some embodiments is a smart phone in Figure 1A and Figure 1B .

[0054] In a plan view, the display device 1 can have a rectangular shape. For example, the display device 1 can have a rectangular planar shape having a short side in an x direction and a long side in a y direction. The edges at which the short side in the x direction and the long side in the y direction intersect each other can be rounded or curved to have a certain curvature or formed to have a right angle. The planar shape of the display device 1 is not limited to a rectangular shape, and can be any of other shapes such as a polygonal shape, an elliptical shape, or an irregular shape.

[0055] The display device 1 can include a display area DA that displays an image by using light emitted by a sub-pixel and a peripheral area PA outside the display area DA. The display device 1 can be a portable bar type as shown in Figure 1A , or can be a portable folding type as shown in Figure 1B . For example, as shown in Figure 1B , the display device 1 can be foldable about an axis AX intersecting the display area DA.

[0056] Figure 2 is a plan view showing a display panel according to some embodiments.

[0057] Referring to Figure 2 , in the display device 1, a sub-pixel PX positioned in the display area DA can emit red light, green light, and / or blue light by using a light emitting diode positioned at a position corresponding to the sub-pixel PX. Signal lines such as data lines DL and scan lines SL electrically connected to a transistor electrically connected to the light emitting diode and a storage capacitor can be positioned in the display area DA. The data lines DL can extend in the y direction in the display area DA, for example, a plurality of data lines DL can pass through the display area DA, and the scan lines SL can extend in the x direction in the display area DA.

[0058] The peripheral area PA can be positioned outside the display area DA and can completely surround the display area DA.

[0059] The first scan driver 20 and the second scan driver 30 can be positioned in the peripheral area PA and can be electrically connected to the scan lines SL. According to some embodiments, some of the scan lines SL can be electrically connected to the first scan driver 20, and the remaining scan lines SL can be connected to the second scan driver 30. Each of the first scan driver 20 and the second scan driver 30 can generate a scan signal, and the generated scan signal can be transmitted to a transistor electrically connected to the light emitting diode through the scan line SL.

[0060] The first scan driver 20 and the second scan driver 30 can be positioned at both sides of the display area DA. For example, as shown in Figure 2As shown in FIG. 1, the first scan driver 20 can be positioned at the left side of the display area DA, and the second scan driver 30 can be positioned at the right side of the display area DA. According to some embodiments, one of the first scan driver 20 and the second scan driver 30 can be omitted.

[0061] The drive voltage supply line 60 can be positioned in the peripheral area PA. The drive voltage supply line 60 can be positioned between the display area DA and the side of the substrate 100 on which the terminal unit 50 is positioned.

[0062] The common voltage supply line 70 can be positioned in the peripheral area PA, and can have a ring shape with one side of the ring shape extending along the display area DA being open. The common voltage supply line 70 can have a substantially U-shape as shown in FIG. 1. The common voltage supply line 70 can extend along each side of the substrate 100 except for the side on which the terminal unit 50 is positioned, and thus, the first scan driver 20 can be positioned between a portion of the common voltage supply line 70 (e.g., the left side portion in FIG. 1) and the display area DA, and the second scan driver 30 can be positioned between another portion of the common voltage supply line 70 (e.g., the right side portion in FIG. 1) and the display area DA. Figure 2 Figure 2 Figure 2

[0063] The integrated circuit 40 can be positioned in the peripheral area PA. The integrated circuit 40 can be positioned between the display area DA and the side of the substrate 100 on which the terminal unit 50 is positioned. The integrated circuit 40 can include a data driver. The integrated circuit 40 used herein can represent a data driver. The integrated circuit 40 can be electrically connected to the pad electrode positioned below the integrated circuit 40. The data signal generated by the integrated circuit 40 (e.g., the data driver) can be transmitted to the signal line (e.g., the data line DL) positioned in the display area DA through the connection line 1100 positioned in the fan-out area POA. The fan-out area POA, which is a part of the peripheral area PA, is located between the integrated circuit 40 and the display area DA.

[0064] ​​​The terminal unit 50 can include terminals 51, 52, 53, and 54. The terminals 51, 52, 53, and 54 can be exposed without being covered by an insulating layer, and can be electrically connected to a controller SC positioned on a flexible printed circuit board 80. The flexible printed circuit board 80 can include opposite terminals 80T corresponding to the terminal unit 50. The opposite terminals 80T of the flexible printed circuit board 80 can be electrically connected to the terminals 51, 52, 53, and 54. The controller SC can generate control signals for controlling the first and second scan drivers 20 and 30 and the integrated circuit 40, and the generated control signals can be transmitted to the first and second scan drivers 20 and 30 and the integrated circuit 40 through the terminals 51 and 53 (for example, as shown in FIG. 1B). Figure 2 The generated control signals can be transmitted to the integrated circuit 40 through the terminal 51 and to the first and second scan drivers 20 and 30 through the terminal 53, for example, as shown in FIG. 1B). The controller SC can transmit a driving voltage and a common voltage to the driving voltage supply line 60 and the common voltage supply line 70 through the terminals 52 and 54, respectively.

[0065] Figure 3 is an equivalent circuit diagram illustrating a sub-pixel circuit electrically connected to a light emitting diode provided in a display apparatus according to some embodiments.

[0066] As described with reference to Figure 2 , each sub-pixel PX (see Figure 2 ) can emit light by using a light emitting diode LED. The light emitting diode LED can be electrically connected to the sub-pixel circuit PC.

[0067] The sub-pixel circuit PC can include a first thin film transistor T1, a second thin film transistor T2, a third thin film transistor T3, a fourth thin film transistor T4, a fifth thin film transistor T5, a sixth thin film transistor T6, a seventh thin film transistor T7, and a storage capacitor Cst.

[0068] The second thin film transistor T2, which is a switching thin film transistor, can be connected to a scan line SL and a data line DL, and can transmit a data voltage (or a data signal Dm) input from the data line DL to the first thin film transistor T1 based on a switching voltage (or a switching signal Sn) input from the scan line SL. The storage capacitor Cst can be connected to the first thin film transistor T1 and a driving voltage line PL, and can store a voltage corresponding to a difference between a voltage received from the first thin film transistor T1 and a driving voltage ELVDD supplied to the driving voltage line PL.

[0069] The gate electrode of the first thin film transistor T1 as a driving thin film transistor can be connected to a driving voltage line PL and a storage capacitor Cst, and can control a driving current flowing from the driving voltage line PL to the light emitting diode LED in response to a value of a voltage stored in the storage capacitor Cst. The light emitting diode LED can emit light having a certain brightness due to the driving current. A second electrode (e.g., a cathode) of the light emitting diode LED can receive a common voltage ELVSS.

[0070] The gate electrode of the third thin film transistor T3 as a compensation thin film transistor can be connected to a scan line SL. The source electrode (or drain electrode) of the third thin film transistor T3 can be connected to the drain electrode (or source electrode) of the first thin film transistor T1 and can be connected to the first electrode (e.g., anode) of the light emitting diode LED via the sixth thin film transistor T6. The drain electrode (or source electrode) of the third thin film transistor T3 can be connected to one electrode of the storage capacitor Cst, the source electrode (or drain electrode) of the fourth thin film transistor T4, and the gate electrode of the first thin film transistor T1. The third thin film transistor T3 can be turned on according to a scan signal Sn received through the scan line SL, and can diode-connect the first thin film transistor T1 by connecting the gate electrode of the first thin film transistor T1 to the drain electrode of the first thin film transistor T1.

[0071] The gate electrode of the fourth thin film transistor T4 as an initialization thin film transistor can be connected to a previous scan line SL-1. The drain electrode (or source electrode) of the fourth thin film transistor T4 can be connected to an initialization voltage line VL. The source electrode (or drain electrode) of the fourth thin film transistor T4 can be connected to one electrode of the storage capacitor Cst, the drain electrode (or source electrode) of the third thin film transistor T3, and the gate electrode of the first thin film transistor T1. The fourth thin film transistor T4 can be turned on according to a previous scan signal Sn-1 received through the previous scan line SL-1, and can perform an initialization operation of initializing a voltage of the gate electrode of the first thin film transistor T1 by supplying an initialization voltage Vint to the gate electrode of the first thin film transistor T1.

[0072] The gate electrode of the fifth thin film transistor T5 as an operation control thin film transistor can be connected to an emission control line EL. The source electrode (or drain electrode) of the fifth thin film transistor T5 can be connected to the driving voltage line PL. The drain electrode (or source electrode) of the fifth thin film transistor T5 is connected to the source electrode (or drain electrode) of the first thin film transistor T1 and the drain electrode (or source electrode) of the second thin film transistor T2.

[0073] The gate electrode of the sixth thin-film transistor T6, which is a emission control thin-film transistor, can be connected to an emission control line EL. The source electrode (or drain electrode) of the sixth thin-film transistor T6 can be connected to the drain electrode (or source electrode) of the first thin-film transistor T1 and the source electrode (or drain electrode) of the third thin-film transistor T3. The drain electrode (or source electrode) of the sixth thin-film transistor T6 can be electrically connected to the first electrode of the light-emitting diode LED. The fifth thin-film transistor T5 and the sixth thin-film transistor T6 can be simultaneously turned on according to an emission control signal En received through the emission control line EL, and thus, a driving voltage ELVDD is supplied to the light-emitting diode LED, and a driving current flows through the light-emitting diode LED.

[0074] The seventh thin-film transistor T7 can be an initialization thin-film transistor for initializing the first electrode of the light-emitting diode LED. The gate electrode of the seventh thin-film transistor T7 can be connected to a next scan line SL+1. The source electrode (or drain electrode) of the seventh thin-film transistor T7 can be connected to the first electrode of the light-emitting diode LED. The drain electrode (or source electrode) of the seventh thin-film transistor T7 can be connected to an initialization voltage line VL. The seventh thin-film transistor T7 can be turned on according to a next scan signal Sn+1 received through the next scan line SL+1, and can initialize the first electrode of the light-emitting diode LED.

[0075] Although in Figure 3 , the fourth thin-film transistor T4 and the seventh thin-film transistor T7 are connected to the previous scan line SL-1 and the next scan line SL+1, respectively, according to some embodiments, the fourth thin-film transistor T4 and the seventh thin-film transistor T7 can both be connected to the previous scan line SL-1, and can be driven according to the previous scan signal Sn-1.

[0076] The other electrode of the storage capacitor Cst can be connected to a driving voltage line PL. One electrode of the storage capacitor Cst can be connected to the gate electrode of the first thin-film transistor T1, the drain electrode (or source electrode) of the third thin-film transistor T3, and the source electrode (or drain electrode) of the fourth thin-film transistor T4.

[0077] The second electrode (for example, cathode) of the light-emitting diode LED receives a common voltage ELVSS. The light-emitting diode LED receives a driving current from the first thin-film transistor T1 and emits light.

[0078] The light emitting diode LED can be an organic light emitting diode including an organic material as a light emitting material. According to some embodiments, the light emitting diode can be an inorganic light emitting diode including an inorganic material. The inorganic light emitting diode can include a PN junction diode including an inorganic semiconductor-based material. When a voltage is applied to the PN junction diode in a forward direction, holes and electrons can be injected, and energy generated by recombination of the holes and the electrons can be converted into light energy to emit light of a specific color. The inorganic light emitting diode can have a width of several micrometers to several hundred micrometers or several nanometers to several hundred nanometers. In some embodiments, the light emitting diode LED can include a quantum dot light emitting diode. As described above, the emission layer of the light emitting diode LED can include an organic material, can include an inorganic material, can include a quantum dot, can include an organic material and a quantum dot, or can include an inorganic material and a quantum dot. For ease of description, the following will be described assuming that the light emitting diode LED includes an organic light emitting diode.

[0079] Figure 4 FIG. 1 is a cross-sectional view showing a portion of a display device according to some embodiments.

[0080] Figure 4 A sub-pixel circuit PC and a light emitting diode (e.g., an organic light emitting diode OLED) positioned in a display area DA of the display device 1 are shown.

[0081] The substrate 100 can include a glass material or a polymer resin. According to some embodiments, the substrate 100 can have a structure in which base layers including a polymer resin and barrier layers including an inorganic insulating material such as silicon oxide or silicon nitride are alternately stacked. When the substrate 100 has a structure in which base layers including a polymer resin and barrier layers including an inorganic insulating material are stacked as described above, the flexibility of the display device 1 can be improved as described with reference to FIGS. 1A and 1B, and thus the display device 1 can be foldable. Figure 1B

[0082] Examples of the polymer resin can include polyether sulfone, polyarylate, polyether imide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate.

[0083] The sub-pixel circuit PC can be formed on the substrate 100, and the light emitting diode (e.g., the organic light emitting diode OLED) can be formed on the sub-pixel circuit PC.

[0084] ​Before the sub-pixel circuit PC is formed on the substrate 100, a buffer layer 201 can be formed on the substrate 100 to prevent or reduce the case in which impurities penetrate into the sub-pixel circuit PC. The buffer layer 201 can include an inorganic insulating material such as silicon nitride, silicon oxynitride, or silicon oxide, and can have a single-layer or multi-layer structure including the above inorganic insulating material.

[0085] As described with reference to FIGS. 1A and 1B, the sub-pixel circuit PC can include a plurality of transistors and a storage capacitor. Figure 3 As described with reference to FIGS. 1A and 1B, the sub-pixel circuit PC can include a plurality of transistors and a storage capacitor. Figure 4 The first thin film transistor T1, the third thin film transistor T3, and the storage capacitor Cst are shown.

[0086] The first thin film transistor T1 can include a semiconductor layer (hereinafter, referred to as a first semiconductor layer A1) on the buffer layer 201 and a gate electrode (hereinafter, referred to as a first gate electrode GE1) overlapping a channel region C1 of the first semiconductor layer A1. The first semiconductor layer A1 can include a silicon-based semiconductor material, for example, polysilicon. The first semiconductor layer A1 can include the channel region C1 and a first region B1 and a second region D1 positioned on both sides of the channel region C1. The first region B1 and the second region D1 are regions having a higher impurity concentration than the channel region C1, and one of the first region B1 and the second region D1 can correspond to a source region, and the other can correspond to a drain region.

[0087] The first gate insulating layer 203 can be positioned between the first semiconductor layer A1 and the first gate electrode GE1. The first gate insulating layer 203 can include an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride, and can have a single-layer or multi-layer structure including the above inorganic insulating material.

[0088] The first gate electrode GE1 can include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and can have a single-layer or multi-layer structure including the above material.

[0089] The storage capacitor Cst can include a lower electrode CE1 and an upper electrode CE2 overlapping each other. According to some embodiments, the lower electrode CE1 of the storage capacitor Cst can include the first gate electrode GE1. In other words, the first gate electrode GE1 can include the lower electrode CE1 of the storage capacitor Cst. For example, the first gate electrode GE1 and the lower electrode CE1 of the storage capacitor Cst can be integrally formed with each other.

[0090] The first interlayer insulating layer 205 can be positioned between the lower electrode CE1 and the upper electrode CE2 of the storage capacitor Cst. The first interlayer insulating layer 205 can include an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride, and can have a single-layer or multi-layer structure including the above inorganic insulating material.

[0091] The upper electrode CE2 of the storage capacitor Cst can include a low-resistance conductive material such as molybdenum (Mo), aluminum (Al), copper (Cu), and / or titanium (Ti), and can have a single-layer or multi-layer structure including the above material.

[0092] The second interlayer insulating layer 207 can be positioned on the storage capacitor Cst (e.g., the upper electrode CE2 of the storage capacitor Cst). The second interlayer insulating layer 207 can include an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride, and can have a single-layer or multi-layer structure including the above inorganic insulating material.

[0093] The semiconductor layer (hereinafter, referred to as a third semiconductor layer A3) of the third thin film transistor T3 can be positioned on the second interlayer insulating layer 207. The third semiconductor layer A3 can include an oxide-based semiconductor material. For example, the third semiconductor layer A3 can be formed of a zinc-oxide-based material such as zinc oxide, indium zinc oxide, or indium gallium zinc oxide. In some embodiments, the third semiconductor layer A3 can be formed of an indium gallium zinc oxide (IGZO) semiconductor, an indium tin zinc oxide (ITZO) semiconductor, or an indium gallium tin zinc oxide (IGTZO) semiconductor including a metal such as indium (In), gallium (Ga), or tin (Sn) in ZnO.

[0094] The third semiconductor layer A3 can include a channel region C3 and first and second regions B3 and D3 positioned on both sides of the channel region C3. One of the first and second regions B3 and D3 can correspond to a source region, and the other can correspond to a drain region.

[0095] The third thin film transistor T3 can include a gate electrode (hereinafter, referred to as a third gate electrode GE3) overlapping the channel region C3 of the third semiconductor layer A3. The third gate electrode GE3 can have a dual gate structure including a lower gate electrode G3A positioned below the third semiconductor layer A3 and an upper gate electrode G3B positioned above the channel region C3.

[0096] The lower gate electrode G3A can be positioned on the same layer (e.g., the first interlayer insulating layer 205) as the upper electrode CE2 of the storage capacitor Cst. The lower gate electrode G3A can include the same material as that of the upper electrode CE2 of the storage capacitor Cst.

[0097] The upper gate electrode G3B can be positioned above the third semiconductor layer A3, with a second gate insulating layer 209 interposed between the upper gate electrode G3B and the third semiconductor layer A3. The second gate insulating layer 209 can include an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride, and can have a single-layer or multi-layer structure including the above inorganic insulating material.

[0098] A third interlayer insulating layer 210 can be positioned on the upper gate electrode G3B. The third interlayer insulating layer 210 can include an inorganic insulating material such as silicon oxynitride, and can have a single-layer or multi-layer structure including the above inorganic insulating material.

[0099] Although the first thin film transistor T1 and the third thin film transistor T3 among the plurality of thin film transistors described with reference to Figure 3 are illustrated, and the first semiconductor layer A1 and the third semiconductor layer A3 are positioned on different layers in Figure 4 , the present disclosure is not limited thereto.

[0100] The second thin film transistor T2, the fifth thin film transistor T5, the sixth thin film transistor T6, and the seventh thin film transistor T7 described with reference to Figure 3 (see Figure 3 ) can each have the same structure as that of the first thin film transistor T1 described with reference to Figure 4 . For example, each of the second thin film transistor T2, the fifth thin film transistor T5, the sixth thin film transistor T6, and the seventh thin film transistor T7 (see Figure 3 ) can include a semiconductor layer positioned on the same layer as the first semiconductor layer A1 of the first thin film transistor T1 and a gate electrode formed on the same layer as the first gate electrode GE1 of the first thin film transistor T1. The semiconductor layer of the second thin film transistor T2, the fifth thin film transistor T5, the sixth thin film transistor T6, and the seventh thin film transistor T7 (see Figure 3 ) can be integrally connected to the first semiconductor layer A1.

[0101] The fourth thin film transistor T4 described with reference to Figure 3 (see Figure 3 ) can have the same structure as that of the third thin film transistor T3 described with reference to Figure 4 . For example, the fourth thin film transistor T4 can include a semiconductor layer positioned on the same layer as the third semiconductor layer A3 of the third thin film transistor T3 and a gate electrode formed on the same layer as the third gate electrode GE3 of the third thin film transistor T3. The semiconductor layer of the fourth thin film transistor T4 and the third semiconductor layer A3 of the third thin film transistor T3 can be integrally connected to each other.

[0102] The first thin-film transistor T1 and the third thin-film transistor T3 can be electrically connected to each other through a node connection line 166. The node connection line 166 can be positioned on the third interlayer insulating layer 210. One side of the node connection line 166 can be connected (e.g., via a via hole) to the first gate electrode GE1 of the first thin-film transistor T1, and the other side of the node connection line 166 can be connected (e.g., via a via hole) to the third semiconductor layer A3 of the third thin-film transistor T3.

[0103] The node connection line 166 can include aluminum (Al), copper (Cu), and / or titanium (Ti), and can have a single-layer or multi-layer structure including the above materials. For example, the node connection line 166 can have a three-layer structure including a titanium layer, an aluminum layer, and a titanium layer.

[0104] The first organic insulating layer 211 can be positioned on the node connection line 166. The first organic insulating layer 211 can include an organic insulating material. The organic insulating material can include Akril, benzocyclobutene (BCB), polyimide, or hexamethyldisiloxane (HMDSO).

[0105] The data line DL and the driving voltage line PL can be positioned on the first organic insulating layer 211, and can be covered by the second organic insulating layer 213. Each of the data line DL and the driving voltage line PL can include aluminum (Al), copper (Cu), and / or titanium (Ti), and can have a single-layer or multi-layer structure including the above materials. For example, each of the data line DL and the driving voltage line PL can have a three-layer structure including a titanium layer, an aluminum layer, and a titanium layer.

[0106] The second organic insulating layer 213 can include an organic insulating material such as Akril, BCB, polyimide, and / or HMDSO. Although in Figure 4 In the above embodiment, the data line DL and the driving voltage line PL are formed on the first organic insulating layer 211, but the present disclosure is not limited thereto. According to some embodiments, one of the data line DL and the driving voltage line PL can be positioned on the same layer (e.g., the third interlayer insulating layer 210) as the node connection line 166.

[0107] Light emitting diodes (e.g., organic light emitting diodes OLEDs) can be positioned on the second organic insulating layer 213.

[0108] The first electrode 221 of the organic light emitting diode (OLED) can include a reflective film including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compound thereof. According to some embodiments, the first electrode 221 can further include a conductive oxide layer positioned above and / or below the reflective film. The conductive oxide layer can include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and / or aluminum zinc oxide (AZO). According to some embodiments, the first electrode 221 can have a three-layer structure including an ITO layer, an Ag layer, and an ITO layer.

[0109] A bank layer 215 can be positioned on the first electrode 221. The bank layer 215 can have an opening overlapping the first electrode 221 and can cover edges of the first electrode 221. The bank layer 215 can include an organic insulating material such as polyimide.

[0110] The intermediate layer 222 includes an emission layer 222b. The intermediate layer 222 can include a first functional layer 222a positioned below the emission layer 222b and / or a second functional layer 222c positioned above the emission layer 222b. The emission layer 222b can include a high molecular weight organic material or a low molecular weight organic material that emits light of a specific color. The second functional layer 222c can include an electron transport layer (ETL) and / or an electron injection layer (EIL). Each of the first functional layer 222a and the second functional layer 222c can include an organic material.

[0111] The second electrode 223 can be formed of a conductive material having a low work function. For example, the second electrode 223 can include a (semi-)transparent layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or an alloy thereof. Alternatively, the second electrode 223 can further include a layer formed of ITO, IZO, ZnO, or In2O3 positioned on the (semi-)transparent layer including the above materials.

[0112] The emission layer 222b can be formed in the display area DA to overlap the first electrode 221 through the opening of the bank layer 215. In contrast, the first functional layer 222a, the second functional layer 222c, and the second electrode 223 can completely cover the display area DA.

[0113] A spacer 217 can be formed on the bank layer 215. The spacer 217 and the bank layer 215 can be formed together in the same process, or can be formed separately in separate processes. According to some embodiments, the spacer 217 can include an organic insulating material such as polyimide. Alternatively, the bank layer 215 can include an organic insulating material including a light-shielding dye, and the spacer 217 can include an organic insulating material such as polyimide.

[0114] The organic light emitting diode OLED can be covered by an encapsulation layer 300. The encapsulation layer 300 can include at least one organic encapsulation layer and at least one inorganic encapsulation layer. According to some embodiments, in FIG. Figure 4 The encapsulation layer 300 includes a first inorganic encapsulation layer 310 and a second inorganic encapsulation layer 330, and an organic encapsulation layer 320 positioned between the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330.

[0115] Each of the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 can include at least one inorganic material among aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride. Each of the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 can have a single layer or a multi-layer structure including the above materials. The organic encapsulation layer 320 can include a polymer-based material. Examples of the polymer-based material can include acrylic resin, epoxy resin, polyimide, and polyethylene. According to some embodiments, the organic encapsulation layer 320 can include an acrylate polymer.

[0116] The thicknesses of the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 can be different from each other. The thickness of the first inorganic encapsulation layer 310 can be greater than the thickness of the second inorganic encapsulation layer 330. Alternatively, the thickness of the second inorganic encapsulation layer 330 can be greater than the thickness of the first inorganic encapsulation layer 310, or the thicknesses of the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 can be the same.

[0117] An input sensing layer 400 can be positioned on the encapsulation layer 300. The input sensing layer (may also be referred to as a "touch input layer") 400 can include a plurality of touch electrodes TE positioned in the display area DA and at least one touch insulating layer. In this regard, in FIG. Figure 4 The input sensing layer 400 includes a first touch insulating layer 410 on the second inorganic encapsulation layer 330, a first conductive line 420 on the first touch insulating layer 410, a second touch insulating layer 430 on the first conductive line 420, a second conductive line 440 on the second touch insulating layer 430, and a third touch insulating layer 450 on the second conductive line 440. As Figure 4As illustrated in FIG. 10, at least one touch insulating layer (e.g., the first touch insulating layer 410, the second touch insulating layer 430, and the third touch insulating layer 450) can overlap the second organic insulating layer 213.

[0118] Each of the first touch insulating layer 410, the second touch insulating layer 430, and the third touch insulating layer 450 can include an inorganic insulating material and / or an organic insulating material. For example, at least one touch insulating layer (e.g., the first touch insulating layer 410, the second touch insulating layer 430, and the third touch insulating layer 450) can include at least one of an organic insulating material and an inorganic insulating material. According to some embodiments, each of the first touch insulating layer 410 and the second touch insulating layer 430 can include an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride, and the third touch insulating layer 450 can include an organic insulating material.

[0119] Each of the touch electrodes TE of the input sensing layer 400 can have a structure in which the first conductive lines 420 and the second conductive lines 440 are connected to each other. Alternatively, the touch electrode TE can include one of the first conductive lines 420 and the second conductive lines 440, and in this case, the second touch insulating layer 430 can be omitted.

[0120] Each of the first conductive lines 420 and the second conductive lines 440 can include aluminum (Al), copper (Cu), and / or titanium (Ti), and can have a single-layer or multi-layer structure including the above materials. For example, each of the first conductive lines 420 and the second conductive lines 440 can have a three-layer structure including a titanium layer, an aluminum layer, and a titanium layer.

[0121] Figure 5A is a plan view illustrating an arrangement of a pad electrode and a first organic insulating layer positioned in a peripheral area of a display device according to some embodiments. Figure 5B is a plan view illustrating an arrangement of a pad electrode and a first organic insulating layer positioned in a peripheral area of a display device according to some embodiments. Figure 5A is a plan view illustrating an integrated circuit positioned on the pad electrode of Figure 6 is an image illustrating stress induced in a display device during bonding of an integrated circuit.

[0122] Referring to Figure 5A , the pad electrode 1200 is positioned between a side of the substrate 100 on which the terminal unit 50 is positioned and the display area DA. The pad electrode 1200 can be arranged in a row in the x direction. According to some embodiments, although the pad electrode 1200 is arranged in two rows in Figure 5A , the present disclosure is not limited thereto. According to some embodiments, the pad electrode 1200 can be arranged in three or more rows.

[0123] Each of the pad electrodes 1200 can extend in the oblique direction ob to have an acute angle with respect to the x direction and the y direction. In some embodiments, the pad electrodes 1200 can have a substantially parallelogramic planar shape. Some of the pad electrodes 1200 can be electrically connected to signal lines (e.g., data lines DL) positioned in the display area DA through the connection lines 1100. The connection lines 1100 and the data lines DL can be connected to each other through contact holes CNT formed in at least one insulating layer positioned between the connection lines 1100 and the data lines DL. Other of the pad electrodes 1200 can be electrically connected to terminals of the terminal unit 50 through the external connection lines 1300.

[0124] Referring to Figure 4 The first organic insulating layer 211 described can be positioned not only in the display area DA but also in the peripheral area PA. The first organic insulating layer 211 can have an opening 211OP to electrically connect the pad electrodes 1200 to the integrated circuit 40 (see Figure 5B ), which are exposed through the opening 211OP. The opening 211OP overlaps the pad electrodes 1200.

[0125] The opening 211OP can have a shape corresponding to a shape of the integrated circuit 40 described below with reference to Figure 5B . Referring to Figure 5A and Figure 5B , for example, the integrated circuit 40 can have a substantially quadrangular planar shape, and the opening 211OP can also have a substantially quadrangular planar shape. First, second, third, and fourth edges 211E1, 211E2, 211E3, and 211E4 of the first organic insulating layer 211 defining the opening 211OP can be positioned adjacent to first, second, third, and fourth edges 40E1, 40E2, 40E3, and 40E4 of the integrated circuit 40, respectively.

[0126] Referring to Figure 5B , the integrated circuit 40 can overlap the pad electrodes 1200. The integrated circuit 40 can be electrically connected to the pad electrodes 1200 through a conductive adhesive layer such as an anisotropic conductive film.

[0127] In a plan view, the integrated circuit 40 can be positioned within the opening 211OP of the first organic insulating layer 211. In a plan view, first, second, third, and fourth edges 211E1, 211E2, 211E3, and 211E4 of the first organic insulating layer 211 defining the opening 211OP can be positioned outside first, second, third, and fourth edges 40E1, 40E2, 40E3, and 40E4 of the integrated circuit 40, respectively.

[0128] The first edge 211E1, the second edge 211E2, the third edge 211E3, and the fourth edge 211E4 of the first organic insulating layer 211 are spaced apart from the first edge 40E1, the second edge 40E2, the third edge 40E3, and the fourth edge 40E4 of the integrated circuit 40, respectively. Each of the first distance d1, the second distance d2, the third distance d3, and the fourth distance d4 between the first edge 40E1, the second edge 40E2, the third edge 40E3, and the fourth edge 40E4 of the integrated circuit 40 and the first edge 211E1, the second edge 211E2, the third edge 211E3, and the fourth edge 211E4 of the first organic insulating layer 211 can be about 40 pm or more.

[0129] During the bonding of the integrated circuit 40, stress can be concentrated on and around the first edge 211E1, the second edge 211E2, the third edge 211E3, and the fourth edge 211E4 of the first organic insulating layer 211. Figure 6 The stress generated away from the first edge 40E1 of the integrated circuit 40 is shown, indicating that the darker the color, the greater the stress. In Figure 6 In the middle, stress is concentrated on the "SA" area, and the "SA" area corresponds to a portion of the structure LSR positioned below the integrated circuit 40. The structure LSR located below the integrated circuit 40 can include the substrate 100 (see Figure 5A ) and elements and layers located between the substrate 100 and the integrated circuit 40. As described in Figure 5A and Figure 5B , the insulating layer, the connection line 1100, and the pad electrode 1200 can be provided between the substrate 100 and the integrated circuit 40.

[0130] Because the distances d1, d2, d3, and d4 between the first edge 211E1, the second edge 211E2, the third edge 211E3, and the fourth edge 211E4 of the first organic insulating layer 211 and the first edge 40E1, the second edge 40E2, the third edge 40E3, and the fourth edge 40E4 of the integrated circuit 40 are approximately 40 µm or more, the first edge 211E1, the second edge 211E2, the third edge 211E3, and the fourth edge 211E4 of the first organic insulating layer 211 can not be positioned in the “SA” area, and thus, stress caused on and around the edges of the first organic insulating layer 211 can be effectively distributed. When each of the first distance d1, the second distance d2, the third distance d3, and the fourth distance d4 is less than 40 µm, in other words, when the first edge 211E1, the second edge 211E2, the third edge 211E3, and the fourth edge 211E4 of the first organic insulating layer 211 and the first edge 40E1, the second edge 40E2, the third edge 40E3, and the fourth edge 40E4 of the integrated circuit 40 are spaced apart from each other to have a distance less than 40 µm, stress can be concentrated on the first edge 211E1, the second edge 211E2, the third edge 211E3, and the fourth edge 211E4 of the first organic insulating layer 211. In this case, a crack can occur around the integrated circuit 40, and when the crack can propagate to a bonding portion of the integrated circuit 40, the bonding quality of the integrated circuit 40 can be deteriorated, or a driving malfunction of the integrated circuit 40 (e.g., a data driver) can be caused.

[0131] In some embodiments, each of the first distance d1, the second distance d2, the third distance d3, and the fourth distance d4 can be in a range from approximately 40 µm to approximately 80 µm. For example, each of the second distance d2 and the fourth distance d4 in a range from approximately 40 µm to approximately 80 µm can be appropriate. Each of the second distance d2 and the fourth distance d4 is approximately 40 µm or more in consideration of stress, and each of the second distance d2 and the fourth distance d4 does not exceed approximately 80 µm in consideration of the overlapping structure between the first organic insulating layer 211 and the connection line 1100 or the external connection line 1300 positioned in the fan-out area POA, which can be appropriate.

[0132] When each of the second distance d2 and the fourth distance d4 is greater than about 80 pm, in other words, when the second edge 211E2 and the fourth edge 211E4 of the first organic insulating layer 211 are spaced apart from the second edge 40E2 and the fourth edge 40E4 of the integrated circuit 40 to have a distance greater than 80 pm, the area of the portion of each of the connection line 1100 and the external connection line 1300 that does not overlap the first organic insulating layer 211 can increase, and in this case, the quality of the connection line 1100 and the external connection line 1300 and their surroundings can deteriorate. Each of the first distance d1 and the third distance d3 can be about 80 pm or less, as with the second distance d2 and the fourth distance d4.

[0133] The first distance d1, the second distance d2, the third distance d3, and the fourth distance d4 can be selected within the above ranges, and can have the same value. For example, the first edge 211E1, the second edge 211E2, the third edge 211E3, and the fourth edge 211E4 of the first organic insulating layer 211 can be spaced apart from the first edge 40E1, the second edge 40E2, the third edge 40E3, and the fourth edge 40E4 of the integrated circuit 40 to have the same distance (e.g., d1 = d2 = d3 = d4). According to some embodiments, two or more selected from the first distance d1, the second distance d2, the third distance d3, and the fourth distance d4 can be different. For example, at least one distance among the first distance d1, the second distance d2, the third distance d3, and the fourth distance d4 can be different from the other distances among the first distance d1, the second distance d2, the third distance d3, and the fourth distance d4.

[0134] Figure 7 is an enlarged plan view showing a portion VII of Figure 5B . Figure 8 is a cross-sectional view taken along lines A-A' and B-B' of Figure 7 . Figure 9 is a cross-sectional view taken along line C-C' of Figure 7 .

[0135] Referring to Figure 7 , the integrated circuit 40 overlaps the pad electrode 1200 positioned in the opening 211OP of the first organic insulating layer 211. The opening 211OP of the first organic insulating layer 211 is defined by the edges of the first organic insulating layer 211 described with reference to Figure 5A , and Figure 7 the first edge 211E1 and the second edge 211E2 of the first organic insulating layer 211 are shown.

[0136] As described above, some of the pad electrodes 1200 can be connected to the connection line 1100, and the connection line 1100 can extend away from the integrated circuit 40 toward the display area.

[0137] Reference along Figure 7 The cross-sectional view of line A-A' (i.e.) Figure 8 The first distance d1 between the first edge 211E1 of the first organic insulating layer 211 and the first edge 40E1 of the integrated circuit 40 can be about 40 μm or more as described above, and according to some embodiments, the first distance d1 can be in the range of about 40 μm to about 80 μm.

[0138] An inorganic insulating layer located on substrate 100 can be positioned below the first organic insulating layer 211. According to some embodiments, in... Figure 8 In this configuration, the buffer layer 201, the first gate insulating layer 203, the first interlayer insulating layer 205, the second interlayer insulating layer 207, the second gate insulating layer 209, and the third interlayer insulating layer 210 can be positioned between the substrate 100 and the first organic insulating layer 211.

[0139] The second organic insulating layer 213 can be positioned on the first organic insulating layer 211 and can extend beyond the edge of the first organic insulating layer 211 to reach the integrated circuit 40. In this respect, Figure 8 In the process, the second organic insulating layer 213 extends beyond the first edge 211E1 of the first organic insulating layer 211 to reach the integrated circuit 40, and therefore, the first edge 213E1 of the second organic insulating layer 213 is closer to the integrated circuit 40 than the first edge 211E1 of the first organic insulating layer 211.

[0140] The second organic insulating layer 213 may include portions with different thicknesses. For example, the second organic insulating layer 213 may include a first portion 213A overlapping the first organic insulating layer 211 and an edge extending beyond the first organic insulating layer 211 (e.g., Figure 8 The first edge 211E1) of the first part reaches the second part 213B of the integrated circuit 40. The second part 213B is integrally formed with the first part 213A.

[0141] The second thickness t2 of the second portion 213B can be less than the first thickness t1 of the first portion 213A, and the stepped portion ST can be formed on the connection between the first portion 213A and the second portion 213B. The second organic insulating layer 213 can be formed using a halftone mask. The stepped portion ST can be positioned on the top surface of the first organic insulating layer 211.

[0142] The first thickness t1 of the first portion 213A of the second organic insulating layer 213 can be selected in the range of approximately 10,000 angstroms to approximately 20,000 angstroms. When the second portion 213B has the same thickness as the first portion 213A, such as along... Figure 7 The cross-sectional view taken by line B-B' (i.e. Figure 8 As shown in the diagram, the vertical gap between the pad electrode 1200 and the integrated circuit 40 may increase, and in this case, the electrical connection between the pad electrode 1200 and the integrated circuit 40 using the conductive ball 810 may fail. However, according to some embodiments, because the second thickness t2 of the second portion 213B is less than the first thickness t1 of the first portion 213A, the above problems can be prevented or reduced.

[0143] The stepped portion ST between the first portion 213A and the second portion 213B is positioned opposite the edge of the integrated circuit 40 (e.g., as shown in the image). Figure 8 As shown, opposite to the first edge 40E1 of the integrated circuit 40 or opposite to the side surface 40IS of the integrated circuit 40, the edge of the first organic insulating layer 211 is located between the stepped portion ST and the edge of the integrated circuit 40. For example, as Figure 8 As shown, the first edge 211E1 of the first organic insulating layer 211 can be positioned between the stepped portion ST and the integrated circuit 40. The distance d5 between the stepped portion ST and the first edge 211E1 of the first organic insulating layer 211 can be equal to or similar to the first distance d1. When the distance d5 between the stepped portion ST and the first edge 211E1 of the first organic insulating layer 211 is similar to the first distance d1, this can refer to the distance d5 being in the range of approximately 50% to approximately 150% of the first distance d1. The distance d5 between the stepped portion ST and the first edge 211E1 of the first organic insulating layer 211 can correspond to the distance between the first portion 213A of the second organic insulating layer 213 and the first edge 211E1 of the first organic insulating layer 211. Because the stepped portion ST between the first portion 213A and the second portion 213B can also be a portion on which stress may be concentrated, it may be appropriate to space the stepped portion ST from the integrated circuit 40. In this respect, Figure 8 In the middle, the step portion ST is positioned further away from the integrated circuit 40 than the first edge 211E1 of the first organic insulating layer 211.

[0144] The second organic insulating layer 213 may partially overlap with the integrated circuit 40. For example, a second portion 213B of the second organic insulating layer 213 may overlap with the integrated circuit 40 to form a first overlapping region OL1. The width of the first overlapping region OL1 may be less than the first distance d1. For example, the width of the first overlapping region OL1 may be approximately 10 μm.

[0145] Referring to Figure 4 At least one of the touch insulating layers of the input sensing layer 400 (see Figure 4 ) can overlap the first organic insulating layer 211. According to some embodiments, in Figure 8 , the first touch insulating layer 410, the second touch insulating layer 430, and the third touch insulating layer 450 of the input sensing layer 400 (see Figure 4 ) overlap the first organic insulating layer 211 and the second organic insulating layer 213.

[0146] The first touch insulating layer 410, the second touch insulating layer 430, and the third touch insulating layer 450 can be positioned on the second organic insulating layer 213. As with the second organic insulating layer 213, each of the first touch insulating layer 410, the second touch insulating layer 430, and the third touch insulating layer 450 can extend beyond the edge of the first organic insulating layer 211 to the integrated circuit 40. For example, as shown in Figure 8 , the edges of the first touch insulating layer 410, the second touch insulating layer 430, and the third touch insulating layer 450 can be positioned on the second portion 213B of the second organic insulating layer 213 and can overlap the second portion 213B.

[0147] Although all of the first touch insulating layer 410, the second touch insulating layer 430, and the third touch insulating layer 450 are shown in Figure 8 , according to some embodiments, one or two of the first touch insulating layer 410, the second touch insulating layer 430, and the third touch insulating layer 450 can be omitted.

[0148] Referring to a cross-sectional view taken along line B-B' of Figure 7 , i.e., Figure 8 , the pad electrode 1200 positioned on the substrate 100 can be electrically connected to the connection line 1100 by the contact connection line 1100.

[0149] The connection line 1100 can be positioned on the first gate insulating layer 203 and can include the same material as that of the lower electrode CE1 of the storage capacitor Cst and / or the first gate electrode GE1 described with reference to Figure 4 .

[0150] At least one insulating layer, for example, the first interlayer insulating layer 205, the second interlayer insulating layer 207, the second gate insulating layer 209, and the third interlayer insulating layer 210, can be positioned on the connection line 1100, and the pad electrode 1200 can be connected to the connection line 1100 through a contact hole passing through the first interlayer insulating layer 205, the second interlayer insulating layer 207, the second gate insulating layer 209, and the third interlayer insulating layer 210.

[0151] The pad electrode 1200 can have a structure in which a plurality of conductive layers are stacked. For example, as shown in FIG. 12A, the pad electrode 1200 can include a first pad conductive layer 1210, a second pad conductive layer 1220, and a third pad conductive layer 1230. Figure 8

[0152] The first pad conductive layer 1210 can include the same material as that of the node connection line 166 described with reference to FIG. 6. Figure 4 The second pad conductive layer 1220 can include the same material as that of the data line DL and / or the driving voltage line PL described with reference to FIG. 6. Figure 4 The third pad conductive layer 1230 can include the same material as that of the first wire 420 and / or the second wire 440 described with reference to FIG. 6. The third pad conductive layer 1230 can be connected to the second pad conductive layer 1220 through a contact hole formed in the first touch insulating layer 410 and the second touch insulating layer 430. Figure 4

[0153] Although, in the embodiment of FIG. 12A, the first pad conductive layer 1210 and the second pad conductive layer 1220 are in direct contact with each other and the insulating layer (e.g., the first touch insulating layer 410 and the second touch insulating layer 430) positions between the second pad conductive layer 1220 and the third pad conductive layer 1230, the present disclosure is not limited thereto. According to some embodiments, the insulating layer (e.g., the organic insulating layer) can also be positioned between the first pad conductive layer 1210 and the second pad conductive layer 1220, and the first pad conductive layer 1210 and the second pad conductive layer 1220 can be connected to each other through a contact hole of the insulating layer. Figure 8 The integrated circuit 40 can be electrically connected to the pad electrode 1200 via an anisotropic conductive film (ACF) 800 including conductive balls 810. The bump 42 of the integrated circuit 40 can overlap the pad electrode 1200, the conductive ball 810 can be positioned between the bump 42 and the pad electrode 1200, and thus the bump 42 can be electrically connected to the pad electrode 1200.

[0154] Referring to a cross-sectional view taken along a line C-C' of FIG. 12A (i.e., FIG. 12B), a second edge 211E2 of the first organic insulating layer 211 can be spaced apart from a second edge 40E2 of the integrated circuit 40, and a second distance d2 between the second edge 211E2 and the second edge 40E2 can be in a range of from about 40 µm to about 80 µm as described above.

[0155] Figure 7 Figure 9

[0156] ​​​​​The second organic insulating layer 213 can be positioned on the first organic insulating layer 211, and the second organic insulating layer 213 can extend beyond the second edge 211E2 of the first organic insulating layer 211 to reach the integrated circuit 40. Like the first edge 213E1 of the second organic insulating layer 213, the second edge 213E2 of the second organic insulating layer 213 can be closer to the integrated circuit 40 than the second edge 211E2 of the first organic insulating layer 211. The second portion 213B of the second organic insulating layer 213 can overlap with the integrated circuit 40 to form a shape such that... Figure 9 The second overlapping region OL2 is shown. The width of the second overlapping region OL2 (in other words, the distance between the second edge 213E2 of the second organic insulating layer 213 and the second edge 40E2 of the integrated circuit 40) can be less than the second distance d2. The width of the second overlapping region OL2 can be equal to or different from the reference distance. Figure 8 The width of the first overlapping region OL1 is described. In some embodiments, the width of the second overlapping region OL2 may be approximately 10 μm.

[0157] The connecting wire 1100 can be positioned between the substrate 100 and the first organic insulating layer 211, spaced apart from each other. For example... Figure 7 and Figure 9 As shown, portions of the connecting line 1100 may not overlap with the first organic insulating layer 211. In other words, multiple portions of the connecting line 1100 may overlap with openings 211OP of the first organic insulating layer 211. Therefore, multiple portions of the connecting line 1100 may not be covered by the first organic insulating layer 211, or may not overlap with the first organic insulating layer 211.

[0158] In the comparative example, when the second distance d2 between the second edge 211E2 of the first organic insulating layer 211 and the second edge 40E2 of the integrated circuit 40 exceeds approximately 80 μm, the area of ​​the portion that does not overlap with the first organic insulating layer 211 may increase, and in this case, the connection line 1100 may be damaged by electrostatic discharge (ESD), and the quality of the connection line 1100 and its surroundings may deteriorate.

[0159] Reference Figure 8 and Figure 9 The first edge 211E1 and second edge 211E2 of the first organic insulating layer 211, the first edge 213E1 and second edge 213E2 of the second organic insulating layer 213, and the first edge 40E1 and second edge 40E2 of the integrated circuit 40 have been described. (Refer to...) Figure 5A and Figure 5B The structure between the third edge 211E3 of the first organic insulating layer 211, the third edge 213E3 of the second organic insulating layer 213, and the third edge 40E3 of the integrated circuit 40 can be compared with the reference.Figure 8 The structures described are the same. For example, according to some embodiments, the third distance d3 between the third edge 211E3 of the first organic insulating layer 211 and the third edge 40E3 of the integrated circuit 40 (see...) Figure 5B The thickness can be approximately 40 μm or larger, and can be in the range of approximately 40 μm to approximately 80 μm. The second organic insulating layer 213 can extend beyond the third edge 211E3 of the first organic insulating layer 211 to form a third overlapping region with the integrated circuit 40. The width of the third overlapping region can be equal to or different from the width of the first overlapping region OL1 and / or the second overlapping region OL2. The second organic insulating layer 213 may include a first portion and a second portion with different thicknesses, and the description of the second organic insulating layer 213 is consistent with the reference. Figure 8 The content described is the same.

[0160] Reference Figure 5A and Figure 5B The structure between the fourth edge 211E4 of the first organic insulating layer 211, the fourth edge 213E4 of the second organic insulating layer 213, and the fourth edge 40E4 of the integrated circuit 40 is described and referenced. Figure 9 The structures described are the same. For example, the fourth distance d4 between the fourth edge 211E4 of the first organic insulating layer 211 and the fourth edge 40E4 of the integrated circuit 40 (see...) Figure 5B The fourth distance d4 can be approximately 40 μm or larger, and according to some embodiments, the fourth distance d4 can range from approximately 40 μm to approximately 80 μm. The second organic insulating layer 213 can extend beyond the fourth edge 211E4 of the first organic insulating layer 211 to form a fourth overlapping region with the integrated circuit 40. The width of the fourth overlapping region can be equal to or different from the width of the first overlapping region OL1 and / or the second overlapping region OL2. The second organic insulating layer 213 may include a first portion and a second portion with different thicknesses, and the description of the second organic insulating layer 213 is consistent with reference to... Figure 9 The content described is the same.

[0161] It should be understood that the embodiments described herein should be considered descriptive only and not for limiting purposes. The descriptions of various features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope defined by the scope of the claims and their equivalents.

Claims

1. A display device, wherein, The display device includes: The display area has multiple sub-pixels; Multiple pad electrodes are located in the peripheral area outside the display area; A first organic insulating layer includes an opening overlapping the plurality of pad electrodes; and Integrated circuit, overlapping with and electrically connected to the plurality of pad electrodes. The distance between the edge defining the opening in the first organic insulating layer and the edge of the integrated circuit is 40 micrometers or greater. The display device further includes a second organic insulating layer located on the first organic insulating layer. The second organic insulating layer extends beyond the edge of the first organic insulating layer to overlap with a portion of the integrated circuit.

2. The display device according to claim 1, wherein, The second organic insulating layer includes: The first portion overlaps with the first organic insulating layer; and The second portion extends beyond the edge of the first organic insulating layer to overlap with a portion of the integrated circuit. The thickness of the second part is less than the thickness of the first part.

3. The display device according to claim 2, wherein, The second organic insulating layer includes a connection portion located between the first portion and the second portion, the connection portion of the second organic insulating layer including a stepped portion, wherein the stepped portion is located on the top surface of the first organic insulating layer.

4. The display device according to claim 1, wherein, The distance is in the range of 40 micrometers to 80 micrometers.

5. The display device according to claim 2, wherein, The display device further includes a touch input layer, comprising a plurality of touch electrodes and a touch insulating layer located in the display area. The touch insulating layer overlaps with the second organic insulating layer.

6. The display device according to claim 5, wherein, The touch insulating layer overlaps with the second portion of the second organic insulating layer.

7. The display device according to claim 5, wherein, The touch insulation layer includes at least one of organic and inorganic insulating materials.

8. The display device according to claim 1, wherein, The multiple sub-pixels emit light using light-emitting diodes located on the substrate. A portion of the first organic insulating layer is located between the substrate and the light-emitting diode.

9. The display device according to any one of claims 1 to 8, wherein, The display device further includes: Multiple data cables pass through the display area; and Multiple connecting lines electrically connect the multiple data lines to the multiple pad electrodes.

10. The display device according to claim 9, wherein, Some of the multiple connecting lines overlap with the openings in the first organic insulating layer.

11. A display device, wherein, The display device includes: The display area has multiple sub-pixels; Multiple signal lines are located in the display area; Multiple pad electrodes are located in the peripheral area outside the display area and are electrically connected to the multiple signal lines; A first organic insulating layer includes an opening that overlaps with the plurality of pad electrodes; A second organic insulating layer is located on top of the first organic insulating layer; and Integrated circuit, overlapping with and electrically connected to the plurality of pad electrodes. Wherein, the edge defining the opening in the first organic insulating layer is located outside the integrated circuit and spaced apart from the edge of the integrated circuit. The second organic insulating layer extends beyond the edge of the first organic insulating layer to overlap with a portion of the integrated circuit.

12. The display device according to claim 11, wherein, The distance between the edge of the first organic insulating layer and the edge of the integrated circuit is in the range of 40 micrometers to 80 micrometers.

13. The display device according to claim 11, wherein, The second organic insulating layer includes: The first portion overlaps with the first organic insulating layer; and The second portion extends beyond the edge of the first organic insulating layer to overlap with a portion of the integrated circuit. The thickness of the second part is less than the thickness of the first part.

14. The display device according to claim 13, wherein, The second organic insulating layer includes a connection portion located between the first portion and the second portion, and the connection portion of the second organic insulating layer includes a stepped portion. The stepped portion is opposite to the edge of the integrated circuit, and the edge of the first organic insulating layer is located between the stepped portion and the edge of the integrated circuit.

15. The display device according to claim 11, wherein, The plurality of sub-pixels are configured to emit light using light-emitting diodes located on the substrate. Each of a portion of the first organic insulating layer and a portion of the second organic insulating layer is located between the substrate and the light-emitting diode.

16. The display device according to claim 11, wherein, The display device further includes a touch input layer, comprising a plurality of touch electrodes and a touch insulating layer located in the display area. The touch insulating layer overlaps with the first organic insulating layer and the second organic insulating layer.

17. The display device according to any one of claims 11 to 16, wherein, The display device further includes: multiple connecting lines that electrically connect the data lines of the display area to the multiple pad electrodes of the surrounding area. The multiple connecting lines are located below the first organic insulating layer.

18. The display device according to claim 17, wherein, Some of the multiple connecting lines overlap with the openings in the first organic insulating layer.

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