Semiconductor devices

Abstract

This invention provides a semiconductor device capable of reducing thermal stress applied to semiconductor elements. A plurality of first transistors, comprising a mesa structure made of semiconductor, are disposed on the upper surface of a substrate. A first protrusion, elongated in one direction and connected to the plurality of first transistors, is disposed at a position overlapping the plurality of first transistors in a top view. Second protrusions are disposed at intervals relative to the first protrusions in a direction orthogonal to the long side direction of the first protrusions. A first metal pattern is disposed between the first and second protrusions in a top view. Using the upper surface of the substrate as a height reference, the center height of the first metal pattern in the thickness direction is higher than the upper surface of the mesa structure included by each of the plurality of first transistors, and lower than the lower surface of the first protrusions.

Description

Technical Field

[0001] This invention relates to semiconductor devices. Background Technology

[0002] Transistors used in power amplifier modules that constitute portable devices, for example, heterojunction bipolar transistors (HBTs). These power amplifier modules are typically flip-chip mounted on a module substrate. Furthermore, to increase the design freedom in the placement of bumps, a so-called rewiring layer is used.

[0003] To effectively conduct heat generated by the HBT to the module substrate, a protrusion connected to the HBT is positioned directly above the HBT. This protrusion functions as a heat transfer path from the HBT to the module substrate. Thermal stress is generated during the reflow soldering process when mounting the power amplifier module onto the module substrate. When the HBT is positioned directly below the protrusion, thermal stress is easily applied to the HBT and its vicinity, thus increasing the likelihood of cracks forming in or near the HBT. These cracks contribute to a decrease in the reliability of the power amplifier module. In the semiconductor device disclosed in Patent Document 1, stress mitigation layers are disposed under each wiring included in the redistribution layer to mitigate the stress applied to the HBT and its vicinity.

[0004] Prior art literature

[0005] Patent documents

[0006] Patent Document 1: Japanese Patent Application Publication No. 2019-149485 Summary of the Invention

[0007] The problem that the invention aims to solve

[0008] To further improve the reliability of semiconductor devices, it is desirable to further reduce the thermal stress applied to semiconductor elements such as HBTs included in the semiconductor device. The object of this invention is to provide a semiconductor device capable of reducing the thermal stress applied to semiconductor elements.

[0009] Methods for solving problems

[0010] According to one aspect of the present invention, a semiconductor device is provided, comprising:

[0011] substrate;

[0012] A plurality of first transistors are disposed on the upper surface of the substrate as one side and include a mesa structure made of semiconductors;

[0013] A first protrusion is disposed at a position overlapping the plurality of first transistors in a top view, the shape of which is longer in one direction in a top view, and is connected to the plurality of first transistors;

[0014] The second protrusion is arranged at intervals relative to the first protrusion in a direction orthogonal to the long side direction of the first protrusion; and

[0015] A first metallic pattern, when viewed from above, is positioned between the first protrusion and the second protrusion.

[0016] Using the upper surface of the substrate as a height reference, the height of the center of the first metal pattern in the thickness direction is higher than the upper surface of the mesa structure included by the plurality of first transistors, and lower than the lower surface of the first protrusion.

[0017] According to another aspect of the present invention, a semiconductor device is provided, comprising:

[0018] substrate;

[0019] A plurality of first transistors are disposed on the upper surface of one side of the substrate and include a mesa structure made of semiconductor; and

[0020] A first protrusion is positioned to overlap with the plurality of first transistors in a top view, having an elongated shape in one direction and connected to the plurality of first transistors.

[0021] The first protrusion and the region extending from the first protrusion along its long side are detached from the geometric center of the substrate when viewed from above.

[0022] Furthermore, viewed from above, a first metallic pattern is present in a region closer to the geometric center than the first protrusion, and this first metallic pattern is arranged at a distance from the first protrusion.

[0023] Using the upper surface of the substrate as a height reference, the height of the center of the first metal pattern in the thickness direction is higher than the upper surface of the mesa structure included by the plurality of first transistors, and lower than the lower surface of the first protrusion.

[0024] According to another aspect of the present invention, a semiconductor device is provided, comprising:

[0025] substrate;

[0026] A plurality of first transistors are disposed on the upper surface of the substrate as one side and include a mesa structure made of semiconductors;

[0027] A first protrusion is disposed at a position overlapping the plurality of first transistors in a top view, the shape of which is longer in one direction in a top view, and is connected to the plurality of first transistors;

[0028] The second protrusion is arranged at intervals relative to the first protrusion in a direction orthogonal to the long side direction of the first protrusion; and

[0029] A first metallic pattern, when viewed from above, is positioned between the first protrusion and the second protrusion.

[0030] Using the upper surface of the substrate as a height reference, the height of the center of the first metal pattern in the thickness direction is higher than the upper surface of the mesa structure included by the plurality of first transistors, and lower than the lower surface of the first protrusion.

[0031] In the direction of the long side of the first protrusion, the first metal pattern occupies more than 1 / 2 of the area where the first protrusion is disposed.

[0032] Invention Effects

[0033] The first metal pattern mitigates the thermal stress applied to the first transistor. This suppresses the formation of cracks caused by thermal stress, thereby improving the reliability of the semiconductor device. Attached Figure Description

[0034] Figure 1 This is a diagram showing the planar positional relationship of the main components of the semiconductor device according to the first embodiment.

[0035] Figure 2 yes Figure 1 The sectional view at point 2-2, marked by a single-dotted line.

[0036] Figure 3 yes Figure 1 A cross-sectional view at point 3-3, indicated by a single-dotted line.

[0037] Figure 4A , Figure 4B and Figure 4C This is a diagram showing the configuration and shape of the first bump, the second bump, and the first metal pattern of a semiconductor device in a modified example of the first embodiment.

[0038] Figure 5 This is a cross-sectional view of a semiconductor device, which is another variation of the first embodiment.

[0039] Figure 6 This is a diagram showing the planar positional relationship of the main components of the semiconductor device according to the second embodiment.

[0040] Figure 7 This is a diagram showing the planar positional relationship of the main components of the semiconductor device according to the third embodiment.

[0041] Figure 8 This is a diagram showing the planar positional relationship of the main components of the semiconductor device according to the fourth embodiment.

[0042] Figure 9 This is a diagram showing the planar positional relationship of the main components of the semiconductor device according to the fifth embodiment.

[0043] Figure 10 This is a diagram showing the planar positional relationship of the main components of the semiconductor device in a modified example of the fifth embodiment.

[0044] Figure 11 This is a diagram showing the planar positional relationship of the main components of the semiconductor device according to the sixth embodiment.

[0045] Figure 12 This is a diagram showing the planar positional relationship of the main components of the semiconductor device according to the seventh embodiment.

[0046] Explanation of reference numerals in the attached figures

[0047] 10 substrate;

[0048] 11. The first transistor;

[0049] The ends of the first transistors 11A and 11B;

[0050] The center of the first transistor in 11C;

[0051] 12. Second transistor;

[0052] The end of the 12A second transistor;

[0053] 13B The base electrode of the first transistor;

[0054] The collector electrode of the first transistor in the 13C series;

[0055] The emitter electrode of the first transistor, 13E;

[0056] The emitter electrode of the second transistor, 14E;

[0057] 15A First group of first transistors;

[0058] The second group of the first transistor in the 15B series;

[0059] 21. First emitter wiring;

[0060] 22. Second emitter wiring;

[0061] 31 First pad;

[0062] 32 Second pad;

[0063] 33 Third pad;

[0064] 35 First metal pattern;

[0065] 41, 41A, 41B First protrusion;

[0066] 42 Second protrusion;

[0067] 43. Third protrusion;

[0068] 51, 52 Solder layers;

[0069] 60+ layers of wiring structure;

[0070] 91. The first layer of interlayer insulation film;

[0071] 92. The second layer of interlayer insulation film;

[0072] 92A The lower layer of the second layer interlayer insulating film;

[0073] 92B is the upper layer of the second layer interlayer insulating film;

[0074] 93. Protective film. Detailed Implementation

[0075] [First Embodiment]

[0076] Reference Figure 1 , Figure 2 and Figure 3 The semiconductor device of the first embodiment will be described.

[0077] Figure 1 This is a diagram showing the planar positional relationship of the main components of the semiconductor device according to the first embodiment. A plurality of first transistors 11 and two second transistors 12 are disposed on one side of the substrate (hereinafter referred to as the upper surface). It should be noted that the number of second transistors 12 is not limited to two. Only one second transistor 12 may be disposed, or more than three second transistors 12 may be disposed.

[0078] A plurality of first transistors 11 are arranged in one direction. An orthogonal xy coordinate system is defined on the upper surface of the substrate, with the arrangement direction of the first transistors 11 as the x-direction. Each of the first transistors 11 has a shape that is longer in the y-direction when viewed from above. Two second transistors 12 are also arranged in the x-direction. Furthermore, each of the second transistors 12 has a shape that is longer in the y-direction when viewed from above.

[0079] The first pad 31 and the first bump 41 are configured to include a plurality of first transistors 11 in top view. The first pad 31 and the first bump 41 have an elongated shape in the x-direction in top view. The first bump 41 is configured to cover a range Blx in the x-direction.

[0080] The second pad 32 and the second protrusion 42 are arranged at intervals in the y-direction relative to the first protrusion 41. The y-direction interval between the first protrusion 41 and the second protrusion 42 is denoted as D. The second protrusion 42 is arranged in the x-direction with a coverage area B2x. The second pad 32 and the second protrusion 42 overlap each other in top view. Furthermore, the second pad 32 and the second protrusion 42 contain two second transistors 12 in top view.

[0081] Multiple first transistors 11 are connected in parallel, and two second transistors 12 are also connected in parallel. The multiple first transistors 11 and the two second transistors 12 constitute a two-stage high-frequency amplifier circuit. The two second transistors 12 constitute the primary amplifier circuit, and the multiple first transistors 11 constitute the final amplifier stage.

[0082] In top view, a first metal pattern 35 is disposed between the first protrusion 41 and the second protrusion 42. The first metal pattern 35 is disposed covering a range Mx in the x-direction and covering a range My in the y-direction. Based on the first protrusion 41, on the side opposite to the side where the second protrusion 42 is disposed, no protrusions that include a mesa structure on the upper surface of the substrate 10 in top view are disposed.

[0083] Figure 2 and Figure 3 They are Figure 1 Cross-sectional views at points 2-2 and 3-3. A plurality of first transistors 11 are disposed on the upper surface of the substrate 10. Figure 2 , Figure 3 ) and two second transistors 12 ( Figure 3 It should be noted that, in Figure 3 The cross-section shown reveals a first transistor 11 and a second transistor 12. Both the first transistor 11 and the second transistor 12 include a mesa structure made of semiconductor disposed on the upper surface of the substrate 10. The mesa structure includes a collector layer, a base layer, and an emitter layer sequentially stacked from the substrate side. The collector layer, base layer, and emitter layer are formed, for example, of n-type GaAs, p-type GaAs, and n-type InGaP. That is, the first transistor 11 is a heterojunction bipolar transistor.

[0084] The substrate 10 is formed of a compound semiconductor, such as semi-insulating GaAs, and includes an n-type semiconductor layer with n-type conductivity in a portion of its surface layer. Collector electrodes 13C are disposed at positions sandwiching each of the first transistors 11 along the arrangement direction of the first transistors 11. The collector electrodes 13C are electrically connected to the collector layer via the n-type semiconductor layer in the surface layer of the substrate 10.

[0085] A base electrode 13B and an emitter electrode 13E are disposed on the mesa structure of each of the plurality of first transistors 11. The base electrode 13B and the emitter electrode 13E are electrically connected to the base layer and emitter layer of the first transistor 11, respectively. Similarly, the second transistor 12 is provided with a collector electrode, a base electrode, and an emitter electrode 14E. Figure 3 It should be noted that the collector electrode and base electrode did not appear. Figure 3 In the cross-section shown.

[0086] Over the entire area of ​​the upper surface of the substrate 10, the interlayer insulating film 91 of the first layer is configured to cover the collector electrode 13C, the base electrode 13B, and the emitter electrodes 13E and 14E. The interlayer insulating film 91 is formed of an inorganic insulating material such as silicon oxide or silicon nitride.

[0087] A first wiring layer is disposed on the interlayer insulating film 91. The first wiring layer includes a first emitter wiring 21, a second emitter wiring 22, etc. For example, Au or a metal with Au as the main component is used for the first wiring layer.

[0088] The first emitter wiring 21 is connected to the emitter electrodes 13E of a plurality of first transistors 11 through multiple openings in the interlayer insulating film 91. The emitter layers of the plurality of first transistors 11 are electrically connected to each other through the first emitter wiring 21 of the first layer. The second emitter wiring 22 is connected to the emitter electrodes 14E of the second transistors 12 through two openings in the interlayer insulating film 91. The emitter layers of the two second transistors 12 are electrically connected to each other through the second emitter wiring 22.

[0089] In addition, the wiring layer in the first layer also includes collector wiring and base wiring that are respectively connected to the collector electrode 13C and the base electrode 13B of the first transistor 11. Furthermore, the wiring layer in the first layer includes collector wiring and base wiring that are respectively connected to the collector electrode and the base electrode of the second transistor 12.

[0090] A second interlayer insulating film 92 is disposed on the first wiring layer. The second interlayer insulating film 92 comprises a lower layer 92A on the lower side and an upper layer 92B on the upper side. The lower layer 92A is formed of an inorganic insulating material such as silicon oxide or silicon nitride, and the upper layer 92B is formed of an organic insulating material such as polyimide. The surface of the upper layer 92B is planarized. The second interlayer insulating film 92 has two openings, which, when viewed from above, are respectively contained in the first emitter wiring 21 and the second emitter wiring 22.

[0091] A second wiring layer is disposed on the interlayer insulating film 92. The second wiring layer includes a first pad 31, a second pad 32, and a first metal pattern 35. For example, a low-resistance metal material such as Cu, Al, or Au is used for the second wiring layer.

[0092] The first pad 31 and the second pad 32 are respectively connected to the first emitter wiring 21 and the second emitter wiring 22 of the first layer through openings not placed in the interlayer insulating film 92. The first metal pattern 35 is set to an electrically floating state. Taking the upper surface of the substrate 10 as a height reference, the height of the center of the first metal pattern 35 in the thickness direction is higher than the upper surface of the mesa structure of the first transistor 11 and the second transistor 12, and lower than the lower surface of the first protrusion 41 and the second protrusion 42.

[0093] A protective film 93 is disposed on the second wiring layer. The protective film 93 is formed of an organic insulating material such as polyimide, and its surface is planarized. The protective film 93 has two openings, respectively contained within the first pad 31 and the second pad 32 when viewed from above. A first protrusion 41 and a second protrusion 42 are respectively disposed within the two openings of the protective film 93. The first protrusion 41 is connected to the first pad 31, and the second protrusion 42 is connected to the second pad 32. The first protrusion 41 and the second protrusion 42 are made of a metal material with Cu, Au, or Cu or Au as the main component.

[0094] The first protrusion 41 and the second protrusion 42 may also be configured to include a protruding undermetal layer for improving adhesion and preventing diffusion. The protruding undermetal layer is disposed between the columnar portion, which is mainly composed of Cu, and the first pad 31, the second pad 32, and the protective film 93. For example, Ti, TiW, Ni, etc., can be used for the protruding undermetal layer.

[0095] The first protrusion 41 and the second protrusion 42 protrude upwards from the upper surface of the protective film 93. Furthermore, when viewed from above, they widen from the edge of the opening to its surrounding area. Solder layers 51 and 52 are respectively disposed on the upper surfaces of the first protrusion 41 and the second protrusion 42. For example, a solder with Sn as its main component is used for solder layers 51 and 52. A diffusion-preventing layer may also be disposed between the first protrusion 41 and the solder layer 51, and between the second protrusion 42 and the solder layer 52, to prevent the solder material from diffusing into the protrusion. For example, Ni, Ti, W, etc., are used for the diffusion-preventing layer.

[0096] Next, the superior effects of the first embodiment will be explained.

[0097] The distribution of thermal stress generated when the semiconductor devices of the first embodiment and the comparative example are mounted on the module substrate is determined by simulation. The semiconductor device of the comparative example omits the first metal pattern 35 provided in the semiconductor device of the first embodiment. The simulation was performed under the following conditions: with the semiconductor device facing the module substrate, the solder layers 51, 52, etc. were heated to 260°C to melt them, and when the temperature dropped to 210°C, the solder solidified, and then the temperature dropped to room temperature.

[0098] Based on the simulation results above, in the comparative example semiconductor device without the first metal pattern 35, in the first transistor 11 ( Figure 1 The thermal stresses generated at the end 11A on the side of the second protrusion 42 of the mesa structure of the first transistor 11, the opposite end 11B, and the center 11C are 257 MPa, 156 MPa, and 172 MPa, respectively. In contrast, in the semiconductor device of the first embodiment with the first metal pattern 35, the thermal stresses generated at the ends 11A and 11B and the center 11C of the mesa structure of the first transistor 11 are 232 MPa, 160 MPa, and 172 MPa, respectively. It should be noted that the simulation conditions are the same in both simulations, except for the presence or absence of the first metal pattern 35.

[0099] The simulation results show that the thermal stress is relatively high at the end 11A of the second protrusion 42 side of the mesa structure of the multiple first transistors 11. In particular, it was found that the thermal stress is significantly concentrated in the transistor directly below the protrusion that is longer in one direction. This is because, during the process of mounting the semiconductor device onto the module substrate, after the solder has cured and mechanically fixed the first protrusion 41 and the second protrusion 42 to the module substrate, thermal stress is applied from the module substrate to the semiconductor device through the first protrusion 41 and the second protrusion 42 during the cooling process.

[0100] The thermal stress generated at end 11A is reduced from 257 MPa to 232 MPa by configuring the first metal pattern 35. Thus, it can be seen that configuring the first metal pattern 35 on the end 11A side, where the thermal stress is relatively higher, mitigates the concentration of thermal stress. It should be noted that by configuring the first metal pattern 35, the thermal stress at end 11B increases from 156 MPa to 160 MPa, but even after the increase in thermal stress, the thermal stress at end 11B is still lower than that at end 11A.

[0101] In the first embodiment, by arranging the first metal pattern 35 on the side where thermal stress tends to concentrate when viewed from a transistor array including a plurality of first transistors 11, the thermal stress applied to the first transistors 11 can be reduced. This suppresses the generation of cracks caused by thermal stress and improves the reliability of the semiconductor device.

[0102] Furthermore, since the first metal pattern 35 is set to an electrically floating state, the operation of the electronic circuit provided on the substrate 10 is less affected by the first metal pattern 35, resulting in an excellent effect. It should be noted that the first metal pattern 35 can also be lowered to the ground potential of the electronic circuit provided on the substrate 10. In this case, the excellent effect of the operation of the electronic circuit provided on the substrate 10 being less affected by the first metal pattern 35 is also obtained.

[0103] Next, the preferred position and size of the first metal pattern 35 for achieving the full effect of the first embodiment will be described.

[0104] To reduce the impact of thermal stress on the first transistor 11 from the second protrusion 42, it is preferable that the first metal pattern 35 is configured in the x-direction such that the range Mx where the first metal pattern 35 is configured includes the range B2x where the second protrusion 42 is configured. Furthermore, it is preferable that the first metal pattern 35 is configured in the x-direction such that the range Mx where the first metal pattern 35 is configured occupies more than half of the range B1x where the first protrusion 41 is configured.

[0105] Preferably, the first metal pattern 35 is configured in the y-direction such that the range My of the first metal pattern 35 occupies more than 1 / 2 of the y-direction interval D between the first protrusion 41 and the second protrusion 42.

[0106] Next, refer to Figure 4A , Figure 4B and Figure 4C A modified example of the semiconductor device of the first embodiment will be described. Figure 4A , Figure 4B and Figure 4C This is a top view showing the configuration and shape of the first protrusion 41, the second protrusion 42, and the first metal pattern 35 of a semiconductor device in a modified example of the first embodiment.

[0107] exist Figure 4A In the modified example shown, the first metal pattern 35 protrudes from the region B1x where the first protrusion 41 is disposed in the x direction. In this case, it is preferable that the first metal pattern 35 is configured such that the overlapping range of the region B1x where the first protrusion 41 is disposed and the region Mx where the first metal pattern 35 is disposed occupies more than 1 / 2 of the region B1x where the first protrusion 41 is disposed.

[0108] exist Figure 4BIn the illustrated variation, the shape of the first metal pattern 35 in top view is an irregular shape other than a square or rectangle. The first metal pattern 35 is disposed within the range B1x in the x-direction where the first protrusion 41 is disposed. In this case, it is also preferable that the range Mx where the first metal pattern 35 is disposed occupies more than 1 / 2 of the range B1x where the first protrusion 41 is disposed. Furthermore, it is also preferable that the range My where the first metal pattern 35 is disposed occupies more than 1 / 2 of the interval D in the y-direction.

[0109] exist Figure 4C In the illustrated variation, the second protrusion 42 is positioned in the x-direction at a point detached from the region B1x where the first protrusion 41 is located. In this case, the distance between the first protrusion 41 and the second protrusion 42 in the y-direction can be defined as the interval D between them. In this variation, similarly to the first embodiment, it is preferable that the first metal pattern 35 is configured in the y-direction such that the region My where the first metal pattern 35 is located occupies more than half of the interval D. Furthermore, it is preferable that the first metal pattern 35 is configured in the x-direction such that the overlapping range of the region B2x where the second protrusion 42 is located and the region Mx where the first metal pattern 35 is located occupies more than half of the region B2x where the second protrusion 42 is located.

[0110] Next, refer to Figure 5 A semiconductor device of another variation of the first embodiment will be described.

[0111] Figure 5 This is a cross-sectional view of a semiconductor device, another variation of the first embodiment. In the first embodiment ( Figure 3 In this configuration, a wiring layer including a first emitter wiring 21 and a second emitter wiring 22 is disposed between the emitter electrode 13E and the first pad 31, and between the emitter electrode 14E and the second pad 32. In contrast, in... Figure 5 In the modified example shown, a multilayer wiring structure 60 including multiple wiring layers is arranged between the emitter electrode 13E and the first pad 31 and between the emitter electrode 14E and the second pad 32.

[0112] The first emitter wiring 21 and the second emitter wiring 22 are contained in a wiring layer counting from the substrate 10 side of the multilayer wiring structure 60. The first pad 31, the second pad 32, and the first metal pattern 35 are contained in the uppermost wiring layer of the multilayer wiring structure 60. The first pad 31 and the second pad 32 are electrically connected to the emitter electrodes 13E and 14E respectively via the wiring layers in the multilayer wiring structure 60.

[0113] The uppermost wiring layer in the multilayer wiring structure 60 is sometimes referred to as a rewiring layer. The rewiring layer includes wiring for connecting circuitry on the substrate to external connection terminals such as first protrusion 41 and second protrusion 42, primarily designed to increase the flexibility of the configuration of these external connection terminals. Therefore, the wiring within the rewiring layer is typically connected to external connection terminals such as first protrusion 41 and second protrusion 42. In this modified example, a first metal pattern 35 is disposed in the rewiring layer that is not connected to any of the protrusions.

[0114] Typically, the wiring within the redistribution layer is thicker than the wiring in other wiring layers within the multilayer wiring structure 60. Therefore, the first metal pattern 35 is thicker than any wiring in other wiring layers disposed on its substrate side. By disposing the first metal pattern 35, which has a higher Young's modulus than the organic insulating material of the protective film 93, in the redistribution layer, the effect of suppressing the propagation of thermal stress from the module substrate to the first transistor 11 can be improved.

[0115] It should be noted that, if there is room for metal patterns to be configured in the area directly below the first metal pattern 35 of other wiring layers in the multilayer wiring structure 60, floating metal patterns can also be configured in wiring layers that are closer to the substrate side than the rewiring layer.

[0116] Next, another variation of the first embodiment will be described. In the first embodiment, in the second protrusion 42 ( Figure 3 The mesa structure of the second transistor 12 is disposed directly below the second protrusion 42. Alternatively, even if a semiconductor-made mesa structure is not disposed directly below the second protrusion 42, the first transistor 11 may sometimes be affected by the second protrusion 42 and extend towards the end 11A of the first transistor 11 on the side of the second protrusion 42. Figure 1 This applies relatively large thermal stress. In such cases, thermal stress can be reduced by configuring the first metal pattern 35.

[0117] [Second Embodiment]

[0118] Next, refer to Figure 6 The semiconductor device of the second embodiment will be described below. Hereinafter, the semiconductor device of the first embodiment (…) will be described. Figure 1 , Figure 2 , Figure 3 The common structure is omitted.

[0119] Figure 6 This is a diagram showing the planar positional relationship of the main components of the semiconductor device according to the second embodiment. In the first embodiment ( Figure 1In the first embodiment, the second protrusion 42 is approximately circular when viewed from above. In contrast, in the second embodiment, the second protrusion 42, like the first protrusion 41, is longer in the x-direction when viewed from above. That is, the long side of the first protrusion 41 is parallel to the long side of the second protrusion 42.

[0120] A plurality of second transistors 12, contained in the second protrusion 42, are arranged along the x-direction when viewed from above. The second transistors 12, like the first transistors 11, have an elongated shape in the y-direction when viewed from above. The second pad 32 has an elongated shape in the x-direction when viewed from above, thus containing a plurality of second transistors 12. A first metal pattern 35 is disposed between the first protrusion 41 and the second protrusion 42.

[0121] Next, the superior effects of the second embodiment will be explained.

[0122] In the second embodiment, similarly to the first embodiment, a first metal pattern 35 is disposed between the first protrusion 41 and the second protrusion 42. Therefore, the thermal stress at the end 11A of the first transistor 11 on the second protrusion 42 side can be reduced. Similarly, the thermal stress at the end 12A of the second transistor 12 on the first protrusion 41 side is also reduced. The preferred positional relationship between the second protrusion 42 and the first metal pattern 35 is similar to that in the first embodiment. Figure 1 The preferred positional relationships are the same.

[0123] [Third Embodiment]

[0124] Next, refer to Figure 7 The semiconductor device of the third embodiment will be described below. Hereinafter, the semiconductor device of the first embodiment will be described. Figure 1 , Figure 2 , Figure 3 The common structure is omitted.

[0125] Figure 7 This is a diagram showing the planar positional relationship of the main components of the semiconductor device according to the third embodiment. In the first embodiment ( Figure 1 In the first embodiment, two second transistors 12 are configured, and the second protrusion 42 connected to the second transistors 12 has a generally circular shape when viewed from above. In contrast, in the third embodiment, three or more, for example, seven, second transistors 12 are arranged along the x-direction.

[0126] Two second protrusions 42 are arranged spaced apart in the x-direction. A second pad 32, viewed from top view, extends from one second protrusion 42 to the other. A plurality of second transistors 12, viewed from top view, are contained within the second pads 32. A first metal pattern 35 is disposed between the first protrusion 41 and the two second protrusions 42.

[0127] In the x-direction, the region B2x in which two second protrusions 42 are respectively disposed is included within the region B1x in which the first protrusion 41 is disposed. Furthermore, in the x-direction, the region B2x in which two second protrusions 42 are respectively disposed is included within the region Mx in which the first metallic pattern 35 is disposed.

[0128] Next, the superior effects of the third embodiment will be explained.

[0129] In the third embodiment, similar to the first embodiment, a first metal pattern 35 is disposed between the first protrusion 41 and the second protrusion 42, thereby reducing the thermal stress at the end 11A of the first transistor 11 on the side of the second protrusion 42.

[0130] Next, a variation of the third embodiment will be described.

[0131] In the third embodiment, two second protrusions 42 are configured, but there may also be three or more second protrusions 42. In this case, it is preferable to configure the first metal pattern 35 in the x-direction such that the range B2x in which the plurality of second protrusions 42 are configured is contained within the range Mx in which the first metal pattern 35 is configured.

[0132] [Fourth Embodiment]

[0133] Next, refer to Figure 8 The semiconductor device of the fourth embodiment will be described below. Hereinafter, the semiconductor device compared to the third embodiment (…) Figure 7 The common structure is omitted.

[0134] Figure 8 This is a diagram showing the planar positional relationship of the main components of the semiconductor device according to the fourth embodiment. In the third embodiment ( Figure 7 In the first embodiment, a first protrusion 41 is provided that includes a plurality of first transistors 11 when viewed from above. In contrast, in the fourth embodiment, two first protrusions 41 are provided that are separated in the x-direction. A portion of the plurality of first transistors 11 is contained in one first protrusion 41 when viewed from above, while the remaining plurality of first transistors 11 is contained in the other first protrusion 41 when viewed from above. The two first protrusions 41 are positioned at the same location in the y-direction.

[0135] A first pad 31 extends along the x-direction from one first protrusion 41 to another first protrusion 41 in top view. A plurality of first transistors 11 are contained in the first pad 31 in top view. A first metal pattern 35 is disposed between the two first protrusions 41 and the two second protrusions 42.

[0136] Next, the superior effects of the fourth embodiment will be explained.

[0137] In the fourth embodiment, similarly to the third embodiment, a first metal pattern 35 is disposed between the first protrusion 41 and the second protrusion 42, thereby reducing the thermal stress at the end 11A of the first transistor 11 on the side of the second protrusion 42. In this case, it is preferable to set the position and size of the first metal pattern 35 in the x-direction such that the overlapping range of the range B1x where the first protrusion 41 is disposed and the range Mx where the first metal pattern 35 is disposed occupies more than 1 / 2 of the range B1x where the first protrusion 41 is disposed. The other first protrusion 41 is the same.

[0138] Next, a variation of the fourth embodiment will be described. In the fourth embodiment, two first protrusions 41 separated in the x-direction are provided, but there may also be three or more first protrusions 41. In this case, a first pad 31 is configured to overlap with all of the multiple first protrusions 41 when viewed from above.

[0139] [Fifth Embodiment]

[0140] Next, refer to Figure 9 The semiconductor device of the fifth embodiment will be described below. Hereinafter, the semiconductor device of the fourth embodiment will be discussed. Figure 8 The common structure is omitted.

[0141] Figure 9 This is a diagram showing the planar positional relationship of the main components of the semiconductor device according to the fifth embodiment. In the fourth embodiment ( Figure 8 In the first embodiment, all of the first transistors 11 are arranged at the same position in the y-direction. In contrast, in the fifth embodiment, the first transistors 11 of the first group 15A and the first transistors 11 of the second group 15B are staggered in the y-direction, wherein the first group 15A is located on the negative side of a certain position in the x-direction, and the second group 15B is located on the positive side of a certain position in the x-direction.

[0142] First bumps 41A and 41B are respectively provided for the plurality of first transistors 11 in the first group 15A and the plurality of first transistors 11 in the second group 15B. A first pad 31 overlaps with the two first bumps 41A and 41B in a top view. The first bump 41A corresponding to the first group 15A and the first bump 41B corresponding to the second group 15B are staggered in the y-direction. Therefore, the y-direction spacing DA between one first bump 41A and the second bump 42 and the y-direction spacing DB between the other first bump 41B and the second bump 42 are different. For example, spacing DA is narrower than spacing DB.

[0143] A first metal pattern 35 is disposed between a first protrusion 41A and a second protrusion 42, and between another first protrusion 41B and a second protrusion 42. The first metal pattern 35 extends in the x-direction from the region B1xA where a first protrusion 41A is disposed to the region B1xB where another first protrusion 41B is disposed. Within each region B1xA, B1xB where the first protrusions 41A and 41B are disposed, the first metal pattern 35 is disposed in the y-direction within the regions MyA and MyB.

[0144] Within the region BlxA where a first protrusion 41A is configured, the region MyA in the y-direction where the first metal pattern 35 is configured occupies more than half of the interval DA. Similarly, within the region B1xB where another first protrusion 41B is configured, the region MyB in the y-direction where the first metal pattern 35 is configured occupies more than half of the interval DB.

[0145] In the case where the plurality of first protrusions 41 are staggered in the y direction as in the fifth embodiment, the first metal pattern 35 is arranged in a preferred position relative to each of the plurality of first protrusions 41, and the first metal pattern 35 arranged relative to each of the plurality of first protrusions 41 is continuous in the x direction.

[0146] Next, the superior effects of the fifth embodiment will be explained.

[0147] In the fifth embodiment, a first metal pattern 35 is disposed relative to the plurality of first protrusions 41, and the first metal pattern 35 is disposed in a preferred position relative to each of the plurality of first protrusions 41. Therefore, the thermal stress generated at the end 11A of the first transistor 11 disposed in the region that overlaps with the plurality of first protrusions 41 on the side of the second protrusion 42 can be reduced.

[0148] Next, refer to Figure 10 A modified semiconductor device according to the fifth embodiment will be described.

[0149] Figure 10 This is a diagram showing the planar positional relationship of the main constituent elements of the semiconductor device in a modified example of the fifth embodiment. In the fifth embodiment ( Figure 9 In the first protrusion 41A, 41B, a first metal pattern 35 is provided on both sides. In contrast, in this modified example, a first metal pattern 35 is provided on the first protrusion 41A that is narrower in distance from the second protrusion 42, but no first metal pattern 35 is provided on the first protrusion 41B that is wider in distance.

[0150] The first transistor 11 directly beneath the first protrusion 41B, which has a wider y-direction spacing from the second protrusion 42, is less susceptible to thermal stress from the second protrusion 42 compared to the first transistor 11 directly beneath the first protrusion 41A, which has a narrower y-direction spacing. Therefore, the thermal stress generated at the end 11A of the first transistor 11 directly beneath one first protrusion 41B is less than the thermal stress generated at the end 11A of the first transistor 11 directly beneath the other first protrusion 41A. The first transistor 11 directly beneath the first protrusion 41B, where the generated thermal stress is relatively small, is less prone to cracking. This ensures sufficient reliability of the first transistor 11 directly beneath the first protrusion 41B. Figure 10 As shown in the variant example, the first metal pattern 35 is not configured in the x-direction within the range B1xB where the first protrusion 41B is configured.

[0151] [Sixth Embodiment]

[0152] Next, refer to Figure 11 The semiconductor device of the sixth embodiment will be described below. Hereinafter, the semiconductor device compared to the third embodiment (…) Figure 7 The common structure is omitted.

[0153] Figure 11 This is a diagram showing the planar positional relationship of the main components of the semiconductor device according to the sixth embodiment. In this modified example, a third protrusion 43 is disposed between the first protrusion 41 and the second protrusion 42. The third pad 33 is configured to overlap with the third protrusion 43 in plan view. No transistor is disposed directly below the third protrusion 43. That is, in plan view, no mesa structure of the semiconductor constituting the transistor is disposed in the area included in the third protrusion 43, and the interlayer insulating film 92 of the second layer ( Figure 2 , Figure 3 ) and the first layer interlayer insulating film 91 ( Figure 2 , Figure 3 )touch.

[0154] The thermal stress experienced by the first transistor 11 directly below the first protrusion 41 from the third protrusion 43, which does not have a mesa structure directly below it, is less than the thermal stress experienced from the second protrusion 42, which has a mesa structure directly below it. Therefore, when arranging the first metal pattern 35, the position and shape of the first metal pattern 35 can be determined by taking into account the positions of the first protrusion 41 and the second protrusion 42.

[0155] For example, in the x-direction, the first metal pattern 35 can be configured to bypass the third protrusion 43, such that the area Mx containing the first metal pattern 35 occupies more than half of the area Blx containing the first protrusion 41. In the y-direction, the first metal pattern 35 can be configured such that the area My containing the first metal pattern 35 occupies more than half of the interval D.

[0156] Next, the superior effects of the sixth embodiment will be explained.

[0157] In the sixth embodiment, similarly to the third embodiment, the thermal stress generated at the end 11A of the plurality of first transistors 11 disposed directly below the first protrusion 41 on the side of the second protrusion 42 can be reduced. Since the impact of thermal stress from the third protrusion 43, which has a mesa structure without semiconductors directly below it, is relatively small, the first metal pattern 35 may not be disposed between the first protrusion 41 and the third protrusion 43. It should be noted that if the impact of thermal stress from the third protrusion 43 on reliability is significant, the first metal pattern 35 may be disposed between the first protrusion 41 and the third protrusion 43.

[0158] [Seventh Embodiment]

[0159] Next, refer to Figure 12 The semiconductor device of the seventh embodiment will be described below. Hereinafter, the semiconductor device of the first embodiment will be described. Figure 1 , Figure 2 , Figure 3 The common structure is omitted.

[0160] Figure 12 This is a diagram showing the planar positional relationship of the main components of the semiconductor device according to the seventh embodiment. In the first embodiment ( Figure 1 In the first embodiment, second protrusions 42 are arranged at intervals along the y-direction from the first protrusion 41. In contrast, in the seventh embodiment, no protrusions with a mesa structure on which semiconductors are arranged directly below are arranged, except for the first protrusion 41.

[0161] The first protrusion 41 is positioned at a point detached from the geometric center C of the substrate 10 when viewed from above. Furthermore, the region extending along the long side of the first protrusion 41 is also detached from the geometric center C. Additionally, in the x-direction, the geometric center C is located within the area B1x where the first protrusion 41 is disposed. When viewed from above, in a region closer to the geometric center C than the first protrusion 41, first metal patterns 35 are disposed at intervals from the first protrusion 41.

[0162] Compared with the semiconductor device of the first embodiment ( Figure 3Similarly, taking the upper surface of the substrate 10 as a height reference, the height of the center of the first metal pattern 35 in the thickness direction is higher than the upper surface of the mesa structure of the first transistor 11 and the second transistor 12, and lower than the lower surface of the first protrusion 41 and the second protrusion 42.

[0163] Next, the superior effects of the seventh embodiment will be explained.

[0164] Simulations conducted by the inventors of this application revealed that the stress applied to the first transistor 11 directly below the first protrusion 41, which is longer in one direction, is relatively large at the end 11A on the geometric center C side. In the seventh embodiment, by arranging the first metal pattern 35 in a region closer to the geometric center C side than the first protrusion 41, the thermal stress applied to the first transistor 11 can be reduced.

[0165] To achieve a sufficient effect in reducing thermal stress, it is preferable that the first metal pattern 35 is configured in the y-direction such that the overlap between the interval CBy from the first protrusion 41 to the geometric center C and the range My in which the first metal pattern 35 is configured occupies more than 1 / 2 of the interval CBy.

[0166] The above embodiments are illustrative, and of course, partial substitutions or combinations of the structures shown in different embodiments are possible. The same effects resulting from the same structures in multiple embodiments are not mentioned in each embodiment individually. Furthermore, the present invention is not limited to the above embodiments. For example, those skilled in the art will obviously be able to make various changes, improvements, combinations, etc.

Claims

1. A semiconductor device comprising: substrate; A plurality of first transistors are disposed on the upper surface of the substrate as one side and include a mesa structure made of semiconductors; A first protrusion is disposed at a position overlapping the plurality of first transistors in a top view, the shape of which is longer in one direction in a top view, and is connected to the plurality of first transistors; The second protrusion is arranged at intervals relative to the first protrusion in a direction orthogonal to the long side direction of the first protrusion; as well as A first metallic pattern, when viewed from above, is positioned between the first protrusion and the second protrusion. Using the upper surface of the substrate as a height reference, the height of the center of the first metal pattern in the thickness direction is higher than the upper surface of the mesa structure included by the plurality of first transistors, and lower than the lower surface of the first protrusion. In a direction orthogonal to the long side of the first protrusion, there are no other protrusions between the first protrusion and the second protrusion.

2. The semiconductor device according to claim 1, wherein, The semiconductor device further comprises a multilayer wiring structure disposed on the substrate and the plurality of first transistors, and includes a plurality of wiring layers. The first protrusion and the second protrusion are in contact with the metal pattern of the uppermost wiring layer of the multilayer wiring structure, the first metal pattern being disposed on the uppermost wiring layer of the multilayer wiring structure.

3. The semiconductor device according to claim 1 or 2, wherein, In the direction of the long side of the first protrusion, the first metal pattern is configured to occupy more than 1 / 2 of the area where the first protrusion is disposed.

4. The semiconductor device according to claim 1 or 2, wherein, In a direction orthogonal to the long side of the first protrusion, the first metal pattern occupies more than 1 / 2 of the area between the first protrusion and the second protrusion.

5. The semiconductor device according to claim 1 or 2, wherein, The semiconductor device further includes at least one second transistor, which is disposed at a position overlapping the second protrusion when viewed from above. The second transistor is disposed on the upper surface of the substrate and includes a mesa structure made of semiconductor.

6. The semiconductor device according to claim 5, wherein, Multiple second transistors are arranged in a direction parallel to the long side of the first protrusion. The second protrusion, when viewed from above, has a longer shape in a direction parallel to the long side of the first protrusion.

7. A semiconductor device comprising: substrate; A plurality of first transistors are disposed on the upper surface of one side of the substrate and include a mesa structure made of semiconductor; and A first protrusion is positioned to overlap with the plurality of first transistors in a top view, having an elongated shape in one direction and connected to the plurality of first transistors. The first protrusion and the region extending from the first protrusion along its long side are detached from the geometric center of the substrate when viewed from above. Furthermore, viewed from above, a first metallic pattern is present in a region closer to the geometric center than the first protrusion, and this first metallic pattern is arranged at a distance from the first protrusion. Using the upper surface of the substrate as a height reference, the height of the center of the first metal pattern in the thickness direction is higher than the upper surface of the mesa structure included by the plurality of first transistors, and lower than the lower surface of the first protrusion.

8. The semiconductor device according to claim 7, wherein, In a direction orthogonal to the long side of the first protrusion, the overlapping range of the interval from the first protrusion to the geometric center and the range where the first metal pattern is disposed occupies more than 1 / 2 of the interval from the first protrusion to the geometric center.

9. A semiconductor device comprising: substrate; A plurality of first transistors are disposed on the upper surface of the substrate as one side and include a mesa structure made of semiconductors; A first protrusion is disposed at a position overlapping the plurality of first transistors in a top view, the shape of which is longer in one direction in a top view, and is connected to the plurality of first transistors; The second protrusion is arranged at intervals relative to the first protrusion in a direction orthogonal to the long side direction of the first protrusion; as well as A first metallic pattern, when viewed from above, is positioned between the first protrusion and the second protrusion. Using the upper surface of the substrate as a height reference, the height of the center of the first metal pattern in the thickness direction is higher than the upper surface of the mesa structure included by the plurality of first transistors, and lower than the lower surface of the first protrusion. Along the long side of the first protrusion, the first metal pattern occupies more than half of the area where the first protrusion is disposed. In a direction orthogonal to the long side of the first protrusion, there are no other protrusions between the first protrusion and the second protrusion.

10. The semiconductor device according to claim 9, wherein, The semiconductor device further comprises a multilayer wiring structure disposed on the substrate and the plurality of first transistors, and includes a plurality of wiring layers. The first protrusion and the second protrusion are in contact with the metal pattern of the uppermost wiring layer of the multilayer wiring structure, the first metal pattern being disposed on the uppermost wiring layer of the multilayer wiring structure.

11. The semiconductor device according to claim 9 or 10, wherein, In a direction orthogonal to the long side of the first protrusion, the first metal pattern occupies more than 1 / 2 of the area between the first protrusion and the second protrusion.

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