Multi-core processing equipment, task allocation method, device and storage medium

Abstract

This application discloses a multi-core processing device, a task allocation method, an apparatus, and a storage medium. The multi-core processing device includes: multiple processing cores for executing tasks; and a task allocation circuit for allocating tasks to individual processing cores based on the current resource usage status of the multiple processing cores. This solution can improve core resource utilization.

Description

Technical Field

[0001] The present application relates to the field of information processing technology, and in particular to a multi-core processing device, a task allocation method, an apparatus, and a storage medium. Background Art

[0002] Currently, in hardware design, in order to improve the overall execution performance of the processor, a multi-core parallel design is adopted. A parent task is split into multiple subtasks and assigned to a group of cores for parallel execution. After all subtasks of the parent task are executed, the multiple cores are synchronized before the next subtask of the parent task can be assigned. This method is simple to design, but it will also cause the core that completes the task first to be idle and the core that is not assigned a task to be in an empty task state, thereby wasting core resources. Summary of the Invention

[0003] This application at least provides a multi-core processing device, task allocation method, device and storage medium.

[0004] In a first aspect, the present application provides a multi-core processing device, comprising: a plurality of processing cores for executing tasks; and a task allocation circuit for allocating tasks to a single processing core based on the current resource usage status of the plurality of processing cores.

[0005] Therefore, tasks can be flexibly assigned to processing cores for execution based on the resource usage of the processing cores, with each processing core as a unit. This avoids the situation where allocating tasks to all processing cores at the same time causes idle processing cores to be unable to receive tasks, thereby improving the utilization rate of processing core resources.

[0006] In some embodiments, the task allocation circuit is configured to allocate at least one task to the first processing core if the number of currently uncompleted tasks of the first processing core among the plurality of processing cores meets a task allocation condition.

[0007] Therefore, it is possible to allocate at least one task to the first processing core whose number of currently unfinished tasks meets the task allocation condition for execution. By setting the task allocation condition, the execution efficiency of the tasks can be improved.

[0008] In some embodiments, the device also includes an interface circuit for receiving task instructions of multiple tasks; the task allocation circuit is used to: allocate multiple tasks to a single processing core based on the task instructions of the multiple tasks and the current resource usage status of each processing core in the multiple processing cores.

[0009] Therefore, multiple tasks can be allocated to a single processing core.

[0010] In some embodiments, the plurality of tasks includes a plurality of child tasks of each of the at least one first parent task and / or the at least one second parent task.

[0011] Therefore, it is possible to allocate parent tasks and child tasks in units of a single processing core.

[0012] In some embodiments, the task allocation circuit allocates the multiple tasks, including: determining a task allocation order of the multiple tasks based on the parent tasks to which the multiple tasks respectively belong; and allocating the multiple tasks according to the task allocation order of the multiple tasks.

[0013] Therefore, the allocation is performed according to the task allocation order of the multiple tasks, wherein the allocation order of the multiple tasks is related to the parent tasks to which they belong.

[0014] In some embodiments, the task allocation order of at least two subtasks among multiple tasks that belong to the same parent task is determined based on the task reception order of the at least two subtasks; and / or the task allocation order of at least two tasks among multiple tasks that belong to different parent tasks is determined based on the priority of the parent tasks to which the at least two tasks belong.

[0015] Therefore, the order of task allocation can be determined according to the order in which the tasks are received and / or the priorities of their parent tasks.

[0016] In some embodiments, the device also includes: an identification determination circuit for determining the remapping identifications of at least two first tasks based on the parent tasks to which at least two first tasks belong among a plurality of tasks, wherein at least two first tasks belong to the same parent task; a status confirmation circuit for receiving the remapping identifications of at least two first tasks, and determining whether the parent tasks to which the at least two first tasks belong have been executed based on the remapping identifications of the at least two first tasks and the task execution status information of the at least two first tasks.

[0017] Therefore, it is possible to determine whether the parent tasks to which the at least two first tasks belong are completed according to the remapping identifiers of the at least two first tasks.

[0018] In some embodiments, the device also includes a first cache, including at least one kernel cache space; the task allocation circuit is also used to: determine the task sequence number of each task based on the task allocation order corresponding to each task in at least one task included in the parent task to which it belongs; the status confirmation circuit is also used to: receive the task sequence number sent by the task allocation circuit, and store the identification information of the task allocated to the first processing core in the kernel cache space corresponding to at least one first processing core among the multiple processing cores, the identification information of the task including the task sequence number and the remapping identification.

[0019] Therefore, it is possible to determine whether multiple subtasks belonging to the same parent task have been completed based on the task sequence number.

[0020] In some embodiments, the status confirmation circuit is further used to: receive a task completion indication sent by a second processing core among multiple processing cores, the task completion indication being used to indicate that the second task has been executed; and update the task execution status information of the second task based on the identification information of the second task stored in the core cache space corresponding to the second processing core.

[0021] Therefore, the completed tasks can be recorded based on the task execution status information.

[0022] In some embodiments, the device also includes a second cache, including at least one task cache space, for caching task execution status information of the task; the status confirmation circuit updates the task execution status information of the second task, including: based on the remapping identifier included in the identification information of the second task, obtaining the information of the task cache space of the parent task to which the second task belongs; based on the task sequence number included in the identification information of the second task, determining the target cache position corresponding to the task cache space of the parent task to which the second task belongs; and updating the task execution status information cached at the target cache position to indicate completion of execution.

[0023] Therefore, the corresponding task cache space and the target cache location can be determined based on the stored identification information, so that the task execution status information cached in the target cache location can be updated to indicate execution completion.

[0024] In some embodiments, the status confirmation circuit of the device is used to: cache the cache information of at least two subtasks belonging to the same parent task among multiple tasks into the task cache space of the parent task, wherein the cache information of the subtask includes status indication information indicating the current execution status of the subtask; and determine that the execution of the same parent task has been completed when it is determined based on the cache information of at least two subtasks that all subtasks included in the same parent task have been completed.

[0025] Therefore, it can be determined that the execution of the same parent task is completed when all subtasks included in the same parent task are completed according to the status indication information of the current execution status of at least two subtasks.

[0026] In some embodiments, the task cache space is a ring-shaped cache space.

[0027] In some embodiments, the cache information also includes a last subtask identifier indicating whether the subtask is the last subtask among at least two subtasks contained in the same parent task; the status confirmation circuit determines that the same parent task has been executed, including: when the first cache information in the cache space is read, determining that the same parent task has been executed, wherein the last subtask identifier included in the first cache information indicates that the subtask is the last subtask and the status indication information included in the first cache information indicates that the subtask has been executed.

[0028] Therefore, by reading the last subtask identifier to indicate that the subtask is the last subtask that has been completed, it is determined that the same parent task has been completed.

[0029] The second aspect of the present application provides a task allocation method, which is applied to a multi-core processing device, including: obtaining the current resource usage status of each processing core in multiple processing cores; and allocating tasks based on the current resource usage status of each processing core in the multiple processing cores in units of a single processing core.

[0030] A third aspect of the present application provides a task allocation device, comprising a memory and a processor, wherein the processor is configured to execute program instructions stored in the memory to perform the aforementioned method.

[0031] A fourth aspect of the present application provides a computer-readable storage medium storing program instructions that can be executed by a processor, the program instructions being used to implement the aforementioned method.

[0032] Therefore, tasks can be flexibly assigned to processing cores for execution based on the resource usage of the processing cores, with each processing core as a unit. This avoids the situation where allocating tasks to all processing cores at the same time causes idle processing cores to be unable to receive tasks, thereby improving the utilization rate of processing core resources.

[0033] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The drawings herein are incorporated into and constitute a part of the specification. These drawings illustrate embodiments consistent with the present application and, together with the specification, are used to illustrate the technical solutions of the present application.

[0035] Figure 1 is a schematic block diagram of an example of a multi-core processing device provided by the present application;

[0036] Figure 2 is a schematic block diagram of another example of a multi-core processing device provided by the present application;

[0037] Figure 3is a schematic block diagram of an example of a first buffer and a second buffer in a multi-core processing device provided by the present application;

[0038] Figure 4 This is a flowchart of an example of updating task execution status information in a multi-core processing device provided by the present application;

[0039] Figure 5 is a schematic block diagram of an example of a third buffer in a multi-core processing device provided by the present application;

[0040] Figure 6 This is a flowchart of an example of the task allocation method provided by this application;

[0041] Figure 7 is a flowchart of another example of the task allocation method provided by this application;

[0042] Figure 8 This application provides Figure 7 A schematic flow chart of another example of step S24;

[0043] Figure 9 This is a flowchart of another example of the task allocation method provided by this application;

[0044] Figure 10 This application provides Figure 9 A flowchart of another example of step S353;

[0045] Figure 11 This is a schematic diagram of an example of a task allocation device provided by the present application;

[0046] Figure 12 A schematic diagram of an example of a computer-readable storage medium provided in this application. DETAILED DESCRIPTION

[0047] The following describes the embodiments of the present application in detail with reference to the accompanying drawings.

[0048] In the following description, for the purpose of explanation rather than limitation, specific details such as specific system structures, interfaces, and technologies are provided to facilitate a thorough understanding of the present application.

[0049] The term "and / or" in this article is simply a description of the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent three situations: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects are in an "or" relationship. In addition, "many" in this article means two or more than two. In addition, the term "at least one" in this article means any combination of at least two of any one or more of a plurality of. For example, including at least one of A, B, and C can mean including any one or more elements selected from the set consisting of A, B, and C.

[0050] Currently, for example, a quad-core parallel processor typically divides a parent task into multiples of four subtasks along a certain dimension. Each subtask is added to the task queue of its corresponding core. When the dimension is not a multiple of four, the tasks corresponding to the remainder are added to the task queue of the last core. Since multiple cores are allocated simultaneously, the next allocation can only be made after all four cores have completed their subtasks. However, due to the different completion times of each subtask and the different number of subtasks required by each core, the core that completes its task first becomes idle. Furthermore, when the number of subtasks is less than the number of cores (four), at least one core will be in an empty task state. Therefore, even if there are idle cores, they cannot accept new subtasks, resulting in a waste of core resources.

[0051] See also Figure 1 , Figure 1 1 is a schematic block diagram of an example of a multi-core processing device provided in this application. The multi-core processing device can be a chip or other device type, which is not limited in the embodiments of this disclosure.

[0052] like Figure 1 As shown, the multi-core processing device 10 includes a plurality of processing cores 11 and a task allocation circuit 12. The task allocation circuit 12 is connected to the plurality of processing cores 11 respectively.

[0053] The processing core 11 can be used to execute tasks. Specifically, the processing core can be understood as a hardware unit capable of executing tasks, such as an accelerator. Generally, the multiple processing cores 11 can run in parallel to execute tasks. A task is a logical concept, and typically a task is a single execution of program code. For example, a single execution of program code is equivalent to a single execution of a task.

[0054] Generally, a processing core 11 can only execute one task at a time. Optionally, the number of processing cores 11 in the multi-core processing device 10 can be set according to actual conditions, for example, 4, 8 or 16. Figure 1As shown, in the embodiment of the present disclosure, the multi-core processing device 10 includes 1 to n processing cores 11.

[0055] The task allocation circuit 12 may be configured to allocate tasks to a single processing core 11 based on the current resource usage status of the multiple processing cores 11 .

[0056] It is understandable that currently tasks are assigned to multiple processing cores 11 simultaneously. Although some processing cores 11 have completed execution, they still have to wait for the tasks in other processing cores 11 to be completed before the next task can be assigned together. As a result, the processing cores 11 in the idle state cannot receive new subtasks, resulting in a waste of core resources. In this regard, the embodiment of the present disclosure assigns tasks based on a single processing core 11, avoiding the need to wait for the tasks in all processing cores 11 to be completed before assigning tasks, so that a single processing core 11 in the idle state can receive new tasks, thereby improving the utilization rate of core resources.

[0057] Optionally, the current resource usage status may be the number of currently unfinished tasks. For example, the greater the number of currently unfinished tasks, the higher the current resource usage rate of the processing core 11; the fewer the number of currently unfinished tasks, the lower the current resource usage rate of the processing core 11. Optionally, the currently unfinished tasks may include currently executing tasks and tasks in a queue of tasks waiting to be executed. Generally, a processing core 11 can only execute one task at a time, in which case the number of tasks assigned to each processing core is the number of tasks in the queue of tasks waiting to be executed plus one. In other embodiments, the currently unfinished tasks may also include only tasks in a queue of tasks waiting to be executed.

[0058] The above scheme, by allocating tasks based on a single processing core 11, can avoid waiting for the tasks in all processing cores 11 to be completed before allocating tasks, so that a single processing core 11 in an idle state can receive new tasks, thereby improving the utilization rate of core resources. Secondly, when allocating tasks, the current resource utilization status of multiple processing cores 11 is taken into consideration. Assigning tasks to a processing core 11 with a lower current resource utilization rate can improve the resource utilization rate of the processing core 11 and also improve the execution efficiency of tasks.

[0059] In some disclosed embodiments, the task allocation circuit 12 may also be configured to allocate at least one task to the first processing core 11 if the number of currently uncompleted tasks of the first processing core 11 among the multiple processing cores 11 meets a task allocation condition.

[0060] Optionally, the task allocation condition can be that the number of currently unfinished tasks is the least, that is, when the number of currently unfinished tasks of the first processing core 11 is the least among the multiple processing cores 11, at least one task is allocated to the first processing core 11. For example, a quad-core processing device includes processing cores A, B, C, and D, and the number of currently unfinished tasks of processing cores A, B, C, and D are 10, 50, 100, and 1000, respectively. Then, the processing core with the least number of currently unfinished tasks is A, so that the currently unassigned task can be assigned to processing core A so that the task can be executed more quickly. It can be understood that after the task is assigned to processing core A, the number of currently unfinished tasks of the processing core is 11, which is still the processing core with the least number of currently unfinished tasks among the four processing cores, so the next task can still be assigned to processing core A for execution.

[0061] Optionally, the task allocation condition can be less than a preset unfinished number, that is, when the number of currently unfinished tasks of a first processing core 11 among multiple processing cores 11 is less than the preset unfinished number, at least one task is allocated to the first processing core 11. It is understandable that the number of first processing cores 11 can be greater than 1 at this time. For example, when the preset unfinished number is 80, the current numbers of unfinished tasks of the above-mentioned processing cores A and B are 10 and 50, respectively. It can be seen that the current numbers of unfinished tasks of the above-mentioned processing cores A and B are both less than the preset unfinished number, so at least one task can be allocated to each processing core A and B to enable tasks to be executed more quickly. Optionally, a first processing core that meets the task allocation condition can be randomly selected to be assigned a task.

[0062] In some disclosed embodiments, Figure 2 As shown, the device may further include an interface circuit 23, which is configured to receive task instructions subtask_ins for multiple tasks. Optionally, the interface circuit 23 may include one or more sets (e.g., X sets) of task interfaces, which may receive task instructions for multiple tasks from different sources in parallel. The task interfaces may be physical interfaces or virtual interfaces.

[0063] Optionally, the multiple tasks may include multiple subtasks of each of at least one first parent task and / or at least one second parent task. A parent task may be split into several subtasks, and the multiple subtasks may be processed in parallel by multiple processing cores 11 to improve the processing efficiency of the parent task. Alternatively, the parent task may not be split, and the unsplit parent tasks may be processed by a single processing core 11, such as some parent tasks of file compression software, some gaming software tasks, and so on. In the embodiments of the present disclosure, for ease of description, parent tasks and subtasks are collectively referred to as tasks.

[0064] After receiving the task instructions of the multiple tasks, the task allocation circuit 12 is configured to allocate the multiple tasks to a single processing core 11 based on the task instructions of the multiple tasks and the current resource usage status of each of the multiple processing cores 11 .

[0065] In some disclosed embodiments, the task allocation circuit 12 allocates the multiple tasks, including: determining a task allocation order of the multiple tasks based on the parent tasks to which the multiple tasks respectively belong; and allocating the multiple tasks according to the task allocation order of the multiple tasks.

[0066] The parent task of a task can be itself or another task. For example, if task A is a child task of task B, then the parent task of task A is task B, and the parent task of task B is itself.

[0067] Optionally, the order in which at least two subtasks belonging to the same parent task are assigned to a plurality of tasks may be determined based on the order in which the at least two subtasks are received. For example, the subtask received first by the interface circuit 23 may be assigned first. For another example, the subtask received first by the interface circuit 23 may be assigned later.

[0068] Optionally, the order of task allocation for at least two tasks belonging to different parent tasks among the plurality of tasks is determined based on the priorities of the parent tasks to which the at least two tasks belong. Specifically, the parent task with a higher priority may be allocated first, and the parent task with a lower priority may be allocated after the higher priority task has been allocated, so that the parent task with a higher priority can be executed by the processing core 11 first. The priority may be, but is not limited to, determined by Quality of Service (QoS).

[0069] For example, a multi-core processing device 10 receives tasks A, B, C, and D in sequence. Tasks A, B, C, and D are assigned to a waiting-for-execution task queue of a processing core 11. Task A and Task B belong to the same parent task, so Task A and Task B have the same priority. Task C has a lower priority than Task B, and Task D has no priority set. When Tasks A, B, C, and D are sequentially added to the queue, the order of task assignment is determined based on the aforementioned order of receipt and priority. Task A is added to the first position of the queue, and Task B is added after Task A. Task C has a lower priority than Task B, so Task C is added after Task B. Task D has no priority and is added to the last position of the queue in order. If the preset priorities of the tasks are the same, the tasks can be added to the waiting-for-execution task queue of the first processing core 11 according to the order in which they are received. For example, the task received first in the waiting-for-execution task queue is ranked before the task received later and can be executed first by the processing core 11. The target processing core 11 can be determined based on the current resource usage status of the multiple processing cores 11.

[0070] In one application scenario, the front end is the end that sends the task instructions, which can be specifically a device end or a software end. Generally, after receiving the user instructions, the front end will generate and send the task instructions of multiple tasks to the multi-core processing device 10, and the multi-core processing device 10 will process the multiple tasks and return the processing results. Among them, the task instructions of the multiple tasks will first be received by the interface circuit 23 of the multi-core processing device 10, and then sent to the task allocation circuit 12. The task allocation circuit 12 will allocate the multiple tasks to a single processing core 11 based on the task instructions of the multiple tasks and the current resource usage status of each processing core 11 in the multiple processing cores 11. After the processing core 11 completes the task processing, it will return the processing results to the front end.

[0071] The above scheme, by setting up an interface circuit to receive task instructions of multiple tasks, can allocate multiple tasks to a single processing core based on the task instructions of the multiple tasks and the current resource usage status of each processing core in the multiple processing cores, thereby improving the resource utilization rate of the processing core.

[0072] Furthermore, by allocating tasks to processing cores where the number of currently unfinished tasks meets the task allocation condition, where the task allocation condition is that the number of currently unfinished tasks is the least or less than the preset unfinished number, the task can be executed faster, thereby improving the completion efficiency of the task. By presetting the priority, tasks with the preset priority can be allocated to the target processing core for execution first, thereby improving the completion efficiency of the task.

[0073] Furthermore, the multiple tasks include multiple subtasks of each second parent task in at least one first parent task and / or at least one second parent task. Different parent tasks and subtasks can be executed simultaneously in multiple cores, enabling task allocation for mixed situations of parent tasks and subtasks.

[0074] See also Figure 2 , Figure 2 This is a schematic block diagram of another example of a multi-core processing device provided by this application.

[0075] like Figure 2 As shown, in the embodiment of the present disclosure, the multi-core processing device 20 further includes an identification determination circuit 24 and a state confirmation circuit 25. The identification determination circuit 24 is connected to the interface circuit 23 and the task allocation circuit 22, and the state confirmation circuit 25 is connected to the interface circuit 23, the task allocation circuit 22, and the multiple processing cores 21.

[0076] The identifier determination circuit 24 is configured to determine the remapping identifiers sid of at least two first tasks based on parent tasks to which at least two first tasks in the plurality of tasks belong, wherein the at least two first tasks belong to the same parent task.

[0077] Alternatively, the identifier determination circuit 24 may determine the remapping identifier of each task according to the parent task to which each task belongs. Alternatively, the identifier determination circuit 24 may remap only at least two tasks that are subtasks in the multiple tasks to obtain their corresponding remapping identifiers.

[0078] Optionally, the identification determination circuit 24 can determine the remapping identification of the at least two first tasks based on the first identification information of the at least two first tasks. The first identification information is used to identify each task, and generally the first identification information can be assigned to the task when the task is generated. Specifically, the first identification information can be extracted from the received task instruction. In some embodiments, the first identification information of at least two first tasks belonging to the same parent task is the same, and the first identification information of at least two first tasks belonging to different parent tasks is different. The first identification information can be, but is not limited to, numbers and / or characters. Optionally, the first identification information can be a hexadecimal, decimal, octal and binary number.

[0079] Optionally, the task instructions of each of the multiple tasks sent by the front end carry the first identification information before being received by the multi-core processing device 20, that is, the first identification information is assigned by the outside (upstream module) of the multi-core processing device 20, and the identification determination circuit 24 can obtain the first identification information of each task from the task instructions of each task, and determine the remapping identifications of at least two first tasks based on the first identification information. Alternatively, the task instructions of the multiple tasks can also be assigned the first identification information after being received by the multi-core processing device 20, for example, the first identification information can be assigned in the interface circuit 23, and then the task instructions carrying the first identification information are sent to the identification determination circuit 24.

[0080] For example, parent task A is split into multiple subtasks a1 to a4 before entering the multi-core processing device 20. The parent task of multiple subtasks a1 to a4 is the same parent task A, so the first identification information id of multiple subtasks a1 to a4 is the same and is equal to 1. The identification determination circuit 24 determines the remapping identification sid=1 of at least two first tasks based on the first identification information id=1 of multiple tasks a1 to a4. Since the parent task B is not split, the parent task B does not need to perform identification remapping. In other embodiments, the parent task B can also perform identification remapping, and the first identification information id of the parent task B is 2. Correspondingly, the remapping identification sid=2 of the parent task B.

[0081] In some embodiments, a parent task can be split into subtasks of the same type, and these subtasks do not need to interact with each other. For example, a data transfer DMA task can be split into multiple smaller DMA subtasks and sent to the multi-core processing device 20 for processing to improve the processing efficiency of the parent task. Because these multiple DMA subtasks all originate from the same data transfer DMA task, the first identification information of the multiple DMA subtasks is the same, and thus the remapping identification is also the same.

[0082] It is understandable that since the number of tasks received by the device is innumerable, if a single task is directly assigned to the processing core 21, the burden on the system will increase. Therefore, multiple tasks can be divided into limited task categories, thereby reducing the burden on the system and saving system resources. Among them, tasks with the same remapping identifier belong to the same task category, that is, tasks in the same task category have the same remapping identifier. In the embodiment of the present disclosure, the remapping identifiers of at least two first tasks belonging to the same parent task are the same, that is, they belong to the same task type. Optionally, at least two first tasks belonging to different parent tasks may also belong to the same task type, which is not limited here.

[0083] In some embodiments, the task issuer is the task source of the multi-core processing device 20. Optionally, the task issuer can be the generator of the task instruction, wherein the generator of the task instruction is, for example, a browser or an application, and different task issuers can be different browsers or applications, or the task issuer can also be a task interface for the multi-core processing device 20 to receive tasks, and different task issuers can be different task interfaces. Therefore, when multiple tasks are divided into task categories, tasks from the same task issuer can be first divided into the same task category, and then tasks from different task issuers can be further divided into at least one task category based on the first identification information.

[0084] For example, task A and task B come from the same task interface, and task C comes from another task interface, so task A and task B can be preliminarily divided into the same task category, and task C can be divided into another task category. Furthermore, further division can be performed based on the first identification information of the task to divide the subtasks split from the same parent task into the same task category, where the first identification information id of task A is 1, the first identification information id of task B is 2, and the first identification information of task C is id=1. Since the first identification information of task A and task C is the same, it can be determined that task A and task C are split from the same parent task, so it can be determined that the remapping identifiers of task A and task C are the same, for example, sid=1, that is, task A and task C are divided into the same task category. In summary, through the above division, task A, task B and task C belong to the same task category.

[0085] In other embodiments, multiple tasks can also be divided into at least one task category by determining whether the multiple tasks are related. Generally, multiple related tasks originate from the same parent task. Specifically, it is possible to determine whether multiple tasks carry related information based on the information carried in the tasks. If multiple tasks carry related information, it is determined that the multiple tasks are related. Furthermore, the related tasks among multiple tasks can be divided into one task type, and unrelated tasks can be divided into different task types. For example, it is possible to determine whether there is a successive execution order between multiple tasks based on the time information or character information carried in the tasks. If there is a successive execution order, the multiple tasks can be divided into the same task category, and the remapping identifiers of the same task category are the same.

[0086] It is understandable that, under the premise of classifying the subtasks split from the same parent task into the same task category, there can be multiple division methods, which are not limited here.

[0087] The status confirmation circuit 25 is configured to receive the remapping identifiers of at least two first tasks and determine whether the parent tasks to which the at least two first tasks belong are completed based on the remapping identifiers of the at least two first tasks and the task execution status information of the at least two first tasks.

[0088] It can be understood that the remapping identifiers of at least two first tasks belonging to the same parent task are the same, and the remapping identifiers of at least two first tasks of different parent tasks are different. Therefore, based on the remapping identifiers of the at least two first tasks and the task execution status information of the at least two first tasks, it can be determined whether the parent tasks to which the at least two first tasks belong have been executed. In this way, the subtasks split from the same parent task can also return the task completion signal in order, and further enable the tasks to be allocated to the processing core 21 for execution in a disorderly order when being allocated, without having to be allocated to the core for execution in the order in which the tasks are received, which can improve the flexibility of task allocation.

[0089] In some embodiments, since multiple tasks are divided into at least one task category, the tasks in the same task category carry the same remapping identifier, so the same remapping identifier and the task execution status information of multiple tasks can be used to determine whether the tasks in the same task category have all been completed, so that the tasks in the same category can return a task completion signal in order. Among them, since the subtasks split from the same parent task are divided into the same task category, when it is determined that multiple tasks in the same task category have been completed, it is inevitable that the parent tasks to which at least two first tasks in the task category belong have also been completed, so that the subtasks split from the same parent task can also return a task completion signal in order, further making it possible to allocate tasks to the processing core 21 for execution in a random order when allocating tasks, without having to allocate them to the core in the order in which the tasks were received, thereby improving the flexibility of task allocation.

[0090] The above scheme determines the remapping identifiers of at least two first tasks based on the parent tasks to which at least two first tasks belong among multiple tasks through an identification determination circuit, wherein at least two first tasks belong to the same parent task, and then the status confirmation circuit determines whether the parent tasks to which at least two first tasks belong have been executed based on the remapping identifiers of the tasks and the task execution status information of at least two first tasks.

[0091] Furthermore, the remapping identifiers of the at least two first tasks may be determined according to the first identification information of the at least two first tasks.

[0092] Furthermore, by dividing multiple tasks into at least one task category, the tasks in the same task category carry the same remapping identifier, which not only allows the tasks in the same task category to be assigned to the processing core for execution in disorder, but also allows the task completion signal to be returned to the front end in an order-preserving manner.

[0093] See also Figures 2 to 5 , Figure 3 is a schematic block diagram of an example of a first cache and a second cache in a multi-core processing device provided by the present application. Figure 4 This is a schematic diagram of an example process for updating task execution status information in a multi-core processing device provided by this application. Figure 5 This is a schematic block diagram of an example of a third cache in a multi-core processing device provided by this application.

[0094] In the embodiment of the present disclosure, the task allocation circuit 22 is further configured to determine a task sequence number for each task based on a task allocation order corresponding to each task in at least one task included in its parent task.

[0095] Optionally, the order in which each task within the same parent task is assigned to the kernel can be recorded by counting to obtain a task sequence number. The counting method can be sequential cumulative counting or cyclic cumulative counting, for example, when the recorded value exceeds a preset threshold, cyclic counting is performed. For example, if the preset threshold is 10,000 and the currently recorded value is 10,000, the count will restart from 1 when counting the next task.

[0096] Optionally, counting can be performed using a counter. If it is detected that a task in the same parent task is assigned to the kernel, the counter is incremented by 1, and the corresponding task number is also incremented by 1. Optionally, each parent task corresponds to a counter, and the counters corresponding to different parent tasks do not affect each other. In other embodiments, different parent tasks can also use the same counter, for example, when different parent tasks are assigned to the processing kernel 11 in a time-sharing manner, or the counter supports parallel counting of multiple parent tasks without affecting each other. Among them, tasks with different task numbers have different cache locations in the corresponding task cache space 371.

[0097] In other implementations, the order in which each task of the same task type is assigned to the core may also be recorded by counting to obtain a task sequence number, which will not be described in detail here.

[0098] In the embodiment of the present disclosure, the multi-core processing device 20 further includes a first cache 36, which includes at least one kernel cache space 361. Optionally, each processing core 21 has a corresponding kernel cache space 361. Optionally, the type of the first cache 36 can be a first-in-first-out memory, such as a FIFO (First Input First Output) memory. Figure 3 As shown, the first cache 36 includes n kernel cache spaces 361, where n is any positive integer.

[0099] The status confirmation circuit 25 is further configured to receive the task sequence number sent by the task allocation circuit 22 and store the identification information of the task allocated to the first processing core 21 in the core cache space 361 corresponding to at least one first processing core 21 among the multiple processing cores 21. The identification information of the task includes the task sequence number and the remapping identifier. Figure 3 As shown, the status confirmation circuit 25 receives the task sequence number id_cnt sent by the task assignment circuit 22 and stores the identification information assigned to the first processing core 21, namely, the task sequence number id_cnt and the remapping identifier sid, in the kernel cache space 361 corresponding to at least one first processing core 21 among the n processing cores 21. It will be appreciated that after assigning a task to a processing core 21, the task assignment circuit 22 records the identifier of the first processing core 21 corresponding to the task. Based on the identifier of the first processing core 21, the status confirmation circuit 25 can, upon receiving the task sequence number id_cnt sent by the task assignment circuit 22, locate the kernel cache space 361 corresponding to the identifier of the first processing core 21, and thereby store the identification information assigned to the first processing core 21 in the kernel cache space 361.

[0100] Furthermore, after the processing core 21 completes the task, it returns a task completion indication subtask_ack, which is used to indicate that the second task has been completed. The status confirmation circuit 25 is also used to: receive a task completion indication sent by the second processing core 21 among the multiple processing cores 21; and update the task execution status information of the second task based on the identification information of the second task stored in the kernel cache space 361 corresponding to the second processing core 21. Figure 3 As shown, the status confirmation circuit 25 receives the task completion indication subtask_ack2 sent by the second processing core 21, wherein the second processing core 21 is the processing core 21 that completes the execution of the task among the n processing cores 21; then, based on the task sequence number id_cnt and the remapping identifier sid of the second task stored in the kernel cache space 361 corresponding to the second processing core 21, the task execution status information of the second task is updated to record that the second task has been completed.

[0101] Optionally, the multi-core processing device 20 further includes a second cache 37, which includes at least one task cache space 371 for caching task execution status information. Optionally, the second cache 37 can be a buffer. A buffer is a buffer register, which can be divided into two types: input buffers and output buffers. The former temporarily stores data sent from peripheral devices so that the processor can retrieve it; the latter temporarily stores data sent from the processor to peripheral devices. With a digitally controlled buffer, a high-speed CPU can coordinate and buffer with slower-speed peripherals, achieving synchronized data transmission.

[0102] Alternatively, as Figure 3 As shown, the task cache space 371 can be a circular cache space. The task cache space 371 has at least two sets of write pointers wptr and one set of read pointers rptr.

[0103] For example, Figure 4 As shown, before the second task is assigned to the second processing core 21 for execution, the task execution status information of the second task in the task cache space 371 defaults to a first status value, such as ACK_INVALID, indicating that it has not been executed; after the second task is assigned to the second processing core 21 for execution, the task execution status information is updated to a second status value indicating that the task has not been completed, such as ACK_WAIT, to indicate that the second task has been executed in the second processing core 21, but has not yet been completed. After receiving a task completion indication sent by the second processing core 21 among multiple processing cores 21, the task execution status information is updated to a third status value, such as ACK_VALID, to indicate that execution is complete.

[0104] Specifically, the status confirmation circuit 25 updates the task execution status information of the second task, including: obtaining information of the task cache space 371 of the parent task to which the second task belongs based on the remapping identifier included in the identification information of the second task; determining the target cache position corresponding to the second task in the task cache space 371 of the parent task to which it belongs based on the task sequence number included in the identification information of the second task; and updating the task execution status information cached at the target cache position to indicate completion of execution.

[0105] The status confirmation circuit 25 of the device is used to: cache the cache information send_cmd of at least two subtasks belonging to the same parent task in multiple tasks into the task cache space 371 of the parent task, wherein the cache information of the subtask includes status indication information indicating the current execution status of the subtask; when it is determined based on the cache information of at least two subtasks that all subtasks included in the same parent task have been executed, it is determined that the same parent task has been executed.

[0106] In some embodiments, the cache information also includes a last subtask identifier that indicates whether the subtask is the last subtask among at least two subtasks contained in the same parent task. The last subtask identifier is already carried before the device receives the task, and the last subtask identifier can be obtained by obtaining the task instruction of the task. For example, when a parent task is split into multiple subtasks, first identification information is added to the multiple subtasks, and a last subtask identifier is added to the last subtask, and the task instruction can always carry the first identification information and the last subtask identifier to be able to identify the task in the device.

[0107] The status confirmation circuit 25 determines that the same parent task has been completed, including: determining that the same parent task has been completed when first cache information in the cache space is read, wherein the last subtask identifier included in the first cache information indicates that the subtask is the last subtask and the status indication information included in the first cache information indicates that the subtask has been completed. The last subtask identifier can be used to determine whether all subtasks of the same parent task have been completed. Only after it is determined that all subtasks have been completed will a task completion signal be fed back, so that the subtasks in the same parent task can maintain the order of feeding back task completion signals.

[0108] Optionally, the cache information of the tasks in the task cache space 37 can be read sequentially. If the task execution status information in the cache information of the current reading position is the third status value, the cache information of the next read target cache position is continued to be read until the task execution status information in the read cache information is the third status value and the cache information contains the last subtask identifier, then it is determined that all subtasks of the same parent task in the task category have been executed.

[0109] In some embodiments, the same task type includes multiple subtasks derived from a parent task, that is, there is only one last subtask identifier in the cache information of all tasks. In other embodiments, the same task type includes multiple tasks derived from multiple parent tasks, that is, there are multiple last subtask identifiers in the cache information of all tasks. Regardless of whether the same task type includes one parent task or multiple parent tasks, when the task execution status information in the read cache information is the third state value and the cache information contains the last subtask identifier, it is determined that all subtasks of the same parent task in the task category have been executed.

[0110] When a parent task is not split before being received by the multi-core processing device 20, the parent task may or may not carry the last subtask identifier. When the parent task carries the last subtask identifier, the parent task can return a task completion signal independently after execution. When the parent task does not carry the last subtask identifier, the parent task must wait until all subsequent tasks in the parent task are completed before returning a task completion signal.

[0111] Optionally, the status confirmation circuit 25 can be connected to the interface circuit 23, so that the task completion signal returned by the status confirmation circuit 25 can be directly returned to the front end through the interface circuit 23; or, the task completion signal returned by the status confirmation circuit 25 can pass through the identification determination circuit 24 and then be returned to the front end through the interface circuit 23. Since multiple parent tasks may be executed and completed at the same time, a feedback mechanism after task completion can be designed through the identification determination circuit 24 to avoid conflicts when the task completion signal is returned from the interface. Figure 5As shown, the identification confirmation circuit 24 may be connected to a third buffer 38, which is used to buffer the first execution state of each task according to the remapping identification. The third buffer 38 is, for example, a FIFO buffer.

[0112] Optionally, the first execution status of each task in the third buffer 38 can be polled in sequence according to the order in which the tasks are received, or the first execution status of each task can be polled first according to the preset priority of the task, for example, the first execution status of the task with a high priority in the task category is polled first, and then the first execution status of each task is polled according to the order in which the tasks are received.

[0113] For example, a task category includes tasks A, B, C, D, X, and Y. Tasks A, B, C, and D belong to the same parent task. In response to the completion of all tasks of the same parent task in the task category (i.e., tasks A, B, C, and D), the first execution status of tasks A, B, C, and D is updated from the fourth status value to the fifth status value, that is, the first execution status corresponding to tasks A, B, C, and D is changed from 0 to 1, indicating that tasks A, B, C, and D have been completed. The first execution status of each task is polled. Since task C has priority, the first execution status of task C is polled first. If the first execution status of task C is 1, a completion signal of task C is fed back to the front end. After the polling of the priority task is completed, the first execution status of each remaining task is polled in sequence according to the order in which the tasks are received, that is, the first execution status of tasks A, B, and D is polled in sequence. If the first execution status of tasks A, B, and D are all 1, completion signals are fed back to the front end in sequence. The first execution status of the task is recorded as the fourth status value to indicate that the task has not been completed. Further, when all tasks of the same parent task in the task category are completed, the fourth status value can be updated to the fifth status value to indicate that the task has been completed.

[0114] In addition, the fourth state value and the fifth state value can be any number or character and are not limited here.

[0115] Optionally, different task categories can determine in parallel whether all tasks of the same parent task have been completed, and in response to the completion of all tasks of the same parent task in different task categories, the completion signals of the corresponding tasks under the task category can be fed back to the front end in parallel. Each task category can return a completion signal independently, with complementary effects. Optionally, different task categories can return a completion signal according to the interface corresponding to the received task, that is, it will be returned from the interface from which it is received. Furthermore, different task categories can also return completion signals in sequence according to the order in which the tasks are received, for example, they will be returned in sequence according to the order in which they are received, with the task received first being returned first. In addition, tasks received in parallel by multiple interfaces can also return completion signals of corresponding tasks in parallel, and tasks received by the same interface will return completion signals of corresponding tasks in the order in which they are received. For example, one task category includes tasks A, B, C, and D. Tasks A, B, C, and D belong to the same parent task. Tasks A and B are received from interface 1, task C is received from interface 2, and task D is received from interface 3. Another task category includes tasks E and F. Tasks E and F belong to the same parent task. Task E is also received from interface 2 after task C, and task F is received from interface 4. At the same time, the tasks in the above two task categories are all completed. The order of task reception is tasks A, B, C, E, D, and F. Since tasks A, C, D, and F correspond to different interfaces, tasks A, C, D, and F can return completion signals in parallel. Since tasks A and B belong to the same interface and task B is received after task A, task B needs to return a completion signal after task A. Similarly, although tasks C and E belong to different task categories, they can also be returned in order, that is, the completion signal of task C is returned first, and the completion signal of task E is returned later.

[0116] The above scheme determines the task sequence number of each task based on the task allocation order corresponding to each task in at least one task included in the parent task to which it belongs, receives the task sequence number sent by the task allocation circuit, and stores the identification information of the task allocated to the first processing core in the core cache space corresponding to at least one first processing core among the multiple processing cores. This can realize the judgment of whether multiple subtasks belonging to the same parent task have been executed according to the task sequence number of the task.

[0117] Furthermore, by receiving a task completion indication sent by the second processing core among multiple processing cores, the task completion indication is used to indicate that the second task has been executed; based on the identification information of the second task stored in the kernel cache space corresponding to the second processing core, the task execution status information of the second task is updated, so that the tasks that have been executed can be recorded.

[0118] Furthermore, the corresponding task cache space and target cache location can be determined based on the identification information stored in the kernel cache space, so that the task execution status information cached in the target cache location can be updated to indicate execution completion.

[0119] Furthermore, based on the status indication information of the current execution status of at least two subtasks, it can be determined that the same parent task has been completed when all subtasks included in the same parent task have been completed, and it can be determined that the same parent task has been completed when the last subtask identifier is read to indicate that the subtask has been completed.

[0120] Please continue reading Figures 2 to 5 For ease of understanding, the implementation process of the multi-core processing device described above will be described below with specific examples.

[0121] Interface circuit 23 includes X sets of task interfaces, which receive task instructions (subtask_ins) and first identification information (id) for multiple tasks sent by the front end, and output subtask_ins and id to identification determination circuit 24 for identification remapping to obtain a remapped identification (sid). The tasks received by interface circuit 23 include parent tasks and subtasks. Multiple subtasks split from the same parent task carry the same first identification information, meaning that tasks with the same first identification information belong to the same parent task. The last subtask among multiple subtasks split from the same parent task carries the last subtask identification. Unsplit parent tasks may also carry the last subtask identification.

[0122] The identification determination circuit 24 inputs subtask_ins and id, and outputs subtask_ins and a remapping identification sid. The identification determination circuit 24 can identify and remap multiple tasks according to the id. Since tasks with the same id belong to the same parent task, tasks with the same id can be divided into the same category to achieve the classification of tasks split from the same parent task into the same task category, thereby enabling the subtasks of the same parent task to return task completion signals in disorder. In addition, in order to save system resources, subtasks of different parent tasks can also be divided into the same task category. The remapping identifications of subtasks of different parent tasks after remapping can also be the same.

[0123] The task allocation circuit 22 inputs subtask_ins and sid and outputs cache information send_cmd and subtask_ins. Each time the task allocation circuit 22 sends a task to the processing core 21, it outputs the corresponding task's cache information send_cmd to the status confirmation circuit 25. The cache information includes sid, status indication information of the task execution status, task sequence number id_cnt, the first processing core identifier, and the last subtask identifier. Each parent task (or task type) in the task allocation circuit 22 corresponds to a counter. Each time a task is sent to the processing core 21, the counter of the corresponding parent task (or task type) is incremented by 1, obtaining the task sequence number of the task. This records the order in which the task is assigned to the processing core 21 for execution within the corresponding parent task (or task type), i.e., the number of the parent task (or task type) assigned to the processing core 21 for execution. Among them, the task allocation circuit 22 can determine the first processing core 21 to execute the task based on the number of assigned tasks of each processing core 21, that is, the storage waterline of the instruction queue of each processing core 21, and add the task to the waiting execution task queue of the first processing core 21. The waiting execution task queue can be in the task allocation circuit 22. When the execution completion signal returned by the first processing core 21 is received, the task at the first position in the waiting execution task queue is sent to the processing core 21 for execution. subtask_ins is input to the corresponding processing core 21 for execution. After the execution is completed, the processing core 21 will return a task completion indication subtask_ack. Figure 2 As shown, the multi-core processing device 20 includes n processing cores 21, namely processing cores 1 to n. At each moment, each processing core 21 receives a subtask_ins and returns a task completion indication subtask_ack.

[0124] The status confirmation circuit 25 inputs the task completion indication subtask_ack xn and send_cmd returned by the n processing cores 21, and outputs a task completion signal task_ack xm. Wherein, subtask_ack xn indicates which processing core 21 among the n processing cores 21 the task completion indication corresponds to. Figure 3As shown, the task cache space 371 (ack_merge_buf) has two sets of write pointers wptr and one set of read pointers rptr. The status confirmation circuit 25 receives send_cmd and, on the one hand, determines the task cache space 371 of the task category corresponding to each task and the target cache position in the task cache space 371 of the corresponding task category according to the task sequence number sid and id_cnt in the cache information, and writes the task execution status information and the last identification information in the cache information to the target cache position of the corresponding task category through the write pointer wptr=id_cnt. At this time, the task execution status information is the second state value, as shown in FIG. Figure 4 As shown, the second status value is, for example, ACK_WAIT, indicating that the task has not been completed. On the other hand, before receiving subtask_ack xn, the id_cnt and sid in the cache information of the task are stored in the kernel cache space 361. Each processing core 21 corresponds to a kernel cache space 361, and different processing cores 21 correspond to different kernel cache spaces 361. When the processing core 21 returns subtask_ack xn to the corresponding kernel cache space 361, the id_cnt and sid stored corresponding to the processing core 21 can be obtained from the kernel cache space 361. Based on the obtained sid, the task cache space 371 corresponding to the task category can be determined. Based on the obtained id_cnt, the target cache location in the corresponding task cache space 371 can be determined, so that the task execution status information corresponding to the target cache location is updated to a third status value. The third status value is, for example, ACK_VALID, indicating that the task has been completed.

[0125] Specifically, when the processing core 21 returns subtask_ack xn to the corresponding kernel cache space 361, a write instruction ack_wen is generated. ack_wen is used to control another write pointer wptr=sel_id_cnt of the task cache space 371 to write the task execution status information in the cache information to the target cache location of the corresponding task category. At this time, the task execution status information is the third state value.

[0126] like Figure 4As shown, before receiving the status indication information in send_cmd, the task execution status information of the task defaults to the first status value ACK_INVALID; after receiving the status indication information in send_cmd, it means that the task has been sent to the processing core 21 for execution, then the task execution status information of the task is updated to the second status value ACK_WAIT indicating that the task has not been completed; when the task completion indication of the task is received from the processing core 21, the task execution status information of the task is updated to the third status value ACK_VALID indicating that the task has been completed; after returning the completion signal of the task to the identification determination circuit 24, the third status value ACK_VALID is further restored to the unexecuted status value ACK_INVALID through the instruction read_en.

[0127] Furthermore, the read pointer rptr of the task cache space 371 is used to point to the target cache location of the task in the task cache space 371 of the task category to read the cache information in the target cache location. Optionally, the read pointer rptr can start reading from the smallest id_cnt and can sequentially read the cache information of the tasks in the task cache space 371 of the task category. If the task execution status information in the cache information of the current read position is the third state value, the cache information of the next read position will continue to be read until the task execution status information in the read cache information is the third state value and the cache information contains the last subtask identifier, then it is determined that all subtasks of the same parent task in the task category have been completed, and the corresponding task completion signal task_ack xm is output.

[0128] The identification determination circuit 24 inputs sid and task_ack xm, and outputs a task completion signal resp+id with an id. resp+id can be returned from the corresponding interface in the X socket. Figure 5 As shown, valid_cnt indicates that the first execution state is the fourth state value. When a task instruction is received, the first execution state of the task is recorded as the fourth state value 0 in the identification determination circuit 24. When a task completion signal task_ack xm of a certain task type is received, the first execution state of the corresponding task is updated to the fifth state value 1, that is, valid_cnt = 1, and valid_cnt = 1 is stored in the FIFO memory id_fifo. The first execution state of each task is polled sequentially or according to a preset priority. A completion signal is generated for the task with the first execution state 1, and the completion signal resp+id of the task is fed back to the front end. After the completion signal is fed back to the front end, the first execution state is restored to the first state value 0. The memory id_fifo for different task types can feed back completion signals in parallel.

[0129] See also Figure 6, Figure 6 The following is a flow chart illustrating an example of the task allocation method provided herein. In the disclosed embodiments, the task allocation method is applied to a multi-core processing device, which includes multiple processing cores, such as, but not limited to, the multi-core processing device described in the aforementioned embodiments. Furthermore, the execution entities of each step of this method may be, but are not limited to, the corresponding circuits in the aforementioned multi-core processing device embodiments.

[0130] The method may specifically include the following steps:

[0131] Step S11: obtaining the current resource usage status of each processing core among the multiple processing cores.

[0132] Step S12: Based on the current resource usage status of each processing core among the multiple processing cores, tasks are allocated in units of a single processing core.

[0133] In some disclosed embodiments, task allocation is performed on a per-processing core basis based on a current resource usage status of each of the plurality of processing cores, including allocating at least one task to the first processing core if the number of currently uncompleted tasks of the first processing core among the plurality of processing cores satisfies a task allocation condition.

[0134] See also Figures 7 and 8 , Figure 7 This is a flowchart of an example of the task allocation method provided by this application. Figure 8 This application provides Figure 7 Schematic diagram of another example of step S24 in FIG.

[0135] The method may specifically include the following steps:

[0136] Step S21: receiving task instructions of multiple tasks.

[0137] Step S22: determining remapping identifiers of at least two first tasks based on parent tasks to which at least two first tasks in the plurality of tasks belong, wherein the at least two first tasks belong to the same parent task.

[0138] Step S23: obtaining the current resource usage status of each processing core among the multiple processing cores.

[0139] Step S24 : allocating the multiple tasks to a single processing core based on the task instructions of the multiple tasks and the current resource usage status of each of the multiple processing cores.

[0140] Step S25: Based on the remapping identifiers of the at least two first tasks and the task execution status information of the at least two first tasks, determining whether the parent tasks to which the at least two first tasks belong are completed.

[0141] Optionally, the plurality of tasks may include a plurality of subtasks of each of the at least one first parent task and / or the at least one second parent task.

[0142] In some disclosed embodiments, step S24 includes sub-steps S241 and S242:

[0143] Step S241 : determining a task allocation order of the multiple tasks based on the parent tasks to which the multiple tasks respectively belong.

[0144] Step S242: Allocate the multiple tasks according to their order of assignment.

[0145] Optionally, the task allocation order of at least two subtasks among multiple tasks that belong to the same parent task is determined based on the task reception order of the at least two subtasks; and / or the task allocation order of at least two tasks among multiple tasks that belong to different parent tasks is determined based on the priority of the parent tasks to which the at least two tasks belong.

[0146] In some disclosed embodiments, the steps between step S241 and step S241 also include the following steps: determining the task sequence number of each task based on the task allocation order corresponding to each task in the multiple tasks in at least one task included in the parent task to which it belongs; storing identification information of the task allocated to the first processing core in the kernel cache space corresponding to at least one first processing core in the multiple processing cores, the identification information of the task including the task sequence number and the remapping identifier.

[0147] See also Figures 9 and 10 , Figure 9 This is a flowchart of another example of the task allocation method provided by this application. Figure 10 This application provides Figure 9 A flowchart of another example of step S353 in FIG.

[0148] The method may specifically include the following steps:

[0149] In the embodiment of the present disclosure, step S25 may include sub-steps S351, S352, S353, and S354:

[0150] Step S351: caching cache information of at least two subtasks belonging to the same parent task in the task cache space of the parent task, wherein the cache information of the subtasks includes status indication information indicating the current execution status of the subtasks.

[0151] Step S352: receiving a task completion indication sent by a second processing core among the multiple processing cores, where the task completion indication is used to indicate that the second task has been completed.

[0152] Step S353: updating the task execution state information of the second task based on the identification information of the second task stored in the kernel cache space corresponding to the second processing core.

[0153] Step S354: when it is determined based on the cache information of at least two subtasks that all subtasks included in the same parent task have been completed, it is determined that the same parent task has been completed.

[0154] In some disclosed embodiments, step S353 may include sub-steps S3531, S3532, and S3533:

[0155] Step S3531: Based on the remapping identifier included in the identification information of the second task, obtain the task cache space information of the parent task to which the second task belongs.

[0156] Step S3532: Based on the task sequence number included in the identification information of the second task, determine the target cache location corresponding to the second task in the task cache space of its parent task.

[0157] Step S3533: Update the task execution status information cached at the target cache location to indicate completion of execution.

[0158] In some disclosed embodiments, the task cache space is a ring-shaped cache space.

[0159] In some disclosed embodiments, the cache information also includes a last subtask identifier indicating whether the subtask is the last subtask among at least two subtasks contained in the same parent task, then the above-mentioned step S354 includes: when the first cache information in the cache space is read, determining that the same parent task has been executed, wherein the last subtask identifier included in the first cache information indicates that the subtask is the last subtask and the status indication information included in the first cache information indicates that the subtask has been executed.

[0160] Those skilled in the art will understand that in the above-mentioned method of the specific implementation method, the writing order of each step does not mean a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of each step should be determined by its function and possible internal logic.

[0161] It can be understood that the specific description of each step in the above method embodiment can refer to the corresponding description in the above multi-core processing device embodiment, and will not be repeated here.

[0162] See also Figure 11 , Figure 111 is a schematic diagram of an example of a task assignment device provided herein. Task assignment device 100 includes memory 101 and processor 102. Processor 102 is configured to execute program instructions stored in memory 101 to implement the steps of any of the aforementioned task assignment method embodiments. In a specific implementation scenario, the task assignment device may include, but is not limited to, a microcomputer and a server. Furthermore, the task assignment device may also include mobile devices such as laptops and tablet computers, which are not limited herein.

[0163] Specifically, the processor 102 is used to control itself and the memory 101 to implement the steps of any of the above-mentioned multi-tasking allocation method embodiments. The processor 102 can also be called a CPU (Central Processing Unit). The processor 102 may be an integrated circuit device with signal processing capabilities. The processor 102 can also be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc. In addition, the processor 102 can be implemented by integrated circuit devices.

[0164] The above scheme flexibly allocates tasks to processing cores for execution based on the resource usage of the processing cores, taking a single processing core as a unit. This avoids the situation where allocating tasks to all processing cores at the same time causes idle processing cores to be unable to receive tasks, thereby improving the utilization rate of processing core resources.

[0165] See also Figure 12 , Figure 12 This is a schematic diagram of an example of a computer-readable storage medium provided in this application. The computer-readable storage medium 200 stores program instructions 201 that can be executed by a processor, and the program instructions 201 are used to implement the steps of any of the above-mentioned multi-task allocation method embodiments.

[0166] The above scheme flexibly allocates tasks to processing cores for execution based on the resource usage of the processing cores, taking a single processing core as a unit. This avoids the situation where allocating tasks to all processing cores at the same time causes idle processing cores to be unable to receive tasks, thereby improving the utilization rate of processing core resources.

[0167] It can be understood that the functions or modules included in the apparatus or device provided in the embodiments of the present application can be used to execute the method described in the above method embodiments. The specific implementation thereof can refer to the description of the above method embodiments. For the sake of brevity, it will not be repeated here.

[0168] The above description of the various embodiments tends to emphasize the differences between the various embodiments. The same or similar aspects can be referenced with each other and will not be repeated herein for the sake of brevity.

[0169] In the several embodiments provided in this application, it should be understood that the disclosed methods and devices can be implemented in other ways. For example, the device implementation methods described above are only schematic. For example, the division of modules or units is only a logical function division. There may be other division methods in actual implementation. For example, units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, and the indirect coupling or communication connection of devices or units can be electrical, mechanical or other forms.

[0170] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0171] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) or a processor to execute all or part of the steps of each embodiment method of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

Claims

1. A multi-core processing device, characterized in that: include: An interface circuit receives task instructions of multiple tasks sent by the front end; an identifier determination circuit, configured to determine remapping identifiers of at least two first tasks among the plurality of tasks based on parent tasks to which the at least two first tasks belong, wherein the at least two first tasks belong to the same parent task; and, upon completion of execution of the parent tasks to which the at least two first tasks belong, return task completion signals for each of the first tasks in the parent tasks to the front end in a preset order corresponding to the at least two first tasks; the preset order being determined based on an order in which the at least two first tasks are received, or based on an order in which the at least two first tasks are received and a priority level. a plurality of processing cores for performing said tasks; a task allocation circuit configured to allocate tasks based on current resource usage status of the multiple processing cores and in a task allocation order corresponding to the multiple tasks, with each processing core being a unit, wherein the allocation order of at least two first tasks included in the same parent task is different from a preset order corresponding to the at least two first tasks; The status confirmation circuit is used to receive the remapping identifiers of the at least two first tasks and determine whether the parent tasks to which the at least two first tasks belong are completed based on the remapping identifiers of the at least two first tasks and the task execution status information of the at least two first tasks.

2. The device according to claim 1, characterized in that The task allocation circuit is used to: In a case where the number of currently uncompleted tasks of a first processing core among the plurality of processing cores meets a task allocation condition, at least one task is allocated to the first processing core.

3. The device according to claim 1 or 2, characterized in that The task allocation circuit is configured to allocate the multiple tasks to a single processing core as a unit based on the task instructions of the multiple tasks and a current resource usage status of each of the multiple processing cores.

4. The device according to claim 3, characterized in that The plurality of tasks include a plurality of subtasks of each of at least one first parent task and / or at least one second parent task; And / or, the task allocating circuit allocates the multiple tasks according to the task allocation order corresponding to the multiple tasks, including: Determining a task allocation order of the plurality of tasks based on the parent tasks to which the plurality of tasks respectively belong; The plurality of tasks are allocated according to the task allocation order of the plurality of tasks.

5. The device according to any one of claims 3 to 4, characterized in that The order of assigning tasks to at least two subtasks belonging to the same parent task in the plurality of tasks is determined based on the order of receiving tasks of the at least two subtasks; and / or The task allocation order of at least two tasks among the multiple tasks that belong to different parent tasks is determined based on the priorities of the parent tasks to which the at least two tasks belong.

6. The device according to any one of claims 3 to 5, characterized in that The device also includes a first cache including at least one kernel cache space; The task allocation circuit is further configured to: determine a task sequence number of each task based on a task allocation order corresponding to each task in at least one task included in its parent task; The status confirmation circuit is used to: receive the task sequence number sent by the task allocation circuit, and store identification information of the task allocated to at least one first processing core among the multiple processing cores in the core cache space corresponding to the first processing core, where the identification information of the task includes the task sequence number and the remapping identifier.

7. The device according to any one of claims 3 to 6, characterized in that The status confirmation circuit is also used to: receiving a task completion indication sent by a second processing core among the plurality of processing cores, wherein the task completion indication is used to indicate that the second task has been completed; Based on the identification information of the second task stored in the kernel cache space corresponding to the second processing core, the task execution state information of the second task is updated.

8. The device according to claim 7, characterized in that The device further comprises a second buffer including at least one task buffer space for buffering task execution status information of the task; The status confirmation circuit updates the task execution status information of the second task, including: Obtaining information about a task cache space of a parent task to which the second task belongs based on a remapping identifier included in the identification information of the second task; Determining, based on the task sequence number included in the identification information of the second task, a target cache location corresponding to the second task in the task cache space of its parent task; The task execution status information cached at the target cache location is updated to indicate completion of execution.

9. The device according to any one of claims 3 to 8, characterized in that The task cache space is a circular cache space; and / or, The status confirmation circuit of the device is used to: caching cache information of at least two subtasks belonging to the same parent task among the multiple tasks into the task cache space of the parent task, wherein the cache information of the subtasks includes status indication information indicating the current execution status of the subtasks; In a case where it is determined based on the cache information of the at least two subtasks that all subtasks included in the same parent task are completed, it is determined that the execution of the same parent task is completed.

10. The device according to claim 9, characterized in that The cache information further includes a last subtask identifier indicating whether the subtask is the last subtask among the at least two subtasks included in the same parent task; The state confirmation circuit determines that the same parent task is completed, including: When the first cache information in the cache space is read, it is determined that the same parent task has been completed, wherein the last subtask identifier included in the first cache information indicates that the subtask is the last subtask and the status indication information included in the first cache information indicates that the subtask has been completed.

11. A task allocation method, characterized in that: Applicable to multi-core processing devices, including: Receive task instructions for multiple tasks sent by the front end; determining, based on parent tasks to which at least two first tasks among the plurality of tasks belong, remapping identifiers of the at least two first tasks, wherein the at least two first tasks belong to the same parent task; Obtaining a current resource usage status of each of the plurality of processing cores; Based on a current resource usage state of each processing core in the multiple processing cores, task allocation is performed according to a task allocation order of the multiple tasks with each processing core as a unit; the allocation order of the at least two first tasks included in the same parent task is different from a preset order corresponding to the at least two first tasks, the preset order being determined based on an order in which the at least two first tasks are received, or the preset order being determined based on an order in which the at least two first tasks are received and a priority level; determining, based on the remapping identifiers of the at least two first tasks and the task execution status information of the at least two first tasks, whether parent tasks to which the at least two first tasks belong are completed; When the parent tasks to which the at least two first tasks belong are completed, a task completion signal of each of the first tasks in the parent tasks is returned to the front end according to a preset order corresponding to the at least two first tasks.

12. The method according to claim 11, characterized in that The performing of task allocation based on the current resource usage status of each processing core among the multiple processing cores and taking a single processing core as a unit and in accordance with the task allocation order of the multiple tasks includes: assigning at least one task to a first processing core among the plurality of processing cores if the number of currently uncompleted tasks of the first processing core meets a task assignment condition; And / or, allocating tasks based on a current resource usage state of each processing core in the multiple processing cores and in accordance with the task allocation order of the multiple tasks with a single processing core as a unit, includes: The multiple tasks are allocated to a single processing core based on the task instructions of the multiple tasks and a current resource usage status of each of the multiple processing cores.

13. The method according to claim 12, characterized in that The allocating the multiple tasks according to the task allocation order of the multiple tasks includes: Determining a task allocation order of the plurality of tasks based on the parent tasks to which the plurality of tasks respectively belong; Allocate the multiple tasks according to the task allocation order of the multiple tasks; and / or, the task allocation order of at least two subtasks belonging to the same parent task among the plurality of tasks is determined based on the task reception order of the at least two subtasks; And / or, the task allocation order of at least two tasks belonging to different parent tasks among the multiple tasks is determined based on the priorities of the parent tasks to which the at least two tasks belong.

14. The method according to any one of claims 12 to 13, characterized in that The method further comprises: Determining a task sequence number for each task based on a task allocation order corresponding to each task in at least one task included in its parent task; The identification information of the task allocated to at least one first processing core among the plurality of processing cores is stored in a core cache space corresponding to the first processing core, where the identification information of the task includes a task sequence number and a remapping identifier.

15. The method according to any one of claims 12 to 14, characterized in that The method further comprises: receiving a task completion indication sent by a second processing core among the plurality of processing cores, wherein the task completion indication is used to indicate that the second task has been completed; Based on the identification information of the second task stored in the kernel cache space corresponding to the second processing core, the task execution state information of the second task is updated.

16. The method according to claim 15, characterized in that The updating of the task execution status information of the second task based on the identification information of the second task stored in the kernel cache space corresponding to the second processing core includes: Obtaining information about a task cache space of a parent task to which the second task belongs based on a remapping identifier included in the identification information of the second task; Determining, based on the task sequence number included in the identification information of the second task, a target cache location corresponding to the second task in the task cache space of its parent task; The task execution status information cached at the target cache location is updated to indicate completion of execution.

17. The method according to any one of claims 12 to 16, characterized in that The method further comprises: caching cache information of at least two subtasks belonging to the same parent task among the multiple tasks into the task cache space of the parent task, wherein the cache information of the subtasks includes status indication information indicating the current execution status of the subtasks; If it is determined based on the cache information of the at least two subtasks that all subtasks included in the same parent task have been completed, determining that the same parent task has been completed; and / or, The cache information further includes a last subtask identifier indicating whether the subtask is the last subtask among the at least two subtasks included in the same parent task; The determining that execution of the same parent task is complete when all subtasks included in the same parent task are determined to be complete based on the cache information of the at least two subtasks includes: When the first cache information in the cache space is read, it is determined that the same parent task has been completed, wherein the last subtask identifier included in the first cache information indicates that the subtask is the last subtask and the status indication information included in the first cache information indicates that the subtask has been completed.

18. A task allocation device, characterized in that: The method comprises a memory and a processor, wherein the processor is configured to execute program instructions stored in the memory to perform the method according to any one of claims 11 to 17.

19. A computer-readable storage medium, characterized in that Program instructions that can be executed by a processor are stored, and the program instructions are used to implement the method according to any one of claims 11 to 17.

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