Pipe latch circuit, operation method thereof, and semiconductor memory device including the same

Abstract

Embodiments of the present disclosure relate to a pipeline latch circuit, an operation method thereof, and a semiconductor memory device including the same. The pipeline latch circuit may include a first latch circuit group and a second latch circuit group. The first latch circuit group may control a latch operation and an output operation based on a plurality of pipeline input control signals. The second latch circuit group may control a latch operation and an output operation based on a plurality of pipeline input control signals and a plurality of pipeline output control signals.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2020-0175196 filed in the Korean Intellectual Property Office on December 15, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Exemplary embodiments relate to a pipe latch circuit, an operating method thereof, and a semiconductor memory device including the pipe latch circuit, and particularly to a pipe latch circuit capable of performing a pipe latch operation based on a pipe input control signal and a pipe output control signal, an operating method thereof, and a semiconductor memory device including the pipe latch circuit. Background Art

[0004] Generally, a semiconductor memory device receives and stores data and outputs the stored data. Currently, a semiconductor memory device is designed to process a large amount of data. A semiconductor memory device may include a pipe latch circuit to efficiently process a large amount of data.

[0005] Figure 1 is a block diagram for illustrating the configuration of a conventional pipe latch circuit 10.

[0006] refer to Figure 1 , the pipe latch circuit 10 includes first to eighth latch circuits 11 , 12 , 13 , 14 , 15 , 16 , 17 and 18 .

[0007] Each of the first to eighth latch circuits 11, 12, 13, 14, 15, 16, 17 and 18 receives input data DAT_IN and outputs the input data DAT_IN as output data DAT_OUT. First, the first latch circuit 11 receives the input data DAT_IN based on the first pipe input control signal PIN <1> To latch the input data DAT_IN, and based on the first pipeline output control signal POUT <1> Each of the second to eighth latch circuits 12, 13, 14, 15, 16, 17 and 18 also operates in a similar manner to the first latch circuit 11. In other words, the second to eighth latch circuits 12, 13, 14, 15, 16, 17 and 18 latch the input data DAT_IN based on the second to eighth pipe input control signals PIN<2:8>, respectively, and output the latched data as output data DAT_OUT based on the second to eighth pipe output control signals POUT<2:8>, respectively.

[0008] In this case, the input data DAT_IN includes eight data that are input continuously. Next, the first to eighth pipe input control signals PIN<1:8> are input at the first pipe input control signal PIN<1:8>. <1> In addition, the first to eighth pipeline output control signals POUT<1:8> are signals that are sequentially enabled after the first pipeline output control signal POUT <1> The signal that is sequentially enabled after being enabled. Therefore, the first to eighth latch circuits 11, 12, 13, 14, 15, 16, 17 and 18 sequentially latch the input data DAT_IN based on the first to eighth pipe input control signals PIN<1:8>, respectively. In addition, the first to eighth latch circuits 11, 12, 13, 14, 15, 16, 17 and 18 sequentially output the latched data based on the first to eighth pipe output control signals POUT<1:8>, respectively. That is, the pipe latch circuit 10 latches eight input data DAT_IN and outputs the latched eight input data DAT_IN as output data DAT_OUT.

[0009] As from Figure 1 It can be seen that the conventional pipe latch circuit 10 requires eight first to eighth pipe input control signals PIN<1:8> and eight first to eighth pipe output control signals POUT<1:8>.

[0010] At present, semiconductor memory devices are designed to process a large amount of data. Therefore, the number of the first to eighth latch circuits 11, 12, 13, 14, 15, 16, 17 and 18 included in the pipe latch circuit 10 is gradually increasing. The increase in the number of the first to eighth latch circuits 11, 12, 13, 14, 15, 16, 17 and 18 means that the number of the first to eighth pipe input control signals PIN<1:8> and the number of the first to eighth pipe output control signals POUT<1:8> for controlling the first to eighth latch circuits 11, 12, 13, 14, 15, 16, 17 and 18 are also increasing.

[0011] In this case, the increase in the number of the first to eighth pipe input control signals PIN<1:8> and the number of the first to eighth pipe output control signals POUT<1:8> is a factor that increases the circuit area occupied by the pipe latch circuit 10. In addition, the increase in the number of the first to eighth pipe input control signals PIN<1:8> and the number of the first to eighth pipe output control signals POUT<1:8> causes noise due to interference between the signals. If noise occurs in the first to eighth pipe input control signals PIN<1:8> and the first to eighth pipe output control signals POUT<1:8>, a normal pipe latch operation of the pipe latch circuit 10 may not be guaranteed. Summary of the invention

[0012] In one embodiment, the pipeline latch circuit may include: a first latch circuit group, adapted to control latch operations and output operations for input data based on multiple pipeline input control signals; and a second latch circuit group, adapted to control latch operations for data output by the first latch circuit group based on multiple pipeline input control signals, and to control output operations based on multiple pipeline output control signals.

[0013] In one embodiment, an operation method of a pipe latch circuit may include: a first pipe latch operation step, which performs a latch operation and an output operation on input data based on a plurality of pipe input control signals; a second pipe latch operation step, which performs a latch operation on data that can be output in the first pipe latch operation step based on a plurality of pipe input control signals, and performs an output operation on the latched data based on a plurality of pipe output control signals; and a third pipe latch operation step, which performs a latch operation and an output operation by repeating the first pipe latch operation step and the second pipe latch operation step.

[0014] In one embodiment, a semiconductor memory device may include a first latch circuit group disposed in a core region and a second latch circuit group disposed in a peripheral region. The first latch circuit group may be disposed in the core region and may be adapted to control latch operations and output operations for input data based on a plurality of pipeline input control signals. The second latch circuit group may be disposed in the peripheral region and may be adapted to control latch operations for data that may be output by the first latch circuit group based on a plurality of pipeline input control signals, and to control output operations based on a plurality of pipeline output control signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is a block diagram for illustrating the configuration of a conventional pipe latch circuit.

[0016] Figure 2 is a block diagram for illustrating a configuration of a pipe latch circuit according to one embodiment of the present disclosure.

[0017] Figure 3 is a block diagram for illustrating a configuration of a pipe latch circuit according to another embodiment of the present disclosure.

[0018] Figure 4 is a block diagram for illustrating a configuration of a pipe latch circuit according to still another embodiment of the present disclosure.

[0019] Figure 5 Is used to describe Figure 4 A timing diagram of the circuit operation of a pipe latch circuit to which first and second common data transmission lines are coupled.

[0020] Figure 6 is a block diagram for illustrating a configuration of a semiconductor memory device according to one embodiment of the present disclosure. DETAILED DESCRIPTION

[0021] The description of the present disclosure is only an embodiment for structural and / or functional description. The scope of rights of the present disclosure should not be interpreted as being limited to the embodiments described in the specification. That is, since an embodiment can be modified in various ways and can have various forms, the scope of rights of the present disclosure should be understood to include equivalent forms that can realize the technical spirit. In addition, the purpose or effect proposed in the present disclosure does not mean that a specific embodiment should include all purposes or effects or only include such effects. Therefore, the scope of rights of the present disclosure should not be understood to be limited thereto.

[0022] The meanings of the terms described in the present application should be understood as follows.

[0023] Terms such as "first" and "second" are used to distinguish one element from another element, and the scope of the present disclosure should not be limited by these terms. For example, a first element may be named a second element. Likewise, a second element may be named a first element.

[0024] Unless otherwise clearly indicated in the context, singular expressions should be understood to include plural expressions. Terms such as "including" or "having" should be understood to indicate the existence of the set characteristics, numbers, steps, operations, elements, components or combinations thereof, but do not exclude the possibility of the existence or addition of one or more other characteristics, numbers, steps, operations, elements, components or combinations thereof.

[0025] In each step, symbols (e.g., a, b, and c) are used for ease of description, and the symbols do not describe the order of the steps. Unless a specific order is clearly described in the context, the steps may be performed in an order different from the order described in the context. That is, the steps may be performed according to the described order, may be performed substantially simultaneously with the described order, or may be performed in the reverse order of the described order.

[0026] Unless otherwise defined, all terms (including technical or scientific terms) used herein have the same meaning as those generally understood by those skilled in the art. Unless explicitly defined in the application, terms defined in commonly used dictionaries should be interpreted as having the same meaning as the terms in the context of the relevant technology, and should not be interpreted as having an ideal or overly formal meaning.

[0027] Various embodiments will be described in more detail below with reference to the accompanying drawings. However, the present disclosure may be embodied in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art. Throughout the present disclosure, throughout the various drawings and embodiments of the present disclosure, the same reference numerals refer to the same parts.

[0028] Various embodiments are directed to providing a pipe latch circuit and an operating method thereof that are capable of minimizing the number of control signals for the pipe latch circuit and performing a pipe latch operation.

[0029] Furthermore, various embodiments are directed to providing a semiconductor memory device capable of minimizing the number of data transmission lines coupled between latch circuit groups included in a pipe latch circuit and performing a pipe latch operation.

[0030] Figure 2 is a block diagram for illustrating a configuration of a pipe latch circuit 200 according to one embodiment of the present disclosure.

[0031] refer to Figure 2 , the pipe latch circuit 200 may include a first latch circuit group 210 and a second latch circuit group 220 .

[0032] First, based on a plurality of pipeline input control signals, the first latch circuit group 210 may be an element for controlling a latch operation and an output operation for input data DAT_IN. In other words, based on the first and second pipeline input control signals PIN<1:2>, the first latch circuit group 210 may control a latch operation for input data DAT_IN. Furthermore, based on the first and second pipeline input control signals PIN<1:2>, the first latch circuit group 210 may control an output operation for latched data.

[0033] The first latch circuit group 210 is described in more detail. The first latch circuit group 210 may include a first latch circuit 211 and a second latch circuit 212.

[0034] Based on the first pipe input control signal PIN <1> , the first latch circuit 211 may be an element for latching the input data DAT_IN. In addition, based on the second pipeline input control signal PIN <2> The first latch circuit 211 may be an element for outputting latched data. The output data of the first latch circuit 211 may be output through the first data transmission line DL1.

[0035] Based on the second pipe input control signal PIN <2> , the second latch circuit 212 may be an element for latching the input data DAT_IN. In addition, based on the first pipeline input control signal PIN <1> The second latch circuit 212 may be an element for outputting latched data. The output data of the second latch circuit 212 may be output through the second data transmission line DL2.

[0036] Next, based on a plurality of pipeline input control signals, the second latch circuit group 220 may be an element for controlling a latch operation for data output by the first latch circuit group 210. In addition, based on a plurality of pipeline output control signals, the second latch circuit 220 may be an element for controlling an output operation. In other words, based on the first and second pipeline input control signals PIN<1:2>, the second latch circuit group 220 may control a latch operation for data output by the first latch circuit group 210. In addition, based on the first and second pipeline output control signals POUT<1:2>, the second latch circuit group 220 may control an output operation for latched data.

[0037] The second latch circuit group 220 is described in more detail. The second latch circuit group 220 may include a third latch circuit 221 and a fourth latch circuit 222.

[0038] Based on the first pipe input control signal PIN <1> , the third latch circuit 221 may be an element for latching the output data of the first latch circuit 211. In addition, based on the first pipeline output control signal POUT <1> , the third latch circuit 221 may be an element for outputting the latched data as output data DAT_OUT.

[0039] The fourth latch circuit 222 may be used to input a control signal PIN based on the second pipeline. <2> The second latch circuit 212 is used to receive and latch the output data of the second latch circuit 212. In addition, based on the second pipeline output control signal POUT <2> , the fourth latch circuit 222 may be an element for outputting the latched data as output data DAT_OUT.

[0040] The pipe latch circuit 200 according to one embodiment of the present disclosure may include a first latch circuit group 210 and a second latch circuit group 220. In this case, based on the first and second pipe input control signals PIN<1:2>, the first latch circuit group 210 may perform a latch operation and an output operation for input data DAT_IN. In addition, based on the first and second pipe input control signals PIN<1:2> and the first and second pipe output control signals POUT<1:2>, the second latch circuit group 220 may perform a latch operation and an output operation for data output by the first latch circuit group 210.

[0041] The pipe latch circuit 200 may include a control signal generating circuit 230 .

[0042] The control signal generating circuit 230 may be an element for generating a plurality of pipeline input control signals and a plurality of pipeline output control signals at the time of a read operation.

[0043] First, the plurality of pipeline input control signals may include a first pipeline input control signal PIN <1> , the first pipeline input control signal PIN <1> The pipeline input control signal may include a second pipeline input control signal PIN <2> , the second pipeline input control signal PIN <2> The pipeline output control signal may include a first pipeline output control signal POUT. <1> And the second pipeline output control signal POUT <2> , the first pipeline outputs a control signal POUT <1> The second pipeline output control signal POUT is used to control the output operation of the third latch circuit 221. <2> Used to control the output operation of the fourth latch circuit 222.

[0044] Next, the number of pipe input control signals may correspond to the number of latch circuits included in the first latch circuit group 210. In other words, the two first and second pipe input control signals PIN<1:2> may correspond to the two first and second latch circuits 211 and 212 included in the first latch circuit group 210. In addition, the number of pipe output control signals may correspond to the number of latch circuits included in the second latch circuit group 220. In other words, the two first and second pipe output control signals POUT<1:2> may correspond to the two third and fourth latch circuits 221 and 222 included in the second latch circuit group 220.

[0045] Based on the read command signal RD and the data strobe clock signal CLK, the control signal generating circuit 230 may generate first and second pipe input control signals PIN<1:2> and first and second pipe output control signals POUT<1:2>.

[0046] In this case, the read command signal RD may be a signal enabled at the time of the read operation. In addition, the data strobe clock signal CLK may be a signal for synchronizing the input data DAT_IN with the first and second pipe input control signals PIN<1:2>. In addition, the data strobe clock signal CLK may be a signal for synchronizing the output data DAT_OUT with the first and second pipe output control signals POUT<1:2>. More specifically, based on the data strobe clock signal CLK, the control signal generating circuit 230 may generate the first and second pipe input control signals PIN<1:2> and the first and second pipe output control signals POUT<1:2>. Therefore, based on the first and second pipe input control signals PIN<1:2> synchronized with the data strobe clock signal CLK, the first latch circuit group 210 may perform a latch operation and an output operation. In addition, the second latch circuit group 220 may perform a latch operation and an output operation based on the first and second pipe input control signals PIN<1:2> synchronized with the data strobe clock signal CLK and the first and second pipe output control signals POUT<1:2>.

[0047] In the following, a brief description is given of Figure 2 The pipeline latch operation of the pipeline latch circuit 200 is described. Before the description, at the time of the read operation, the input data DAT_IN including a plurality of data may be input to the first latch circuit group 210. Hereinafter, for the convenience of description, it is assumed that the input data DAT_IN includes four data.

[0048] First, based on the read command signal RD and the data strobe clock signal CLK, the control signal generating circuit 230 may generate first and second pipe input control signals PIN<1:2> and first and second pipe output control signals POUT<1:2> that are sequentially enabled.

[0049] Based on the first pipe input control signal PIN <1> , the first latch circuit 211 can latch the first data of the input data DAT_IN. In addition, based on the second pipeline input control signal PIN <2> , the second latch circuit 212 can latch the second data of the input data DAT_IN. At this time, based on the second pipeline input control signal PIN <2> , the first latch circuit 211 can output the latched first data. In addition, based on the first pipeline input control signal PIN <1> , the second latch circuit 212 may output the latched second data. Hereinafter, for convenience of description, the latching operation and the output operation for the input data DAT_IN performed in the first latch circuit group 210 are defined as a “first pipe latching operation”.

[0050] Next, based on the first pipeline input control signal PIN <1> , the third latch circuit 221 can latch the first data output by the first latch circuit 211. In addition, based on the second pipeline input control signal PIN <2> , the fourth latch circuit 222 can latch the second data output by the second latch circuit 212. Thereafter, based on the first pipeline output control signal POUT <1> , the third latch circuit 221 can output the latched data as output data DAT_OUT. In addition, based on the second pipeline output control signal POUT <2> , the fourth latch circuit 222 can output the latched data as output data DAT_OUT. That is, based on the first and second pipeline output control signals POUT<1:2>, the first data and the second data latched in the third and fourth latch circuits 221 and 222, respectively, can be sequentially output. Hereinafter, for ease of description, the latching operation and the output operation of the output data of the first latch circuit group 210 performed in the second latch circuit group 220 are defined as "second pipeline latching operation".

[0051] Next, the aforementioned first pipe latch operation and second pipe latch operation may be repeated, which is defined as a “third pipe latch operation.” The pipe latch circuit 200 may output third and fourth data of the input data DAT_IN as output data DAT_OUT through the third pipe latch operation.

[0052] As described above, based on the first pipeline input control signal PIN <1> , the first latch circuit 211, the second latch circuit 212 and the third latch circuit 221 can perform operations. That is, the latching operations of the first and third latch circuits 211 and 221 and the output operation of the second latch circuit 212 can be performed simultaneously. In addition, based on the second pipeline input control signal PIN <2> , the first latch circuit 211, the second latch circuit 212, and the fourth latch circuit 222 can perform operations. That is, the latching operations of the second and fourth latch circuits 212 and 222 and the output operation of the first latch circuit 211 can be performed simultaneously.

[0053] The pipe latch circuit 200 according to one embodiment of the present disclosure may include a first latch circuit group 210 and a second latch circuit group 220. In addition, based on the first and second pipe input control signals PIN<1:2>, the pipe latch circuit 200 may control a latch operation and an output operation for the first latch circuit group 210 at the first pipe latch operation. In addition, based on the first and second pipe input control signals PIN<1:2> and the first and second pipe output control signals POUT<1:2>, the pipe latch circuit 200 may control a latch operation and an output operation for the second latch circuit group 220 at the second pipe latch operation. In addition, the pipe latch circuit 200 may perform a third pipe latch operation, and may output the first, second, third, and fourth data included in the input data DAT_IN as output data DAT_OUT through the first to third pipe latch operations.

[0054] exist Figure 2 In the embodiment, the case where the first latch circuit group 210 and the second latch circuit group 220 are coupled in series is described as an example. In this case, each latch circuit group in the first latch circuit group 210 and the second latch circuit group 220 can be defined as a "unit latch circuit group" including a plurality of latch circuits. That is, the pipeline latch circuit according to an embodiment of the present disclosure may include at least two unit latch circuit groups coupled in series. In this case, the second latch circuit group 220 (i.e., the last unit latch circuit group from which the output data DAT_OUT is generated) can perform a second pipeline latch operation. In addition, the first latch circuit group 210 (i.e., at least one unit latch circuit group coupled to the previous stage of the last unit latch circuit group) can perform a first pipeline latch operation.

[0055] The pipe latch circuit 200 according to one embodiment of the present disclosure may include a plurality of unit latch circuit groups, and may generate output data DAT_OUT through a pipe latch operation with respect to input data DAT_IN.

[0056] Figure 3 is a block diagram for illustrating a configuration of a pipe latch circuit 300 according to one embodiment of the present disclosure.

[0057] refer to Figure 3 , the pipe latch circuit 300 may include a first latch circuit group 310, a second latch circuit group 320, and a control signal generating circuit 330. In this case, the first latch circuit group 310, the second latch circuit group 320, and the control signal generating circuit 330 may correspond to Figure 2Therefore, a detailed description of the configuration and operation of each of the first latch circuit group 310, the second latch circuit group 320, and the control signal generating circuit 330 is omitted.

[0058] exist Figure 3 In the pipeline latch circuit 300, the number of latch circuits included in the first latch circuit group 310 and the number of latch circuits included in the second latch circuit group 320 may be the same as Figure 2 The number of latch circuits included in the first latch circuit group 210 and the number of latch circuits included in the second latch circuit group 220 in the pipeline latch circuit 200 are different. That is, the first latch circuit group 310 may include four first to fourth latch circuits 311, 312, 313 and 314. The second latch circuit group 320 may include four fifth to eighth latch circuits 321, 322, 323 and 324. Therefore, the control signal generation circuit 330 may generate four first to fourth pipeline input control signals PIN<1:4> corresponding to the four latch circuits included in the first latch circuit group 310. In addition, the control signal generation circuit 330 may generate four first to fourth pipeline output control signals POUT<1:4> corresponding to the four latch circuits included in the second latch circuit group 320.

[0059] By such a configuration, based on the first to fourth pipe input control signals PIN<1:4>, the pipe latch circuit 300 can control the latch operation and output operation for the first latch circuit group 310. In this case, the output data of the first to fourth latch circuits 311, 312, 313 and 134 can be transferred to the fifth to eighth latch circuits 321, 322, 323 and 324 through the first to fourth data transmission lines DL1, DL2, DL3 and DL4, respectively. In addition, based on the first to fourth pipe input control signals PIN<1:4> and the first to fourth pipe output control signals POUT<1:4>, the pipe latch circuit 300 can control the latch operation and output operation for the second latch circuit group 320. That is, the eight input data DAT_IN can be output as the output data DAT_OUT.

[0060] In the following, Figure 3 The pipeline latch circuit 300 and Figure 1 The pipeline latch circuit 10 is compared and described.

[0061] Figure 1 The pipeline latch circuit 10 and Figure 3Each of the pipeline latch circuits 300 may include eight latch circuits for pipeline latch operations for eight input data DAT_IN. In this case, Figure 1 The pipe latch circuit 10 includes eight first to eighth pipe input control signals PIN<1:8> and eight first to eighth pipe output control signals POUT<1:8> for pipe latch operations. Figure 3 The pipe latch circuit 300 may include four first to fourth pipe input control signals PIN<1:4> and four first to fourth pipe output control signals POUT<1:4>.

[0062] That is, with Figure 1 Compared with the pipeline latch circuit 10, Figure 3 The pipe latch circuit 300 may use only half of the pipe input control signal and also use only half of the pipe output control signal. Using only half of the pipe input control signal and half of the pipe output control signal may mean that the circuit area of ​​the control signal generating circuit 330 that generates the first to fourth pipe input control signals PIN<1:4> and the first to fourth pipe output control signals POUT<1:4> may be reduced by that much.

[0063] Therefore, the pipe latch circuit 300 according to one embodiment of the present disclosure can minimize the area occupied by the pipe latch circuit 300 by minimizing the number of control signals and the circuit area of ​​the control signal generating circuit 330. In addition, by reducing the number of control signals, the pipe latch circuit 300 can minimize the noise occurring in each control signal.

[0064] Figure 4 is a block diagram for illustrating a configuration of a pipe latch circuit 400 according to one embodiment of the present disclosure. Figure 4 The diagram shows Figure 3 Similar configuration, and with Figure 3 The corresponding elements of the control signal generating circuit 330 are omitted.

[0065] refer to Figure 4, each of the first and second latch circuit groups 410 and 420 may include at least three latch circuits. That is, the first latch circuit group 410 may include first to fourth latch circuits 411, 412, 413, and 414. The second latch circuit group 420 may include fifth to eighth latch circuits 421, 422, 423, and 424. The first latch circuit group 410 and the second latch circuit group 420 may be coupled through at least one common data transmission line. That is, the first latch circuit group 410 and the second latch circuit group 420 may include a first common data transmission line CDL1 and a second common data transmission line CDL2. Figure 4 An example in which two common data transmission lines are coupled to a latch circuit group is illustrated.

[0066] More specifically, the first and third latch circuits 411 and 413 and the fifth and seventh latch circuits 421 and 423 may be coupled through the first common data transmission line CDL1. In addition, the second and fourth latch circuits 412 and 414 and the sixth and eighth latch circuits 422 and 424 may be coupled through the second common data transmission line CDL2. Therefore, the output data of the first latch circuit 411 may be transferred to the fifth latch circuit 421 through the first common data transmission line CDL1. The output data of the third latch circuit 413 may also be transferred to the seventh latch circuit 423 through the first common data transmission line CDL1. In addition, the output data of the second latch circuit 412 may be transferred to the sixth latch circuit 422 through the second common data transmission line CDL2. The output data of the fourth latch circuit 414 may also be transferred to the eighth latch circuit 424 through the second common data transmission line CDL2.

[0067] Figure 5 Is used to describe Figure 4 1 is a timing diagram of a circuit operation of the pipe latch circuit 400 , to which a first common data transmission line CDL1 and a second common data transmission line CDL2 are coupled. Figure 5 The diagram illustrates input data DAT_IN, first to fourth pipe input control signals PIN<1:4>, data latched in first to fourth latch circuits 411, 412, 413, and 414, first and second common data transmission lines CDL1 and CDL2, and data latched in fifth to eighth latch circuits 421, 422, 423, and 424. In this case, the input data DAT_IN may include successively input data "1", "2", "3", "4", "5", "6", "7", and "8".

[0068] First, when the first channel input control signal PIN <1> When the first pipe latch operation is enabled, data “1” (ie, the first data of the input data DAT_IN) may be latched in the first latch circuit 411. Next, when the second pipe input control signal PIN <2> When enabled, data "2" (ie, second data) may be latched in the second latch circuit 412. When the third pipe inputs the control signal PIN <3> When enabled, data "3" (ie, the third data) may be latched in the third latch circuit 413. When the fourth channel input control signal PIN <4> When enabled, data "4" (ie, the fourth data) may be latched in the fourth latch circuit 414. At this time, when based on the fourth pipe input control signal PIN <4> , when the data “4” is latched in the fourth latch circuit 414 , the data “1” latched in the first latch circuit 411 may be output to the first common data transmission line CDL1 .

[0069] When the first channel input control signal PIN <1> When the second pipe latch operation is enabled again, the data "5" of the input data DAT_IN may be latched in the first latch circuit 411. At this time, the data "2" latched in the second latch circuit 412 may be output to the second common data transmission line CDL2, and the data "1" transmitted through the first common data transmission line CDL1 may be latched in the fifth latch circuit 421. Next, when the second pipe input control signal PIN <2> When the third pipeline input control signal PIN is enabled, the data "6" may be latched in the second latch circuit 412. At this time, the data "3" latched in the third latch circuit 413 may be output to the first common data transmission line CDL1, and the data "2" transmitted through the second common data transmission line CDL2 may be latched in the sixth latch circuit 422. Thereafter, when the third pipeline input control signal PIN <3> When enabled, data "7" may be latched in the third latch circuit 413. At this time, data "4" latched in the fourth latch circuit 414 may be output to the second common data transmission line CDL2, and data "3" transmitted through the first common data transmission line CDL1 may be latched in the seventh latch circuit 423. Then, when the fourth pipe input control signal PIN <4> When enabled, data “8” may be latched in the fourth latch circuit 414. At this time, data “5” latched in the first latch circuit 411 may be output to the first common data transmission line CDL1, and data “4” transferred through the second common data transmission line CDL2 may be latched in the eighth latch circuit 424.

[0070] Although not shown, based on the first pipeline output control signal POUT <1> , the data "1" latched in the fifth latch circuit 421 can be output as the output data DAT_OUT. Based on the second pipeline output control signal POUT <2> , the data "2" latched in the sixth latch circuit 422 can be output as the output data DAT_OUT. Based on the third pipeline output control signal POUT <3> , the data "3" latched in the seventh latch circuit 423 can be output as the output data DAT_OUT. Based on the fourth pipeline output control signal POUT <4> , the data “4” latched in the eighth latch circuit 424 can be output as the output data DAT_OUT.

[0071] Next, although not shown, when each of the first to fourth pipe input control signals PIN<1:4> is enabled again according to the third pipe latch operation, data “5” of the input data DAT_IN may be latched in the fifth latch circuit 421. Data “6” may be latched in the sixth latch circuit 422. Data “7” may be latched in the seventh latch circuit 423. Data “8” may be latched in the eighth latch circuit 424. In addition, data “5”, “6”, “7”, and “8” latched in the fifth to eighth latch circuits 421, 422, 423, and 424, respectively, may be output as output data DAT_OUT based on the first to fourth pipe output control signals POUT<1:4>, respectively.

[0072] Return to reference Figure 4 In the pipe latch circuit 400 according to one embodiment of the present disclosure, the first latch circuit group 410 and the second latch circuit group 420 may be coupled through the first common data transmission line CDL1 and the second common data transmission line CDL2. That is, the pipe latch circuit 400 may perform a normal pipe latch operation through the two first common data transmission lines CDL1 and the second common data transmission line CDL2.

[0073] exist Figure 3 In the pipeline latch circuit 300, the first latch circuit group 310 and the second latch circuit group 320 can be coupled through four first to fourth data transmission lines DL1, DL2, DL3 and DL4. Figure 4 In the pipeline latch circuit 400, the first latch circuit group 410 and the second latch circuit group 420 can be coupled through two first common data transmission lines CDL1 and second common data transmission lines CDL2. That is, Figure 4 The pipe latch circuit 400 can be used only Figure 3 The pipe latch circuit 300 may use half of the data transmission lines. Using only half of the data transmission lines may mean that the circuit area and noise may be reduced by that much.

[0074] Therefore, the pipe latch circuit 400 according to one embodiment of the present disclosure may minimize the area occupied by the pipe latch circuit 400 and may minimize noise by minimizing the number of data transmission lines.

[0075] Figure 6 is a block diagram for illustrating a configuration of a semiconductor memory device 600 according to one embodiment of the present disclosure.

[0076] refer to Figure 6 , the semiconductor memory device 600 may be divided into a core region 610 and a peripheral region 620 .

[0077] First, the data storage circuit 611 and the first latch circuit group 612 may be provided in the core region 610. In this case, the data storage circuit 611 may be an element including a memory cell array for storing external input data. In addition, the data storage circuit may include a data processing device for sensing and amplifying the stored data and outputting the amplified data as input data DAT_IN. The first latch circuit group 612 may correspond to Figure 4 The first latch circuit group 410.

[0078] Next, the second latch circuit group 621 and the data output circuit 622 may be provided in the peripheral region 620. In this case, the second latch circuit group 621 may correspond to Figure 4 The second latch circuit group 420. In addition, the data output circuit 622 may be an element for outputting the output data DAT_OUT of the second latch circuit group 621 to the input and output pad DQ.

[0079] As reference Figure 4 As described, the first latch circuit group 612 and the second latch circuit group 621 can be coupled through two first common data transmission lines CDL1 and second common data transmission lines CDL2. As described above, using the minimum number of first and second common data transmission lines CDL1 and CDL2 can mean that circuit area and noise can be reduced that much.

[0080] Therefore, the semiconductor memory device 600 according to one embodiment of the present disclosure can minimize the circuit area occupied by the semiconductor memory device 600 and minimize noise between signals by reducing the number of common data transmission lines.

[0081] An effect of one embodiment of the present disclosure is that it can minimize the area occupied by a pipe latch circuit by minimizing the number of control signals used in the pipe latch circuit and minimize noise incorporated in the control signals.

[0082] An effect of one embodiment of the present disclosure is that it can minimize the area of ​​a semiconductor memory device by minimizing the number of data transmission lines coupled between latch circuit groups included in a pipe latch circuit and minimize noise caused by the data transmission lines.

[0083] One embodiment of the present invention may include a pipeline latch circuit, the pipeline latch circuit including: a first latch circuit group, adapted to control latch operations and output operations for input data based on multiple pipeline input control signals that control the multiple latch circuits; a second latch circuit group, adapted to control latch operations for data output by the first latch circuit group based on multiple pipeline input control signals, and to control output operations based on multiple pipeline output control signals that control the multiple latch circuits; and a synchronization circuit, which is connected in series with the first latch circuit group and the second latch circuit group, and sequentially outputs the input data, wherein at least one common data transmission line couples the first latch circuit group and the second latch circuit group according to a synchronization mode.

[0084] Although various embodiments have been described for illustrative purposes, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the present disclosure as defined by the following claims.

Claims

1. A pipeline latch circuit, comprising: A first latch circuit group, adapted to control latch operations and output operations for input data based on a plurality of pipeline input control signals; as well as a second latch circuit group adapted to control a latch operation for data output by the first latch circuit group based on the plurality of pipeline input control signals and to control an output operation based on a plurality of pipeline output control signals, Each of the multiple pipeline input control signals controls the latching operation of one latch circuit in the first latch circuit group and the output operation of another latch circuit in the first latch circuit group, and controls the latching operation of a latch circuit in the second latch circuit group corresponding to the one latch circuit in the first latch circuit group.

2. The pipe latch circuit according to claim 1, wherein the first latch circuit group comprises: a first latch circuit adapted to latch the input data based on a first pipe input control signal included in the plurality of pipe input control signals, and output the latched data based on a second pipe input control signal included in the plurality of pipe input control signals; as well as The second latch circuit is adapted to latch the input data based on the second pipe input control signal and output the latched data based on the first pipe input control signal.

3. The pipe latch circuit according to claim 2, wherein the second latch circuit group comprises: a third latch circuit adapted to latch output data of the first latch circuit based on the first pipe input control signal, and output the latched data as output data based on a first pipe output control signal included in the plurality of pipe output control signals; as well as A fourth latch circuit is adapted to latch output data of the second latch circuit based on the second pipe input control signal, and output the latched data as output data based on a second pipe output control signal included in the plurality of pipe output control signals. 4 . The pipe latch circuit according to claim 1 , further comprising a control signal generating circuit, wherein the control signal generating circuit is adapted to generate the plurality of pipe input control signals and the plurality of pipe output control signals during a read operation. 5 . The pipe latch circuit according to claim 1 , wherein the number of the plurality of pipe input control signals corresponds to the number of latch circuits included in the first latch circuit group. 6 . The pipe latch circuit according to claim 1 , wherein the number of the plurality of pipe output control signals corresponds to the number of latch circuits included in the second latch circuit group.

7. The pipe latch circuit of claim 1 , wherein: Each of the first latch circuit group and the second latch circuit group includes at least three latch circuits, and The first latch circuit group and the second latch circuit group are coupled through at least one common data transmission line.

8. A method for operating a pipeline latch circuit, comprising: In a first pipeline latch operation, a latch operation and an output operation are performed on input data based on a plurality of pipeline input control signals; In a second pipe latch operation, a latch operation is performed on the data output in the first pipe latch operation step based on the plurality of pipe input control signals, and an output operation is performed on the latched data based on the plurality of pipe output control signals; as well as In a third pipeline latch operation, a latch operation and an output operation are performed by repeating the first pipeline latch operation step and the second pipeline latch operation step, Each of the multiple pipeline input control signals controls the latching operation of one latch circuit in the first latch circuit group of the pipeline latch circuit and the output operation of another latch circuit in the first latch circuit group, and controls the latching operation of one latch circuit in the second latch circuit group of the pipeline latch circuit corresponding to the one latch circuit in the first latch circuit group.

9. The operating method according to claim 8, further comprising: During a read operation, the plurality of pipeline input control signals and the plurality of pipeline output control signals are generated.

10. The operating method according to claim 8, wherein the first pipe latching operation step comprises: In a first latching step, the input data is latched in a first latch circuit based on a first pipe input control signal included in the plurality of pipe input control signals; In a second latching step, the input data is latched in a second latch circuit based on a second pipe input control signal included in the plurality of pipe input control signals; In a first output step, the data latched in the first latch circuit is output based on the second pipe input control signal; and In a second output step, the data latched in the second latch circuit is output based on the first pipe input control signal.

11. The operating method according to claim 10, wherein the second pipe latching operation step comprises: In a third latching step, based on the first pipeline input control signal, the output data of the first latch circuit is latched in a third latch circuit; In a fourth latching step, based on the second pipe input control signal, the output data of the second latch circuit is latched in a fourth latch circuit; as well as In a third output step, the data latched in the third latch circuit and the fourth latch circuit are sequentially output based on the plurality of pipe output control signals.

12. The operating method according to claim 11, comprising: Based on the first pipeline input control signal, the first latching step, the third latching step and the second outputting step are simultaneously performed; as well as Based on the second pipe input control signal, the second latching step and the fourth latching step and the first outputting step are simultaneously performed.

13. The operating method according to claim 8, comprising: performing the first pipe latch operation, the second pipe latch operation, and the third pipe latch operation by latching using a plurality of unit latch circuit groups, each unit latch circuit group including a plurality of latch circuits coupled in series; performing the second pipe latch operation step by using a last unit latch circuit group from which output data is generated; as well as The first pipe latch operation step is performed by using at least one unit latch circuit group coupled to a previous stage of the last unit latch circuit group.

14. A semiconductor memory device comprising: A first latch circuit group is disposed in the core region and is adapted to control a latch operation and an output operation for input data based on a plurality of pipeline input control signals; as well as a second latch circuit group, disposed in the peripheral region and adapted to control a latch operation for data output by the first latch circuit group based on the plurality of pipeline input control signals, and to control an output operation based on a plurality of pipeline output control signals, Each of the multiple pipeline input control signals controls the latching operation of one latch circuit in the first latch circuit group and the output operation of another latch circuit in the first latch circuit group, and controls the latching operation of a latch circuit in the second latch circuit group corresponding to the one latch circuit in the first latch circuit group. 15 . The semiconductor memory device according to claim 14 , further comprising a control signal generating circuit adapted to generate the plurality of pipeline input control signals and the plurality of pipeline output control signals in a read operation.

16. The semiconductor memory device according to claim 14, wherein: Each of the first latch circuit group and the second latch circuit group includes at least three latch circuits, and The first latch circuit group and the second latch circuit group include at least one common data transmission line.

Images