Memory subsystem media management group

Abstract

This application relates to a memory subsystem media management group. A system includes a memory device and a processing device coupled to the memory device. The processing device can assign each of a plurality of superblocks to one of a plurality of groups. The processing device can monitor an order in which each of the groups is written. The processing device can write data to a first block of a first superblock of a first one of the plurality of groups.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to a memory subsystem, and more specifically, to a memory subsystem media management group. Background Technology

[0002] The memory subsystem may include one or more memory devices for storing data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, the host system can utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the Invention

[0003] According to one aspect of this application, a media management group system for a memory subsystem is provided. The system includes: a memory device; and a processing device coupled to the memory device, the processing device being configured to perform operations including: assigning each of a plurality of superblocks to one of a plurality of groups to perform media management operations; monitoring the order in which each of the plurality of groups is written; and writing data to a specific portion of a first superblock of a first group based at least in part on the monitored order.

[0004] According to another aspect of this application, a method for media management groups in a memory subsystem is provided. The method includes: assigning each of a plurality of superblocks to one of a plurality of groups at a processing device coupled to a memory device; monitoring the order in which data is written to each of the plurality of groups at the processing device; writing data to a first block of a first superblock of a first group, at least in part based on the monitored order; and erasing a second superblock of the first group concurrently with the first superblock to which data was written.

[0005] According to another aspect of this application, a memory subsystem media management group device is provided. The device includes: a memory device including a plurality of superblocks; a processing means coupled to the memory device, the processing means being configured to perform operations including: assigning each of the plurality of superblocks to one of a plurality of groups at the processing means coupled to the memory device; monitoring the order of the groups at the processing means based on the order in which the groups are written or wear leveling characteristics; writing data to a specific superblock of one of the plurality of groups; erasing an additional superblock following the specific superblock; and, in response to receiving a message from a host, stopping the writing to the specific superblock and continuing the writing to a second additional superblock previously erased between the specific superblock and the additional superblock. Attached Figure Description

[0006] This disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of the various embodiments thereof.

[0007] Figure 1 This describes an example computing system including a memory subsystem according to some embodiments of the present disclosure.

[0008] Figure 2A Examples of several superblocks according to some embodiments of this disclosure are described.

[0009] Figure 2B Examples of media management groups according to some embodiments of this disclosure are described.

[0010] Figure 2C Examples of multiple media management groups according to some embodiments of this disclosure are described.

[0011] Figure 3 A flowchart illustrating a method corresponding to the use of a media management group according to some embodiments of this disclosure.

[0012] Figure 4 This is a flowchart corresponding to a method of using a media management group according to some embodiments of this disclosure.

[0013] Figure 5 This is a block diagram of an example computer system operable in accordance with embodiments of this disclosure. Detailed Implementation

[0014] This disclosure relates to a wear leveling group associated with a memory subsystem, and more specifically, with a memory subsystem comprising group components. The memory subsystem may be a storage device, a memory module, or a hybrid of a storage device and a memory module. An example of a memory subsystem is a storage system, such as a solid-state drive (SSD). The following is combined with… Figure 1 Describe examples of storage devices and memory modules. Generally, a host system may utilize a memory subsystem that includes one or more components that are, for example, "memory devices" for storing data. The host system can provide data that will be stored in the memory subsystem and can request data that will be retrieved from the memory subsystem.

[0015] The memory device can be a non-volatile memory device. An example of a non-volatile memory device is a NAND flash memory device (also known as flash memory). The following section combines... Figure 1Other examples of non-volatile memory devices are described below. A non-volatile memory device is a package of one or more dies. Each die may consist of one or more planes. Planes may be divided into logical units (LUNs). For some types of non-volatile memory devices (e.g., NAND devices), each plane includes a set of physical blocks. Each block consists of a set of pages. Each page consists of a set of memory cells (“cells”). A cell is an electronic circuit that stores information. A block, hereinafter, refers to a unit of memory device used to store data and may contain a group of memory cells, a group of word lines, a word line, or individual memory cells. For some memory devices, a block (hereinafter also referred to as a “memory block”) is the smallest erasable unit. Pages cannot be erased individually; only the entire block can be erased.

[0016] Each memory device may contain one or more arrays of memory cells. Depending on the cell type, a cell may be written to store one or more bits of binary information and has various logic states related to the number of bits stored. These logic states may be represented by binary values ​​such as "0" and "1" or combinations thereof. Various types of cells exist, such as single-level cells (SLC), multi-level cells (MLC), three-level cells (TLC), and four-level cells (QLC). For example, an SLC may store one bit of information and have two logic states.

[0017] Some NAND memory devices employ a floating gate architecture, where memory access is controlled based on the relative voltage variation between the bit lines and word lines. Other instances of NAND memory devices may employ an alternative gate architecture, which may include a word line layout that allows charges corresponding to data values ​​to be trapped within the memory cell based on the properties of the materials used to construct the word lines.

[0018] SSDs are a type of memory subsystem that uses integrated circuit assemblies to permanently store data (typically using flash memory). An SSD may comprise a memory device including one or more arrays of memory cells. The performance, durability, and / or retention capability of an SSD can be related to the type of memory cells used in the SSD. Generally, as the number of bits stored per cell increases, the retention capability of the memory cell (the ability to maintain the integrity of the stored data over a specified period of time) tends to increase in sensitivity to temperature fluctuations. Retention failures can lead to errors and can cause events performed by the SSD to fail or occur incorrectly. Temperature fluctuations can occur for extended periods during the shipping process after the SSD is manufactured. As an example, memory cells storing data in single-level cell (SLC) mode may be less susceptible to damage attributable to high temperature fluctuations than memory cells storing data in non-SLC modes (e.g., multi-level (MLC), three-level (TLC), or four-level (QLC), five-level (PLC) cell modes).

[0019] Flash memory devices may include a flash translation layer (FTL), which can (e.g., during programming operations performed on the flash memory device) be used to map logical addresses to physical addresses in the flash memory (e.g., via a logic-to-physical (L2P) table). As an example, in some prior methods, entries in the logic-to-physical (L2P) address mapping table may contain references to dies, blocks, planes, and pages of memory in which portions of data are stored. Furthermore, a die may comprise several planes, each plane may contain several blocks, and each block may contain several pages.

[0020] Vehicles may include a storage subsystem, such as a solid-state drive (SSD). The storage subsystem can be used by various components of the vehicle to store data, such as applications running on the vehicle's host system. An example of this application is the vehicle's event logger, also known as a "black box" or incident data logger. The event logger needs to be able to store host data in response to triggering events such as an incident for later retrieval, but the event logger does not necessarily need to store host data faster than required to keep up with the throughput.

[0021] The emergence of autonomous vehicles, the Internet of Things (IoT), and monitoring devices has led to a greater gap between the total bytes written (TBW) over the available lifetime of a memory subsystem and its user capacity. For example, the TBW to user capacity ratio for some memory systems used in such applications has increased by one to three orders of magnitude. Some autonomous vehicles require real-time buffering of telemetry data, such as that from cameras, radar, lidar, ultrasound, and other sensors necessary for replaying sequences prior to an incident. The data from these sensors collectively represents a large processing requirement per unit time (e.g., 1 gigabyte per second (GB / sec) sequential write processing from the host). After an event is triggered, a certain amount of data corresponding to a predetermined playback time immediately preceding the event needs to be captured (e.g., to determine the cause of the event). The recorded telemetry sensor data corresponding to the predetermined playback time can be referred to as a “snapshot.” ​​Event loggers are such applications where user capacity requirements can be as low as 128 (128) GB, but TBW requirements can be as high as hundreds of petabytes. Examples of the given values ​​are not limiting, but emphasize the relative difference between capacity requirements and TBW requirements. The event logger may need to store at least some recent snapshots.

[0022] If snapshots are particularly large or difficult to monitor (e.g., large amounts of data stored in a mapping table or transferred across a flash translation layer (FTL), storing and monitoring these snapshots can be very data-intensive. However, as the size of the mapped memory (e.g., a non-volatile memory array, NAND) increases, or if a larger portion of the memory is stored to access the specific physical location of snapshots in memory, the size of the address mapping table (e.g., the amount of data stored in the address mapping table) can become very large. Main memory (e.g., in DRAM) can be expensive and space-constrained. As in the previous approach, a fixed, large address mapping table can be difficult to fit into already limited memory (e.g., a non-volatile memory array, NAND) space. The larger the address mapping table, the more difficult it becomes to cache portions of it without affecting cache hit rates. Furthermore, as the size of the memory mapped by the FTL increases, the size of the address mapping table can increase to a size that becomes unmanageable. Additionally, in the example of storing L2P tables in SLC mode, the amount of time the L2P table is accessed can affect the performance of the memory cells storing the L2P table.

[0023] Furthermore, the location of memory within the memory device can be monitored and located using an FTL (Fault Tolerance Module) to determine a set of data to be written based on wear leveling characteristics and constraints. The more data used for wear leveling purposes, the more data locations need to be tracked. As described below, by dedicating a larger portion of the data to wear leveling purposes, fewer data portions can be tracked and the memory mapped by the FTL can be reduced for wear leveling of the memory device.

[0024] This disclosure addresses the aforementioned and other drawbacks by performing loss leveling using a larger portion of the data. As an example, more than one data superblock can be used for the media management group to monitor and perform loss leveling operations. In situations where a large portion of the data is received from sensor and / or memory infrastructure (e.g., in an autonomous vehicle environment) and data integrity is critical for data processing purposes, increasing the size of the loss leveling blocks (which may be referred to herein as "groups") provides a more efficient and less resource-intensive process for performing loss leveling. In this way, access to the received data is simplified, and the amount of data used in L2P tables and / or FTLs is reduced. Advantages of this disclosure include minimizing the amount of data to be monitored and / or tracked for loss leveling. The embodiments described herein include group components residing on the memory subsystem (e.g., on the memory subsystem controller) to enable monitoring of the media management group by the memory subsystem.

[0025] By increasing the size of each portion of the data used for wear leveling, the size of the data used for the L2P table, or the size of L2P table entries, SLC memory cells storing the L2P table can have improved durability over the duration of use. Furthermore, the L2P table and / or FTL can be smaller, thereby dedicating less memory space to the L2P table. Additionally, the L2P table can be rebuilt in a shorter time and with less processing resources. As memory drive sizes continue to increase, methods to reduce the size of the address mapping table and / or FTL can allow for larger memory drive sizes without correspondingly increasing the address mapping table or FTL used to map logical addresses to physical addresses. In this way, the physical memory space used to store the address mapping table can be minimized, and the scalability of the address mapping table can be improved. Moreover, restricting data storage to SLC mode provides a more beneficial experience. For example, memory cells in SLC mode can be accessed and written faster, thereby providing an improved user experience.

[0026] Figure 1 This description describes an example computing system 100 including a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination thereof.

[0027] The memory subsystem 110 may be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small form factor DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0028] The computing system 100 may be a computing device including, for example, a desktop computer, a laptop computer, a web server, a mobile device, a vehicle (e.g., an airplane, drone, train, car or other means of transport), an Internet of Things (IoT) enabled device, an embedded computer (e.g., an embedded computer contained in a vehicle, industrial equipment or networked commercial device), or such a computing device including memory and processing.

[0029] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1This describes an example of a host system 120 coupled to a memory subsystem 110. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intermediary component), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

[0030] Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). Host system 120 uses memory subsystem 110 (for example) to write data to and read data from memory subsystem 110.

[0031] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include (but are not limited to) Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Small Computer System Interface (SCSI), Double Data Rate (DDR) memory bus, Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM socket interfaces supporting Double Data Rate (DDR)), Open NAND Flash Interface (ONFI), Double Data Rate (DDR), Low Power Double Data Rate (LPDDR), or any other interface. The physical host interface can be used to transfer data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a PCIe interface, host system 120 can further utilize NVM High Speed ​​(NVMe) interface access components (e.g., memory device 130). The physical host interface provides an interface for transmitting control, address, data and other signals between the memory subsystem 110 and the host system 120. Figure 1 The memory subsystem 110 is described as an example. Generally, the host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0032] Memory devices 130 and 140 may include various combinations of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (such as memory device 140) may be (but are not limited to) random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0033] Some examples of non-volatile memory devices (such as memory device 130) include NAND flash memory and in-situ write memory, such as a three-dimensional crosspoint ("3D crosspoint") memory device, which is a crosspoint array of non-volatile memory cells. Crosspoint non-volatile memory arrays can perform bit storage based on volume resistance variations along with a stacked crossgate format data access array. Furthermore, compared to many flash-based memories, crosspoint non-volatile memories can perform in-situ write operations, where non-volatile memory cells can be programmed without prior erasing of the non-volatile memory cells. NAND flash memories include, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0034] Each of the memory devices 130 and 140 may include one or more arrays of memory cells. For example, one type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), and five-level cell (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination thereof. In some embodiments, a particular memory device may include SLC portions and MLC portions, TLC portions, QLC portions, or PLC portions of memory cells. The memory cells of the memory device 130 may be grouped into pages, which may refer to logical units of the memory device used to store data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0035] Although a three-dimensional cross-point array of non-volatile memory cells and a NAND-type memory (e.g., 2D NAND, 3D NAND) are described, the memory device 130 may be based on any other type of non-volatile memory or storage device, such as read-only memory (ROM), phase-change memory (PCM), self-select memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0036] The memory subsystem controller 115 (or, for simplicity, controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, or erasing data at the memory device 130, and other such operations. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system having dedicated (i.e., hard-coded) logic for performing the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0037] The memory subsystem controller 115 may include a processor 117 (e.g., a processing device) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logical flows, and routines for controlling the operation of the memory subsystem 110 (including handling communication between the memory subsystem 110 and the host system 120).

[0038] In some embodiments, local memory 119 may include memory registers storing memory pointers, fetched data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although already... Figure 1 The instance memory subsystem 110 is described as including a memory subsystem controller 115, but in another embodiment of this disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, and may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0039] Generally, the memory subsystem controller 115 can receive commands or operations from the host system 120 and can translate these commands or operations into instructions or appropriate commands to achieve the desired access to memory devices 130 and / or 140. The memory subsystem controller 115 may handle other operations, such as wear leveling, scrap collection, error detection and error correction (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses (LBAs), namespaces) and physical addresses (e.g., physical block addresses, physical media locations, etc.) associated with memory device 130. The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into command instructions for accessing memory devices 130 and / or 140, and can also translate responses associated with memory devices 130 and / or 140 into information for the host system 120.

[0040] The memory subsystem 110 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 110 may include caches or buffers (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access memory devices 130 and / or 140.

[0041] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 is a managed memory device, which is a native memory device combined with a local controller (e.g., local controller 135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0042] The memory subsystem 110 includes a group component 113, which can be configured to orchestrate and / or assist the execution of wear leveling operations to determine which portion of the data to be erased and currently written, and can do so using various components, data paths, and / or interfaces of the memory subsystem 110. The group component 113 may include various circuitry that facilitates the erasure and storage of data in memory cells and their corresponding LBAs in the logic-to-physical (L2P) table. For example, the group component 113 may include dedicated circuitry in the form of an ASIC, FPGA, state machine, and / or other logic circuitry or software and / or firmware that allows the group component 113 to orchestrate and / or perform media management operations such as wear leveling operations and communicate with various components, data paths, and / or interfaces of the memory subsystem 110.

[0043] Group component 113 is communicatively coupled to memory devices 130, 140 and has access to internal data paths of memory devices 130, 140, memory subsystem 110, and / or interfaces of memory subsystem 110 to perform the operations described herein and / or transfer stored data to additional elements of memory subsystem 110. In some embodiments, the operations performed by group component 113 may be performed during the initialization or pre-initialization phase of data transfer within memory subsystem 110 and / or memory subsystem controller 115. Thus, in some embodiments, group component 113 may perform the operations described herein prior to data transfer to determine the mode of storing data, which may affect the rate of subsequent data transfers from cells stored in that particular mode.

[0044] In some embodiments, the memory subsystem controller 115 includes at least a portion of the group component 113. For example, the memory subsystem controller 115 may include a processor 117 (processing means) configured to execute instructions stored in local memory 119 for performing the operations described herein. In some embodiments, the group component 113 is part of the host system 120, an application, or an operating system.

[0045] According to some embodiments of this disclosure Figure 1 The memory devices 130 and 140 may comprise several physical blocks. For example, memory devices 130 and 140 may comprise a NAND flash memory array comprising several physical blocks. However, embodiments of this disclosure are not limited to a particular type of memory or memory array. For example, the memory array may be a DRAM array, an RRAM array, or a PCRAM array, as well as other types of memory arrays. Furthermore, the memory array may be positioned on a specific semiconductor die along with various peripheral circuitry systems associated with its operation.

[0046] The memory cells of the memory array can be mixed-mode cells operable as SLC and / or XLC (e.g., additional level cells that can operate at levels greater than SLC). The number of physical blocks in the memory array can be 128 blocks, 512 blocks, or 1,024 blocks, but embodiments are not limited to specific multiples of 128 or to any specific number of physical blocks in the memory array. Furthermore, different portions of the memory can act as dynamic SLC caches for wear leveling and / or waste collection purposes. For example, the size of different portions of the memory can dynamically increase and / or decrease as memory requirements increase and / or decrease, and wear leveling and waste collection address these requirements more efficiently.

[0047] Each physical block of the memory array may contain several physical rows of memory cells coupled to access lines (e.g., word lines). The number of rows (e.g., word lines) in each physical block may be 32, but embodiments are not limited to a specific number of rows per physical block. Furthermore, memory cells may be coupled to sensing lines (e.g., data lines and / or digital lines).

[0048] Each row may contain several memory cell pages (e.g., physical pages). A physical page refers to a programming and / or sensing unit (e.g., several memory cells programmed and / or sensed together as a functional group). Each row may include one memory cell physical page. However, embodiments of this disclosure are not limited thereto. For example, in several embodiments, each row may include multiple memory cell physical pages (e.g., one or more even-numbered memory cell pages coupled to an even-numbered bit line and one or more odd-numbered memory cell pages coupled to an odd-numbered bit line). Additionally, for embodiments including XLC, a memory cell physical page may store data from multiple pages (e.g., logical pages) (e.g., data from the previous page and data from the next page, wherein each cell in the physical page stores one or more bits of data towards the previous page and one or more bits of data towards the next page).

[0049] In a non-limiting example, the device (e.g., computing system 100) may include a memory subsystem group component 113. The memory subsystem group component 113 may reside on a memory subsystem 110. As used herein, the term "resides on" means something physically located on a particular component. For example, "resides on memory subsystem 110" means that the hardware circuitry including the memory subsystem group component 113 is physically located on the memory subsystem 110. As referenced herein, the term "resides on" may be used interchangeably with other terms such as "deployed on" or "located on".

[0050] The memory subsystem grouping component 113 can be configured to determine which portions of the data reside within which wear leveling group. Each wear leveling group may contain more data than a single superblock stored in the memory. For example, data stored in more than one superblock may reside in multiple wear leveling groups. As used herein, a “superblock” is a set of data blocks spanning multiple dies written in an interleaved manner. In some cases, a superblock may span all dies within the memory subsystem or memory device. A superblock may contain multiple data blocks from a single die. In some embodiments, a superblock may be a management unit within the memory subsystem. Thus, a superblock may refer to multiple blocks containing one block from each NAND memory device attached to a solid-state drive (SSD). In addition to determining from which additional wear leveling group to erase, the memory subsystem grouping component 113 may also determine to which initial wear leveling group data to write data to, where erasure occurs when data is expected to be written to that additional wear leveling group during a switch from the initial wear leveling group.

[0051] The memory subsystem grouping component 113 can switch to a memory block group, which may be simply referred to herein as a "wear leveling group," in response to several different events, as described further below. In one instance, the memory subsystem grouping component 113 can switch from writing to the initial wear leveling group to writing to an additional wear leveling group in response to a host request to switch wear leveling groups. In one instance, the memory subsystem grouping component 113 can switch from writing to the initial wear leveling group to writing to an additional wear leveling group in response to reaching the storage capacity of the initial wear leveling group. In one instance, the memory subsystem grouping component 113 can switch from writing to the initial wear leveling group to writing to an additional wear leveling group in response to a programming error occurring in the initial wear leveling group.

[0052] Figure 2A This description illustrates example blocks of memory cells 201 comprising or constituting multiple superblocks 220-1, 220-2 according to some embodiments of the present disclosure. Each of the multiple superblocks 220-1, 220-2 may span multiple memory dies 221-1 to 221-L. Each of the multiple superblocks 220-1, 220-2 may include multiple planes 223-1 to 223-P and multiple pages 225-1 to 225-Q. Although not explicitly shown, pages 225-1 to 225-Q may be coupled to word lines (e.g., access lines) and may be referred to herein as word lines 225-1 to 225-Q where appropriate in the given context. In some embodiments, a block of memory cells may include at least one set of interleaved NAND memory cells coupled to a stacked cross-gate memory cell array (e.g., a 3-D NAND device) and / or may be part of a replacement gate NAND device.

[0053] Data can be written to as described above and in conjunction with this article. Figures 2B to 2C This describes the portions of multiple superblocks 220-1 and 220-2 that operate in that manner. For example, group component 213 (e.g.) Figure 1 The group component 113 described herein can control the assignment of each of the multiple superblocks 220-1, 220-2 to multiple groups (e.g., in this document). Figure 2C One of the groups (227-1 to 227-4) described herein is used to perform media management operations. The group component may further perform operations including monitoring the order in which each of the multiple groups is written and writing data to a specific portion of the first superblock (e.g., superblock 220-1) of the first of the multiple groups based at least in part on the monitored order.

[0054] Furthermore, each of the plurality of superblocks may comprise a plurality of blocks of memory of the memory device. Data may be written to each block of each of the superblocks in a particular group, and in response to writing to the end of the first group, data may continue to be written to the beginning of the first group, thereby overwriting data previously written at the beginning. Additional superblocks in the first group may be erased before writing to the preceding superblock is complete. Second superblocks may be ordered to be written after the preceding superblock. Additional superblocks may be erased concurrently with the preceding superblock to which data was written to the first group.

[0055] In some embodiments, in response to a failure to write to the first superblock, additional data can be written to the second superblock. In response to a failure from the host (e.g., Figure 1 When the host system 120 receives a request to write to a second of multiple groups, it can record or save the last write position at which the data was written when the request was received. Additional groups among the multiple groups to which data is to be written can be determined based on loss leveling characteristics.

[0056] Figure 2B Examples of media management groups 227 according to some embodiments of the present disclosure are described. In an alternative example, media management group 227 may be referred to as a "loss leveling group". Loss leveling group 227 may include multiple superblocks (SBs) 220-1, 220-2, 220-3, 220-4, 220-5, 220-6, 220-7, 220-8 (hereinafter collectively referred to as multiple superblocks 220). Superblocks 220 may be similar to Figure 2ASuperblocks 220-1 and 220-2 are included. Wear leveling group 227 can be used to perform several media management operations, such as wear leveling operations. Multiple superblocks can be pre-assigned to wear leveling group 227 before data writing begins. In some embodiments, data can be written across each block in superblock 220 of wear leveling group 227 before being written to another wear leveling group. In this way, the location of large amounts of data can be within a single wear leveling group, thereby minimizing the amount of locations that the memory subsystem may have to track and / or monitor.

[0057] As an example, in response to data being written to a block in the first superblock 220-1, data can be written to a block in the second superblock 220-2, and so on, until each of the superblocks 220 has been written (e.g., in this example, the first superblock 220-1, then the second superblock 220-2, then the third superblock 220-3, and so on up to the eighth superblock 220-8). Although eight superblocks are described as being in the wear leveling group 227, the example is not limited to this. Any number of superblocks can be in the wear leveling group 227, depending on how large or small the wear leveling group 227 is expected to be based on several parameters, such as the amount of storage locations available for tracking data. That is, if the amount of storage locations available for tracking data is large, then the number of superblocks 220 in the wear leveling group 227 can be smaller because more wear leveling groups 227 can be tracked. In an alternative example, if the amount of storage locations available for tracking data is small, then the number of superblocks 220 in the wear leveling group 227 can be larger because fewer wear leveling groups 227 can be tracked.

[0058] Once data has been written to each block of each of the superblocks 220 in the loss balancing group 227, data can begin to be written to the first block by overwriting the data in the first block. For example, as data is written to the last block of the eighth superblock 220-8, data can then be written to the first block of the first superblock 220-1. In this way, data can be cyclically written to the loss balancing group 227 until a message or instruction is received in another manner. This creates a snapshot or specific record of data that can be retrieved for subsequent analysis. In response to receiving a message to switch to a new loss balancing group (e.g., loss balancing group 227-1), the previous loss balancing group (e.g., loss balancing group 227-8) can then be used as a previous snapshot of the complete data for a specific period of time or for a specific amount of data.

[0059] Figure 2CThis description illustrates instances of several media management groups 227-1, 227-2, 227-3, and 227-4 according to some embodiments of this disclosure. In some embodiments, data may be written to the superblock of the first loss balancing group 227-1 (e.g., Figure 2B The memory subsystem can begin writing data to the first block of the first superblock of the second loss balancing group 227-2 in response to receiving a message to switch to the next loss balancing group. The first loss balancing group 227-1 can be used as a snapshot if data is written across every block of every superblock in the first loss balancing group 227-1. When there is no valid data in the second loss balancing group 227-2 when the memory subsystem switches to writing to the second loss balancing group 227-2, data can be written to the second loss balancing group 227-2 without further modification. However, in response to the second loss balancing group 227-2 containing valid data, the valid data in the block to be written can be transferred to the previously written block in the first loss balancing group 227-1, while data continues to be written to blocks in the second loss balancing group 227-2. In this way, a snapshot of the valid data in the second loss balancing group 227-2 is preserved. In this way, valid data in the second loss balancing group 227-2 continues to be written to the first loss balancing group 227-1 as it is erased and overwritten, while new data is written to the second loss balancing group 227-2.

[0060] In some embodiments, when the first block of the first superblock 220-1 is written, the second block of the first superblock 220-2 may have been previously erased, and the third block of the first superblock 220-1 may be actively erased when the first block is written. In this way, in response to a failure within the first block, writing can continue in the second block, where the third block is ready to be written. For example, when the first block is written, the second block has been erased, and the third block is actively erased. In response to a failure in the first block, data begins to be written to the second block, the third block is immediately completely erased, and the erasure of the fourth block begins when data is written to the second block. In this way, the entire block following the written block is erased and additional blocks are erased to be ready for use when this switch is anticipated during a failure.

[0061] Blocks within a superblock and therefore within a wear leveling group can be ordered so that they can be accessed sequentially, for example, using linked lists or other contiguous access data structures. The ordering of blocks can be adjusted based on the number of events occurring in relation to that (e.g., a particular) wear leveling group. Blocks can be arranged based on performance, based on whether a group is valid (“good”) or where specific data is within a particular block and invalid (“bad”) data is within another group of blocks. In some embodiments, the next block to be written can be the oldest block in the wear leveling group or the block with the fewest erases within a given time period (in an attempt to level the wear on the system). The oldest block can refer to a block in which data was written prior to any other block that has not yet been erased or invalidated.

[0062] By using the wear leveling groups described above, snapshots of data for a specific time period or a specific amount can be retrieved with less data to describe the location of that data. For example, the beginning of a snapshot at the start of, say, the first wear leveling group 227-1, can be stored, and the first wear leveling group 227-1 contains complete snapshots spanning multiple superblocks. If the memory subsystem receives a message to switch to a later wear leveling group, then the previous wear leveling group (227-1) becomes the previous snapshot and the new snapshot is compiled.

[0063] Figure 3 The flowchart illustrates a method 350 corresponding to the use of a media management group according to some embodiments of the present disclosure. Method 350 may be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, method 350 is performed by… Figure 1 Group component 113 executes. Although shown in a specific order or sequence, the order of processes is modifiable unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. Furthermore, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0064] In operation 351, each of a plurality of superblocks can be assigned to one of a plurality of groups. The plurality of groups can be used to perform several media management operations. The several media management operations may include several wear leveling operations. The plurality of groups may include multiple wear leveling groups for performing the several wear leveling operations. Assignment can be made by means of a connection to a memory device (e.g., ...). Figure 1 The processing apparatus of the memory device 130 and / or 140 in the memory device performs the operation. The memory device may be similar to Figure 1Memory devices 130 and / or 140. In some embodiments, the loss balancing group may be determined to include a specific number of superblocks, such as in combination Figures 2A to 2C Description. The number of superblocks in a loss group can be two, four, six, eight, etc., which are given as possible numbers of instances, and other instances are not limited to these numbers.

[0065] In operation 352, the order of each member in the loss balancing group can be monitored. For example, the first loss balancing group (e.g., first loss balancing group 227-1) can be ranked first, the second loss balancing group (e.g., second loss balancing group 227-2) can be ranked second, and so on. In operation 353, data can be written to a specific superblock of one of the loss balancing groups. As an example, data can be written to a block in the specific superblock of the first loss balancing group (e.g., the first superblock), then to a block in the superblock of the second loss balancing group, and so on.

[0066] In operation 354, an additional superblock following a specific superblock (e.g., the third superblock of the first loss balancing group, since the second superblock may have been previously erased) can be erased. In operation 355, a message can be received from the host. In response to not receiving a message from the host (“No”), data continues to be written to the specific superblock until the specific superblock is filled with data, then data is written to the second superblock, and so on. In operation 356, in response to receiving a message from the host (“Yes”), writing data to the specific superblock can be stopped. A message from the host may indicate that data should be written to the next subsequent superblock. A message from the host may indicate an error and / or failure during data writing. In operation 357, data can continue to be written to a second additional superblock that was previously erased and is between the specific superblock and the additional superblock.

[0067] In some embodiments, in response to completing writing data to a specific block of a first wear leveling group, data may be written to the next block in the first group. In some embodiments, in response to completing writing data to a specific superblock of the first wear leveling group, data is written to the next superblock in the first wear leveling group. In some embodiments, in response to completing writing data to the first wear leveling group, data is written to the beginning portion of the first wear leveling group and previously written data is overwritten. In some embodiments, in response to a programming failure in the first block of the first superblock, the block location and page location where the programming failure occurred are recorded, and subsequent data is written to a third superblock that was erased before the writing of data to the first block was initiated. In some embodiments, in response to a second programming failure while writing to the third superblock, subsequent data is written to an erased second superblock. In some embodiments, method 350 may further include, in response to receiving a request from the host to send snapshot data, recording the last page position in the superblock that the processing device is writing to when the request is received. In some embodiments, method 350 may further include sending data written to the first wear leveling group to the host as snapshot data and writing subsequent data to the next group in the first group.

[0068] Figure 4 This is a flowchart corresponding to method 470 using a media management group according to some embodiments of the present disclosure. Method 470 may be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, method 470 is performed by… Figure 1 Group component 113 executes. Although shown in a specific order or sequence, the order of processes is modifiable unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. Furthermore, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0069] In operation 471, each of a plurality of superblocks can be assigned to one of a plurality of groups. The plurality of groups can be plurality of wear leveling groups. The plurality of wear leveling groups can be used for several memory management operations, such as wear leveling operations. The groups can be determined at a processing device coupled to the memory device. Each of the wear leveling groups can contain a superblock of the memory device. Determination can be made by a processing device coupled to the memory device (e.g., ...). Figure 1 The processing apparatus of the memory device 130 and / or 140 in the memory device performs the operation. The memory device may be similar to Figure 1Memory devices 130 and / or 140. In some embodiments, the loss balancing group may be determined to include a specific number of superblocks, such as in combination Figures 2A to 2C Description. The number of superblocks in a loss group can be two, four, six, eight, etc., which are given as possible numbers of instances, and other instances are not limited to these numbers.

[0070] In operation 472, the order in which each of the loss balancing groups is written can be monitored at the processing device. For example, the first loss balancing group (e.g., first loss balancing group 227-1) may be first, the second loss balancing group (e.g., second loss balancing group 227-2) may follow the first loss balancing group, and so on.

[0071] In operation 473, data can be written to the first block of the first superblock of the first group in the loss balancing group. In response to the completion of writing data to the first block, data can be written to the second block of the first superblock. In response to the completion of writing data to the second block, data can be written to the third block of the first superblock, and so on, until the first group has stored data in each of its superblocks.

[0072] In operation 474, the second superblock of the first group can be erased concurrently with the writing of data to the first superblock of the first group. While the writing of data to the first superblock is complete, the third superblock can be erased while data is being written to the second superblock (which was previously erased). While the writing of data to the second superblock is complete, the fourth superblock can be erased while data is being written to the third superblock (which was previously erased), and so on in a repeating pattern.

[0073] Figure 5 This is a block diagram of an example computer system 500 operable in embodiments of this disclosure. For example, Figure 5 This describes an example machine of a computer system 500, in which a set of instructions for causing a machine to perform any or more of the methodologies discussed herein can be executed. In some embodiments, the computer system 500 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., a memory subsystem). Figure 1 The memory subsystem 110) or can be used to perform controller operations (e.g., execute the operating system to perform operations corresponding to...). Figure 1 (Operation of storage mode component 113). In alternative embodiments, the machine may be connected (e.g., networked) to a LAN, internal network, external network, and / or other machines on the Internet. The machine may operate as a server or client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

[0074] A machine can be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network device, a server, a network router, a switch, or a bridge, or any machine capable of (sequentially or otherwise) executing a set of instructions specifying actions to be taken by said machine. Furthermore, while a single machine is described, the term "machine" should also be considered as any collection of machines that individually or jointly execute one (or more) instructions to perform any or more of the methodologies discussed herein.

[0075] The example computer system 500 includes a processing device 502, a main memory 504 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (e.g., synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), a static memory 506 (e.g., flash memory, static random access memory (SRAM)) and the like) and a data storage system 518, which communicate with each other via a bus 531.

[0076] Processing device 502 represents one or more general-purpose processing devices, such as microprocessors, central processing units, or the like. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or multiple processors implementing combinations of instruction sets. Processing device 502 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, or the like. Processing device 502 is configured to execute instructions 526 for performing the operations and steps discussed herein. Computer system 500 may further include a network interface device 508 for communication via network 511.

[0077] The data storage system 518 may include a machine-readable storage medium 524 (also referred to as a computer-readable medium) on which one or more sets of instructions 526 or software embodying any or more of the methodologies or functions described herein are stored. The instructions 526 may also reside wholly or at least partially in main memory 504 and / or processing device 502 during execution by computer system 500, which also constitute machine-readable storage media. The machine-readable storage medium 524, data storage system 518, and / or main memory 504 may correspond to... Figure 1 The memory subsystem 110.

[0078] In one embodiment, instruction 526 includes implementing a component corresponding to a group (e.g., Figure 1The functional instructions of the group component 113). Although the machine-readable storage medium 524 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be understood to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be understood to include any medium capable of storing or encoding a set of instructions that are executed by a machine and cause the machine to perform any or more of the methodologies of this disclosure. The term "machine-readable storage medium" should be understood accordingly to include (but is not limited to) solid-state memory, optical media, and magnetic media.

[0079] In some embodiments, the computing system 500 may include a memory subsystem within a vehicle, the memory subsystem may include a controller (e.g., Figure 1 The controller 115 in the system and a non-volatile memory device. The vehicle including the computing system 500 can be a car (e.g., a sedan, train, truck, etc.), a connected vehicle (e.g., a vehicle with computing capabilities to communicate with an external server), an autonomous vehicle (e.g., a vehicle with self-automation capabilities such as self-driving), a drone, an aircraft, a ship, and / or anything used to transport people and / or goods. The computing system 500 (and the host coupled to the computing system 500 (e.g., a controller 115 in the system) and a non-volatile memory device. Figure 1 The host system 120 in the system can be coupled directly or via a transceiver to several sensors. The transceiver may be able to wirelessly receive time-based telemetry sensor data from the sensors, for example, via radio frequency communication. In at least one embodiment, each of the sensors can wirelessly communicate with the computing system 500 via a transceiver. In at least one embodiment, each of the sensors is directly connected to the computing system 500 (e.g., via leads or optical cables). As used herein, telemetry sensor data means data collected by the sensors remotely from the memory subsystem (receiving device) where the data is stored. Telemetry sensor data is time-based because the data is time-dependent. The time corresponding to each data point can be stored along with the telemetry data or data derived from it based on some metric, such as the known start time and date of the data. Time can be used, for example, to replay sequences preceding the incident.

[0080] The sensor may include a camera sensor that collects data from the front of the vehicle. Some sensors may be microphone sensors that collect data from the front, middle, and rear of the vehicle. Some sensors may be camera sensors that collect data from the rear of the vehicle. As another example, the sensor may be a tire pressure sensor. As another example, the sensor may be a navigation sensor, such as a Global Positioning System (GPS) receiver. As another example, the sensor may be a speedometer. As another example, the sensor may represent several engine sensors, such as a temperature sensor, a pressure sensor, a voltmeter, an ammeter, a tachometer, a fuel gauge, etc. As another example, the sensor may represent a camera.

[0081] A host computer (e.g., host system 120 that can be coupled to computing system 500) can execute instructions to provide a comprehensive control system and / or operating system to the vehicle. The host computer can be a controller designed to assist in the vehicle's automation efforts. For example, the host computer can be an Advanced Driver Assistance System (ADAS) controller. ADAS can monitor data to prevent accidents and provide warnings of potentially unsafe situations. For example, ADAS can monitor controllers in the vehicle and control the vehicle's operation to avoid accidents or injuries (e.g., to avoid accidents in the presence of an incapacitated user of the vehicle). The host computer may need to act quickly and make decisions to avoid accidents. A memory subsystem can store reference data in a non-volatile memory device 616 so that time-based telemetry sensor data from sensors can be compared with the reference data by the host computer to make rapid decisions.

[0082] Some parts of the foregoing detailed description have been presented based on the algorithms and symbolic representations of operations on data bits within computer memory. These algorithmic descriptions and representations are methods used by those skilled in the art of data processing to most effectively convey the essence of their work to others skilled in the art. Algorithms are, and generally are, conceived herein as self-consistent sequences of operations that lead to desired results. An operation is an operation that requires the physical manipulation of physical quantities. These quantities are, though not necessarily, in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has proven convenient, and sometimes, for the sake of custom, these signals are referred to in principle as bits, values, elements, symbols, characters, items, numbers, or the like.

[0083] However, it should be remembered that all these and similar terms are associated with appropriate physical quantities and are merely convenient labels for application to these quantities. This disclosure may refer to the operation and processes of a computer system or similar electronic computing device, which manipulates or transforms data representing physical (electronic) quantities in the registers and memories of the computer system into other data similarly represented in the memory or registers of the computer system or other such information storage systems.

[0084] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for its intended purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. This computer program may be stored in a computer-readable storage medium, such as (but not limited to) any type of disk (including solid-state drives (SSDs), hard disk drives (HDDs), floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0085] The algorithms and displays presented herein do not inherently relate to any particular computer or other device. Various general-purpose systems can be used in conjunction with the programs taught herein, or it may prove convenient to construct more specialized devices to implement the methods. Structures for various such systems will appear as described below. Furthermore, this disclosure is not intended to refer to any particular programming language. It should be understood that various programming languages ​​can be used to implement the teachings of this disclosure as described herein.

[0086] This disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, the instructions being used to program a computer system (or other electronic device) to perform processes according to this disclosure. The machine-readable medium includes any means for storing information in a form readable by a machine (e.g., a computer). In some embodiments, the machine-readable (e.g., computer-readable) medium includes machine-readable storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory devices, etc.

[0087] In the foregoing description, embodiments of the present disclosure have been described with reference to specific exemplary embodiments. It will be apparent that various modifications may be made thereto without departing from the broader spirit and scope of the embodiments of the present disclosure set forth in the appended claims. The description and drawings should therefore be regarded in an illustrative rather than restrictive sense.

Claims

1. A media management group system for a storage subsystem, comprising: Memory devices; and A processing device coupled to the memory device, the processing device being configured to perform operations including: Monitor the order in which multiple superblock groups are written, including: Each superblock consists of a set of data blocks; and Each of the plurality of superblock groups includes at least two superblocks, wherein each of the superblocks in the plurality of superblock groups is assigned to perform media management operations, and wherein a first number of superblocks in each of the plurality of superblock groups is determined by the number of storage locations available for tracking data, such that when there is a first number of storage locations available for tracking the data, each of the plurality of superblock groups has a first number of superblocks, and when there is a second number of storage locations available for tracking the data, each of the plurality of superblock groups has a second number of superblocks less than the first number of superblocks, and the second number of storage locations available for tracking the data is greater than the first number of storage locations available for tracking the data; Based at least in part on the monitored order, the data is written to a portion of the first superblock of the first group within the plurality of superblock groups; and Additional data is written to an additional portion of the second superblock in the second group of the plurality of superblock groups, based at least in part on the detected order and the occurrence of the events.

2. The system according to claim 1, wherein: The media management operations include loss leveling operations; and The event includes one of the following: receiving a request from the host to switch to a group different from the first group in the plurality of superblock groups, reaching the threshold loss limit of the first group in the plurality of superblock groups, a programming error, or a combination thereof.

3. The system of claim 1, wherein each of the plurality of superblock groups comprises a plurality of blocks of the memory of the memory device.

4. The system of claim 1, wherein the processing device is configured to further perform operations including: Write data to each of the blocks in each of the superblocks in the first group; and In response to writing to the end of the first group, data continues to be written to the beginning of the first group, overwriting the previously written data at the beginning.

5. The system of claim 1, wherein the processing device is configured to further perform an operation including erasing the third superblock of the first group, wherein: The third superblock is ordered to be written after the first superblock; and The third superblock is concurrently erased with the write of the data to the first block of the first superblock.

6. The system of claim 5, wherein the processing means is configured to further perform the operation of writing additional data to the third superblock in response to a failure to write to the first block.

7. The system of claim 1, wherein the processing means is configured to further perform operations including recording the last write position to which data was written when the request was received in response to receiving a request from the host to write to a second group in the plurality of superblock groups.

8. The system of claim 7, wherein the processing means is configured to further perform operations including determining additional groups among the plurality of superblock groups to be written based on loss leveling characteristics.

9. A method for media management groups in a storage subsystem, comprising: At the processing unit, the order in which multiple superblock groups are written is monitored, including: Each superblock consists of a set of data blocks; and Each of the plurality of superblock groups includes at least two superblocks, wherein each of the superblocks in the plurality of superblock groups is assigned to perform media management operations, and wherein the number of superblocks in each of the plurality of superblock groups is determined by the number of storage locations available for tracking data, such that when there is a first number of storage locations available for tracking the data, each of the plurality of superblock groups has a first number of superblocks, and when there is a second number of storage locations available for tracking the data, each of the plurality of superblock groups has a second number of superblocks less than the first number of superblocks, and the second number of storage locations available for tracking the data is greater than the first number of storage locations available for tracking the data; The data is written to the first block of the first superblock in the first group of the plurality of superblock groups, based at least in part on the detected order. The second superblock of the first group is erased concurrently with the first superblock that writes data to the first group; Determine the oldest group among the plurality of superblock groups; and Based at least in part on the monitored order and the determination of the oldest group, additional data is written to the first superblock of the second group among the plurality of superblock groups.

10. The method of claim 9, further comprising writing data to the next block in the first group in response to completing the writing of data to the block in the first group.

11. The method of claim 9, further comprising writing data to the next superblock in the first group in response to completing the writing of data to the superblock of the first group.

12. The method of claim 9, further comprising writing data to the beginning portion of the first group and overwriting previously written data in response to completing writing data to the first group.

13. The method of claim 9, further comprising responding to a programming failure of the first block in response to the first superblock: Record the block location and page location where the programming failure occurred; and Subsequent data is written to a third superblock that was erased before the write to the first block was initiated.

14. The method of claim 13, further comprising writing subsequent data to the erased second superblock in response to a second programming failure during writing to the third superblock.

15. The method of claim 9, further comprising recording the last page position in the superblock that the processing device is writing at the time the request is received, in response to receiving a request from the host to send snapshot data.

16. The method of claim 15, further comprising: The data written to the first group is sent to the host as the snapshot data; and Subsequent data will be written to the next group in the order.

17. A memory subsystem media management group device, comprising: A memory device comprising multiple superblocks, wherein each superblock comprises a set of data blocks; A processing device coupled to the memory device, the processing device being configured to perform operations including: At the processing device, the monitoring sequence is as follows: Multiple superblock groups are written to and the loss balancing characteristics associated with each of the multiple superblock groups are monitored; and Each of the superblocks associated with a corresponding group in the plurality of superblock groups is written; Each of the plurality of superblock groups comprises at least two superblocks, each of the superblocks in the plurality of superblock groups is assigned to perform media management operations, and the number of superblocks in each of the plurality of superblock groups is determined by the number of storage locations available for tracking data, such that when there is a first number of storage locations available for tracking the data, each of the plurality of superblock groups has a first number of superblocks, and when there is a second number of storage locations available for tracking the data, each of the plurality of superblock groups has a second number of superblocks less than the first number of superblocks, and the second number of storage locations available for tracking the data is greater than the first number of storage locations available for tracking the data; The data is written to the first superblock of the first group in the plurality of superblock groups; Erase any additional superblocks following the first superblock in the first group; and In response to a programming failure: Stop the write to the first superblock; Record the block location and page location where the programming failure occurred; Continue writing to the previously erased additional superblock; and In response to returning to the first superblock for subsequent writing, writing begins at the recorded block position and the recorded page position.

18. The device of claim 17, wherein the processing means is configured to further perform the operation of writing to a superblock located after the additional superblock.

19. The apparatus of claim 17, wherein the processing means is configured to further perform operations including stopping writing to the first group and continuing writing to a second group of the plurality of superblock groups following the first group in response to receiving a message from the host.

20. The apparatus of claim 19, wherein the processing means is configured to further perform an operation including moving valid data previously written to the second group to the first group in response to writing to the second group.

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