Data programming techniques that store multiple bits of data per memory cell with high reliability

Abstract

This application relates to data programming techniques that store multiple bits of data per memory cell with high reliability. A memory system generates data and has a relationship among groups of data to reliably store a predetermined number of bits in each of the memory cells. For example, a second group of data bits is generated from a first group of data bits. A predetermined number of groups of data is formed having the first group and the second group and having a predetermined relationship (e.g., XOR or XNOR) among the groups of data. Threshold levels of memory cells in a group of memory cells are determined based on a predetermined mapping, where the threshold level of each memory cell is determined to represent one bit from each of the groups of data. In the predetermined mapping, the bit values represented by any two consecutive threshold levels differ by one bit. Threshold voltages in the group of memory cells are programmed according to the threshold levels, thereby storing the groups of data with improved reliability.

Description

Technical Field

[0001] At least some of the embodiments disclosed herein generally relate to memory systems, and more specifically (but not limited to) to techniques for programming voltage thresholds of memory cells in a memory system to store multiple data bits per memory cell. Background Technology

[0002] A memory subsystem may include one or more memory devices for storing data. Memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize a memory subsystem to store data at memory devices and retrieve data from memory devices. Summary of the Invention

[0003] In one aspect, this disclosure relates to a method comprising: receiving a first group of data bits; generating a second group of data bits from the first group to form a plurality of data groups including the first group and the second group and having a predetermined relationship among the data groups; determining a threshold level of a group of memory cells based on a predetermined mapping between bit value combinations and threshold levels, wherein each corresponding memory cell in the group of memory cells is determined to have a corresponding threshold level representing a bit value combination with a bit from each of the plurality of data groups, and wherein the values ​​of data bits represented by any two consecutive threshold levels in the predetermined mapping differ by one bit; and programming threshold voltages of memory cells in the group of memory cells according to the threshold levels to store the plurality of data groups.

[0004] In another aspect, this disclosure relates to a memory device comprising: an integrated circuit package enclosing the memory device; and a plurality of memory cell groups formed on at least one integrated circuit die; wherein, in response to a command identifying a memory cell group within the plurality of memory cell groups, the memory device is configured to: receive a first group of data bits; generate a second group of data bits from the first group to form a plurality of data groups including the first group and the second group; determine a threshold level of a memory cell in the memory cell group based on a predetermined mapping between bit value combinations and threshold levels, wherein each corresponding memory cell in the memory cell group is determined to have a corresponding threshold level representing a bit value combination with a bit from each of the plurality of data groups, and wherein the values ​​of data bits represented by any two consecutive threshold levels in the predetermined mapping differ by only one bit; and program threshold voltages of the memory cells in the memory cell group according to the threshold levels to store the plurality of data groups.

[0005] In another aspect, this disclosure relates to a memory subsystem comprising: a processing means; and at least one memory device having a group of memory cells formed on an integrated circuit die, the memory device being configured to program a threshold level of the group of memory cells in a predetermined number of bits per memory cell according to Gray code, thereby representing a bit value stored in the memory cell by the threshold level of the memory cell; wherein the processing means is configured to generate a plurality of data groups from a first group of data bits having a number of bits less than the predetermined number of bits per memory cell of the group of memory cells, the plurality of data groups having a predetermined number of bits per memory cell of the group of memory cells; and wherein the processing means is configured to provide the plurality of data groups to the memory device to store a bit from each of the plurality of data groups in each memory cell of the group of memory cells. Attached Figure Description

[0006] The embodiments are illustrated by way of example and not by way of limitation in the figures, in which similar references indicate similar elements.

[0007] Figure 1 This describes an example computing system having a memory subsystem according to some embodiments of the present disclosure.

[0008] Figure 2 This describes an integrated circuit memory device according to one embodiment, which has a threshold voltage configured as a programmable memory cell to store data.

[0009] Figure 3 An example is shown of a programmable memory cell according to one embodiment that stores multiple bits per memory cell.

[0010] Figure 4 and 5 This describes a technique, according to some embodiments, for generating data groups to program memory cells at threshold levels determined by Gray code, thereby improving reliability.

[0011] Figure 6 Explanation of reading and using Figure 4 and 5 The reliability of data when programming with this technology is improved.

[0012] Figure 7 Showing recovery from use Figure 4 and 5 The technology is a technique for retrieving data from memory cells using programming techniques.

[0013] Figure 8 A method for writing data into a memory cell according to some embodiments is shown.

[0014] Figure 9 This is a block diagram of an example computer system in which embodiments of the present disclosure can be operated. Detailed Implementation

[0015] At least some aspects of this disclosure are related to techniques for improving the reliability of storing data in memory cells within a memory subsystem. The following is combined with... Figure 1 Describe examples of storage devices and memory modules. Generally, a host system may utilize a memory subsystem that includes one or more components, such as a memory device for storing data. The host system can provide data to be stored in the memory subsystem and can request to retrieve data from the memory subsystem.

[0016] Integrated circuit memory cells (e.g., flash memory cells) can be programmed to store data by means of their states at predefined voltages. For example, if a memory cell is configured / programmed to be in a state that allows a large current to flow through the memory cell at a predefined voltage, the memory cell positively stores a bit one; otherwise, the memory cell positively stores a bit zero. Furthermore, a memory cell can store multiple data bits by being configured / programmed differently at multiple predefined voltages. For example, a memory cell can store multiple data bits by having combinations of states at multiple predefined voltages; and the different combinations of states of the memory cell at predefined voltages can be interpreted to represent different states of the data bits stored in the memory cell.

[0017] However, after the state of the integrated circuit memory cell is configured / programmed using the write operation to store data in the memory cell, the optimized threshold voltage for reading the memory cell can be shifted due to several factors, such as charge loss, read interference, cross-temperature effects (e.g., write and read at different operating temperatures), especially when the memory cell is programmed to store multiple data bits.

[0018] Data can be encoded with redundant information to facilitate error detection and recovery. When data with encoded redundant information is stored in a memory subsystem, the memory subsystem can detect errors in data retrieved directly from memory cells within the memory subsystem and / or recover the original data used to generate the data stored in the memory cells. Recovery operations can be successful (or have a high probability of success) when the data retrieved directly from memory cells in the memory subsystem contains fewer errors or has a low bit error rate. For example, error correction codes (ECC), such as low-density parity-check (LDPC) codes, can be used to perform error detection and data recovery.

[0019] In some cases, it may be desirable to store a reduced number of bits (e.g., N-1) per memory cell in a memory device having a circuitry that programs a threshold voltage for a group of memory cells to store a predetermined number of bits (e.g., N) per memory cell. Adding a separate circuitry optimized to independently program the threshold voltage for a group of memory cells to store a reduced number of bits (e.g., N-1) per memory cell can increase the complexity and / or cost of the memory device hardware. Alternatively, dummy data appendages (e.g., all zeros or all ones) can be supplied to increase the number of bits per cell (e.g., up to N), thereby matching the functionality of the memory device's existing circuitry at the programming threshold voltage. However, storing dummy data appendages (e.g., all zeros or all ones) for a given amount of data with a reduced number of bits (e.g., N-1) per memory cell, such that the total number of bits per memory cell equals a predetermined number (e.g., N), can reduce the reliability of retrieving data from memory cells compared to programming memory cells with a reduced number of bits (e.g., N-1) per memory cell.

[0020] At least some aspects of this disclosure address the above and other drawbacks by generating dummy data appendage groups from given data having a reduced number of bits. Data appendage groups can be generated to establish predetermined relationships within the data groups, thereby improving the reliability of retrieving data from memory cells programmed with a predetermined number of bits per memory cell (e.g., N).

[0021] For example, a memory device can be configured to map a predetermined number of bits (e.g., N) to a threshold voltage according to Gray code (also known as reflected binary code or reflected binary) when programming a threshold voltage of a memory cell to store data. Data appendage groups can be generated based on an XOR operation over a reduced number of bits (e.g., N-1). Alternatively, the inverse of the XOR result (corresponding to XNOR over a reduced number of bits) can be used. Programming data appendage groups with given data to a predetermined number of bits (e.g., N) per memory cell produces highly reliable data retrieval.

[0022] Different combinations of the values ​​of the predetermined number of bits N can be used to represent numbers from 0 to 2. N Different numbers from -1. Gray code is a mapping where the value of one and only one bit changes as the number represented by the bit combination changes to the next larger or smaller number. It can be 2... NA threshold voltage for a programmable memory cell at a given voltage level represents a combination of values ​​for a predetermined number of bits (N). The threshold voltage of a memory cell programmed at a voltage level represents the combination of N bits of values ​​stored in the memory cell corresponding to that voltage level. In the case of Gray code used for mapping bit value combinations and voltage threshold levels, only one bit changes value when the threshold level is shifted up or down in an increment. By generating data appendage groups based on XOR / XNOR, the dataset to be programmed may lack odd-numbered voltage threshold levels or have even-numbered voltage threshold levels. This arrangement increases the gap between possible voltage thresholds representing different data and thus improves the reliability of reading data from the memory cell. Furthermore, when a predetermined bit stored in the memory cell is found to be corrupted, the corrupted bit can be recovered from the remaining bits via XOR. Therefore, the reliability of retrieving data programmed in this manner is improved.

[0023] Figure 1 This description describes an example computing system 100 including a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of the like.

[0024] The memory subsystem 110 may be a storage device, a memory module, or a combination of both. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0025] The computing system 100 may be a computing device, such as a desktop computer, a laptop computer, a web server, a mobile device, a vehicle (e.g., an airplane, a drone, a train, a car or other means of transport), a device with Internet of Things (IoT) capabilities, an embedded computer (e.g., an embedded computer contained in a vehicle, industrial equipment or a networked business device), or such a computing device containing memory and processing devices.

[0026] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. Figure 1This describes an example of a host system 120 coupled to a memory subsystem 110. As used herein, “coupled to…” or “coupled with…” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intervening component), whether wired or wireless, including connections such as electrical, optical, and magnetic connections.

[0027] Host system 120 may include a processor chipset (e.g., processing device 118) and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., controller 116) (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a Peripheral Component Interconnect High Speed ​​(PCIe) controller, a Serial Advanced Technology Attachment (SATA) controller). Host system 120 uses memory subsystem 110, for example, to write data to and read data from memory subsystem 110.

[0028] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS) interfaces, Dual Data Rate (DDR) memory bus interfaces, Small Computer System Interface (SCSI), Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM socket interfaces supporting Dual Data Rate (DDR)), Open NAND Flash Interface (ONFI), Dual Data Rate (DDR) interfaces, Low Power Dual Data Rate (LPDDR) interfaces, or any other interfaces. The physical host interface can be used to transmit data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a PCIe interface, host system 120 can further utilize an NVM High Speed ​​(NVMe) interface to access components (e.g., memory device 130). The physical host interface provides an interface for transmitting control, address, data and other signals between the memory subsystem 110 and the host system 120. Figure 1 The memory subsystem 110 is described as an example. Generally, the host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0029] The processing unit 118 of the host system 120 may be, for example, a microprocessor, a central processing unit (CPU), a processor core, an execution unit, etc. In some instances, the controller 116 may be referred to as a memory controller, a memory management unit, and / or an initiator. In one instance, the controller 116 controls communication on a bus coupled between the host system 120 and the memory subsystem 110. Generally, the controller 116 may send commands or requests for access to memory devices 130, 140 to the memory subsystem 110. The controller 116 may additionally include an interface circuitry for communicating with the memory subsystem 110. The interface circuitry may translate responses received from the memory subsystem 110 into information for the host system 120.

[0030] The controller 116 of the host system 120 can communicate with the controller 115 of the memory subsystem 110 to perform operations, such as reading, writing, or erasing data at memory devices 130, 140, and other such operations. In some cases, the controller 116 is integrated within the same package as the processing device 118. In other cases, the controller 116 is separated from the package of the processing device 118. The controller 116 and / or the processing device 118 may include hardware such as one or more integrated circuits (ICs) and / or discrete components, buffer memories, cache memories, or combinations thereof. The controller 116 and / or the processing device 118 may be a microcontroller, a special-purpose logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or another suitable processor.

[0031] Memory devices 130 and 140 may contain different types of non-volatile memory components and / or any combination of volatile memory components. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0032] Some examples of non-volatile memory components include negative-and / not-AND (NAND) type flash memory and in-place write memory, such as three-dimensional crosspoint ("3D crosspoint") memory. Crosspoint arrays of non-volatile memory can be combined with stackable cross-grid data access arrays to perform bit storage based on changes in volume resistance. Furthermore, compared to many flash-based memories, crosspoint non-volatile memory can perform in-place write operations, where non-volatile memory cells can be programmed without pre-erasing them. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0033] Each of the memory devices 130 may include one or more arrays of memory cells. One type of memory cell (e.g., single-level cell (SLC)) may store one bit per cell. Other types of memory cells (e.g., multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), and five-level cell (PLC)) may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, PLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion, an MLC portion, a TLC portion, a QLC portion, and / or a PLC portion of memory cells. The memory cells of the memory device 130 may be grouped into pages, which may refer to logical units of the memory device used for storing data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0034] While non-volatile memory devices, such as 3D crosspoint and NAND type memories (e.g., 2D NAND, 3D NAND), are described, memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), auto-select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0035] The memory subsystem controller 115 (or simply controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, or erasing data at the memory device 130, and other such operations (e.g., in response to commands scheduled on the command bus by controller 116). Controller 115 may include hardware such as one or more integrated circuits (ICs) and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system with dedicated (e.g., hard-decoded) logic to perform the operations described herein. Controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or another suitable processor.

[0036] Controller 115 may include processing device 117 (e.g., processor) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines for controlling the operation of memory subsystem 110, including communication between memory subsystem 110 and host system 120.

[0037] In some embodiments, local memory 119 may include memory registers storing memory pointers, fetched data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although in Figure 1 The instance memory subsystem 110 has been described as including a memory subsystem controller 115, but in another embodiment of this disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but instead may rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0038] Generally, controller 115 can receive commands or operations from host system 120 and can translate these commands or operations into instructions or appropriate commands to enable the desired access to memory device 130. Controller 115 may handle other operations such as wear leveling, garbage collection, error detection and error correction (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses, namespaces) and physical addresses (e.g., physical block addresses) associated with memory device 130. Controller 115 may additionally include a host interface circuitry for communicating with host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into instructions for accessing memory device 130 and responses associated with memory device 130 into information for host system 120.

[0039] The memory subsystem 110 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 110 may include caches or buffers (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that can receive addresses from the controller 115 and decode the addresses to access the memory device 130.

[0040] In some embodiments, memory device 130 includes a local media controller 150, which operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 is a managed memory device, which is a native memory device combined with a local controller (e.g., local media controller 150) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0041] Controller 115 and / or memory device 130 may include a programming manager 113 configured to program a threshold voltage of a memory cell to store a predetermined number of bits per memory cell by generating additional data from a dataset having a reduced number of bits per memory cell. In some embodiments, controller 115 in memory subsystem 110 and / or controller 150 in memory device 130 may include at least a portion of programming manager 113. In other embodiments, or in combination, controller 116 and / or processing device 118 in host system 120 may include at least a portion of programming manager 113. For example, controller 115, controller 116, and / or processing device 118 may include a logic circuitry system implementing programming manager 113. For example, controller 115 or processing device 118 of host system 120 (e.g., a processor) may be configured to execute instructions stored in memory for performing the operations of programming manager 113 described herein. In some embodiments, programming manager 113 is implemented in an integrated circuit chip disposed in memory subsystem 110. In other embodiments, the programming manager 113 may be part of the following: firmware of the memory subsystem 110, operating system of the host system 120, device driver, or application, or any combination thereof.

[0042] For example, a programming manager 113 implemented in controller 115 and / or controller 150 may receive a reduced number (e.g., N-1) of data groups (e.g., pages) to be programmed into memory cells in memory device 130, which stores a predetermined number (e.g., N) of bits per memory cell. The programming manager 113 generates additional data groups (e.g., pages) by applying an XOR (or XNOR) operation to the reduced number of data groups. The combination of the additional groups and the reduced number of groups provides a predetermined number of groups to be stored in the memory cell group. When memory device 130 has the predetermined number of data groups, memory device 130 programs the threshold voltage of the memory cell group to store the predetermined number of data groups in a predetermined number of bits per memory cell using a Gray code mapping between threshold voltage levels and bit value combinations. This improves the reliability of retrieving data from the memory cells.

[0043] Figure 2 This describes an integrated circuit memory device according to one embodiment, having a threshold voltage configured as a programmable memory cell to store data. For example, Figure 1 The memory device 130 in the memory subsystem 110 can be used Figure 2 The integrated circuit memory device 130 is used for implementation.

[0044] The integrated circuit memory device 130 may be enclosed in a single integrated circuit package. The integrated circuit memory device 130 includes multiple groups 131, ..., 133 of memory cells that may be formed in one or more integrated circuit dies. A typical memory cell in group 131 (or group 133) may be programmed to store one or more data bits.

[0045] Some memory cells in the integrated circuit memory device 130 can be configured to operate together for a specific type of operation. For example, memory cells on an integrated circuit die can be organized into planes, blocks, and pages. A plane contains multiple blocks; a block contains multiple pages; and a page can have multiple strings of memory cells. For example, an integrated circuit die can be the smallest unit capable of independently executing commands or reporting status; the same concurrent operation can be performed in parallel on multiple planes in the integrated circuit die; a block can be the smallest unit for performing an erase operation; and a page can be the smallest unit for performing a data programming operation (writing data into a memory cell). Each string of memory cells is connected to a common bit line; and the control gate of a memory cell at the same location in a string within a block or page is connected to a common word line. Control signals can be applied to the word line and bit line to address individual memory cells.

[0046] The integrated circuit memory device 130 has a communication interface 147 to receive a command with address 135 from the controller 115 of the memory subsystem 110, retrieve memory data 144 from the memory cell identified by memory address 135, and provide at least the memory data 144 as a response to the command. Optionally, the memory device 130 may decode the memory data 144 (e.g., using error correction code (ECC) technology) and provide decoded data as a response to the command. The address decoder 141 of the integrated circuit memory device 130 translates address 135 into a control signal to select a group of memory cells in the integrated circuit memory device 130; and the read / write circuitry 143 of the integrated circuit memory device 130 performs an operation to determine the memory data 144 stored in the memory cell at address 135.

[0047] Integrated circuit memory device 130 has a latch set 145 to temporarily hold memory data 144 while read / write circuitry 143 is programming a threshold voltage of a group of memory cells (e.g., 131 or 133). For example, read / write circuitry 143 programs the threshold voltage of memory cells in group 131 to store N bits per memory cell. Group of memory cells (e.g., 131 or 133) has M memory cells. Latch 145 is configured to store N×M data bits in the form of N data groups. Each of the data groups has M data bits that will be stored in the M memory cells of the group of memory cells (e.g., 131 or 133).

[0048] When latch 145 has N data groups to be stored in a group of memory cells (e.g., 131), programming manager 113 is configured to determine and program the threshold voltage levels of the memory cells in the group of memory cells (e.g., 131). The threshold voltage levels are determined based on bit values ​​in memory data 144 and Gray codes that map combinations of bit values ​​to threshold levels, such that any two combinations of bit values ​​represented by two consecutive threshold levels differ by exactly one bit.

[0049] In one embodiment, when memory device 130 receives N-1 data groups for storage in a group of memory cells (e.g., 131), programming manager 113 generates the Nth data group by applying XOR (or XNOR) to the N-1 data groups. Since programming manager 113 programs the threshold voltage of the memory cell group (e.g., 131) according to Gray code, the threshold voltage of the memory cells in the group (e.g., 131) is automatically optimized to achieve high reliability, such as... Figure 6 As illustrated in the examples.

[0050] In another embodiment, a programming manager 113 implemented in the controller 115 of the memory subsystem 110 is configured to generate an Nth data group such that the N data groups provided in latch 145 for storage in a group of memory cells (e.g., 131) are correlated with each other via XOR (or XNOR). In this scenario, the read / write circuitry 143 does not need to know about the generation of the Nth data group or the relationships among the N data groups. The memory device 130 can program the N XOR-correlated (or XNOR-correlated) data groups in latch 145 in the same manner as programming N independent data groups. By programming the N data groups generated by the controller 115 of the memory subsystem 110 to have an XOR / XNOR relationship, the reliability of retrieving data from the group of memory cells (e.g., 131) is automatically improved, such as... Figure 6 As illustrated in the examples.

[0051] In another embodiment, a programming manager 113 implemented in host system 120 is configured to generate N data groups correlated with each other via XOR or XNOR. When such a collection of N data groups is provided as memory data 144 to latch 145 for programming into memory cell groups (e.g., 131 or 133) according to Gray code, the reliability of retrieving data from memory cell group (e.g., 131) is automatically improved.

[0052] Figure 3 An example is shown where a programmable memory cell, according to one embodiment, stores multiple bits per memory cell. For example, Figure 3 Instances can be implemented in Figure 1 and / or Figure 2 In the memory device 130.

[0053] exist Figure 3 In this configuration, memory cell group 131 has memory cells 137, ..., 139. Several data groups 151, 157, ..., 159 provide data bits to be stored in memory cells 137, ..., 139. The number of bits provided in each data group (e.g., 157, 159, or 151) is equal to the number of memory cells 137 to 139 in memory cell group 131. Each memory cell (e.g., 139 or 137) stores a set of bits, with each of the data groups 151, 157, ..., and 159 contributing one bit.

[0054] For example, data bits 161, 163, ..., 165 from data groups 151, 157, ..., 159 are stored in a memory cell 137; and the voltage threshold of memory cell 137 is programmed by read / write circuitry 143 to represent the values ​​of data bits 161, 163, ..., 165. Similarly, data bits 171, 173, ..., 175 from data groups 151, 157, ..., 159 are stored in another memory cell 139 and represented by the voltage threshold level of memory cell 139.

[0055] Optionally, the data bits in the data group may be organized in codewords 153, ..., 155 according to error detection and data recovery techniques (such as error correction codes (ECC), low-density parity-check (LDPC) codes).

[0056] For example, codeword 153 in data group 151 may contain data bits 161 to 162. When an error occurs in one of the data bits in codeword 153, the error can be detected and corrected (e.g., using a low-density parity check (LDPC) technique).

[0057] When data groups 151, 157, ..., 159 are stored in latches 181, 183, ..., 185, the read / write circuit 143 programs the threshold values ​​of memory cells 137, ..., 139, such that the voltage threshold values ​​of memory cells 137, ..., 139 represent the values ​​of the corresponding data bits from data groups 151, 157, ..., 159.

[0058] Based on Gray code, combinations of values ​​of data bits (e.g., 161, 163, ..., 165) to be stored in memory cells (e.g., 137) are mapped to voltage threshold levels of the memory cells (e.g., 137). For example, the read / write circuit 143 may include a Gray code table (e.g., as provided by...) mapping between the values ​​of the bit set (e.g., 161, 163, ..., 165) of the memory cells (e.g., 137) and the threshold levels of the values ​​of the representation bit set (e.g., 161, 163, ..., 165) of the memory cells (e.g., 137). Figure 6 (As illustrated in the table).

[0059] When a reduced number of data groups (e.g., 157 to 159) need to be stored in memory cell group 131, additional data groups (e.g., 151) can be calculated based on XOR (or XNOR) operation, thereby automatically improving and / or optimizing the reliability of memory data 144 stored in memory cells (e.g., 137 to 139) in the form of voltage thresholds programmed according to Gray code.

[0060] Figure 4 and 5 This describes a technique, according to some embodiments, for generating data groups to program memory cells at threshold levels determined by Gray code, thereby improving reliability.

[0061] exist Figure 4 In this process, data bit 161 is computed by applying XOR operation 201 to data bits 163 to 165. For example, after computed the XOR result of two of the data bits 163 to 165, an updated result can be obtained by XORing said result with another of the data bits 163 to 165, until all data bits 163 to 165 have participated in the XOR computation once. Therefore, data bits 161, 163, ..., 165 form an XOR relationship, where any one of the data bits (e.g., 161 or 163) is equal to the result of applying XOR operation 201 to the other data bits.

[0062] For example, for use Figure 3 The read / write circuit 143 stores data groups 157 to 159 into memory cell group 131, and calculates additional data group 151 by XORing data groups 151, 157 to 159. Each data bit (e.g., 161) in data group 151 is obtained by applying XOR operation 201 to the corresponding data bits (e.g., 163, ..., 165) in a given data group 157, ..., 159.

[0063] Therefore, each codeword in data group 151 (e.g., 153) is also the result of a bitwise XOR operation of the corresponding codeword in given data groups 157, ..., 159; and the codewords in data groups 151, 157, ..., 159 form an XOR relationship, where any codeword in data group (e.g., 157) is equal to the XOR operation of the corresponding codeword from the remaining data groups (e.g., 151, 159, ...). This property / relationship can be used to recover codewords in data groups when codewords fail to be decoded in ECC / LDPC operations.

[0064] Figure 4 This illustrates an instance where the XOR operation 201 produces an additional data group 151. Similarly, Figure 5This illustrates another instance of using XNOR operation 202 to generate additional data group 151. The additional data group 151 calculated using XNOR operation 202 is equal to the bitwise inversion of the corresponding data group 151 calculated using XNOR operation 202. When XNOR operation 202 is used to generate additional data group 151, the codewords in data groups 151, 157, ..., 159 form an XNOR relationship, where any codeword in data group (e.g., 157) is equal to the XNOR of the corresponding codeword from the remaining data groups (e.g., 151, 159, ...). This property / relationship can also be used to recover codewords in data groups when codewords fail to be decoded in ECC / LDPC operations.

[0065] exist Figure 4 and 5 In the Gray code-based mapping 203, the set of data bits 161, 163, ..., 165 with an XOR or XNOR relationship is used to determine the threshold level 205 to be programmed for memory cell 137. After the threshold programming 207 of memory cell 137 reaches the threshold level 205, memory cell 137 has a threshold voltage 209 that can be detected / tested via read / write circuit 143; and the values ​​of data bits 161, 163, ..., 165 can be determined / inferred from the threshold voltage 209 of memory cell 137.

[0066] The XOR or XNOR relationships in data groups 151, 157, ..., 159 not only allow the recovery of failed codewords from other data groups, but also improve the reliability of determining the threshold level (e.g., 205) of memory cells (e.g., 137) and thus improve the reliability of reading memory data 144 represented by a programmed threshold voltage (e.g., 209), as in Figure 6 Further explanation is provided below.

[0067] Figure 6 Explanation of reading and using Figure 4 and 5 The reliability of data when programming with this technology is improved.

[0068] Figure 6 This illustrates an example of data programming in a QLC mode where the threshold voltage of a memory cell (e.g., 137) is programmed to represent a four-bit value. Memory cell pages are programmed (written) together. Since each cell stores four bits, a memory cell page can store the data bits of four data pages, where the number of data bits in a data page equals the number of memory cells in the memory cell page. For example, each data page is... Figure 3 The data group described herein is an instance; and a memory cell page is Figure 3 Examples of memory cell groups described herein.

[0069] Conventionally and / or for convenience, the four data pages used in QLC mode are named Lower Page (LP), Upper Page (UP), Additional Page (XP), and Top Page (TP), respectively. A memory cell (e.g., 137) stores one bit from each of the four pages. Since the values ​​of the four bits stored in the memory cell (e.g., 137) have 16 different combinations, such as... Figure 6 As illustrated in the table, the threshold voltage 209 of the memory cell (e.g., 137) is thus programmed to be one of 16 threshold levels to represent a corresponding combination of bit values.

[0070] Figure 6 The table shown illustrates an example Gray code mapping between the values ​​of four bits (e.g., 161, 163, ..., 165) stored in a QLC memory cell (e.g., 137) and the threshold level 205 of the memory cell (e.g., 137). For example, when a memory cell (e.g., 137) is determined to have a threshold level of 0, the memory cell (e.g., 137) is considered to store 1 as the TP bit, 1 as the XP bit, 1 as the UP bit, and 1 as the LP bit. Similarly, in order to store 0, 1, 1, and 1 as the TP, XP, UP, and LP bits in the memory cell (e.g., 137), the threshold voltage is programmed to level 1. An increase in the threshold level indicates an increase in the threshold voltage 209 programmed for the memory cell (e.g., 137).

[0071] Gray code (e.g., as...) Figure 6 (As illustrated in the table) has the characteristic / property that one and only one bit value changes between two consecutive threshold levels. For example, in Figure 6 In the table, when the threshold level changes from 0 to 1, only the TP bit changes from 1 to 0. Similarly, when the threshold level changes between 1 and 2 (or, 2 and 3, 3 and 4, 4 and 5, etc.), only the LP bit changes (or, only the TP bit, UP bit, TP bit, etc. change, respectively).

[0072] Generally, different Gray codes can be used to map bit value combinations to threshold levels. For example, by... Figure 6 The bits in the table are inverted to obtain alternative Gray codes for mapping bit values ​​to threshold levels. The techniques disclosed herein are not limited to using a specific Gray code.

[0073] Generally, after the read / write circuit 143 completes its operation of programming the threshold voltage 209 of the memory cell 137 according to the threshold level 205, the threshold voltage 209 of the memory cell 137 may not be at the precisely predetermined voltage. After threshold programming 207, the threshold voltage 209 of the memory cell 137 is most likely to be at the predetermined voltage, and the probability of it being at other voltages far from the predetermined voltage decreases.

[0074] For example, when memory cell 137 is programmed to a threshold level of 0, the probability that the threshold voltage 209 of memory cell 137 is at voltage V0 is highest. Curve 211 illustrates the probability distribution of the threshold voltage 209 of memory cell 137 being at a voltage close to V0.

[0075] Similarly, curve 213 illustrates the probability distribution of the threshold voltage 209 of memory cell 137 being close to V1 when memory cell 137 is programmed to threshold level 1.

[0076] In voltage region 219, probability distribution curves 211 and 213 overlap, indicating an ambiguity regarding whether memory cell 137 is programmed to represent one set of bit values ​​at threshold level 0 or another set of bit values ​​when the threshold voltage 209 of memory cell 137 is found to be within region 219. This ambiguity arises because the bit values ​​represented by threshold level 0 and those represented by threshold level 1 differ by one bit (e.g., when using...). Figure 6 The probability of incorrectly reading the TP bit (as described in the table for Gray code) based on the threshold voltage of memory cell 137 is very small. Errors in such bits can typically be detected and corrected via ECC / LPDC decoding of the codeword (e.g., 153) in the data group (e.g., 151) containing the bit.

[0077] When the TP, XP, UP, and LP bits are known to have an XOR relationship, Figure 6 The combination of bit values ​​corresponding to threshold level 1 in the table is impossible. For example, the combination of bit values ​​corresponding to threshold level 1 does not have an XOR relationship and is therefore removed from the possible data items stored in memory cell 137. Therefore, the distribution curve 215 closest to curve 211 is for threshold level 2 and is more sufficiently separated from curve 211 by the margin of the voltage threshold. This reduces / eliminates the possibility of read errors when the threshold voltage of memory cell 137 is found to be in voltage region 219.

[0078] Similarly, Gray code and XOR relationships are used to eliminate combinations of bit values ​​corresponding to threshold levels (e.g., 3, 5, ..., 15) for other odd-numbered numbers. Therefore, distribution curves such as 211, 215, etc., can be sufficiently separated to improve data reliability.

[0079] Similarly, when the TP, XP, UP, and LP bits are configured with an XNOR relationship, combinations of bit values ​​corresponding to even threshold levels (e.g., 0, 2, ..., 14) are removed. Therefore, distribution curves 213, 217, etc., are also sufficiently separated to improve data reliability.

[0080] therefore, Figure 6 This demonstrates how configuring the TP, XP, UP, and LP bits to have an XOR or XNOR relationship improves the reliability of retrieving the TP, XP, UP, and LP bits by determining the level of the threshold voltage 209 of the memory cell 137.

[0081] Generally, the separation of distribution curves can be achieved using any Gray code for data bits with an XOR or XNOR relationship. Therefore, the improvement is not limited to using... Figure 6 The table describes specific Gray codes. Furthermore, the separation is not limited to QLC memory cells. For example, the technique can be applied to TLC memory cells or PLC memory cells.

[0082] The threshold voltage of a memory cell can vary due to several factors, such as charge loss, read interference, and cross-temperature effects (e.g., writes and reads at different operating temperatures). These variations and / or other factors can introduce errors when reading memory cells. Such errors can typically be detected and / or corrected during codeword decoding using ECC / LDPC techniques. However, when a codeword fails to be decoded, the XOR relation (or XNOR relation) can be used to... Figure 7 The codewords are recovered using the method described in the document.

[0083] Figure 7 Showing recovery from use Figure 4 and 5 The technology is a technique for retrieving data from memory cells using programming techniques.

[0084] exist Figure 7 In this process, after a codeword is read from memory cell group 131, one of codewords 153, 154, ..., 156 may encounter a failure 223 during the decoding operation 221 using ECC / LDPC technology. For example, codeword 154 may fail to be decoded. Since codewords 153, 154, ..., 156 correspond to the corresponding codewords in data groups 151, 157, ..., 159 with an XOR (or XNOR) relationship, codeword 154 can be replaced during recovery 225 by applying the corresponding operation 210 (e.g., XOR or XNOR) to the remaining codewords 153 to 156.

[0085] Figure 8A method for writing data into a memory cell according to some embodiments is shown. Figure 8 The method can be executed by processing logic, which may include hardware (e.g., processing device, circuit system, special-purpose logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, Figure 8 The method is at least in part by Figure 1 Controller 115 or Figure 2 The processing logic in the memory device 130 is executed. Although shown in a specific order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in each embodiment. Other process flows are also possible.

[0086] For example, it is possible Figure 1 The memory subsystem 110 described herein uses Figure 2 The integrated circuit memory device 130 is Figures 3 to 7 Data programming techniques execution Figure 8 The method.

[0087] At block 301, a first group (e.g., 157, ..., 159) of data bits (e.g., 163, ..., 173, 165, ..., 175) is received for storage in a group of memory cells (e.g., 131) of memory device 130. Memory device 130 may program a larger group of data bits than the first group (e.g., 157, ..., 159) into the group of memory cells (e.g., 131).

[0088] At box 303, a second group (e.g., 151) of data bits (e.g., 161, ..., 162, ..., 171) is generated from a first group (e.g., 157, ..., 159) to form a plurality of data groups (e.g., 151, 157, ..., 159). The plurality of data groups (e.g., 151, 157, ..., 159) includes the first group (e.g., 157, ..., 159) and the second group (e.g., 151) and has a predetermined relationship within the data groups (e.g., 151, 157, ..., 159).

[0089] For example, the predetermined relation may be an XOR relation such that any one of the data groups (e.g., 151, 157, ..., 159) is equal to the XOR of the remaining groups. Alternatively, the predetermined relation may be an XNOR relation such that any one of the data groups (e.g., 151, 157, ..., 159) is equal to the XNOR of the remaining groups.

[0090] Each corresponding data bit (e.g., 161) in the second group (e.g., 151) can be XORed based on a set of data bits (e.g., 163, ..., 165) having data bits from each of the first group (e.g., 157, ..., 159).

[0091] For example, the corresponding data bit (e.g., 161) is equal to the XOR of the data bits (e.g., 163, ..., 165) in the data bit set having each of the data bits in the first group (e.g., 157, ..., 159), and / or calculated from its XOR.

[0092] Alternatively, the corresponding data bit (e.g., 161) is equal to the inverse of the XOR of the data bits (e.g., 163, ..., 165) in the data bit set of each data bit from the first group (e.g., 157, ..., 159). For example, the corresponding data bit (e.g., 161) can be computed as the XNOR of the data bits (e.g., 163, ..., 165) in the data bit set of each data bit from the first group (e.g., 157, ..., 159).

[0093] For example, a second group (e.g., 151) can be generated from a first group (e.g., 157, ..., 159) by bitwise XOR or bitwise XNOR.

[0094] At block 305, memory device 130 is based on a predetermined mapping between bit value combinations and threshold levels (e.g., as illustrated, via...). Figure 6 The Gray code shown in the table determines the threshold level (e.g., 205) of a group of memory cells (e.g., 131). Each corresponding memory cell in the group of memory cells is determined to have a corresponding threshold level representing a combination of bit values ​​from each of the plurality of data groups; and the values ​​of any two consecutive threshold levels in a predetermined mapping differ by exactly one bit, as in Gray code (also known as reflected binary code).

[0095] At block 307, memory device 130 programs the threshold voltage (e.g., 209) of memory cells (e.g., 137) in a group of memory cells (e.g., 131) according to a threshold level (e.g., 205) determined by a predetermined mapping to store multiple data groups (e.g., 151, 157, ..., 159).

[0096] For example, by generating a second group (e.g., 151) from three first groups (e.g., 157, ..., 159), the threshold voltage (e.g., 209) of the memory cell (e.g., 137) in the four-level cell (QLC) group (e.g., 131) can be programmed in a four-level cell (QLC) mode, thereby storing four bits per memory cell with high reliability.

[0097] Generally, XOR or XNOR can be used to generate the Nth data group from the N-1 data group, and then the N data groups can be stored in the memory cell group in a manner of N bits per memory cell.

[0098] As an example, multiple data groups may include a third group (e.g., 157) and a fourth group (e.g., 151, 159, ...). When memory data 144 is retrieved from memory cell group 131 based on the threshold voltage of memory cells (e.g., 137) in the test memory cell group (e.g., 131), the third group (e.g., 157) may include a first codeword (154) in the third group (e.g., 157) that failed to be decoded in the ECC / LDPC decoder. In response, a second codeword (e.g., 153, ..., 156) in the fourth group (e.g., 151, 159, ...) can be used to calculate an alternative version of the first codeword (154).

[0099] Figure 9 This describes an instance machine of computer system 400, within which an instruction set is executable to cause the machine to perform any or more of the methods discussed herein. In some embodiments, computer system 400 may correspond to including, coupled to, or using a memory subsystem (e.g., Figure 1 The memory subsystem 110) or can be used to perform the operations of the programming manager 113 (e.g., execute instructions to perform operations corresponding to the reference). Figure 1-8 The host system (e.g., the described operation of the programming manager 113) Figure 1 (Host system 120). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment, operating at the capacity of a server or client machine in a client-server network environment.

[0100] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular telephone, network appliance, server, network router, switch, or bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions specifying actions to be taken by the machine. Furthermore, although a single machine is described, the term "machine" should also be understood to include any collection of machines that individually or collectively execute one or more sets of instructions to perform any one or more of the methods discussed herein.

[0101] The example computer system 400 includes a processing device 402, a main memory 404 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), static random access memory (SRAM), etc.), and a data storage system 418, which communicate with each other via a bus 430 (which may include multiple buses).

[0102] Processing device 402 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a combination of instruction sets. Processing device 402 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 402 is configured to execute instructions 426 for performing the operations and steps discussed herein. Computer system 400 may additionally include a network interface device 408 for communication on network 420.

[0103] Data storage system 418 may include machine-readable medium 424 (also referred to as computer-readable medium) storing one or more sets of instructions 426 or software embodying any or more of the methods or functions described herein. Instructions 426 may also reside wholly or at least partially in main memory 404 and / or processing device 402 during execution by computer system 400, which also constitute machine-readable storage media. Machine-readable medium 424, data storage system 418, and / or main memory 404 may correspond to... Figure 1 The memory subsystem 110.

[0104] In one embodiment, instruction 426 includes implementations corresponding to programming manager 113 (e.g., reference 113). Figure 1-8The description describes the functional instructions of the programming manager 113. Although the machine-readable medium 424 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions for machine execution and causing the machine to perform any one or more of the methods of this disclosure. The term "machine-readable storage medium" should therefore be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0105] Some parts of the previously described algorithms and symbolic representations of operations on data bits within computer memory have been presented. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. In this document, and generally in general, an algorithm is conceived as a self-consistent sequence of operations that produce a desired result. An operation is an operation that requires physical manipulation of a physical quantity. Typically (but not always), these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has been shown that it is sometimes convenient to refer to these signals as bits, values, elements, symbols, characters, items, numbers, etc., primarily for common use.

[0106] However, it should be remembered that all these and similar terms will be associated with appropriate physical quantities and are merely convenient notations for application to those quantities. This disclosure can refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities in the registers and memories of a computer system into other data similarly represented as physical quantities in the computer system's memory or registers or other such information storage systems.

[0107] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for the desired purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. This computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards or optical cards, or any type of media suitable for storing electronic instructions, each connected to a computer system bus.

[0108] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may prove convenient to construct more specialized devices to perform the methods described herein. The structures of various such systems will be presented as illustrated in the description below. Furthermore, this disclosure is described without reference to any particular programming language. It should be understood that the teachings of this disclosure as described herein can be implemented using various programming languages.

[0109] This disclosure may be provided as a computer program product or software, which may include machine-readable media on which instructions are stored for programming a computer system (or other electronic device) to perform processes according to this disclosure. Machine-readable media includes any means for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, machine-readable (e.g., computer-readable) media includes machine-readable (e.g., computer-readable) storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory components, etc.

[0110] In this specification, various functions and operations are described as being performed by or caused by computer instructions for the sake of simplicity. However, those skilled in the art will recognize that such expressions are intended to mean that the functions are produced by one or more controllers or processors (e.g., microprocessors) executing computer instructions. Alternatively or in combination, the functions and operations may be implemented using dedicated circuitry with or without software instructions, such as using application-specific integrated circuits (ASICs) or field-programmable gate arrays (FPGAs). Embodiments may be implemented using wired circuitry without software instructions or in combination with software instructions. Therefore, the technology is not limited to any particular combination of hardware circuitry and software, nor to any particular source of instructions executed by the data processing system.

[0111] In the foregoing description, embodiments of this disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made to this disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than restrictive sense.

Claims

1. A method for data programming, comprising: receiving a first group of data bits; generating a second group of data bits from the first group to form a plurality of data groups including the first group and the second group and having a predetermined relationship among the data groups, wherein each respective data bit in the second group is based on an exclusive-OR of a set of data bits having one from each of the first group; determining threshold levels for a group of memory cells based on a predetermined mapping between a bit value combination and a threshold level, wherein each respective memory cell in the group of memory cells is determined to have a respective threshold level representing a bit value combination of one bit from each of the plurality of data groups, and wherein in the predetermined mapping the values of data bits represented by any two consecutive threshold levels differ by one bit; and programming threshold voltages of memory cells in the group of memory cells according to the threshold levels to store the plurality of data groups.

2. The method of claim 1, wherein the respective data bit is equal to an exclusive-OR of data bits in the set of data bits having one from each of the first group.

3. The method of claim 1, wherein the respective data bit is equal to an inverse of an exclusive-OR of data bits in the set of data bits having one from each of the first group.

4. The method of claim 1, wherein the second group is generated from an XOR of the first group.

5. The method of claim 1, wherein the second group is generated from an XNOR of the first group.

6. The method of claim 1, wherein the threshold voltages of memory cells in the group of memory cells are programmed in a four-level cell mode to store four bits per memory cell; and a group count of the first group is three.

7. The method of claim 1, wherein the plurality of data groups includes a third group and a fourth group; wherein the method additionally comprises: reading the group of memory cells based on threshold voltages of memory cells in the group of memory cells to retrieve memory data corresponding to the plurality of data groups; determining that a first codeword in the memory data corresponding to the third group fails to be decoded; and computing a version of the first codeword from a second codeword in the memory data corresponding to the fourth group.

8. A memory device, comprising: an integrated circuit package enclosing the memory device; and a plurality of groups of memory cells formed on at least one integrated circuit die; wherein in response to a command identifying a group of memory cells within the plurality of groups of memory cells, the memory device is configured to: receive a first group of data bits; generate a second group of data bits from the first group to form a plurality of data groups including the first group and the second group, wherein each respective data bit in the second group is generated based on an exclusive-OR of a set of data bits having one from each of the first group; determining threshold levels of memory cells in the group of memory cells based on a predetermined mapping between bit value combinations and threshold levels, wherein each respective memory cell in the group of memory cells is determined to have a respective threshold level representing a bit value combination of one bit from each of the plurality of groups of data, and wherein in the predetermined mapping, values of data bits represented by any two consecutive threshold levels differ by and only by one bit; and programming threshold voltages of memory cells in the group of memory cells according to the threshold levels to store the plurality of groups of data.

9. The memory device of claim 8, wherein the memory device is configured to apply an XOR operation on the set of data bits to generate the respective data bits.

10. The memory device of claim 8, wherein the memory device is configured to apply an XNOR operation on the set of data bits to generate the respective data bits.

11. The memory device of claim 8, wherein the memory device is configured to generate the plurality of groups of data having an XOR relationship.

12. The memory device of claim 8, wherein the memory device is configured to generate the plurality of groups of data having an XNOR relationship.

13. A memory subsystem comprising: a processing device; and at least one memory device having a group of memory cells formed on an integrated circuit die, the memory device configured to program threshold levels of the group of memory cells in a predetermined number of bits per memory cell according to a Gray code, whereby bit values stored in memory cells are represented by threshold levels of the memory cells; wherein the processing device is configured to generate a second group of data bits from a first group of data bits to form a plurality of groups of data including the first group of data bits and the second group of data bits, the first group of data bits having a number of bits less than the predetermined number of bits per memory cell of the group of memory cells, the plurality of groups of data having the predetermined number of bits per memory cell of the group of memory cells, wherein each respective data bit in the second group is generated based on an exclusive OR of a set of data bits having data bits from each of the first group; and wherein the processing device is configured to provide the plurality of groups of data to the memory device to store one bit from each of the plurality of groups of data in each memory cell in the group of memory cells.

14. The memory subsystem of claim 13, wherein bit values represented by two consecutive threshold levels differ by and only by one bit.

15. The memory subsystem of claim 13, wherein the processing device is configured to calculate the second group of data bits as an XOR of the first group of data bits.

16. The memory subsystem of claim 13, wherein the processing device is configured to calculate the second group of data bits as an XNOR of the first group of data bits.

17. The memory sub-system of claim 13, wherein the group of data provided to the memory device for storage is a plurality of first groups of data; the processing device is configured to receive a plurality of second groups of data from the memory device to read the group of memory cells; and in response to a first codeword in the second group of data failing to be decoded based on an error correcting code, the processing device is further configured to compute a replacement for the first codeword from second codewords, each of the second codewords being from a different group of data in the second group of data.

18. The memory sub-system of claim 17, wherein the error correcting code comprises a low density parity check code; and the replacement for the first codeword is computed from an XOR or XNOR of the second codewords.

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