Oscillation detection and mitigation in bit-flipping decoder

Abstract

The present disclosure relates to apparatuses, systems, and methods for detecting and mitigating oscillations in a bit flip decoder associated with non-volatile memory. An example method includes receiving a noisy codeword based on a transmitted codeword, the transmitted codeword generated according to a low-density parity-check code; performing a first plurality of decoding iterations on the noisy codeword, the first plurality of decoding iterations including performing a message passing algorithm in a first order; based on completion of the first plurality of decoding iterations, computing a plurality of syndrome values and a plurality of bit flip counts corresponding to the first plurality of decoding iterations; determining that the plurality of syndrome values and the plurality of bit flip counts are periodic, the period being less than a predetermined threshold; and performing a subsequent decoding iteration on the noisy codeword, the subsequent decoding iteration including performing the message passing algorithm in a second order different from the first order.

Description

TECHNICAL FIELD

[0001] The present patent document generally relates to non-volatile memory devices, and more specifically, to error correction in non-volatile memory devices. BACKGROUND

[0002] Data integrity is an important feature of any data storage device and data transmission. Robust error correction codes (ECC) are recommended for use with various types of data storage devices, including NAND flash memory devices.

[0003] Solid state drives (SSDs) use multi-level NAND flash devices for permanent storage. However, multi-level NAND flash devices can be inherently unreliable, and typically require the use of ECC to substantially improve data reliability at the cost of additional storage space for ECC parity bits. More efficient decoding methods are needed that can provide data protection with improved decoding performance. SUMMARY

[0004] Embodiments of the disclosed technology relate to improving decoding performance of a bit flip decoder associated with a non-volatile memory by detecting oscillations and mitigating the oscillations. Detecting and mitigating oscillations in the bit flip decoder reduces the failure rate of the bit flip decoder, thereby improving the throughput and read QoS (quality of service) of the non-volatile memory.

[0005] In an example aspect, a method for improving decoding performance of a bit flip decoder is described. The method includes receiving a noisy codeword based on a transmitted codeword, the transmitted codeword being generated according to a low-density parity-check (LDPC) code; performing a first plurality of decoding iterations on the noisy codeword, at least one decoding iteration of the first plurality of decoding iterations including performing a message passing algorithm in a first order; computing a plurality of syndrome values and a plurality of bit flip counts corresponding to the first plurality of decoding iterations based on completion of the first plurality of decoding iterations; determining that the plurality of syndrome values and the plurality of bit flip counts are periodic with a period less than a predetermined threshold (T); and performing a subsequent decoding iteration on the noisy codeword, the subsequent decoding iteration including performing the message passing algorithm in a second order different from the first order.

[0006] In yet another example aspect, the above-described methods can be implemented by a processor coupled to a memory.

[0007] In yet another example aspect, the methods can be embodied in the form of instructions stored on a computer readable program medium, which instructions are runtable by a processor.

[0008] The subject matter described in this patent document can be implemented in specific ways that provide one or more of the following features. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 An example of a memory system is shown.

[0010] Figure 2 is a diagram of an example non-volatile memory device.

[0011] Figure 3 is an example graph showing a cell voltage level distribution (V th ) of a non-volatile memory device.

[0012] Figure 4 is another example graph showing a cell voltage level distribution (V th ) of a non-volatile memory device.

[0013] Figure 5 is an example graph showing a cell voltage level distribution (V th ) of a non-volatile memory device before and after program disturb.

[0014] Figure 6 is an example graph showing a cell voltage level distribution (V th ) of a non-volatile memory device as a function of a reference voltage.

[0015] Figure 7 A flowchart for oscillation detection and mitigation is shown.

[0016] Figure 8 A flowchart of an example method for improving decoding performance of a bit flip decoder associated with a non-volatile memory is shown. DETAILED DESCRIPTION

[0017] Solid state drives (SSDs) are a new generation of storage devices used in computers. SSDs replace traditional mechanical hard drives by using flash-based memory that is significantly faster. SSDs significantly speed up computers due to their low read access time and fast throughput. SSDs can be configured to use irregular quasi-cyclic low-density parity check (QC-LDPC) codes to correct any bit errors in pages read from NAND media. QC-LDPC codes are used to ensure data integrity in memory systems that use new generation NAND flash memory. Iterative decoders for LDPC codes, and in particular decoders for irregular QC-LDPC codes, generally have wide complexity. Two main types of decoders are low complexity bit flip (BF) decoders that have low error correction capability and high complexity min-sum (MS) decoders that have high error correction capability.

[0018] For typical SSD applications, most page reads (over 99%) are performed by bit flipping decoders. Thus, it is critical to design a hardware for a fast and efficient bit flipping (BF) decoder that exhibits improved convergence characteristics, especially in mobile and client SSD applications, as they have strict power limitations and throughput requirements.

[0019] This document first outlines an example of a non-volatile memory system that can implement a bit flipping decoder to decode an irregular QC-LDPC code, and then describes methods, systems, and apparatuses to improve the decoding performance of a bit flipping decoder by, for example, computing the number of bit flips on a previous number of cyclic columns in an irregular QC-LDPC code and then updating a bit flipping threshold.

[0020] Figures 1-6 A non-volatile memory system (e.g., a flash-based memory or a NAND flash) that can implement embodiments of the disclosed technology is outlined.

[0021] Figure 1 is a block diagram of an example of a memory system 100 implemented based on some embodiments of the disclosed technology. The memory system 100 includes a memory module 110 that can be used to store information for use by other electronic devices or systems. The memory system 100 can be incorporated into other electronic devices and systems (e.g., located on a circuit board). Alternatively, the memory system 100 can be implemented as an external storage device such as a USB flash drive and a solid state drive (SSD).

[0022] The memory module 110 included in the memory system 100 can include memory regions (e.g., memory arrays) 102, 104, 106, and 108. Each of the memory regions 102, 104, 106, and 108 can be included in a single memory die or multiple memory dies. The memory die can be included in an integrated circuit (IC) chip.

[0023] Each of the memory regions 102, 104, 106, and 108 includes a plurality of memory cells. A read operation, a program operation, or an erase operation can be performed based on a memory unit. Thus, each memory unit can include a predetermined number of memory cells. The memory cells in a memory region 102, 104, 106, or 108 can be included in a single memory die or multiple memory dies.

[0024] The memory cells in each of the memory regions 102, 104, 106, and 108 can be arranged in rows and columns in memory elements. Each of the memory elements can be a physical element. For example, a group of multiple memory cells can form a memory element. Each of the memory elements can also be a logical element. For example, a memory element can be a block or a page, which can be identified by a unique address such as a block address or a page address, respectively. For another example, where the memory regions 102, 104, 106, and 108 can include computer memory including memory banks as logical elements for data storage, the memory elements can be banks that can be identified by a bank address. During a read operation or a write operation, a unique address associated with a particular memory element can be used to access the particular memory element. Based on the unique address, information can be written to or retrieved from one or more memory cells in the particular memory element.

[0025] The memory cells in the memory regions 102, 104, 106, and 108 can include non-volatile memory cells. Examples of non-volatile memory cells include flash memory cells, phase change random access memory (PRAM) cells, magnetoresistive random access memory (MRAM) cells, or other types of non-volatile memory cells. In example implementations where the memory cells are configured as NAND flash memory cells, read operations or write operations can be performed on a page basis. However, erase operations in NAND flash memory are performed on a block basis.

[0026] Each of the non-volatile memory cells can be configured as a single-level cell (SLC) or a multi-level memory cell. A single-level cell can store one bit of information per cell. A multi-level memory cell can store more than one bit of information per cell. For example, each of the memory cells in the memory regions 102, 104, 106, and 108 can be configured as a multi-level cell (MLC) that stores two bits of information per cell, a triple-level cell (TLC) that stores three bits of information per cell, or a quad-level cell (QLC) that stores four bits of information per cell. In another example, each of the memory cells in the memory regions 102, 104, 106, and 108 can be configured to store at least one bit of information (e.g., one bit of information or more than one bit of information), and each of the memory cells in the memory regions 102, 104, 106, and 108 can be configured to store more than one bit of information.

[0027] As Figure 1As shown, the memory system 100 includes a controller module 120. The controller module 120 includes a memory interface 121 for communicating with the memory module 110, a host interface 126 for communicating with a host (not shown), a processor 124 for running firmware layer code, and a buffer / cache 123 and system memory 122 for temporarily or permanently storing executable firmware / instructions and associated information, respectively. In some embodiments, the controller unit 120 can include an error correction code (ECC) engine 125 to perform error correction operations on information stored in the memory module 110. The error correction code engine 125 can be configured to detect / correct single-bit errors or multiple-bit errors. In another embodiment, the error correction code engine 125 can be located in the memory module 110.

[0028] The host can be a device or system that includes one or more processors that operate to retrieve data from or store or write data to the memory system 100. In some embodiments, examples of the host can include a personal computer (PC), a portable digital apparatus, a digital camera, a digital multimedia player, a television, and a wireless communication apparatus.

[0029] In some embodiments, the controller module 120 can also include a host interface 126 to communicate with the host. The host interface 126 can include components that comply with at least one of the host interface specifications including, but not limited to, serial advanced technology attachment (SATA), serial attached small computer system interface (SAS) specification, peripheral component interconnect express (PCIe).

[0030] Figure 2 An example of a memory cell array implemented based on some embodiments of the disclosed technology is shown.

[0031] In some embodiments, the memory cell array can include a NAND flash memory array divided into a number of blocks, and each block includes a number of pages. Each block includes a plurality of strings of memory cells, and each string of memory cells includes a plurality of memory cells.

[0032] In some embodiments where the memory cell array is a NAND flash memory array, read operations and write (program) operations are performed on a page basis, and erase operations are performed on a block basis. Before performing program operations on any pages included in a block, all memory cells within the same block must be simultaneously erased. In embodiments, the NAND flash memory can use an even / odd bit line structure. In another embodiment, the NAND flash memory can use an all-bit-line structure. In the even / odd bit line structure, even bit lines and odd bit lines are interleaved along each word line and are accessed alternately so that each pair of even and odd bit lines can share peripheral circuits such as page buffers. In the all-bit-line structure, all bit lines are accessed simultaneously.

[0033] Figure 3 An example of threshold voltage distribution curves in a multi-layer cell device is shown, where the number of cells for each program / erase state is plotted as a function of threshold voltage. As shown, the threshold voltage distribution curves include an erase state (denoted as "ER" and corresponding to "11") with the lowest threshold voltage, and three program states (denoted as "Pl", "P2", and "P3", corresponding to "01", "00", and "10", respectively) with read voltages located between these states (indicated by the dashed lines). In some embodiments, each of the threshold voltage distributions for the program / erase states has a finite width due to differences in material characteristics across the memory array. Figure 3

[0034] Although Figure 3 The multi-layer cell device is shown by way of example, but each of the memory cells can be configured to store any number of bits per cell. In some embodiments, each of the memory cells can be configured as single-layer cells (SLC) storing one bit of information per cell, or as three-layer cells (TLC) storing three bits of information per cell, or as quad-layer cells (QLC) storing four bits of information per cell.

[0035] In writing more than one bit of data to a memory cell, the threshold voltage level of the memory cell needs to be finely set due to the reduced distance between adjacent distributions. This is achieved by using incremental step pulse programming (ISPP), i.e., a programming and verification method that uses a staircase of programming voltages applied to a word line to repeatedly program memory cells on the same word line. Each program state is associated with a verify voltage used in a verify operation, and a target position of each threshold voltage distribution window is set.

[0036] ​Distortion or overlap of threshold voltage distributions can cause read errors. Due to, for example, program and erase (P / E) cycles, inter-cell interference, and data retention errors, ideal memory cell threshold voltage distributions can be significantly distorted or overlapped (this will be discussed below), and in most cases, these read errors can be managed by using error correction codes (ECC).

[0037] Figure 4 An example of an ideal threshold voltage distribution curve 410 and an example of a distorted threshold voltage distribution curve 420 are shown. The vertical axis represents the number of memory cells with a particular threshold voltage represented on the horizontal axis.

[0038] For an n-bit multi-level cell NAND flash memory, the threshold voltage of each cell can be programmed to 2npossible values. In an ideal multi-level cell NAND flash memory, each value corresponds to a non-overlapping threshold voltage window. n

[0039] Flash memory P / E cycles cause damage to the tunnel oxide of the floating gate of the charge trapping layer of the cell transistor, which results in threshold voltage shifts, thereby gradually reducing the memory device noise margin. As the P / E cycles increase, the margin between adjacent distributions of different program states decreases, and eventually the distributions start to overlap. Data bits stored in memory cells whose threshold voltages are programmed in the overlapping range of adjacent distributions can be misjudged as a value different from the original target value.

[0040] Figure 5 An example of inter-cell interference in NAND flash memory is shown. Inter-cell interference can also cause the threshold voltage of a flash memory cell to be distorted. A threshold voltage shift of one memory cell transistor can affect the threshold voltage of its neighboring memory cell transistors through parasitic capacitive coupling effects between the interfering cell and the victim cell. The amount of inter-cell interference can be affected by the NAND flash memory bit line structure. In an even / odd bit line structure, memory cells on one word line are connected to even bit lines and odd bit lines alternately, and in the same word line, even cells are programmed before odd cells. Therefore, even cells and odd cells are subject to different amounts of inter-cell interference. Cells in a full bit line structure are subject to less inter-cell interference than even cells in an even / odd bit line structure, and a full bit line structure can effectively support high speed current sensing to improve memory read and verify speed.

[0041] Figure 5 The dashed line in FIG. 4A represents the nominal distribution of the P / E states of the considered cell (before program interference), and the “adjacent state value” represents the value to which the adjacent state has been programmed. As Figure 5 ​As shown, if the neighboring state is programmed as PI, the threshold voltage distribution of the cell under consideration is shifted by a certain amount. However, if the neighboring state is programmed as P2, which has a higher threshold voltage than PI, this results in a larger shift compared to the case where the neighboring state is PI. Similarly, when the neighboring state is programmed as P3, the shift of the threshold voltage distribution is the largest.

[0042] Figure 6 An example of retention errors in NAND flash memory is shown by comparing the normal threshold voltage distribution with the shifted threshold voltage distribution. Data stored in NAND flash memory tends to deteriorate over time, which is referred to as data retention errors. Retention errors result from loss of charge stored in the floating gate or charge trapping layer of the cell transistor. Memory cells with more program-erase cycles are more prone to retention errors due to wear of the floating gate or charge trapping layer. In the example of Figure 1, the top row of voltage distributions (before deterioration) is compared with the bottom row of distributions (contaminated by retention errors). Figure 6

[0043] Bit flipping decoders are generally used as the first step in decoding LDPC codewords in non-volatile memory devices (e.g., as described in Figures 1-6 However, for certain error patterns, bit flipping decoders can get stuck (or stall) during decoding, for example, due to reaching a certain error pattern and then repeatedly flipping the same set or series of bits. In these cases, the syndrome and the number of flipped bits per iteration start to oscillate.

[0044] According to some embodiments of the disclosed technology, methods, systems, and apparatuses improve the decoding performance of bit flipping decoder implementations for LDPC codes by detecting and mitigating oscillations that can occur during the decoding process. Embodiments described herein are also applicable to quasi-cyclic LDPC (QC-LDPC) codes.

[0045] Quasi-cyclic codes are defined by the property that for an integer n0, a cyclic shift of the codeword by n0 positions is still the codeword. For a (n = mn0, k = mk0) quasi-cyclic linear code of a system, the corresponding parity check matrix H is represented as:

[0046]

[0047] In this context, n denotes the length of the code, k denotes the rank of the code (corresponding to the number of codewords in its basis and the number of rows in its generator matrix), m denotes the size of the circulant matrix, k0is an integer based on the values of n, m, and n0, I n-k denotes an (n-k) x (n-k) identity matrix, and each C'​i,j is an mxm circulant matrix (of size circulantSize or circSize) of the form:

[0048]

[0049] In contrast to quasi-cyclic codes with all columns having equal column weight (e.g., each column having the same number of 1s), at least two columns of an irregular quasi-cyclic code have different numbers of 1s, i.e., at least two columns have different weights.

[0050] Both regular and irregular LDPC codes can be represented using a Tanner graph, which includes a set of nodes (or vertices) and a set of edges connecting the nodes. A Tanner graph corresponding to an M x N parity check matrix includes M variable nodes (or bit nodes) and N check nodes (or syndrome nodes), and provides a graphical representation of the parity check matrix it corresponds to. The performance and decoding of an LDPC code (regular or irregular) is based on the row weights and column weights of the parity check matrix, or equivalently, on the cycles in the Tanner graphical representation.

[0051] In a bit-flipping algorithm, at each iteration and for each variable node, the number of unsatisfied check nodes is compared to a threshold, and if the number of unsatisfied check nodes is greater than the threshold, the hard decision estimate for the variable node is flipped. In existing implementations, bit-flipping decoders typically use a predetermined scheduling algorithm that fixes the order of processing variable nodes in each iteration. However, some error patterns can be sensitive to the fixed order of processing, because if a certain error pattern causes oscillation, using the same order of processing variable nodes in each iteration cannot avoid the oscillation and results in unsuccessful decoding operations.

[0052] When this error occurs, embodiments of the disclosed technology can detect the oscillation using one or more decoder parameters (e.g., the number of flipped bits, the value of the syndrome, etc.). In an example, due to the oscillation of the variable nodes, the number of flipped bits and the value of the syndrome repeat with a certain period. In this case, the bit-flipping decoder can be configured to use a randomized order to process the variable nodes, thereby enabling the decoder to avoid the oscillation to improve decoding performance.

[0053] In some embodiments, because determining the period (T) of the decoder parameters can require additional hardware, the randomized order can only be implemented if the period of the oscillation is less than a predetermined threshold. In an example, T < 10.

[0054] For most error patterns, oscillations in the bit flip detector are caused by the processing order of the variable nodes. Thus, changing the flipping order of the variable nodes can help the decoder avoid oscillations. However, in conventional non-volatile memories (e.g., the example embodiments described in Figures 1-6 U.S. Patent No. 8, 1 1 1, 1 1 1 ) changing the processing order of the variable nodes by changing the hardware design is not practically feasible due to the increased complexity of the state machine running the bit flip decoder.

[0055] An effective technique to change the flipping order of the variable nodes in the bit flip decoder without changing the hardware design is to randomly flip bits that have already been configured to flip by the bit flip decoder. That is, the decoder accepts the decision of the flipped bits with a certain probability, thereby rejecting some of the bit flip decisions in which. However, this type of random implementation generally slows down the bit flip decoder.

[0056] Embodiments of the disclosed technology use random decisions to accept or reject bit flip decisions only when oscillations are detected, thereby reducing any loss in throughput. In examples, when a variable node that flipped during an oscillation is skipped due to a random decision, the decoding trajectory starts to deviate from the previous iteration. This advantageously enables the decoder to avoid oscillations and converge to the correct codeword in a few more iterations. In some embodiments, the random decisions can be generated in a pseudo-random manner by a linear feedback shift register (LFSR) that requires minimal hardware resources.

[0057] Example algorithm for oscillation detection and mitigation

[0058] For an iterative bit flip decoder, let i (0≤i≤i max ) denote the iteration number, denote the decision of variable node j at the i-th decoding iteration, be the decision vector at the i-th decoding iteration, and the check node at the i-th iteration be where H is the parity check matrix of the LDPC code.

[0059] It is further assumed that is the received word used as the initial decision vector, and s (-1) = yH T is the initial check node vector. It is also assumed that the following symbols:

[0060] -CS_arr[i] is the check sum at the i-th decoding iteration;

[0061] -flip_num_arr[i] is the number of flipped bits at the i-th decoding iteration;

[0062] -T is a periodic threshold;

[0063] - p is the probability of the decoder accepting a flip decision; and

[0064] - is a threshold for the flip energy of the jth cyclic column in the ith decoding iteration. An example algorithm for oscillation detection and mitigation includes:

[0065] Step 0: Set i = 0, curr flip bits = 0, compute s (-1) and go to Step 1;

[0066] Step 1: i = i + 1, if maximum iterations are reached, stop decoding. Otherwise, go to Step 2;

[0067] Step 2: if |s| = 0, stop decoding. Otherwise, go to Step 3;

[0068] Step 3: (oscillation detection)

[0069] - store CS arr[i - 1] = |s|, flip num arr[i - 1] = cur flip bits.

[0070] - check if CS arr and flip num arr are both periodic (period < T)

[0071] - if they are both periodic, generate a pseudo-random array P of size n circ bits such that the probability of P[j] = 1 is p.

[0072] - otherwise, set P to 1 for all cyclic columns 1 < j < n circ .

[0073] Step 4:

[0074] - update the flip energy E[v] of all VNs v in the jth cyclic column.

[0075] - if P[j] is equal to 1

[0076] - flip the hard decision estimate of the VN, flip energy

[0077] - otherwise

[0078] - skip the jth cyclic column (oscillation mitigation)

[0079] - add the number of flipped bits to cur flip bits.

[0080] - compute and update s.

[0081] Step 5: go to Step 1.

[0082] Figure 7 A flowchart of a method for oscillation detection and mitigation is shown. As shown therein, the method 700 starts at operation 710, where i is set to 0, curr_flip_bits is set to 0, and the syndrome S is computed (-1) = yH T which corresponds to step 0 described above.

[0083] In operation 715, i is incremented and the method determines whether it should continue decoding by checking whether the maximum number of iterations has been exceeded or the syndrome is zero in operation 720, which corresponds to steps 1 and 2 described above.

[0084] If the maximum number of iterations has been exceeded or the syndrome is zero, the bit-flipping decoder stops in operation 790 (‘No’ branch in 720). Otherwise, the decoding continues through operation 730 (‘Yes’ branch in 720).

[0085] In operation 730, the syndrome in the previous iteration (denoted as CS_arr[i] for the i-th decoding iteration) and the number of flips (denoted as flip_num_arr[i] for the i-th decoding iteration, and is equivalent to the trace of bit-flips) are updated.

[0086] In operation 740, the method 700 checks whether the trace is periodic. In an example, the periodicity of the trace must be below a predetermined threshold. If the trace is periodic (‘Yes’ branch in 740), in operation 742, P[j] is set to a probability generated by a random number generator (RNG) for all j. On the other hand, if the trace is not periodic (‘No’ branch in 740), in operation 744, P[j] is set to 1 for all j. The method continues with operation 746, where the number of currently flipped bits (cur_flip_bits) and the cyclic column index (j) are set to 0.

[0087] In operation 750, the cyclic column index (j) is incremented, and in operation 760, the method determines whether all cyclic columns have been processed, i.e., checks whether j is less than or equal to n circ (the number of cyclic columns). If all cyclic columns have been processed (‘No’ branch in 760), the algorithm starts the next iteration (by incrementing the cyclic column index i in operation 715), but if at least one cyclic column has not been processed (‘Yes’ branch in 760), the method continues to operation 770.

[0088] In operation 770, the method checks whether the randomly assigned probability for the jth cycle column is equal to 0. If so (the "Yes" branch in 770), the random decision process will not flip the bit associated with the jth variable node, and the method loops back to operation 750 to process the next cycle column. However, if the probability P[j] is not zero (the "No" branch in 770), then (i) the flip energy E[v] is computed for all variable nodes v in the jth cycle (operation 780), (ii) the bit is flipped for all v, where P[j] > 0 (operation 782), and (iii) the number of current flip bits (cur flip bits) and the syndrome vector are updated. The method 700 then loops back to operation 750 to process the next cycle column.

[0089] In the method 700, operations 730-760 correspond to the remaining operations shown in step 3, Figure 7 above, and operations 770-782 correspond to steps 4 and 5 above.

[0090] In some embodiments, the example algorithm for oscillation detection and mitigation (and as described above) is applicable to both LDPC codes and QC-LDPC codes. Figure 7

[0091] In some embodiments, the example algorithm for oscillation detection and mitigation (and as described above) is applicable to bit flip decoders that use more than 1 bit to store the estimate for each variable node. Figure 7

[0092] In some embodiments, an array of bits is used to store the cycle columns that are flipped in an iteration after an oscillation is detected. At the start of a new period, the P values for the other cycle columns remain at 1, and only the variable nodes that are flipped during the entire period use a pseudo-random bit for the corresponding element in the P array for that variable node.

[0093] Figure 8 A flowchart illustrating a method of improving decoding performance of a bit flip decoder associated with a non-volatile memory based on detecting and mitigating oscillations is shown. The method 800 includes, at operation 810, receiving a noisy codeword based on a transmitted codeword, the transmitted codeword being generated according to a low-density parity-check (LDPC) code.

[0094] The method 800 includes, at operation 820, performing a first plurality of decoding iterations on the noisy codeword, at least one decoding iteration of the first plurality of decoding iterations including performing a message passing algorithm in a first order.

[0095] The method 800 includes, at operation 830, based on completion of the first plurality of decoding iterations, computing a plurality of syndrome values and a plurality of bit flip counts corresponding to the first plurality of decoding iterations. ​​

[0096] The method 800 includes determining, at operation 840, that the plurality of syndrome values and the plurality of bit flip counts are periodic with a period less than a predetermined threshold (T).

[0097] The method 800 includes, at operation 850, performing a subsequent decoding iteration on the noisy codeword, the subsequent decoding iteration including performing the message passing algorithm in a second order different from the first order.

[0098] In some embodiments, each decoding iteration of the first plurality of decoding iterations includes passing one or more messages between a plurality of variable nodes and a plurality of check nodes of a parity check matrix representing the LDPC code.

[0099] In some embodiments, the bit-flipping decoder uses two or more bits to store an estimate for each of the plurality of variable nodes.

[0100] In some embodiments, the first order includes a first decoding order of the plurality of variable nodes in the decoding iteration, and the second order includes a second decoding order of the plurality of variable nodes in the decoding iteration.

[0101] In some embodiments, the subsequent decoding iteration includes performing the message passing algorithm N times for each of N circulant columns, the N circulant columns comprising the parity check matrix of the LDPC code, N being an integer.

[0102] In some embodiments, the method 800 further includes an operation of determining the second order based on generating a bit pseudo-random array of length N, where each bit in the bit pseudo-random array has a probability p of having a value of 1, and where the second order includes flipping bits when a corresponding bit in the bit pseudo-random array has a value of 1.

[0103] In some embodiments, p = 0.8 and T = 10.

[0104] In some embodiments, the method 800 further includes an operation of calculating a syndrome, and refraining from performing additional decoding iterations of the bit-flipping decoder after the subsequent decoding iteration when a maximum number of iterations has been performed or the syndrome is equal to zero.

[0105] In some embodiments, the LDPC code is a non-regular QC-LDPC code.

[0106] Implementations of the subject matter and the functional operations described in this patent document can be implemented in various systems, digital electronic circuitry, or in computer software, firmware, or hardware, including the structures disclosed in this specification and their equivalent structures, or in combinations of one or more of them. The subject matter described in this specification can be implemented as one or more computer program products, i.e., one or more modules of computer program instructions encoded on a tangible and non-transitory computer readable medium for execution by, or to control the operation of, data processing apparatus. The computer readable medium can be a machine-readable storage device, a machine-readable storage substrate, a memory device, a composition of matter effecting a machine-readable propagated signal, or a combination of one or more of them. The term“data processing apparatus” or“data processing equipment” encompasses all apparatus, devices, and machines for processing data, including by way of example a programmable processor, a computer, or multiple processors or computers. The apparatus can include, in addition to hardware, code that creates an execution environment for the computer program in question, e.g., code that constitutes processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of them.

[0107] A computer program (also known as a program, software, software application, script, or code) can be written in any form of programming language, including compiled or interpreted languages, and it can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. A computer program does not necessarily correspond to a file in a file system. A program can be stored in a portion of a file that holds other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files that store one or more modules, sub programs, or portions of code). A computer program can be deployed to operate on one computer or on multiple computers that are located at one site or distributed across multiple sites and are interconnected by a communication network.

[0108] The processes and logic flows described in this specification can be performed by one or more programmable processors executing one or more computer programs to perform functions by operating on input data and generating output. The processes and logic flows can also be performed by, and apparatus can also be implemented as, special purpose logic circuitry, e.g., an FPGA (field programmable gate array) or an ASIC (application specific integrated circuit).

[0109] Processors suitable for the execution of a computer program include, by way of example, both general and special purpose microprocessors, and any one or more processors of any kind of digital computer. Generally, a processor will receive instructions and data from a read-only memory or a random access memory or both. The essential elements of a computer are a processor for executing instructions and one or more memory devices for storing instructions and data. Generally, a computer will also include, or be operatively coupled to receive data from or transfer data to, or both, one or more mass storage devices for storing data, e.g., magnetic, magneto-optical disks, or optical disks. However, a computer need not have such devices. Computer readable media suitable for storing computer program instructions and data include all forms of non-volatile memory, media and memory devices, including by way of example semiconductor memory devices, e.g., EPROM, EEPROM, and flash memory devices. The processor and the memory can be supplemented by, or incorporated in, special purpose logic circuitry.

[0110] Although the present patent document includes many details, these should not be construed as limiting the scope of any invention or of the scope of patentable subject matter in which an invention can be claimed. Certain features described in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment can also be implemented separately or in any suitable subcombination. Moreover, although features can be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination and the claimed combination can be directed to a subcombination or variation of a subcombination.

[0111] Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring such order, nor that all illustrated operations be performed, to achieve desirable results. In addition, the separation of various system components in the embodiments described in this patent document should not be understood as requiring such separation in all embodiments.

[0112] Only a few implementations and examples are described and other implementations, enhancements and variations can be made based on what is described and illustrated in this patent document.

Claims

1. A method of improving decoding performance of a bit flipping decoder associated with a non-volatile memory, comprising: receiving a noisy codeword based on a transmitted codeword, the transmitted codeword generated according to a low density parity check (LDPC) code; performing a first plurality of decoding iterations on the noisy codeword, at least one decoding iteration of the first plurality of decoding iterations including performing a message passing algorithm in a first order; based on completion of the first plurality of decoding iterations, computing a plurality of syndrome values and a plurality of bit flipping counts corresponding to the first plurality of decoding iterations; determining that the plurality of syndrome values and the plurality of bit flipping counts are periodic with a period less than a predetermined threshold T; and performing a subsequent decoding iteration on the noisy codeword, the subsequent decoding iteration including performing the message passing algorithm in a second order different from the first order, wherein the subsequent decoding iteration includes performing the message passing algorithm N times for each of N circulant columns, the N circulant columns comprising a parity check matrix of the LDPC code, and N is an integer.

2. The method of claim 1, wherein, each decoding iteration of the first plurality of decoding iterations includes passing one or more messages between a plurality of variable nodes and a plurality of check nodes of a parity check matrix representing the LDPC code.

3. The method of claim 2, wherein, the bit flipping decoder uses two or more bits to store an estimate for each of the plurality of variable nodes.

4. The method of claim 2, wherein, the first order includes a first decoding order of the plurality of variable nodes in a decoding iteration, and wherein the second order includes a second decoding order of the plurality of variable nodes in a decoding iteration.

5. The method of claim 1, further comprising: determining the second order based on generating a bit pseudo-random array of length N, wherein each bit in the bit pseudo-random array has a probability p of having a value of 1, and wherein the second order includes flipping bits when a respective bit in the bit pseudo-random array has a value of 1.

6. The method of claim 5, wherein, p = 0.8 and T = 10.

7. The method of claim 1, further comprising: computing a syndrome; and avoiding performing additional decoding iterations of the bit flipping decoder after the subsequent decoding iteration upon determining that a maximum number of iterations has been performed or that the syndrome is equal to zero.

8. The method of claim 1, wherein, the LDPC code is an irregular quasi-cyclic low density parity check (QC-LDPC) code.

9. A system of improving decoding performance of a bit flipping decoder associated with a non-volatile memory, comprising: a processor and a memory, the memory including instructions stored thereon, wherein the instructions, when executed by the processor, cause the processor to: receive a noisy codeword based on a transmitted codeword, the transmitted codeword generated according to a non-regular quasi-cyclic low density parity check (QC-LDPC) code; perform a first plurality of decoding iterations on the noisy codeword, at least one decoding iteration of the first plurality of decoding iterations including performing a message passing algorithm in a first order; based on completion of the first plurality of decoding iterations, compute a plurality of syndrome values and a plurality of bit flipping counts corresponding to the first plurality of decoding iterations; determining that the plurality of syndrome values and the plurality of bit flip counts are periodic with a period less than a predetermined threshold T; and performing a subsequent decoding iteration on the noisy codeword, the subsequent decoding iteration comprising executing the message passing algorithm in a second order different from the first order, wherein the subsequent decoding iteration comprises executing the message passing algorithm N times on each of N circulant columns of a parity check matrix of the QC-LDPC code, and N is an integer.

10. The system of claim 9, wherein, each decoding iteration of the first plurality of decoding iterations comprises passing one or more messages between a plurality of variable nodes and a plurality of check nodes representing a parity check matrix of the QC-LDPC code.

11. The system of claim 10, wherein, the first order comprises a first decoding order of the plurality of variable nodes in a decoding iteration, and wherein the second order comprises a second decoding order of the plurality of variable nodes in a decoding iteration.

12. The system of claim 9, wherein, the instructions, when executed by the processor, configure the processor to: determine the second order based on generating a bit pseudo-random array of length N, wherein each bit of the bit pseudo-random array has a probability p of having a value of 1, and wherein the second order comprises flipping bits when a respective bit in the bit pseudo-random array has a value of 1.

13. The system of claim 12, wherein, p = 0.8 and T = 10.

14. A non-transitory computer-readable storage medium having stored thereon instructions for improving decoding performance of a bit flip decoder associated with a non-volatile memory, the instructions comprising: instructions to receive a noisy codeword based on a transmitted codeword, the transmitted codeword being generated according to a quasi-cyclic low-density parity-check code (QC-LDPC) code; instructions to perform a first plurality of decoding iterations on the noisy codeword, at least one decoding iteration of the first plurality of decoding iterations comprising executing a message passing algorithm in a first order; instructions to calculate, based on completion of the first plurality of decoding iterations, a plurality of syndrome values and a plurality of bit flip counts corresponding to the first plurality of decoding iterations; instructions to determine that the plurality of syndrome values and the plurality of bit flip counts are periodic with a period less than a predetermined threshold T; and instructions to perform a subsequent decoding iteration on the noisy codeword, the subsequent decoding iteration comprising executing the message passing algorithm in a second order different from the first order, wherein the subsequent decoding iteration comprises executing the message passing algorithm N times on each of N circulant columns of a parity check matrix of the QC-LDPC code, and N is an integer. each decoding iteration of the first plurality of decoding iterations comprises passing one or more messages between a plurality of variable nodes and a plurality of check nodes representing a parity check matrix of the QC-LDPC code, wherein the first order comprises a first decoding order of the plurality of variable nodes in a decoding iteration, and wherein the second order comprises a second decoding order of the plurality of variable nodes in a decoding iteration.

15. The non-transitory computer-readable storage medium of claim 14, wherein, ​ 16. The non-transitory computer-readable storage medium of claim 15, wherein, The bit-flipping decoder uses two or more bits to store an estimate for each variable node in the plurality of variable nodes.

17. The non-transitory computer-readable storage medium of claim 14, further comprising: instructions to determine the second order based on generating a bit pseudorandom array of length N, wherein each bit in the bit pseudorandom array has a probability p of having a value of 1, and wherein the second order includes flipping bits when a corresponding bit in the bit pseudorandom array has a value of 1.

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