Method of forming a semiconductor structure

Abstract

A method for forming a semiconductor structure, the method comprising: providing a substrate, including a target layer for forming a target pattern, a pattern definition layer formed on the target layer, a first sacrificial layer formed in the pattern definition layer and extending along a first direction and penetrating through the pattern definition layer, the first sacrificial layer and the pattern definition layer having an etching selectivity; performing a first pattern definition process, the first pattern definition process comprising: removing the pattern definition layer and the first sacrificial layer at the interface between the pattern definition layer and the first sacrificial layer along a second direction, the second direction being perpendicular to the first direction, to form an opening surrounded by the pattern definition layer, the first sacrificial layer and the target layer; forming a first sidewall layer on the sidewall of the opening; after the first pattern definition process, removing the first sacrificial layer; after the first sacrificial layer is removed, etching the target layer to form the target pattern using the first sidewall layer and the pattern definition layer as a mask. Thus, it is beneficial to further reduce the pitch between the target patterns.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a method for forming a semiconductor structure. Background Technology

[0002] With the rapid growth of the integrated circuit (IC) industry, semiconductor technology, driven by Moore's Law, continues to advance towards smaller process nodes, enabling integrated circuits to develop in the direction of smaller size, higher circuit precision, and higher circuit complexity.

[0003] In the development of integrated circuits, as the functional density (i.e. the number of interconnects in each chip) gradually increases, the geometric size (i.e. the smallest component size that can be produced by process steps) also gradually decreases, which correspondingly increases the difficulty and complexity of integrated circuit manufacturing.

[0004] Currently, with the technology nodes constantly shrinking, overcoming the current limitations imposed by lithography equipment to meet the increasingly smaller linewidth requirements of metal interconnects has become a challenge. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a method for forming a semiconductor structure, which is beneficial to further reduce the pitch between target patterns.

[0006] This invention provides a method for forming a semiconductor structure, comprising: providing a substrate including a target layer for forming a target pattern, wherein a pattern definition layer is formed on the target layer, and a first sacrificial layer is formed in the pattern definition layer extending along a first direction and penetrating the pattern definition layer, wherein the first sacrificial layer and the pattern definition layer have an etching selectivity ratio; performing a first pattern definition process, the first pattern definition process comprising: removing a portion of the pattern definition layer and the first sacrificial layer at the junction of the pattern definition layer and the first sacrificial layer along a second direction to form an opening surrounded by the pattern definition layer, the first sacrificial layer and the target layer, wherein the second direction is perpendicular to the first direction; forming a first sidewall layer on the sidewall of the opening; removing the first sacrificial layer after the first pattern definition process; and etching the target layer using the first sidewall layer and the pattern definition layer as a mask after removing the first sacrificial layer to form the target pattern.

[0007] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0008] This invention provides a method for forming a semiconductor structure. First, a first pattern definition process is performed. This first pattern definition process includes: along a second direction, at the boundary between the pattern definition layer and the first sacrificial layer, removing a portion of the pattern definition layer and the first sacrificial layer to form an opening surrounded by the pattern definition layer, the first sacrificial layer, and a target layer. The second direction is perpendicular to the first direction. A first sidewall layer is formed on the sidewall of the opening. After the first pattern definition process, the first sacrificial layer is removed. After removing the first sacrificial layer, the target layer is etched using the first sidewall layer and the pattern definition layer as a mask to form a target pattern. In this embodiment of the invention, during the process of forming an opening, a portion of the pattern definition layer and the first sacrificial layer at the junction along the second direction is removed. This reduces the size of the remaining first sacrificial layer along the second direction compared to the size of the first sacrificial layer along the second direction before forming the opening, and also makes the size of the opening along the second direction smaller. Since a portion of the first sacrificial layer is removed, the initial size of the first sacrificial layer along the second direction is larger, which correspondingly increases the process window for the lithography process during the formation of the first sacrificial layer. Furthermore, by forming a first sidewall layer on the sidewall of the opening, the size of the opening along the second direction is reduced. Therefore, this embodiment can meet the requirement of continuously reducing the linewidth of the target pattern while increasing the process window of the lithography process, thereby facilitating further reduction of the pitch between target patterns. Attached Figure Description

[0009] Figures 1 to 13 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0010] Currently, due to limitations in lithography equipment, the linewidth of metal interconnects formed in semiconductor devices is too large, which cannot meet the process requirements of increasingly smaller metal interconnect linewidths.

[0011] To address the aforementioned technical problem, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate including a target layer for forming a target pattern, wherein a pattern definition layer is formed on the target layer, and a first sacrificial layer is formed in the pattern definition layer extending along a first direction and penetrating the pattern definition layer, wherein the first sacrificial layer and the pattern definition layer have an etching selectivity ratio; performing a first pattern definition process, the first pattern definition process comprising: removing a portion of the pattern definition layer and the first sacrificial layer at the junction of the pattern definition layer and the first sacrificial layer along a second direction to form an opening surrounded by the pattern definition layer, the first sacrificial layer and the target layer, wherein the second direction is perpendicular to the first direction; forming a first sidewall layer on the sidewall of the opening; removing the first sacrificial layer after the first pattern definition process; and after removing the first sacrificial layer, etching the target layer using the first sidewall layer and the pattern definition layer as a mask to form the target pattern.

[0012] In the scheme disclosed in the embodiments of the present invention, a first pattern definition process is first performed. The first pattern definition process includes: along a second direction, at the junction of the pattern definition layer and the first sacrificial layer, removing a portion of the pattern definition layer and the first sacrificial layer to form an opening surrounded by the pattern definition layer, the first sacrificial layer and the target layer, wherein the second direction is perpendicular to the first direction; forming a first sidewall layer on the sidewall of the opening; after the first pattern definition process, removing the first sacrificial layer; after removing the first sacrificial layer, using the first sidewall layer and the pattern definition layer as a mask, etching the target layer to form a target pattern. In this embodiment of the invention, during the process of forming an opening, a portion of the pattern definition layer and the first sacrificial layer at the junction along the second direction is removed. This reduces the size of the remaining first sacrificial layer along the second direction compared to the size of the first sacrificial layer along the second direction before forming the opening, and also makes the size of the opening along the second direction smaller. Since a portion of the first sacrificial layer is removed, the initial size of the first sacrificial layer along the second direction is larger, which correspondingly increases the process window for the lithography process during the formation of the first sacrificial layer. Furthermore, by forming a first sidewall layer on the sidewall of the opening, the size of the opening along the second direction is reduced. Therefore, this embodiment can meet the requirement of continuously reducing the linewidth of the target pattern while increasing the process window of the lithography process, thereby facilitating further reduction of the pitch between target patterns.

[0013] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0014] Figures 1 to 13 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0015] refer to Figures 1 to 2 A substrate is provided, including a target layer 100 for forming a target graphic, on which a graphic definition layer 170 is formed, wherein a graphic definition layer 170 is formed along a first direction (e.g., Figure 2 (b) As shown in the X direction, the first sacrificial layer 106 extends and penetrates the pattern definition layer 170, and there is an etch selectivity between the first sacrificial layer 106 and the pattern definition layer 170.

[0016] in, Figure 1 (b) is a top view. Figure 1 (a) is Figure 1 (b) Cross-sectional view along secant line AB; Figure 2 (b) is a top view. Figure 2 (a) is Figure 2 (b) Sectional view along AB secant line.

[0017] The substrate is used to provide a process platform for subsequent process manufacturing.

[0018] In this embodiment, semiconductor devices such as transistors and capacitors can be formed in the substrate, and functional structures such as resistive structures and conductive structures can also be formed in the substrate.

[0019] The target layer 100 is used as a material layer that needs to be subsequently patterned to form a target graphic.

[0020] The target pattern can be a gate structure, an interconnect trench in a back end of line (BEOL) process, a fin in a FinFET, a channel stack in a gate all-around (GAA) transistor or a forksheet transistor, a hard mask (HM) layer, or other patterns.

[0021] In this embodiment, the target layer 100 is a dielectric layer. The target layer 100 is then patterned, and multiple interconnect trenches are formed in the target layer 100. Subsequently, metal interconnects are formed in the interconnect trenches. The target layer 100 is used to achieve electrical isolation between metal interconnects in the subsequent manufacturing process.

[0022] Therefore, the material of the target layer 100 is a low-k dielectric material (a low-k dielectric material refers to a dielectric material with a relative permittivity greater than or equal to 2.6 and less than or equal to 3.9), an ultra-low-k dielectric material (an ultra-low-k dielectric material refers to a dielectric material with a relative permittivity less than 2.6), silicon oxide, silicon nitride, or silicon oxynitride, etc.

[0023] In this embodiment, the target layer 100 is made of an ultra-low k dielectric material, thereby reducing the parasitic capacitance between subsequent interconnects and thus reducing the subsequent RC delay. Specifically, the target layer 100 can be made of SiOCH.

[0024] In this embodiment, the substrate further includes a hard mask material layer (not shown) located on the target layer 100, and an etch stop layer (not shown) located on the hard mask material layer.

[0025] The hard mask material layer is used to form a hard mask layer (not shown) after subsequent patterning processes.

[0026] Specifically, the pattern is first transferred to a hard mask material layer to form a hard mask layer, and then the target layer 100 is etched using the hard mask layer as a mask, which helps to improve the stability and effect of the patterning process.

[0027] In this embodiment, the material of the hard mask material layer is silicon nitride. In other embodiments, the material of the hard mask material layer may also be silicon oxide, silicon oxynitride, silicon carbide, titanium, titanium oxide, titanium nitride, tantalum, tantalum oxide, tantalum nitride, boron nitride, copper nitride, aluminum nitride, or tungsten nitride, etc.

[0028] Subsequent processes include multiple pattern definition processes. The etch stop layer is used to define the etch stop position in the subsequent pattern definition etching process, which helps to reduce the wear on the target layer 100, improve the depth consistency of the etching process, and thus improve the effect of subsequent patterning processes.

[0029] In this embodiment, the etching stop layer is made of silicon oxide. In other embodiments, the etching stop layer may also be made of silicon nitride, aluminum oxide, titanium nitride, tungsten nitride, or aluminum nitride, etc.

[0030] In this embodiment, the pattern definition layer 170 and the first sacrificial layer 106 are formed on the etch stop layer.

[0031] Subsequently, along the second direction (e.g.) Figure 2 (b) As shown in the Y direction, at the junction of the pattern definition layer 170 and the first sacrificial layer 106, a portion of the pattern definition layer 170 and the first sacrificial layer 106 is removed to form an opening surrounded by the pattern definition layer 170, the first sacrificial layer 106, and the target layer 100. After forming a first sidewall layer on the sidewall of the opening, the first sacrificial layer 106 is removed. Subsequently, the target layer 100 is etched using the first sidewall layer and the pattern definition layer 170 as a mask to form the target pattern. Therefore, the first sacrificial layer 106, with a portion of its width along the second direction, is used to define the position and size of a portion of the target pattern. The second direction is perpendicular to the first direction.

[0032] In this embodiment, there is an etch selectivity ratio between the first sacrificial layer 106 and the pattern definition layer 170.

[0033] It should be noted that the first sacrificial layer 106 will be removed subsequently, and the target layer 100 will be etched using the first sidewall layer and the pattern definition layer 170 as a mask. To achieve this, by having an etching selectivity ratio between the first sacrificial layer 106 and the pattern definition layer 170, the probability of the pattern definition layer 170 being preserved and damaged is low while the first sacrificial layer 106 is removed.

[0034] The etch selectivity between the first sacrificial layer 106 and the pattern definition layer 170 means that, under the same etching process conditions, the first sacrificial layer 106 and the pattern definition layer 170 are etched at different rates.

[0035] In this embodiment, the steps of forming the first sacrificial layer 106 and the graphics definition layer 170 include: as follows Figure 1 As shown, a patterned material layer 101 is formed on top of the target layer 100; as Figure 2 As shown, a portion of the pattern material layer 101 is doped, with the doped pattern material layer 101 serving as the pattern definition layer 170, and the remaining undoped pattern material layer 101 serving as the first sacrificial layer 106.

[0036] The graphic material layer 101 provides the technological basis for forming the graphic definition layer 170 and the first sacrificial layer 106.

[0037] In this embodiment, the material of the patterned material layer 101 is amorphous silicon.

[0038] It should be noted that the lattice structure of amorphous silicon has unstable characteristics, making it easy to subsequently dope the pattern material layer 101 with ions to change the etching rate of the amorphous silicon material, thereby creating an etching selectivity between the first sacrificial layer 106 and the pattern definition layer 170.

[0039] In this embodiment, the patterned material layer 101 is doped using an ion implantation process.

[0040] It should be noted that the ion implantation process features uniform large-area ion implantation, more accurate control of ion doping depth, and high repeatability.

[0041] Specifically, after the pattern material layer 101 is doped, the pattern material layer 101 doped with ions serves as the pattern definition layer 170, and the pattern material layer 101 without ions serves as the first sacrificial layer 106. There is an etching selectivity between the pattern definition layer 170 and the first sacrificial layer 106, which provides a process basis for the subsequent removal of the first sacrificial layer 106.

[0042] In this embodiment, the doping depth of the doping process is the entire thickness of the patterned material layer 101.

[0043] In the step of doping the patterned material layer 101, the dopant ions include boron ions, phosphorus ions, or argon ions. As an example, the dopant ion is a boron ion.

[0044] In this embodiment, before doping the patterned material layer 101, the method for forming the semiconductor structure further includes: forming a third mask layer 105 on top of the patterned material layer 101, wherein the third mask layer 105 covers a portion of the top of the patterned material layer 101.

[0045] The third mask layer 105 is used to block areas in the pattern material layer 101 that are not desired to be doped.

[0046] In this embodiment, the third mask layer 105 includes a first organic material layer 102, a first anti-reflective coating 103 located on the first organic material layer 102, and a first photoresist layer 104 located on the first anti-reflective coating 103.

[0047] The first organic material layer 102 is made of organic materials. In this embodiment, the organic material layer 102 is made of spin-on carbon (SOC). In other embodiments, the organic material layer may also be made of other organic materials, such as one or more of the following: ODL (organic dielectric layer), DUO (Deep UV Light Absorbing Oxide), and APF (Advanced Patterning Film).

[0048] The material of the first anti-reflective coating 103 includes a BARC (bottom anti-reflective coating) material. As an example, the BARC material is a Si-ARC (silicon-containing anti-reflective coating) material.

[0049] In this embodiment, during the formation of the third mask layer 105, the first photoresist layer 104 is used as a mask to sequentially etch the first anti-reflective coating 103 and the organic material layer 102.

[0050] In this embodiment, after doping the pattern material layer 101, the method further includes removing the remaining third mask layer 105.

[0051] It should be noted that, in other embodiments, during the doping process of the pattern material layer in a certain region, the pattern material layer doped with ions may also be used as a first sacrificial layer, and the remaining undoped pattern material layer may be used as a pattern definition layer.

[0052] refer to Figures 3 to 5 The first graphic definition process includes: along a second direction, at the junction of the graphic definition layer 170 and the first sacrificial layer 106, removing a portion of the graphic definition layer 170 and the first sacrificial layer 106 to form an opening 112 surrounded by the graphic definition layer 170, the first sacrificial layer 106 and the target layer 100, wherein the second direction is perpendicular to the first direction; and forming a first sidewall layer 113 on the sidewall of the opening 113.

[0053] in, Figure 3 (b) is a top view. Figure 3 (a) is Figure 3 (b) Cross-sectional view along secant line AB; Figure 4 (b) is a top view. Figure 4 (a) is Figure 4 (b) Cross-sectional view along secant line AB; Figure 5 (b) is a top view. Figure 5 (a) is Figure 5 (b) Sectional view along AB secant line.

[0054] It should be noted that in this embodiment, a first pattern definition process is performed first. After the first pattern definition process, the first sacrificial layer 106 is removed. After removing the first sacrificial layer 106, the target layer 100 is etched using the first sidewall layer 113 and the pattern definition layer 170 as a mask to form the target pattern. In this embodiment, during the formation of the opening 112, a portion of the pattern definition layer 170 and the first sacrificial layer 106 at the junction of the pattern definition layer 170 and the first sacrificial layer 106 is removed along the second direction. This reduces the size of the remaining first sacrificial layer 106 along the second direction compared to the size of the first sacrificial layer 106 before the formation of the opening 112, and also reduces the size of the opening 112 along the second direction. Since a portion of the first sacrificial layer 106 is removed, the initial size of the first sacrificial layer 106 along the second direction is larger, which correspondingly increases the process window for the photolithography process during the formation of the first sacrificial layer 106. Furthermore, by forming a first sidewall layer 113 on the sidewall of the opening 112, the size of the opening 112 along the second direction is reduced. Therefore, this embodiment can meet the requirement of continuously reducing the linewidth of the target pattern while increasing the process window of the photolithography process, thereby facilitating further reduction of the pitch between target patterns.

[0055] refer to Figure 3 In this embodiment, before forming the opening 112 during the first pattern definition process, the method further includes: forming a first mask layer 110 with a first mask opening 180 on top of the pattern definition layer 170 and the first sacrificial layer 106. The first mask opening 180 extends along the first direction and exposes part of the pattern definition layer 170 and the first sacrificial layer 106 in the second direction. The first mask opening 180 is located at the top of the junction of the pattern definition layer 170 and the first sacrificial layer 106.

[0056] Subsequently, using the first mask opening 180 as a mask, the pattern definition layer 170 and the first sacrificial layer 106 exposed by the first mask opening 180 are removed to form an opening 112. In this embodiment, compared to a scheme where an opening is formed in the pattern definition layer on the side of the first sacrificial layer to expose the sidewall of the first sacrificial layer, the first mask opening 180 is located at the top of the junction of the pattern definition layer 170 and the first sacrificial layer 106. This helps to reduce the alignment accuracy requirements in the photolithography process, thereby increasing the process window for the photolithography process when forming the first mask opening 180.

[0057] In this embodiment, the first mask layer 110 includes a second organic material layer 107, a second anti-reflective coating 108 located on the second organic material layer 107, and a second photoresist layer 109 located on the second anti-reflective coating 108.

[0058] For a detailed description of the first mask layer 110, please refer to the corresponding description of the third mask layer 105 above, which will not be repeated here.

[0059] refer to Figure 4 In the step of removing part of the pattern definition layer 170 and the first sacrificial layer 106 at the junction of the pattern definition layer 170 and the first sacrificial layer 106, the pattern definition layer 170 and the first sacrificial layer 106 exposed by the first mask opening 180 are removed using the first mask layer 110 as a mask, forming an opening 112 surrounded by the pattern definition layer 170, the first sacrificial layer 106 and the target layer 100.

[0060] In this embodiment, an anisotropic dry etching process is used to remove a portion of the pattern definition layer 170 and the first sacrificial layer 106 at the junction of the pattern definition layer 170 and the first sacrificial layer 106.

[0061] The anisotropic dry etching process has the characteristics of anisotropic etching, so its longitudinal etching rate is much greater than its transverse etching rate, which can obtain a fairly accurate pattern transfer and improve the sidewall morphology quality of the opening 112.

[0062] In this embodiment, along the second direction, at the junction of the pattern definition layer 170 and the first sacrificial layer 106, a portion of the first sacrificial layer 106 is removed, with a size of 1 nanometer to 15 nanometers.

[0063] It should be noted that the size of the removed portion of the first sacrificial layer 106 should not be too large or too small. If the size of the removed portion of the first sacrificial layer 106 is too large, the size of the remaining first sacrificial layer 106 will be too small, which may lead to the target pattern formed below the remaining first sacrificial layer 106 being too small, failing to meet process requirements, and thus affecting the performance of the metal interconnect. If the size of the removed portion of the first sacrificial layer 106 is too small, the size of the remaining first sacrificial layer 106 will be too large, which may lead to the target pattern formed below the remaining first sacrificial layer 106 being too large, failing to meet the requirement of continuously shrinking linewidth of the target pattern, and thus affecting the performance of the metal interconnect. Alternatively, in order to make the size of the remaining first sacrificial layer 106 meet process requirements, the initial size of the first sacrificial layer 106 may be too small, resulting in a smaller process window for forming the first sacrificial layer 106. Therefore, in this embodiment, along the second direction, at the junction of the pattern definition layer 170 and the first sacrificial layer 106, the size of the removed portion of the first sacrificial layer 106 is 1 nanometer to 15 nanometers. For example, along the second direction, at the junction of the pattern definition layer 170 and the first sacrificial layer 106, a portion of the first sacrificial layer 106 is removed, with a size of 3 nanometers, 7 nanometers, or 10 nanometers.

[0064] In the process of forming the target pattern in the target layer 100, the first sidewall layer 113 is used as an etching mask.

[0065] In this embodiment, the size of the first sidewall layer 113 along the second direction is 10 nanometers to 20 nanometers.

[0066] It should be noted that the size of the first sidewall layer 113 should not be too large or too small. If the size of the first sidewall layer 113 is too large, it will easily occupy too much space in the opening 112, which may result in the target pattern being too small, thus failing to meet the linewidth requirements of the target pattern, or causing the spacing between target patterns to fail to reach the minimum design interval, thereby affecting the performance of the metal interconnect. If the size of the first sidewall layer 113 is too small, it may result in the remaining space in the opening 112 being too large, which may result in the target pattern being too large when the target layer 100 is etched using the first sidewall layer 113 as a mask, thus failing to meet the requirement of continuously shrinking linewidth of the target pattern, thereby affecting the performance of the metal interconnect. Alternatively, in order to make the linewidth of the target pattern meet the process requirements, the size of the opening 112 needs to be reduced accordingly, which may easily reduce the process window for forming the opening 112. Therefore, in this embodiment, the size of the first sidewall layer 113 along the second direction is 10 nanometers to 20 nanometers. For example, along the second direction, the dimensions of the first sidewall layer 113 are 13 nanometers, 15 nanometers, or 17 nanometers.

[0067] It should be noted that in this embodiment, the first sidewall layer 113 has a small dimension along the second direction, thereby enabling a smaller interval between subsequent adjacent target patterns.

[0068] In this embodiment, the process for forming the first sidewall layer 113 includes atomic layer deposition.

[0069] The atomic layer deposition process involves multiple atomic layer deposition cycles, which helps improve the thickness uniformity of the first sidewall layer 113, enabling it to cover the sidewalls of the pattern definition layer 170 and the first sacrificial layer 106. In other embodiments, the first sidewall layer can also be formed using chemical vapor deposition (CVD).

[0070] It should be noted that the first sidewall layer 113 is used as an etching mask for the subsequent etching target layer 100.

[0071] In this embodiment, the material of the first sidewall layer 113 can be titanium oxide, titanium nitride, silicon oxide, silicon nitride, or aluminum oxide. In this embodiment, the material of the first sidewall layer 113 is titanium oxide. Titanium oxide has a relatively high etching selectivity compared to amorphous silicon or silicon nitride. The first sidewall layer 113 can be retained during the subsequent removal of the first sacrificial layer 106 and the second sacrificial layer to form the interconnect trench, and the target layer 100 can be etched subsequently using the first sidewall layer 113 as a mask.

[0072] In this embodiment, the step of forming the first sidewall layer 113 includes: forming a first sidewall material layer (not shown) on the top and sidewalls of the graphic definition layer 170 and the first sacrificial layer 106, and on the exposed top of the target layer 100; removing the first sidewall material layer on the top of the graphic definition layer 170, the first sacrificial layer 106 and the target layer 100; and the remaining first sidewall material layer as the first sidewall layer 113.

[0073] It should be noted that in this embodiment, in the second direction, only a portion of the first sacrificial layer 106 on one side is etched, thereby forming an opening 112 on one side of the remaining first sacrificial layer 106. In other embodiments, depending on process requirements, portions of the first sacrificial layer on both sides can also be etched to form openings on both sides of the remaining first sacrificial layer.

[0074] In this embodiment, after forming the opening 112, the method further includes: removing the remaining first mask layer 110.

[0075] refer to Figures 6 to 10 After the first graphic definition processing, the first sacrificial layer 106 is removed.

[0076] in, Figure 6 (b) is a top view. Figure 6 (a) is Figure 6 (b) Cross-sectional view along secant line AB; Figure 7 (b) is a top view. Figure 7 (a) is Figure 7 (b) Cross-sectional view along secant line AB; Figure 8 (b) is a top view. Figure 8 (a) is Figure 8 (b) Cross-sectional view along secant line AB; Figure 9 (b) is a top view. Figure 9 (a) is Figure 9 (b) Cross-sectional view along secant line AB; Figure 10 (b) is a top view. Figure 10 (a) is Figure 10 (b) Sectional view along AB secant line.

[0077] It should be noted that the first sacrificial layer 106 is removed to expose the area to be etched.

[0078] In this embodiment, a wet etching process is used to remove the first sacrificial layer 106.

[0079] The wet etching process is an isotropic etching process, characterized by high etching efficiency, simple process, and strong surface uniformity. There is an etching selectivity ratio between the first sacrificial layer 106 and the pattern definition layer 170; therefore, a maskless etching method can be used to remove the first sacrificial layer 106, thereby enhancing the process effect of removing the first sacrificial layer 106.

[0080] In this embodiment, the etching solution for the wet etching process comprises ammonia water with a concentration of 10% to 40%. In other embodiments, the etching solution may also be a TMAH solution (tetramethylammonium hydroxide solution).

[0081] It should be noted that, in this embodiment, after the first graphic definition process and before removing the first sacrificial layer 106, the forming method further includes: performing one or more second graphic definition processes, the second graphic definition process including: Figure 6 As shown, a second sacrificial layer 114 is formed in the remaining space of the opening 112; as Figures 7 to 8 As shown, after the second sacrificial layer 114 is formed, along the second direction, at the junction of the graphic definition layer 170 and the second sacrificial layer 114, a portion of the graphic definition layer 170 and the second sacrificial layer 114 is removed to form another opening 120 enclosed by the graphic definition layer 170, the second sacrificial layer 114, and the target layer 100; as shown Figure 9 As shown, after forming another opening 120 surrounded by the graphic definition layer 170, the second sacrificial layer 114 and the target layer 100, a second sidewall layer 121 is formed on the sidewall exposed by the other opening 120.

[0082] In each second graphic definition process, during the formation of another opening 120 surrounded by the graphic definition layer 170, the second sacrificial layer 114 and the target layer 100, the first sidewall layer 113 or the second sidewall layer 121 located between the graphic definition layer 170 and the second sacrificial layer 114 in the second direction is also removed.

[0083] It should be noted that removing the first sidewall layer 113 or the second sidewall layer 121 located between the graphic definition layer 170 and the second sacrificial layer 114 results in another opening 120 that exposes the sidewalls of the graphic definition layer 170 and the remaining second sacrificial layer 114. The first sidewall layer 113 or the second sidewall layer 121 is not formed in the other opening 120.

[0084] In this embodiment of the invention, by forming another opening 120, the opening 112 and the other opening 120 together define the shape of the target shape, thereby increasing the number of target shapes according to design requirements.

[0085] In the process of forming another opening 120, along the second direction, a portion of the pattern definition layer 170 and the second sacrificial layer 114 at the junction of the pattern definition layer 170 and the second sacrificial layer 114 is removed, making the size of the remaining second sacrificial layer 114 along the second direction smaller than the size of the second sacrificial layer 114 along the second direction before forming the other opening 120, and making the size of the other opening 120 along the second direction smaller as well. Since a portion of the second sacrificial layer 114 is removed, the initial size of the second sacrificial layer 114 along the second direction is larger, which correspondingly increases the process window of the photolithography process for forming the second sacrificial layer 114. Furthermore, by forming a second sidewall layer 121 on the sidewall of the other opening 120, the size of the other opening 120 along the second direction is reduced. Therefore, this embodiment can meet the requirement of continuously reducing the linewidth of the target pattern while increasing the process window of the photolithography process, thereby facilitating further reduction of the pitch between target patterns.

[0086] In this embodiment, the second graphic definition process is performed only once. In other embodiments, the second graphic definition process may be performed multiple times.

[0087] It should be noted that, in this embodiment, since only one second graphic definition process is performed, only the first sidewall layer 113 located between the graphic definition layer 170 and the second sacrificial layer 114 is removed during the formation of another opening 120. In other embodiments, when the Nth (N is a natural number greater than 1) second graphic definition process is performed, the second sidewall layer located between the graphic definition layer and the second sacrificial layer is removed during the formation of another opening surrounded by the graphic definition layer, the second sacrificial layer, and the target layer.

[0088] The second graphic definition process will be described in detail below with reference to the accompanying drawings.

[0089] refer to Figure 6 A second sacrificial layer 114 is formed in the remaining space of the opening 112.

[0090] The second sacrificial layer 114 provides the technological basis for the subsequent formation of another opening 120.

[0091] The material of the second sacrificial layer 114 is an organic material.

[0092] It should be noted that the etching selectivity between the organic material and the materials of the first sidewall layer 113 and the second sidewall layer 121 is relatively large, which is beneficial for the subsequent removal of the second sacrificial layer 114.

[0093] The material of the second sacrificial layer 114 includes one or more of spin-coated glass, ion-reinforced silicon dioxide, and tetraethyl orthosilicate.

[0094] refer to Figure 7 and Figure 8 In this embodiment, an anisotropic dry etching process is used to remove a portion of the pattern definition layer 170 and the second sacrificial layer 114 at the junction of the pattern definition layer 170 and the second sacrificial layer 114.

[0095] The anisotropic dry etching process has the characteristics of anisotropic etching, so its longitudinal etching rate is much greater than its transverse etching rate, which can obtain a fairly accurate pattern transfer, thereby improving the morphological quality and dimensional accuracy of the other opening 120.

[0096] In this embodiment, along the second direction, at the junction of the pattern definition layer 170 and the second sacrificial layer 114, a portion of the second sacrificial layer 114 is removed, with a size of 1 nanometer to 15 nanometers.

[0097] It should be noted that the size of the removed portion of the second sacrificial layer 114 should not be too large or too small. If the size of the removed portion of the second sacrificial layer 114 is too large, the size of the remaining second sacrificial layer 114 will be too small, which may lead to the target pattern formed below the remaining second sacrificial layer 114 being too small, failing to meet process requirements, and thus affecting the performance of the metal interconnect. If the size of the removed portion of the second sacrificial layer 114 is too small, the size of the remaining second sacrificial layer 114 will be too large, which may lead to the target pattern formed below the remaining second sacrificial layer 114 being too large, failing to meet the requirement of continuously shrinking linewidth of the target pattern, and thus affecting the performance of the metal interconnect. Alternatively, in order to make the size of the remaining second sacrificial layer 114 meet process requirements, the initial size of the second sacrificial layer 114 may be too small, resulting in a smaller process window for forming the second sacrificial layer 114. Therefore, in this embodiment, along the second direction, at the junction of the pattern definition layer 170 and the second sacrificial layer 114, the size of the removed portion of the second sacrificial layer 114 is 1 nanometer to 15 nanometers. For example, along the second direction, at the junction of the pattern definition layer 170 and the second sacrificial layer 114, a portion of the second sacrificial layer 114 is removed, with a size of 3 nanometers, 7 nanometers, or 10 nanometers.

[0098] It should be noted that the step of removing part of the graphic definition layer 170 and the second sacrificial layer 114 at the junction of the graphic definition layer 170 and the second sacrificial layer 114 further includes: removing the first sidewall layer 113 located between the graphic definition layer 170 and the second sacrificial layer 114.

[0099] refer to Figure 9 A second sidewall layer 121 is formed on the sidewall of the other opening 120.

[0100] It should be noted that by forming a second sidewall layer 121 on the sidewall exposed by the other opening 120, the size of the other opening 120 along the second direction is reduced, thereby satisfying the requirement of continuously reducing the linewidth of the target pattern while increasing the process window of the photolithography process. At the same time, in the subsequent process of forming the target pattern in the target layer 100, the second sidewall layer 121 will also be used as an etching mask.

[0101] In this embodiment, the size of the second sidewall layer 121 along the second direction is 10 nanometers to 20 nanometers.

[0102] It should be noted that the size of the second sidewall layer 121 should not be too large or too small. If the size of the second sidewall layer 121 is too large, it will easily occupy too much space in the other opening 120, which may result in the target pattern being too small, thus failing to meet the linewidth requirements of the target pattern, or causing the spacing between target patterns to fail to reach the minimum design interval, thereby affecting the performance of the metal interconnect. If the size of the second sidewall layer 121 is too small, it may result in the remaining space in the other opening 120 being too large, which may result in the target pattern being too large when the target layer 100 is etched using the second sidewall layer 121 as a mask, thus failing to meet the requirement of continuously shrinking linewidth of the target pattern, thereby affecting the performance of the metal interconnect. Alternatively, in order to make the linewidth of the target pattern meet the process requirements, the size of the other opening 120 needs to be reduced accordingly, which may easily reduce the process window for forming the other opening 120. Therefore, in this embodiment, the size of the second sidewall layer 121 along the second direction is 10 nanometers to 20 nanometers. For example, along the second direction, the dimensions of the second sidewall layer 121 are 13 nanometers, 15 nanometers, or 17 nanometers.

[0103] It should be noted that in this embodiment, the second sidewall layer 121 has a small dimension along the second direction, thereby enabling a smaller interval between subsequent adjacent target patterns.

[0104] In this embodiment, the process for forming the second sidewall layer 121 includes atomic layer deposition.

[0105] The atomic layer deposition process includes multiple atomic layer deposition cycles, which helps improve the thickness uniformity of the second sidewall layer 121, enabling it to cover the sidewalls of the pattern definition layer 170 and the second sacrificial layer 114. In other embodiments, the first sidewall layer can also be formed using chemical vapor deposition (CVD).

[0106] In this embodiment, the material of the second sidewall layer 121 can be titanium oxide, titanium nitride, silicon oxide, silicon nitride, or aluminum oxide. In this embodiment, the material of the second sidewall layer 121 is titanium oxide. Titanium oxide has a relatively high etching selectivity compared to amorphous silicon or silicon nitride. The second sidewall layer 121 can be retained during the subsequent removal of the first sacrificial layer 106 and the second sacrificial layer 114 to form interconnect trenches, and the target layer 100 can be etched subsequently using the second sidewall layer 121 as a mask.

[0107] In this embodiment, the step of forming the second sidewall layer 121 includes: forming a second sidewall material layer (not shown) on the top of the graphic definition layer 170, the second sacrificial layer 114, the target layer 100, the first sacrificial layer 106, and the first sidewall layer 113, as well as the bottom and sidewall of the other opening 120; removing the second sidewall material layer from the top of the graphic definition layer 170, the first sacrificial layer 106, the first sidewall layer 113, the second sacrificial layer 114, and the target layer 100, as well as from the bottom of the other opening 120; and the remaining second sidewall material layer serves as the second sidewall layer 121.

[0108] It should be noted that, in this embodiment, a first sacrificial layer 106 is formed on one side of the second sacrificial layer 114 in the second direction. Therefore, only a portion of the second sacrificial layer 114 on one side is etched, thereby forming the other opening 120 on the remaining side of the second sacrificial layer 114.

[0109] refer to Figure 7 In this embodiment, during the second pattern definition process, after the formation of the second sacrificial layer 114 and before the formation of the other opening 120, the process further includes: forming a second mask layer 118 with a second mask opening 119 on the top of the pattern definition layer 170, the first sacrificial layer 106, the second sacrificial layer 114 and the first sidewall layer 113. The second mask opening 119 extends along the first direction and exposes a portion of the pattern definition layer 170 and the second sacrificial layer 114 in the second direction. The second mask opening 119 is located at the top of the junction of the pattern definition layer 170 and the second sacrificial layer 114.

[0110] Subsequently, using the second mask opening 119 as a mask, the pattern definition layer 170 and the second sacrificial layer 114 exposed by the second mask opening 119 are removed to form another opening 120. In this embodiment, compared to the scheme of forming an opening in the pattern definition layer on the side of the second sacrificial layer to expose the sidewall of the second sacrificial layer, the first mask opening 180 is located at the top of the junction of the pattern definition layer 170 and the first sacrificial layer 106. This helps to reduce the alignment accuracy requirements in the photolithography process, thereby increasing the process window for the photolithography process when forming the second mask opening 119.

[0111] In this embodiment, the second mask layer 118 includes a third organic material layer 115, a third anti-reflective coating 116 located on the third organic material layer 115, and a third photoresist layer 117 located on the third anti-reflective coating 116.

[0112] For a detailed description of the second mask layer 118, please refer to the foregoing description of the third mask layer 105, which will not be repeated here.

[0113] In this embodiment, in the step of removing part of the graphic definition layer 170 and the second sacrificial layer 114 at the junction of the graphic definition layer 170 and the second sacrificial layer 114, the second mask layer 118 is used as a mask to remove the graphic definition layer 170 and the second sacrificial layer 114 exposed by the second mask opening 119, forming another opening 120 surrounded by the graphic definition layer 170, the second sacrificial layer 114 and the target layer 100.

[0114] It should be noted that after forming the other opening 120, the process also includes removing the second mask layer 118.

[0115] refer to Figures 11 to 12 After removing the first sacrificial layer 106 and the second sacrificial layer 114, the target layer 100 is etched using the first sidewall layer 113 and the pattern definition layer 170 as a mask to form the target pattern 150.

[0116] in, Figure 11 (b) is a top view. Figure 11 (a) is Figure 11 (b) Cross-sectional view along secant line AB; Figure 12 (b) is a top view. Figure 12 (a) is Figure 12 (b) Sectional view along AB secant line.

[0117] As can be seen from the foregoing description, this embodiment can meet the requirement of continuously reducing the linewidth of the target pattern 150 while increasing the process window of the photolithography process, which correspondingly improves the pattern accuracy and pattern quality of the target pattern 150.

[0118] It should be noted that the target layer 100 is a dielectric layer. Therefore, after etching the target layer 100 using the first sidewall layer 113 and the pattern definition layer 170 as masks, the target pattern 150 is an interconnect trench.

[0119] In this embodiment, a hard mask material layer (not shown) and an etch stop layer (not shown) are also formed on the target layer 100, and the bottom of the opening 112 and the other opening 120 exposes the etch stop layer.

[0120] Therefore, using the first sidewall layer 113 and the pattern definition layer 170 as masks, the etching stop layer and hard mask material layer at the bottom of the opening 112 and the other opening 120 are etched in sequence. After the remaining hard mask material layer is used as a hard mask layer (not shown), the target layer 100 is etched using the hard mask layer as a mask.

[0121] By first transferring the patterns of the opening 112 and the other opening 120 to the hard mask material layer to form a hard mask layer, it is beneficial to improve the process stability and process effect of etching the target layer 100 and improve the accuracy of pattern transfer.

[0122] It should be noted that in this embodiment, the second sidewall layer 121 is also used as a mask in the step of etching the target layer 100.

[0123] Reference Figure 11 In this embodiment, before etching the target layer 100 using the first sidewall layer 113 and the pattern definition layer 170 as a mask, the formation method further includes: removing the second sacrificial layer 114 (e.g., ...). Figure 10 (As shown).

[0124] It should be noted that removing the second sacrificial layer 114 provides a process basis for subsequently etching the target layer 100 using the second sidewall layer 121 as a mask.

[0125] In this embodiment, the process of removing the second sacrificial layer 114 includes one or both of an ashing process and a wet desizing process.

[0126] The ashing process and wet degumming process for removing organic materials are characterized by high efficiency and low cost. Therefore, in this embodiment, the process for removing the second sacrificial layer 114 includes one or both of the ashing process and the wet degumming process.

[0127] It should be noted that this embodiment uses the example of removing the first sacrificial layer 106 first, and then removing the second sacrificial layer 114. In other embodiments, the second sacrificial layer may be removed first, and then the first sacrificial layer may be removed.

[0128] refer to Figure 13 The forming method further includes: after forming the interconnect trench, forming a metal interconnect 160 in the interconnect trench.

[0129] in, Figure 13 (b) is a top view. Figure 13 (a) is Figure 13 (b) Sectional view along AB secant line.

[0130] Metal interconnect 160 is used to realize electrical connection between semiconductor structure and external circuit or other interconnect structure.

[0131] As described above, this embodiment can meet the requirement of continuously shrinking interconnect trench linewidth while increasing the process window of the photolithography process, and the spacing between adjacent interconnect trenches can easily meet the design minimum spacing, which is conducive to making the spacing of metal interconnect 160 meet the design minimum spacing, and also conducive to improving the pattern accuracy of metal interconnect 160, thereby improving the electrical connection performance of metal interconnect 160.

[0132] In this embodiment, the material of the metal interconnect 160 is copper. In other embodiments, the material of the metal interconnect can also be conductive materials such as aluminum.

[0133] In this embodiment, the metal interconnect 160 is formed in the interconnect trench using copper electroplating.

[0134] Accordingly, the process of forming the metal interconnect 160 includes a conductive material filling step and a conductive material planarization step to remove conductive material above the top of the dielectric layer.

[0135] In this embodiment, a chemical mechanical polishing process is used to planarize the conductive material.

[0136] The chemical mechanical polishing process gives the metal interconnects 160 formed in the interconnect trench a flat surface, thereby improving the electrical connection effect of the metal interconnects 160.

[0137] In this embodiment, during the formation of the metal interconnect 160, the remaining pattern definition layer 170, first sidewall layer 113, second sidewall layer 121, etch stop layer, and hard mask layer are also removed, thereby exposing the top surface of the target layer 100 to prepare for subsequent processes.

[0138] The specific description of the metal interconnect 160 will not be repeated here.

[0139] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method of forming a semiconductor structure, characterized by, The method comprises the following steps: providing a substrate, which comprises a target layer for forming a target pattern, a pattern definition layer formed on the target layer, a first sacrificial layer formed in the pattern definition layer and extending along a first direction and penetrating through the pattern definition layer, and an etching selectivity between the first sacrificial layer and the pattern definition layer; performing a first pattern definition process, which comprises: removing part of the pattern definition layer and the first sacrificial layer at the interface between the pattern definition layer and the first sacrificial layer along a second direction to form an opening surrounded by the pattern definition layer, the first sacrificial layer and the target layer, and forming a first sidewall layer on the sidewall of the opening, wherein the second direction is perpendicular to the first direction; after the first pattern definition process, performing one or more second pattern definition processes, which comprises: forming a second sacrificial layer in the remaining space of the opening; after forming the second sacrificial layer, removing part of the pattern definition layer and the second sacrificial layer at the interface between the pattern definition layer and the second sacrificial layer along the second direction to form another opening surrounded by the pattern definition layer, the second sacrificial layer and the target layer; after forming the other opening surrounded by the pattern definition layer, the second sacrificial layer and the target layer, forming a second sidewall layer on the sidewall of the other opening; removing the first sacrificial layer and the second sacrificial layer; after removing the first sacrificial layer and the second sacrificial layer, etching the target layer with the first sidewall layer, the second sidewall layer and the pattern definition layer as masks to form a target pattern.

2. The method according to claim 1, wherein in each second pattern definition process, during the process of forming the other opening surrounded by the pattern definition layer, the second sacrificial layer and the target layer, the first sidewall layer or the second sidewall layer located between the pattern definition layer and the second sacrificial layer in the second direction is also removed. The step of forming the first sacrificial layer and the pattern definition layer comprises forming a pattern material layer on the top of the target layer.

3. The method of forming a semiconductor structure of claim 1, wherein, Part of the pattern material layer is subjected to a doping treatment, and the pattern material layer doped with ions serves as the pattern definition layer, and the remaining pattern material layer without ions serves as the first sacrificial layer. The doping treatment of the pattern material layer is performed by an ion implantation process.

4. The method of forming a semiconductor structure of claim 3, wherein, The material of the pattern material layer is amorphous silicon.

5. The method of forming a semiconductor structure of claim 3, wherein In the step of doping the pattern material layer, the doping ions include boron ions, phosphorus ions or argon ions. During the first pattern definition process, before forming the opening, a first mask layer with a first mask opening is formed on the top of the pattern definition layer and the first sacrificial layer, the first mask opening extends along the first direction and exposes part of the pattern definition layer and the first sacrificial layer in the second direction, and the first mask opening is located on the top of the interface between the pattern definition layer and the first sacrificial layer.

6. The method of forming a semiconductor structure of claim 1, wherein, ​ At the junction of the pattern definition layer and the first sacrificial layer, in the step of removing part of the pattern definition layer and the first sacrificial layer, the pattern definition layer and the first sacrificial layer exposed by the first mask layer are removed.

7. The method of forming a semiconductor structure of claim 2, wherein, In the process of the second pattern definition, after the second sacrificial layer is formed, before the other opening is formed, the method further comprises: forming a second mask layer with a second mask opening on top of the pattern definition layer, the first sacrificial layer, the second sacrificial layer and the first sidewall layer, the second mask opening extends along the first direction and exposes part of the pattern definition layer and the second sacrificial layer in the second direction, and the second mask opening is located on top of the junction of the pattern definition layer and the second sacrificial layer. At the junction of the pattern definition layer and the second sacrificial layer, in the step of removing part of the pattern definition layer and the second sacrificial layer, the pattern definition layer and the second sacrificial layer exposed by the second mask layer are removed.

8. The method of forming a semiconductor structure of claim 1, wherein, An anisotropic dry etching process is used to remove part of the pattern definition layer and the first sacrificial layer at the junction of the pattern definition layer and the first sacrificial layer.

9. The method of forming a semiconductor structure of claim 1, wherein, In the second direction, the size of part of the first sacrificial layer removed at the junction of the pattern definition layer and the first sacrificial layer is 1-15 nanometers.

10. The method of forming a semiconductor structure of claim 1, wherein, In the second direction, the size of the first sidewall layer is 10-20 nanometers.

11. The method of forming a semiconductor structure of claim 1, wherein, The first sidewall layer is formed by an atomic layer deposition process.

12. The method of forming a semiconductor structure of claim 1, wherein, The first sacrificial layer is removed by a wet etching process.

13. The method of forming a semiconductor structure of claim 2, wherein, The material of the second sacrificial layer is an organic material.

14. The method of forming a semiconductor structure of claim 13, wherein, The material of the second sacrificial layer comprises one or more of spin-on glass, ion enhanced silicon oxide and tetraethyl orthosilicate.

15. The method of forming a semiconductor structure of claim 2, wherein, An anisotropic dry etching process is used to remove part of the pattern definition layer and the second sacrificial layer at the junction of the pattern definition layer and the second sacrificial layer.

16. The method of forming a semiconductor structure of claim 2, wherein, In the second direction, the size of part of the second sacrificial layer removed at the junction of the pattern definition layer and the second sacrificial layer is 1-15 nanometers.

17. The method of forming a semiconductor structure of claim 2, wherein, In the second direction, the size of the second sidewall layer is 10-20 nanometers.

18. The method of forming a semiconductor structure of claim 2, wherein, The second sidewall layer is formed by an atomic layer deposition process.

19. The method of forming a semiconductor structure of claim 2, wherein, The process of removing the second sacrificial layer comprises one or both of a gray etching process and a wet adhesive removal process.

20. The method of forming a semiconductor structure of claim 1, wherein, The target layer is a dielectric layer, and the target pattern is an interconnection trench. The forming method further comprises: after the interconnection trench is formed, forming a metal interconnection line in the interconnection trench.

Images