Display substrate and manufacturing method thereof, display panel and display device

Abstract

The present invention relates to a display substrate and a method for preparing the same, a display panel and a display device. The display substrate includes a first thin film transistor and a second thin film transistor; the gate electrode of the first thin film transistor and the source and drain electrode of the second thin film transistor are a same-layer structure formed synchronously. In the above-mentioned display substrate, the gate electrode of the first thin film transistor and the source and drain electrode of the second thin film transistor are a same-layer structure formed synchronously. In other words, when preparing the display substrate, the gate electrode of the first thin film transistor and the source and drain electrode of the second thin film transistor are formed in a common one-time mask process, without the need to prepare each of them through a one-time mask process. In this way, one mask process is reduced. Specifically, the time required for one mask process is saved, and the cost of materials and equipment required for one mask process is also saved, thereby improving the preparation efficiency of the display substrate on the one hand, and reducing the cost of the display substrate on the other hand.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display substrate and a preparation method thereof, a display panel and a display device. Background Art

[0002] Thin film transistors are an indispensable basic component in display panels. Moreover, many types of display panels may have multiple types of thin film transistors. These different types of thin film transistors may specifically be thin film transistors with different active layer materials or with different active layer positions.

[0003] For existing display panels with multiple types of thin film transistors, when preparing multiple types of thin film transistors, it is necessary to prepare the gate, active layer, source and drain electrode, gate insulation layer, interlayer insulation layer and planarization layer and other layer structures of each thin film transistor separately and individually, and the preparation of each thin film transistor requires multiple patterning (mask) processes. When preparing multiple types of thin film transistors, the number of masking processes required is superimposed, which ultimately leads to a higher total number of masking processes required, which ultimately leads to reduced efficiency and increased costs. Summary of the invention

[0004] The present invention provides a display substrate and a method for preparing the same, a display panel and a display device, so as to solve the technical problem in the prior art that a large number of mask processes are required, resulting in reduced efficiency and increased cost.

[0005] The display substrate provided by the present invention comprises a first thin film transistor and a second thin film transistor; the gate electrode of the first thin film transistor and the source-drain electrode of the second thin film transistor are synchronously formed in the same layer structure.

[0006] The source and drain electrodes of the first thin film transistor and the gate electrode of the second thin film transistor are synchronously formed in the same layer.

[0007] The gate electrode of the first thin film transistor and the source-drain electrode of the second thin film transistor are located above or below the source-drain electrode of the first thin film transistor and the gate electrode of the second thin film transistor.

[0008] The first thin film transistor is a low-temperature polysilicon thin film transistor, and the second thin film transistor is an oxide thin film transistor; or the first thin film transistor is an oxide thin film transistor, and the second thin film transistor is a low-temperature polysilicon thin film transistor.

[0009] Among them, the source and drain electrodes of the first thin film transistor are arranged above the gate of the first thin film transistor, and the active layer of the first thin film transistor is arranged below the gate of the first thin film transistor or between the gate of the first thin film transistor and the source and drain electrodes of the first thin film transistor; a source via and a drain via are arranged on the layer structure between the source and drain electrodes of the first thin film transistor and the active layer of the first thin film transistor, the source of the first thin film transistor is connected to the active layer of the first thin film transistor through the source via, and the drain of the first thin film transistor is connected to the active layer of the first thin film transistor through the drain via; the active layer of the second thin film transistor is arranged above the source and drain electrodes of the second thin film transistor and is connected to the source and drain electrodes of the second thin film transistor; the gate of the second thin film transistor is arranged above the active layer of the second thin film transistor.

[0010] Among them, a via hole penetrating to the active layer of the oxide thin film transistor is arranged on the layer structure above the active layer of the oxide thin film transistor, and the active layer of the oxide thin film transistor is connected to the pixel electrode through the via hole; or, a via hole penetrating to the active layer of the oxide thin film transistor is arranged on the layer structure above the active layer of the oxide thin film transistor, and the active layer of the oxide thin film transistor is connected to the switching layer connected to the pixel electrode through the via hole; or, a partial area of ​​the active layer of the oxide thin film transistor is a conductive semiconductor layer that has been subjected to conductor treatment, and the conductive semiconductor layer serves as a pixel electrode.

[0011] Wherein, the slope of the edge of the data line connected to the source and drain electrodes of the oxide thin film transistor is less than 70 degrees.

[0012] A first interlayer insulating layer is arranged above the source and drain electrodes of the oxide thin film transistor, and a via is arranged on the first interlayer insulating layer. The active layer of the oxide thin film transistor is connected to the source and drain electrodes of the oxide thin film transistor through the via on the first interlayer insulating layer.

[0013] Wherein, the slope of the via hole in the first interlayer insulating layer ranges from 45 to 70 degrees.

[0014] Wherein, the material of the active layer of the oxide thin film transistor is IGZO.

[0015] Wherein, the material of the first interlayer insulating layer is silicon oxide.

[0016] Among them, the low-temperature polysilicon thin film transistor is arranged in the non-display area of ​​the display substrate and is connected to the gate driving circuit in the non-display area; the oxide thin film transistor is arranged in the display area of ​​the display substrate, and at least one oxide thin film transistor is arranged in each sub-pixel in the display area of ​​the display substrate.

[0017] The projection of the effective channel region in the active layer of the oxide thin film transistor on the source and drain electrodes of the oxide thin film transistor is located within the source and drain electrodes of the oxide thin film transistor.

[0018] Wherein, the distance between the edge of the source-drain electrode of the oxide thin film transistor and the edge of the projection of the effective channel region on the source-drain electrode of the oxide thin film transistor is 0-2 micrometers.

[0019] Wherein, the thickness of the gate electrode of the low-temperature polysilicon thin film transistor and the source and drain electrode of the oxide thin film transistor ranges from 1000 to 5000 angstroms.

[0020] Wherein, the thickness of the first interlayer insulating layer is 1000 to 6000 angstroms.

[0021] The present invention provides a method for preparing a display substrate, which comprises:

[0022] A first material layer is deposited on a substrate, and a pattern of a gate electrode of a first thin film transistor is formed in a first region of the substrate through a patterning process, and a pattern of a source-drain electrode of a second thin film transistor is formed in a second region of the substrate.

[0023] Wherein, the method for preparing the display substrate further comprises:

[0024] A second material layer is deposited, and a pattern of a source-drain electrode of a first thin film transistor is formed in a first region of the substrate through a patterning process, and a pattern of a gate electrode of a second thin film transistor is formed in a second region of the substrate.

[0025] The first thin film transistor is a low-temperature polysilicon thin film transistor, and the second thin film transistor is an oxide thin film transistor; or the first thin film transistor is an oxide thin film transistor, and the second thin film transistor is a low-temperature polysilicon thin film transistor.

[0026] Among them, the area where the low-temperature polycrystalline silicon thin film transistor is formed is the non-display area of ​​the display substrate, and the formed low-temperature polycrystalline silicon thin film transistor is connected to the gate driving circuit of the display substrate; each sub-pixel area on the display substrate has at least one area where the oxide thin film transistor is formed.

[0027] The method for preparing the display substrate further includes, before forming the patterns of the gate electrode of the first thin film transistor and the source and drain electrode of the second thin film transistor:

[0028] forming a pattern of an active layer of a first transistor;

[0029] A gate insulating layer of the first transistor is patterned.

[0030] The method for preparing the display substrate further includes, after forming the pattern of the gate electrode of the first thin film transistor and the pattern of the source and drain electrode of the second thin film transistor, and before forming the pattern of the source and drain electrode of the first thin film transistor and the pattern of the gate electrode of the second thin film transistor:

[0031] forming a pattern of a gate insulating layer of a first transistor;

[0032] forming a pattern of an active layer of a first transistor;

[0033] An interlayer insulating layer is patterned.

[0034] The method for preparing the display substrate further includes, after forming the pattern of the gate electrode of the first thin film transistor and the pattern of the source-drain electrode of the second thin film transistor, and before forming the pattern of the source-drain electrode of the first thin film transistor and the pattern of the gate electrode of the second thin film transistor:

[0035] Depositing an insulating material on the pattern of the gate electrode of the first thin film transistor and the pattern of the source and drain electrode of the second thin film transistor to form a first interlayer insulating layer, and forming a via hole penetrating the first interlayer insulating layer in the second region by a patterning process, wherein the lower end of the via hole is connected to the source and drain electrode of the second thin film transistor;

[0036] forming a pattern of an active layer of a second thin film transistor in the second region, wherein the pattern of the active layer of the second thin film transistor is connected to a source-drain electrode of the second thin film transistor through a via hole on the first interlayer insulating layer;

[0037] A pattern of a gate insulating layer of the second thin film transistor is formed.

[0038] Wherein, the method for preparing the display substrate further comprises, after forming the pattern of the source and drain electrodes of the first thin film transistor and the pattern of the gate electrode of the second thin film transistor:

[0039] depositing an insulating material to form a second interlayer insulating layer;

[0040] A via hole is formed in the region where the oxide thin film transistor is located by a patterning process, the via hole penetrating the second interlayer insulating layer and having a lower end connected to the active layer of the oxide thin film transistor;

[0041] forming a pattern of a transfer layer in the region of the oxide thin film transistor, wherein the pattern of the transfer layer is connected to the active layer of the oxide thin film transistor through a via hole penetrating through the second interlayer insulating layer;

[0042] Forming a pattern of the planarization layer, and forming a via hole penetrating the planarization layer in the region of the oxide thin film transistor by a patterning process, wherein the lower end of the via hole is connected to the transfer layer;

[0043] forming a pattern of a pixel electrode, wherein the pattern of the pixel electrode is connected to the transfer layer through a via hole on the planarization layer;

[0044] or

[0045] depositing an insulating material to form a second interlayer insulating layer;

[0046] Forming a via hole penetrating the second interlayer insulating layer in the region of the oxide thin film transistor by a patterning process, the via hole having a lower end connected to the active layer of the oxide thin film transistor;

[0047] forming a pattern of a pixel electrode, wherein the pattern of the pixel electrode is connected to the active layer of the oxide thin film transistor through a via hole penetrating through the second interlayer insulating layer;

[0048] or

[0049] Conductive processing is performed on a partial area of ​​the active layer of the oxide thin film transistor, so that the conductive part of the active layer of the oxide thin film transistor can be used as a pixel electrode.

[0050] The display panel provided by the present invention includes the above-mentioned display substrate.

[0051] The display device provided by the present invention includes the above-mentioned display panel.

[0052] The display substrate and the manufacturing method thereof, the display panel and the display device provided by the embodiments of the present invention have the following advantages compared with the prior art:

[0053] In the display substrate provided by the embodiment of the present invention, the gate electrode of the first thin film transistor and the source and drain electrode of the second thin film transistor are the same-layer structures formed synchronously. In other words, when preparing the display substrate, the gate electrode of the first thin film transistor and the source and drain electrode of the second thin film transistor are formed in a common one-time patterning (mask) process, without the need to prepare each of them through a mask process. This reduces one mask process, specifically, saves the time required for one mask process, and also saves the cost of materials and equipment required for one mask process, thereby improving the preparation efficiency of the display substrate on the one hand, and reducing the cost of the display substrate on the other hand.

[0054] The method for preparing a display substrate provided by an embodiment of the present invention forms the pattern of the gate electrode of the first thin film transistor and the pattern of the source and drain electrode of the second thin film transistor in the first region and the second region respectively through a single patterning process after depositing the first material layer, and only one mask process is required in the process. Compared with the solution of forming the pattern of the gate electrode of the first thin film transistor and the pattern of the source and drain electrode of the second thin film transistor respectively through a separate patterning process, which requires two mask processes, it is obvious that the method in the present invention omits one mask process when preparing the display substrate, thereby saving the time required for one mask process, and also saving the cost of materials and equipment required for one mask process, which improves the preparation efficiency of the display substrate on the one hand, and reduces the cost of the display substrate on the other hand.

[0055] The display panel provided by the embodiment of the present invention includes the above-mentioned display substrate and has the same beneficial effects as the above-mentioned display substrate, which will not be described in detail.

[0056] The display device provided by the embodiment of the present invention includes the above-mentioned display panel and has the same beneficial effects as the above-mentioned display panel, which will not be described in detail. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0058] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0059] Figure 1 A schematic diagram of the structure of a display substrate in an embodiment of the present invention;

[0060] Figure 2 for Figure 1 A schematic structural diagram of an alternative embodiment of the display substrate is shown;

[0061] Figure 3 for Figure 1 A schematic structural diagram of another alternative embodiment of the display substrate is shown;

[0062] Figure 4 for Figure 3 A schematic diagram of a second active layer in a display substrate is shown;

[0063] Figure 5 for Figure 3The schematic diagram of the second active layer and the second source-drain electrode in the display substrate is shown;

[0064] Figure 6 is a flow chart of a method for preparing a display substrate in an embodiment of the present invention;

[0065] Figure 7 A schematic diagram of preparing a substrate;

[0066] Figure 8 A schematic diagram of preparing the first active layer;

[0067] Fig. 9 A schematic diagram of preparing a gate insulating layer of a first thin film transistor;

[0068] Fig.10 A schematic diagram of preparing a first gate electrode and a second source-drain electrode;

[0069] Fig.11 A schematic diagram of preparing a first interlayer insulating layer;

[0070] Fig.12 A schematic diagram of preparing the second active layer;

[0071] Fig.13 A schematic diagram of preparing a gate insulating layer of a second thin film transistor;

[0072] Fig.14 A schematic diagram of preparing a first source-drain electrode and a second gate;

[0073] Fig.15 is a flow chart of steps for forming a pixel electrode in an embodiment of the present invention;

[0074] Fig.16 for Fig.15 A schematic diagram of the structure when a transfer layer is formed in the steps shown;

[0075] Fig.17 for Fig.15 A schematic structural diagram of a display substrate formed by the steps shown;

[0076] Fig.18 for Fig.15 A flow chart showing an alternative embodiment of the steps of forming a pixel electrode;

[0077] Fig.19 for Fig.18 A schematic structural diagram of a display substrate formed by the steps shown.

[0078] In the figure:

[0079] 10-Substrate;

[0080] 11- substrate;

[0081] 12-a first thin film transistor;

[0082] 120 - first gate electrode; 121 - first active layer; 122 - first source electrode; 123 - first drain electrode; 13 - second thin film transistor;

[0083] 130 - second gate; 131 - second active layer; 132 - second source-drain electrode; 14, 15 - gate insulating layer;

[0084] 16-a first interlayer insulating layer;

[0085] 17- a second interlayer insulating layer;

[0086] 18- transfer layer;

[0087] 19-planarization layer;

[0088] 20-pixel electrode;

[0089] 21- Common electrode. DETAILED DESCRIPTION

[0090] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0091] Embodiments of a display substrate and a method for manufacturing the same, a display panel, and a display device provided by the present invention are described below with reference to the accompanying drawings.

[0092] (1) Embodiment of display substrate

[0093] See also Figure 1 The display substrate provided in this embodiment includes a substrate 10, a substrate 11, and structures such as a first thin film transistor 12 and a second thin film transistor 13. The first thin film transistor 12 includes a gate, an active layer, and a source-drain electrode, and the second thin film transistor 13 also includes a gate, an active layer, and a source-drain electrode.

[0094] Specifically, for the sake of description, the gate, active layer and source-drain electrode of the first thin film transistor 12 are referred to as the first gate 120, the first active layer 121 and the first source-drain electrode, respectively, and the gate, active layer and source-drain electrode of the second thin film transistor 13 are referred to as the second gate 130, the second active layer 131 and the second source-drain electrode 132, respectively; wherein, the first source-drain electrode is distinguished in some descriptions as the first source 122 and the first drain 123. It can be understood that the second source-drain electrode 132 can also be distinguished as the second source and the second drain, but this is not distinguished in the description of this article, and it is collectively referred to as the second source-drain electrode 132. In addition, the above-mentioned application of "first" and "second" to the gate, active layer, source-drain electrode, source, and drain belongs to an exhaustive enumeration indicating the subordination of the first thin film transistor 12 and the second thin film transistor 13, and the first and second used before other components or structures do not indicate that they are subordinate to the first thin film transistor 12 or the second thin film transistor 13.

[0095] In this embodiment, the first gate electrode 120 and the second source-drain electrode 132 are formed in the same layer structure simultaneously. In other words, when preparing the display substrate, the first gate electrode 120 and the second source-drain electrode 132 are formed in a common one-time patterning (mask) process, and there is no need to prepare each of them through a mask process. In this way, one mask process is reduced. Specifically, the time required for one mask process is saved, and the cost of materials and equipment required for one mask process is also saved, thereby improving the preparation efficiency of the display substrate on the one hand, and reducing the cost of the display substrate on the other hand.

[0096] Specifically, the material of the first gate 120 and the second source-drain electrode 132 can be molybdenum, or a three-layer stacked structure of titanium / aluminum / titanium, etc. Taking the material of the first gate 120 and the second source-drain electrode 132 as molybdenum as an example, when preparing the first gate 120 and the second source-drain electrode 132, a molybdenum material layer is first deposited, and then the deposited molybdenum material layer is patterned by a patterning process. Specifically, the molybdenum material is retained in the area where the first gate 120 and the second source-drain electrode 132 are to be formed, and the molybdenum material is removed in other areas. The molybdenum material retained in different areas on the substrate 10 is the pattern of the first electrode or the pattern of the second source-drain electrode 132. Through the above process, the preparation of the first gate 120 and the second source-drain electrode 132 is completed by a single mask process. For the prepared first gate 120 and the second source-drain electrode 132, the two are synchronously formed in the same layer structure.

[0097] Furthermore, the first source-drain electrode and the second gate 130 are also formed in the same layer structure simultaneously. In other words, when preparing the display substrate, the first source-drain electrode and the second gate 130 are also formed in a common one-time patterning (mask) process, and there is no need to prepare them separately through a mask process, so that for the preparation of the display substrate, one more mask process can be reduced, and two mask processes are reduced as a whole, which further improves the preparation efficiency of the display substrate and further reduces the preparation cost of the display substrate.

[0098] In this embodiment, if Figure 1 As shown, the first gate 120 and the second source-drain electrode 132 are located below the first source-drain electrode and the second gate 130. However, in other embodiments of the present invention, the first gate 120 and the second source-drain electrode 132 may also be located above the first source-drain electrode and the second gate 130.

[0099] In this embodiment, the first thin film transistor 12 is a low temperature polycrystalline silicon (LTPS) thin film transistor, and the second thin film transistor 13 is an oxide thin film transistor; or, the first thin film transistor 12 is an oxide thin film transistor, and the second thin film transistor 13 is a low temperature polycrystalline silicon (LTPS) thin film transistor. For example, when the first thin film transistor 12 is a low temperature polycrystalline silicon thin film transistor and the second thin film transistor 13 is an oxide thin film transistor, the first active layer 121 is made of polycrystalline silicon, and the second active layer 131 is made of oxide, which can be specifically IGZO.

[0100] For the oxide thin film transistors in the first thin film transistor 12 and the second thin film transistor 13, they can be arranged in the display area of ​​the display substrate, and specifically, at least one oxide thin film transistor can be arranged in each sub-pixel area of ​​the display substrate. For the low-temperature polysilicon thin film transistors in the first thin film transistor 12 and the second thin film transistor 13, they can be arranged in the non-display area of ​​the display substrate, and specifically, they can be arranged in the gate drive circuit (GOA unit) in the non-display area of ​​the display substrate or connected to the GOA unit.

[0101] like Figure 1As shown, the first source-drain electrode is arranged above the first gate electrode 120, and the first active layer 121 is arranged below the first gate electrode 120; a source via and a drain via are arranged on the layer structure between the source-drain electrode of the first thin film transistor 12 and the first active layer 121, and the source of the first thin film transistor 12 is connected to the active layer of the first thin film transistor 12 through the source via, and the drain of the first thin film transistor 12 is connected to the active layer of the first thin film transistor 12 through the drain via. The second active layer 131 is arranged above the second source-drain electrode 132 and connected to the second source-drain electrode 132; the second gate electrode 130 is arranged above the second active layer 131.

[0102] Apart from Figure 1 In addition to the illustrated embodiment, in other embodiments of the present invention, the first active layer 121 may also be disposed between the first gate 120 and the first source-drain electrode.

[0103] When the first thin film transistor 12 is a low temperature polysilicon thin film transistor and the second thin film transistor 13 is an oxide thin film transistor, as Figure 2 As shown, a via hole penetrating the second active layer 131 is provided on the layer structure above the second active layer 131, and the second active layer 131 is connected to the pixel electrode 20 through the via hole. When the second thin film transistor 13 is in an on state, the second source-drain electrode 132 can transmit the voltage signal on the data line to the pixel electrode 20, and generate a voltage difference between the pixel electrode 20 and the common electrode 21 to deflect the liquid crystal molecules (when the display substrate is applied to a liquid crystal display panel), so as to realize display.

[0104] Apart from Figure 2 In addition to the embodiment shown, in other embodiments of the present invention, when the first thin film transistor 12 is a low temperature polysilicon thin film transistor and the second thin film transistor 13 is an oxide thin film transistor, it is also possible to Figure 1 As shown, a via hole penetrating the second active layer 131 is provided on the layer structure above the second active layer 131, and the second active layer 131 is connected to the transfer layer 18 connected to the pixel electrode 20 through the via hole. When the second thin film transistor 13 is in the on state, the second source-drain electrode 132 can transmit the voltage signal on the data line to the transfer layer 18, and transmit it to the pixel electrode 20 through the transfer layer 18, and generate a voltage difference between the pixel electrode 20 and the common electrode 21 to deflect the liquid crystal molecules (when the display substrate is applied to a liquid crystal display panel) for display. Specifically, the material of the transfer layer 18 can be selected as a transparent material, such as ITO (indium tin oxide); the transfer layer 18 formed of a transparent material, such as an ITO transfer layer 18, can be light-transmissive in the transfer layer 18 area compared to the transfer layer 18 formed of other non-transparent materials, thereby increasing the aperture ratio of the display substrate.

[0105] Apart from Figure 1 and Figure 2 In addition to the embodiment shown, in other embodiments of the present invention, when the first thin film transistor 12 is a low temperature polysilicon thin film transistor and the second thin film transistor 13 is an oxide thin film transistor, it is also possible to Figure 3 and Figure 4 As shown, a partial area of ​​the second active layer 131 is a conductive semiconductor layer that has been subjected to a conductive treatment, and the conductive semiconductor layer serves as the pixel electrode 20. After the partial area of ​​the second active layer 131 is subjected to a conductive treatment, the partial conductive semiconductor layer has the characteristics of a conductor and can be used for the conduction of electrical signals. It can generate a voltage difference with the common electrode 21, and thus can serve as the pixel electrode 20. Conductive treatment of semiconductor materials is a known process in the prior art, and this embodiment will not be described in detail. Compared with the above-mentioned solution of connecting the second active layer 131 and the pixel electrode 20 or the transfer layer 18, the solution of conducting a partial area of ​​the second active layer 131 and using the conductive semiconductor layer obtained after the treatment as the pixel electrode 20 can save multiple process flows, such as forming the transfer layer 18, the pixel electrode 20 and the via, thereby helping to simplify the process and reduce costs.

[0106] Specifically, the material of the second active layer 131 can be selected as IGZO. When the second active layer 131 is selected as IGZO or other materials, the material of the first interlayer insulating layer 16 is selected as silicon oxide. The reason is that when the second interlayer insulating layer 17 is prepared with common silicon nitride, the second interlayer insulating layer 17 will make the second thin film transistor 13 whose second active layer 131 is IGZO present the characteristic of conductorization. Therefore, the first interlayer insulating layer 16 is not prepared with silicon nitride, but silicon oxide is selected to prepare the first interlayer insulating layer 16.

[0107] When the first thin film transistor 12 is an oxide thin film transistor and the second thin film transistor 13 is a low temperature polysilicon thin film transistor, the first active layer 121 of the first thin film transistor 12 can be similar to Figure 2 In the second active layer 131, a via hole penetrating to the first active layer 121 is provided on the layer structure above the first active layer 121, and the first active layer 121 is connected to the pixel electrode 20 through the via hole. Or, similarly Figure 1 In the second active layer 131, a via hole penetrating the first active layer 121 is provided on the layer structure above the first active layer 121, and the first active layer 121 is connected to the switching layer 18 connected to the pixel electrode 20 through the via hole. Or, similarly Figure 3 The second active layer 131 in the first active layer 121 is partially a conductive semiconductor layer that has been subjected to a conductive treatment, and the conductive semiconductor layer serves as the pixel electrode 20 .

[0108] Figure 1 , Figure 2 and Figure 3 The second thin film transistor 13 shown is a vertical thin film transistor. In this embodiment, when one of the first thin film transistor 12 and the second thin film transistor 13 is an oxide thin film transistor, the structure of the oxide thin film transistor can be selected as follows: Figure 1 , Figure 2 and Figure 3 The structure of the second thin film transistor 13 shown or other vertical thin film transistor structures. The vertical thin film transistor occupies a small size on the display substrate. The oxide thin film transistor in the display area of ​​the display substrate, for example, one or more oxide thin film transistors in each sub-pixel area, is set as the above-mentioned vertical thin film transistor, which can reduce the area occupied by the oxide thin film transistor in each sub-pixel area of ​​the display substrate and in the overall display area, thereby improving the aperture ratio of the display substrate.

[0109] In this embodiment, when an oxide thin film transistor is provided on the display substrate and the oxide thin film transistor is a vertical thin film transistor, a first interlayer insulating layer 16 is provided above the source and drain electrodes of the oxide thin film transistor, and a via is provided on the first interlayer insulating layer 16, and the active layer of the oxide thin film transistor is connected to the source and drain electrodes of the oxide thin film transistor through the via on the first interlayer insulating layer 16. For example Figure 1 , Figure 2 and Figure 3 As shown in , a first interlayer insulating layer 16 is arranged above the second source-drain electrode 132, and a via is arranged on the first interlayer insulating layer 16, and the second active layer 131 is connected to the second source-drain electrode 132 through the via on the first interlayer insulating layer 16. It can be seen that the active layer of the oxide thin film transistor is not a planar structure, and a part of its area is connected to the source-drain electrode of the oxide thin film transistor through the via in the first interlayer insulating layer 16. In this case, the active layer of the oxide thin film transistor needs to climb at the via in the first interlayer insulating layer 16, and also needs to cross the data line connected to the source-drain electrode of the oxide thin film transistor to connect to the opening area of ​​the display substrate (for connection with the pixel electrode 20, or connection with the transfer layer 18, or as the pixel electrode 20 after conductorization, etc.). In this embodiment, the slope of the edge of the data line connected to the source and drain electrodes of the oxide thin film transistor is set to be less than 70 degrees, and the slope of the via hole in the first interlayer insulating layer 16 is set to be in the range of 45 to 70 degrees. This facilitates the formation of a good active layer morphology at the edge of the data line connected to the source and drain electrodes of the oxide thin film transistor and at the via hole in the first interlayer insulating layer 16 when preparing the active layer of the oxide thin film transistor, thereby avoiding problems such as broken wires due to excessive slopes.

[0110] like Figure 5 As shown, the second thin film transistor 13 is an oxide thin film transistor, and the projection of the effective channel region in the second active layer 131 on the second source-drain electrode 132 is located within the second source-drain electrode 132 and the data line connected to the second source-drain electrode 132 (hereinafter collectively referred to as the second source-drain electrode 132). That is, the effective channel region of the second active layer 131 overlaps and corresponds to the second source-drain electrode 132 in a direction perpendicular to the display substrate. As the active layer of the oxide thin film transistor, the second active layer 131 is sensitive to light. When irradiated by light, it will cause the negative bias temperature illumination stability (Negative Bias Temperature Illumination Stress, referred to as NBTIS) of the oxide thin film transistor to be poor. Under the effect of NBTIS stress, the threshold voltage of the oxide thin film transistor will have a large negative drift, and then the afterimage problem will occur during the display process. In this embodiment, the second active layer 131 is arranged above the second source-drain electrode 132 and overlaps with the second source-drain electrode 132 correspondingly in the direction perpendicular to the display substrate. The second source-drain electrode 132 can block the light irradiated from below to the second active layer 131 in the data line direction (generally the longitudinal direction of the display substrate), and can provide a good shading effect for the second active layer 131, thereby ensuring that the second thin film transistor 13 has good NBTIS performance.

[0111] Specifically, Figure 5 As shown, the distance L between the edge of the second source-drain electrode 132 and the edge of the projection of the effective channel region of the second active layer 131 on the second source-drain electrode 132 is in the range of 0 to 2 microns. That is, the second source-drain electrode 132 can vertically (perpendicular to the display substrate) wrap and shield the effective channel region of the second active layer 131, and on this basis, the second source-drain electrode 132 can also have a wider additional width of no more than 2 microns to better ensure the shielding and wrapping of the effective channel region of the second active layer 131.

[0112] In this embodiment, see for example Figure 1 The gate electrode of the low temperature polysilicon thin film transistor and the source and drain electrode of the oxide thin film transistor have a thickness ranging from 1000 to 5000 angstroms. The thickness of the first interlayer insulating layer 16 is 1000 to 6000 angstroms.

[0113] In summary, the display substrate provided by the present invention has a first gate electrode 120 and a second source-drain electrode 132 that are formed synchronously in the same layer. In other words, when preparing the display substrate, the first gate electrode 120 and the second source-drain electrode 132 are formed in a common one-time patterning (mask) process, and there is no need to prepare each of them through a one-time mask process. This reduces one mask process, specifically, saves the time required for one mask process, and also saves the cost of materials and equipment required for one mask process, thereby improving the preparation efficiency of the display substrate on the one hand, and reducing the cost of the display substrate on the other hand.

[0114] (2) Example of a method for preparing a display substrate

[0115] In this embodiment, the method for preparing the display substrate includes the following steps S1 to S9: Figure 6 shown.

[0116] Step S1, providing a substrate 10, forming a pattern of a substrate 11 on the substrate 10, such as Figure 7 shown.

[0117] Specifically, in step S1, the substrate 10 may be a glass substrate 10. The substrate 11 may be a double-layer stacked structure, wherein the materials of the double-layer structure are silicon nitride and silicon oxide, wherein the silicon nitride layer is at the bottom and directly connected to the substrate 10, and the silicon oxide layer may be formed on the silicon nitride layer. The thickness of the formed silicon nitride layer may be 500 to 1000 angstroms, and the thickness of the formed silicon oxide layer may be 2000 to 4000 angstroms.

[0118] Step S2, forming a pattern of the active layer of the first thin film transistor 12, such as Figure 8 shown.

[0119] In step S2, specifically, the first thin film transistor 12 may be a low temperature polysilicon thin film transistor. When the first thin film transistor 12 is a low temperature polysilicon thin film transistor, forming the pattern of the active layer of the first thin film transistor 12 may specifically include: first depositing an amorphous silicon layer (aSi); then, waiting for the amorphous silicon layer to crystallize, and after the amorphous silicon layer is crystallized, performing a patterning process on it to form the following: Figure 8 The structure shown.

[0120] When the first thin film transistor 12 is a low temperature polysilicon thin film transistor, it can be used in a gate drive circuit (GOA) of a display substrate. If the first thin film transistor 12 is a low temperature polysilicon thin film transistor for GOA, in step S2, when the crystallized amorphous silicon is patterned, the crystallized amorphous silicon material is retained in the GOA region in the non-display region on the display substrate, and the crystallized amorphous silicon material is removed in other regions, especially the display region of the display substrate, to form a gate drive circuit (GOA) of the display substrate. Figure 8 The graphic shown.

[0121] Step S3, forming a pattern of the gate insulating layer 14 of the first thin film transistor 12, such as Fig. 9 shown.

[0122] After the step S3 is performed and the pattern of the gate insulating layer 14 of the first thin film transistor 12 is prepared, the structure formed is as follows: Fig. 9 shown.

[0123] Step S4, depositing a first material layer on the substrate 10, and forming a pattern of a gate electrode of the first thin film transistor 12 in a first region of the substrate 10 by a patterning process, and forming a pattern of a source and drain electrode of the second thin film transistor 13 in a second region of the substrate 10, such as Fig.10 shown.

[0124] Specifically, the pattern of the active layer of the first thin film transistor 12 formed in step S2 is located in the first region. In step S4, the pattern of the gate of the first thin film transistor 12 is continuously formed in the first region, and the pattern of the source and drain electrode of the second thin film transistor 13 is formed in another region, that is, the second region.

[0125] In this embodiment, the so-called "first region" and "second region" refer to the region of the first thin film transistor 12 to be formed and the region of the second thin film transistor 13 to be formed, respectively, rather than the region of a certain structure in the first thin film transistor 12 or the second thin film transistor 13. For example, forming the pattern of the gate of the first thin film transistor 12 in the first region means that the pattern of the gate of the first thin film transistor 12 is formed in the first region, and does not mean that the region where the pattern of the gate of the first thin film transistor 12 is formed is the complete first region.

[0126] In step S4, the material of the first material layer may be a single material, such as molybdenum, etc. In addition, the first material layer may also include multiple materials, that is, the first material layer is multi-layered, and the multi-layered materials form a stacked structure; specifically, when the first material layer is a multi-layered stacked structure, it may include a titanium layer, an aluminum layer and a titanium layer (Ti / Al / Ti) three-layer structure.

[0127] When the first material layer is formed by deposition, the thickness of the deposited first material layer ranges from 1000 to 5000 angstroms.

[0128] The "depositing a first material layer on the substrate 10" mentioned in step S4 includes two situations: the first situation is that the first material layer is directly formed on the substrate 10 and the substrate 11 (usually on the substrate 11), and there is no other layer structure between the first material layer and the substrate 10 and the substrate 11 (usually between the substrate 11); the second situation is that before depositing the first material layer, the step of forming other layer structures has been carried out, and the first material layer is deposited and formed on other layer structures, and there are other layer structures between the first material layer and the substrate 10 and the substrate 11. As mentioned in the above steps S2 and S3, in this embodiment, it belongs to the second situation; but it should be noted that in other embodiments of the present invention, or when preparing the first thin film transistor 12 and the second thin film transistor 13 of other structures, it can also be the first situation mentioned above.

[0129] In step S4, after the first material layer is formed by deposition, the pattern of the gate electrode of the first thin film transistor 12 and the pattern of the source and drain electrode of the second thin film transistor 13 are formed in the first region and the second region respectively through a patterning process, and only one mask process is required in the process. Compared with the solution of forming the pattern of the gate electrode of the first thin film transistor 12 and the pattern of the source and drain electrode of the second thin film transistor 13 respectively through a separate patterning process, which requires two mask processes, it is obvious that the method in this embodiment saves one mask process when preparing the display substrate, thereby saving the time required for one mask process, and also saving the cost of materials and equipment required for one mask process, which improves the preparation efficiency of the display substrate on the one hand, and reduces the cost of the display substrate on the other hand.

[0130] Step S5, forming a pattern of the first interlayer insulating layer 16, and forming a via hole in the second area.

[0131] Specifically, in step S5, an insulating material is deposited on the pattern of the gate electrode of the first thin film transistor 12 and the pattern of the source and drain electrode of the second thin film transistor 13 to form a first interlayer insulating layer 16. Fig.11 and forming a via hole penetrating the first interlayer insulating layer 16 in the second region by a patterning process, wherein the lower end of the via hole is connected to the source and drain electrode of the second thin film transistor 13.

[0132] The first interlayer insulating layer 16 may be a single-layer structure or a multi-layer stacked structure. When the first interlayer insulating layer 16 is a single-layer structure, it may be silicon oxide or silicon nitride; when the first interlayer insulating layer 16 is a multi-layer stacked structure, it may include a silicon oxide layer and a silicon nitride layer.

[0133] In this embodiment, the second thin film transistor 13 may be an oxide thin film transistor. When the second thin film transistor 13 is an oxide thin film transistor, especially when the active layer of the second thin film transistor 13 is IGZO, the first interlayer insulating layer 16 is specifically selected to be a single layer structure of silicon oxide, or a stacked structure of a silicon oxide layer and a silicon nitride layer, rather than a single layer structure of silicon nitride. The reason is that the first interlayer insulating layer 16 made of silicon nitride material will contact the active layer of the second thin film transistor 13 (such as Fig.12 As shown), the contact between the two will cause the second thin film transistor 13 to have a conductive characteristic, which is not conducive to the normal operation of the second thin film transistor 13.

[0134] Specifically, in step S5 , the thickness of the formed first interlayer insulating layer 16 is 1000 to 6000 angstroms.

[0135] Step S6, forming a pattern of an active layer of a second thin film transistor 13 in the second region, such as Fig.12 shown.

[0136] After the pattern of the active layer of the second thin film transistor 13 is formed in the second region, the pattern of the active layer of the second thin film transistor 13 is connected to the source and drain electrodes of the second thin film transistor 13 through the via holes on the first interlayer insulating layer 16. Fig.12 shown.

[0137] Specifically, the second thin film transistor 13 may be an oxide thin film transistor, and the material of its active layer may be IGZO. When the second thin film transistor 13 is an oxide thin film transistor, and the material of its active layer is IGZO, in step S6, the IGZO material is deposited and patterned to obtain Fig.12 The pattern of the active layer of the second thin film transistor 13 is shown.

[0138] Specifically, when depositing IGZO material, the selected target material may be a target material of In:Ga:Zn=1:1:1, or an oxide material with other ratios of the three, or an oxide material with other components.

[0139] Step S7 , forming a pattern of the gate insulating layer 15 of the second thin film transistor 13 .

[0140] After the step S7 is performed and the pattern of the gate insulating layer 15 of the second thin film transistor 13 is prepared, the structure formed is as follows: Fig.13 shown.

[0141] Step S8, depositing a second material layer, and forming a pattern of a source and drain electrode of the first thin film transistor 12 in the first region of the substrate 10 by a patterning process, and forming a pattern of a gate electrode of the second thin film transistor 13 in the second region of the substrate 10, such as Fig.14 shown.

[0142] Specifically, in step S8, after the second material layer is formed by deposition, the pattern of the source and drain electrodes of the first thin film transistor 12 and the pattern of the gate electrode of the second thin film transistor 13 are formed in the first region and the second region respectively through a single patterning process, and only one mask process is required in the process. Compared with the solution of forming the pattern of the source and drain electrodes of the first thin film transistor 12 and the pattern of the gate electrode of the second thin film transistor 13 through separate patterning processes, which requires two mask processes, it is obvious that the method in this embodiment saves one mask process when preparing the display substrate, thereby saving the time required for one mask process, and also saving the cost of materials and equipment required for one mask process, which improves the preparation efficiency of the display substrate on the one hand, and reduces the cost of the display substrate on the other hand.

[0143] In this embodiment, one of the first thin film transistor 12 and the second thin film transistor 13 may be an oxide thin film transistor, which may be arranged in the display area of ​​the display substrate, for example, one or more may be arranged in each sub-pixel area, for connecting to the pixel electrode 20 and transmitting a voltage signal to the pixel electrode 20; and the other may be a low-temperature polycrystalline silicon thin film transistor, which is formed in the non-display area of ​​the display substrate, for connecting to the gate drive circuit (GOA) of the display substrate.

[0144] In the following step S9 , the subsequent steps of the method for preparing the display substrate are described by taking the second thin film transistor 13 as an oxide thin film transistor, which is disposed in the display area of ​​the display substrate and is used to connect to the pixel electrode 20 as an example.

[0145] Step S9 , forming a pattern of the pixel electrode 20 connected to the source and drain electrodes of the second thin film transistor 13 .

[0146] Specifically, step S9 may include the following steps S9a1 to S9a5: Fig.15 shown.

[0147] Step S9a1, depositing insulating material to form a second interlayer insulating layer 17, such as Fig.16 shown.

[0148] Step S9a2, forming a via hole penetrating the second interlayer insulating layer 17 and connecting the lower end of the via hole to the second active layer 131 in the region of the second thin film transistor 13 by a patterning process, such as Fig.16 shown.

[0149] Specifically, in step S9 a 2 , the via hole penetrates the second interlayer insulating layer 17 and the gate insulating layer of the second thin film transistor 13 , so that the lower end of the via hole is connected to the second active layer 131 .

[0150] Step S9a3, forming a pattern of a switching layer 18 in the region of the second thin film transistor 13, the pattern of the switching layer 18 is connected to the second active layer 131 through a via hole penetrating the second interlayer insulating layer 17, such as Fig.16 shown.

[0151] In step S9a3, the material of the transfer layer 18 can be selected as a transparent material, such as ITO, etc. Compared with the transfer layer 18 formed of a non-transparent material, the transfer layer 18 formed of a transparent material can increase the area of ​​the light-transmitting region of the display substrate, thereby improving the aperture ratio of the display substrate.

[0152] Step S9a4, forming a pattern of the planarization layer 19, and forming a via hole penetrating the planarization layer 19 in the region of the second thin film transistor 13 by a patterning process, wherein the lower end of the via hole is connected to the transfer layer 18, such as Fig.17 shown.

[0153] Step S9a5, forming a pattern of the pixel electrode 20, the pattern of the pixel electrode 20 is connected to the transfer layer 18 through the via hole on the planarization layer 19, such as Fig.17 shown.

[0154] After completing step S9a5, the prepared pixel electrode 20 is connected to the transfer layer 18 through the via hole in the planarization layer 19, and the transfer layer 18 is connected to the second active layer 131 through the via hole formed in the second interlayer insulating layer 17 and the gate insulating layer of the second thin film transistor 13, thereby finally achieving connection with the second source-drain electrode 132.

[0155] Specifically, as an alternative, in other embodiments of the present invention, step S9 may also include the following steps S9b1 to S9b3: Fig.18 shown.

[0156] Step S9b1, depositing insulating material to form a second interlayer insulating layer 17.

[0157] Step S9b2: forming a via hole penetrating the second interlayer insulating layer 17 and connecting the lower end of the via hole to the second active layer 131 in the region of the second thin film transistor by a patterning process.

[0158] Specifically, in step S9 b 2 , the via hole penetrates the second interlayer insulating layer 17 and the gate insulating layer 15 of the second thin film transistor 13 , so that the lower end of the via hole is connected to the second active layer 131 .

[0159] Step S9b3, forming a pattern of the pixel electrode 20, the pattern of the pixel electrode 20 is connected to the second active layer 131 through a via hole penetrating the second interlayer insulating layer 17, such as Fig.19 shown.

[0160] After completing step S9b3 , the prepared pixel electrode 20 is connected to the second active layer 131 through via holes formed in the second interlayer insulating layer 17 and the gate insulating layer of the second thin film transistor 13 , and finally connected to the second source-drain electrode 132 .

[0161] Specifically, as an alternative, in other embodiments of the present invention, step S9 includes:

[0162] Conductivity treatment is performed on a partial area of ​​the second active layer 131 , so that the conductive portion of the second active layer 131 can be used as the pixel electrode 20 .

[0163] Specifically, conducting the semiconductor material is a known process in the prior art, and will not be described in detail in this embodiment. Compared with the embodiment of steps S9a1 to S9a5, or compared with the embodiment of steps S9b1 to S9b3, this alternative embodiment conducts a conductor process on a portion of the second active layer 131, and uses the conductorized semiconductor layer obtained after the process as the pixel electrode 20, which can save multiple process flows, such as forming the transfer layer 18, the pixel electrode 20 and the via hole, thereby helping to simplify the process and reduce costs.

[0164] Through the above steps S1 to S9, the method for preparing a display substrate provided in this embodiment can prepare Figure X Furthermore, since one mask process is omitted in each of step S4 and step S8, in this embodiment, the time required for two mask processes can be saved, and the cost of materials and equipment required for the two mask processes can also be saved, which improves the preparation efficiency of the display substrate on the one hand, and reduces the cost of the display substrate on the other hand.

[0165] In the above steps S1 to S9, the description is generally carried out based on the first thin film transistor 12 being a low-temperature polycrystalline silicon thin film transistor and the second thin film transistor 13 being an oxide thin film transistor. However, in fact, the first thin film transistor 12 may also be an oxide thin film transistor or other types of thin film transistors, and the second thin film transistor 13 may also be a low-temperature polycrystalline silicon thin film transistor or other types of thin film transistors.

[0166] It should be noted that, in terms of the implementation of the present invention, changes can be made based on the above embodiments. For example, other steps except step S4 can be changed to obtain different technical effects, and to obtain a display substrate having different structures of the first thin film transistor 12 and the second thin film transistor 13.

[0167] For example, step S8 can be transformed. In step S8, the source and drain electrodes of the first thin film transistor 12 and the gate of the second thin film transistor 13 can be formed separately. In this way, as far as the basic preparation method of the display is concerned, the technical effect that can be achieved is to reduce the mask process once. Correspondingly, the improvement in the preparation efficiency of the display substrate is small, and the reduction in the preparation cost of the display substrate is small.

[0168] For another example, steps S2 and S3 may be transformed, and the patterns of the active layer and gate insulating layer of the first thin film transistor 12 are not prepared before the pattern of the gate of the first thin film transistor 12 is formed. The following steps may be performed after the patterns of the gate of the first thin film transistor 12 and the source-drain electrode of the second thin film transistor 13 are formed in step S4, and before the patterns of the source-drain electrode of the first thin film transistor 12 and the gate of the second thin film transistor 13 are formed in step S8: forming the pattern of the gate insulating layer of the first thin film transistor 12; forming the pattern of the active layer of the first thin film transistor 12; and forming the pattern of the first interlayer insulating layer 16. Thus, different structures of the first thin film transistor 12 and the display substrate having the structure are obtained.

[0169] In summary, the method for preparing a display substrate provided by the present invention forms the pattern of the gate electrode of the first thin film transistor 12 and the pattern of the source and drain electrode of the second thin film transistor 13 in the first region and the second region respectively through a single patterning process after the first material layer is deposited, and only one mask process is required in the process. Compared with the solution of forming the pattern of the gate electrode of the first thin film transistor 12 and the pattern of the source and drain electrode of the second thin film transistor 13 respectively through a separate patterning process, which requires two mask processes, it is obvious that the method in the present invention saves one mask process when preparing the display substrate, thereby saving the time required for one mask process, and also saving the cost of materials and equipment required for one mask process, which improves the preparation efficiency of the display substrate on the one hand, and reduces the cost of the display substrate on the other hand.

[0170] (3) Embodiment of display panel

[0171] In this embodiment, the display panel includes the display substrate described in the above embodiment of the display substrate.

[0172] The display substrate provided in this embodiment includes the display substrate described in the above embodiment, and has the same beneficial effects as the display substrate in the above embodiment, which will not be described in detail.

[0173] (4) Embodiments of display device

[0174] In this embodiment, the display device includes the display panel described in the above embodiment of the display panel.

[0175] The display device provided in this embodiment includes the display panel described in the above embodiment, and has the same beneficial effects as the display panel in the above embodiment, which will not be described in detail.

[0176] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0177] The foregoing is merely a specific embodiment of the present invention, which enables those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A display substrate, characterized in that: The display substrate includes a first thin film transistor and a second thin film transistor; The gate electrode of the first thin film transistor and the source and drain electrode of the second thin film transistor are synchronously formed in the same layer structure; The source and drain electrodes of the first thin film transistor and the gate electrode of the second thin film transistor are synchronously formed in the same layer structure; The first thin film transistor is a low temperature polysilicon thin film transistor, and the second thin film transistor is an oxide thin film transistor; or The first thin film transistor is an oxide thin film transistor, and the second thin film transistor is a low temperature polysilicon thin film transistor; A via hole penetrating the active layer of the oxide thin film transistor is provided on the layer structure above the active layer of the oxide thin film transistor, and the active layer of the oxide thin film transistor is connected to the pixel electrode through the via hole; or A via hole penetrating the active layer of the oxide thin film transistor is provided on the layer structure above the active layer of the oxide thin film transistor, and the active layer of the oxide thin film transistor is connected to the switching layer connected to the pixel electrode through the via hole; or A partial area of ​​the active layer of the oxide thin film transistor is a conductive semiconductor layer that has been subjected to a conductive treatment, and the conductive semiconductor layer serves as a pixel electrode.

2. The display substrate according to claim 1, characterized in that: The gate electrode of the first thin film transistor and the source-drain electrode of the second thin film transistor are located above or below the source-drain electrode of the first thin film transistor and the gate electrode of the second thin film transistor.

3. The display substrate according to claim 2, characterized in that: The source and drain electrodes of the first thin film transistor are arranged above the gate of the first thin film transistor, and the active layer of the first thin film transistor is arranged below the gate of the first thin film transistor or between the gate of the first thin film transistor and the source and drain electrodes of the first thin film transistor; A source via and a drain via are provided on the layer structure between the source and drain electrodes of the first thin film transistor and the active layer of the first thin film transistor, the source of the first thin film transistor is connected to the active layer of the first thin film transistor through the source via, and the drain of the first thin film transistor is connected to the active layer of the first thin film transistor through the drain via; The active layer of the second thin film transistor is arranged above the source and drain electrodes of the second thin film transistor and is connected to the source and drain electrodes of the second thin film transistor; the gate of the second thin film transistor is arranged above the active layer of the second thin film transistor.

4. The display substrate according to claim 1, characterized in that: The slope of the edge of the data line connected to the source and drain electrodes of the oxide thin film transistor is less than 70 degrees.

5. The display substrate according to claim 1, characterized in that: A first interlayer insulating layer is disposed above the source and drain electrodes of the oxide thin film transistor. A via is disposed on the first interlayer insulating layer. The active layer of the oxide thin film transistor is connected to the source and drain electrodes of the oxide thin film transistor through the via on the first interlayer insulating layer.

6. The display substrate according to claim 5, characterized in that: The slope of the via hole in the first interlayer insulating layer ranges from 45 to 70 degrees.

7. The display substrate according to claim 1, characterized in that: The material of the active layer of the oxide thin film transistor is IGZO.

8. The display substrate according to claim 5, characterized in that: The material of the first interlayer insulating layer is silicon oxide.

9. The display substrate according to claim 2, characterized in that: The low-temperature polysilicon thin film transistor is arranged in the non-display area of ​​the display substrate and is connected to the gate driving circuit in the non-display area; The oxide thin film transistor is disposed in a display area of ​​the display substrate, and at least one oxide thin film transistor is disposed in each sub-pixel in the display area of ​​the display substrate.

10. The display substrate according to claim 2, characterized in that: A projection of an effective channel region in the active layer of the oxide thin film transistor on the source and drain electrodes of the oxide thin film transistor is located within the source and drain electrodes of the oxide thin film transistor.

11. The display substrate according to claim 10, characterized in that: The distance between the edge of the source-drain electrode of the oxide thin film transistor and the edge of the projection of the effective channel region on the source-drain electrode of the oxide thin film transistor is 0-2 micrometers.

12. The display substrate according to claim 2, characterized in that: The thickness of the gate electrode of the low-temperature polysilicon thin film transistor and the source and drain electrode of the oxide thin film transistor ranges from 1000 to 5000 angstroms.

13. The display substrate according to claim 5, characterized in that: The thickness of the first interlayer insulating layer is 1000-6000 angstroms.

14. A method for preparing a display substrate, characterized in that: The method for preparing the display substrate comprises: Depositing a first material layer on a substrate, and forming a pattern of a gate electrode of a first thin film transistor in a first region of the substrate through a patterning process, and forming a pattern of a source and drain electrode of a second thin film transistor in a second region of the substrate; The method for preparing the display substrate further includes: Depositing a second material layer, and forming a pattern of a source and drain electrode of a first thin film transistor in a first region of the substrate through a patterning process, and forming a pattern of a gate electrode of a second thin film transistor in a second region of the substrate; The first thin film transistor is a low temperature polysilicon thin film transistor, and the second thin film transistor is an oxide thin film transistor; or The first thin film transistor is an oxide thin film transistor, and the second thin film transistor is a low temperature polysilicon thin film transistor; The method for preparing the display substrate further comprises, after forming the pattern of the source and drain electrodes of the first thin film transistor and the pattern of the gate electrode of the second thin film transistor: depositing an insulating material to form a second interlayer insulating layer; A via hole is formed in the region where the oxide thin film transistor is located by a patterning process, the via hole penetrating the second interlayer insulating layer and having a lower end connected to the active layer of the oxide thin film transistor; forming a pattern of a transfer layer in the region of the oxide thin film transistor, wherein the pattern of the transfer layer is connected to the active layer of the oxide thin film transistor through a via hole penetrating through the second interlayer insulating layer; Forming a pattern of the planarization layer, and forming a via hole penetrating the planarization layer in the region of the oxide thin film transistor by a patterning process, wherein the lower end of the via hole is connected to the transfer layer; forming a pattern of a pixel electrode, wherein the pattern of the pixel electrode is connected to the transfer layer through a via hole on the planarization layer; or depositing an insulating material to form a second interlayer insulating layer; Forming a via hole penetrating the second interlayer insulating layer in the region of the oxide thin film transistor by a patterning process, the via hole having a lower end connected to the active layer of the oxide thin film transistor; forming a pattern of a pixel electrode, wherein the pattern of the pixel electrode is connected to the active layer of the oxide thin film transistor through a via hole penetrating through the second interlayer insulating layer; or Conductive processing is performed on a partial area of ​​the active layer of the oxide thin film transistor, so that the conductive part of the active layer of the oxide thin film transistor can be used as a pixel electrode.

15. The method for preparing a display substrate according to claim 14, characterized in that: The area where the low-temperature polysilicon thin film transistor is formed is a non-display area of ​​the display substrate, and the formed low-temperature polysilicon thin film transistor is connected to a gate driving circuit of the display substrate; Each sub-pixel region on the display substrate has at least one region where the oxide thin film transistor is formed.

16. The method for preparing a display substrate according to claim 14, characterized in that: The method for preparing the display substrate further includes, before forming the patterns of the gate electrode of the first thin film transistor and the source and drain electrode of the second thin film transistor: forming a pattern of an active layer of a first transistor; A gate insulating layer of the first transistor is patterned.

17. The method for preparing a display substrate according to claim 14, characterized in that: The method for preparing the display substrate further includes, after forming the pattern of the gate electrode of the first thin film transistor and the pattern of the source and drain electrode of the second thin film transistor, and before forming the pattern of the source and drain electrode of the first thin film transistor and the pattern of the gate electrode of the second thin film transistor: forming a pattern of a gate insulating layer of a first transistor; forming a pattern of an active layer of a first transistor; An interlayer insulating layer is patterned.

18. The method for preparing a display substrate according to claim 14, characterized in that: The method for preparing the display substrate further includes, after forming the pattern of the gate electrode of the first thin film transistor and the pattern of the source-drain electrode of the second thin film transistor, and before forming the pattern of the source-drain electrode of the first thin film transistor and the pattern of the gate electrode of the second thin film transistor: Depositing an insulating material on the pattern of the gate electrode of the first thin film transistor and the pattern of the source and drain electrode of the second thin film transistor to form a first interlayer insulating layer, and forming a via hole penetrating the first interlayer insulating layer in the second region by a patterning process, wherein the lower end of the via hole is connected to the source and drain electrode of the second thin film transistor; forming a pattern of an active layer of a second thin film transistor in the second region, wherein the pattern of the active layer of the second thin film transistor is connected to a source-drain electrode of the second thin film transistor through a via hole on the first interlayer insulating layer; A pattern of a gate insulating layer of the second thin film transistor is formed.

19. A display panel, characterized in that: The display panel includes the display substrate according to any one of claims 1 to 13.

20. A display device, characterized in that: The display device comprises the display panel according to claim 19.

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