Gallium Oxide Field Effect Transistor

Abstract

The present invention belongs to the technical field of semiconductor devices, and discloses a gallium oxide field effect transistor with a vertical structure, and the gallium oxide field effect transistor has an enhanced structure. In the field effect transistor structure design, the present invention uses the depletion region generated by the heterogeneous pn junction composed of a p-type material layer and a gallium oxide drift layer to close a part of the conductive channel, thereby forming a normally-off device; and a second gallium oxide drift layer grown by homoepitaxial growth on a first gallium oxide drift layer and a gallium oxide layer grown by homoepitaxial growth on a gallium oxide insulating layer can reduce the power loss of the gallium oxide field effect transistor and improve reliability.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and in particular relates to a gallium oxide field effect transistor with a vertical structure. The gallium oxide field effect transistor has an enhanced structure. Background Art

[0002] Gallium oxide (Ga 2 O 3 ) is a semiconductor material with an ultra-wide bandgap, with a bandgap width between 4.7 and 5.3 eV, and has outstanding advantages in terms of breakdown field strength, on-resistance, Baliga figure of merit and cost. It can be used to make high-performance power electronic devices, ultraviolet sensors, photodetectors, etc., and has a wide range of promising applications.

[0003] Gallium oxide (Ga 2 O 3 ) substrate can be prepared by melt growth method, with low manufacturing cost and high crystal quality, and successful reports of 6-inch large-size wafers have been reported. 2 O 3 ) has also been well and controllably doped. With its ultra-wide bandgap, Ga 2 O 3 The theoretical critical field strength is as high as 8MV / cm, which is 20 times that of silicon (Si) and more than twice that of silicon carbide (SiC) and gallium nitride (GaN). 2 O 3 It has significant advantages in the field of power semiconductors and can produce power devices with higher voltage resistance and smaller size.

[0004] However, gallium oxide (Ga 2 O 3 ) also has some thorny problems, such as the large effective hole mass and high acceptor activation energy of its p-type doping, and the p-type doping problem has not been solved. Due to the existence of this problem, the development of devices such as MOSFET has been greatly restricted.

[0005] At present, there are reported Ga 2 O 3 There are three main types of vertical MOS devices. The first type is Ga with a current blocking layer. 2 O 3 Vertical MOSFET, the second type is Ga with a p-type metal oxide current blocking layer 2 O 3 Vertical MOSFET, the third type is fin-gate Ga 2 O 3 Vertical MOSFET.

[0006] The first type is Ga with a current blocking layer 2 O 3 Vertical MOSFET, as shown in the attached Figure 1 As shown, its structure includes: heavily doped n-type Ga 2 O 3 Substrate, grown on Ga 2 O 3 Lightly doped n-type Ga on substrate 2 O 3 Drift layer, N-implanted n-type Ga on both sides of the drift layer 2 O 3 The current blocking layer is a heavily doped n-type Ga 2 O 3 Channel layer, Ga 2 O 3 The drain on the back of the substrate, Ga 2 O 3 The source on the channel layer is set on Ga 2 O 3 The gate dielectric on the substrate channel layer and the gate electrode arranged on the gate dielectric layer. The current blocking layer of the device is an n-type Ga implanted by N. 2 O 3 The current will flow laterally along the channel through the current aperture area and then vertically toward the drain.

[0007] The first type of structural design has many advantages, such as it is a vertical device and the size can be made relatively smaller; however, the device of this structural design is a normally-on (depletion-type) device and needs to be used in conjunction with a normally-off (enhancement-type) MOS tube.

[0008] The second type is Ga with a p-type metal oxide current blocking layer. 2 O 3 Vertical MOSFET, as shown in the attached Figure 2 As shown, its structure includes: heavily doped n-type Ga 2 O 3 Substrate, grown on Ga 2 O 3 Lightly doped n-type Ga on substrate 2 O 3 Drift layer, p-type metal oxide current blocking layers on both sides of the drift layer, heavily doped n-type Ga 2 O 3 Channel layer, Ga 2 O 3 The drain on the back of the substrate, Ga 2 O 3 The source on the channel layer is set on Ga2 O 3 The gate dielectric on the substrate channel layer, and the gate electrode on the gate dielectric layer. The current blocking layer of the device is a p-type doped metal oxide material, and the metal oxide material is any one of nickel oxide, tin oxide, cuprous oxide, tungsten trioxide, molybdenum trioxide, and vanadium pentoxide. The p-type metal oxide current blocking layer is connected to Ga 2 O 3 Drift layer and Ga 2 O 3 The channel layer forms two heterojunctions to close the channel, thereby forming a normally-off MOSFET.

[0009] The second type of structural design also has many advantages, such as it is a vertical device, the size can be made relatively smaller; for example, it is a normally off device; for example, there is a heterogeneous pn junction inside the device, and its breakdown voltage can be made higher than that of the first type of device structure. However, since p-type metal oxide is a polycrystalline material and is similar to Ga 2 O 3 It is a heterogeneous material, so the Ga formed on it by heteroepitaxial 2 O 3 The crystal quality of the channel layer film is poor, and it is impossible to grow a single crystal with high crystal quality Ga 2 O 3 Channel layer, which will increase the power loss of the device and affect the reliability of the device.

[0010] The third type is fin-gate Ga 2 O 3 Vertical MOSFET has relatively good device performance. For example, its breakdown voltage can reach over 2000V. However, the preparation process of this type of MOSFET is very complicated and difficult to implement. Summary of the invention

[0011] In view of this, the present invention aims at the above-mentioned deficiencies of the prior art and provides a normally-off (enhancement mode) gallium oxide field effect transistor with high thin film crystal quality. The device has a simple manufacturing process and is suitable for industrial production.

[0012] The present invention provides a gallium oxide field effect transistor, comprising:

[0013] Drain electrode;

[0014] A gallium oxide substrate is disposed on the drain electrode;

[0015] A first gallium oxide drift layer is disposed on a gallium oxide substrate;

[0016] A single crystal gallium oxide insulating layer is disposed on both sides of the first gallium oxide drift layer;

[0017] A second gallium oxide drift layer is disposed on the first gallium oxide drift layer and the single crystal gallium oxide insulating layer;

[0018] A single crystal gallium oxide layer is formed by epitaxial growth on the single crystal gallium oxide insulating layer, and the single crystal gallium oxide layer is located on both sides of the second gallium oxide drift layer, and a source electrode is provided on the single crystal gallium oxide layer;

[0019] A p-type material layer is disposed on the first gallium oxide drift layer, and the p-type material layer and the first gallium oxide drift layer form a heterogeneous pn junction;

[0020] The gate insulating layer is arranged on the p-type material layer, and a gate electrode is arranged on the gate insulating layer.

[0021] Preferably, the first gallium oxide drift layer is provided with a groove in the central area, and the second gallium oxide drift layer is provided with a through hole above the groove, which is connected with the groove and penetrates the upper and lower surfaces of the second gallium oxide drift layer; the p-type material layer is arranged in the groove of the first gallium oxide drift layer and the through hole of the second gallium oxide drift layer.

[0022] Preferably, the p-type material layer is made of a p-type metal oxide material, and the p-type metal oxide material is any one of nickel oxide, tin oxide, cuprous oxide, iridium oxide, tungsten trioxide, molybdenum trioxide, and vanadium pentoxide.

[0023] Preferably, the drain electrode forms an ohmic contact with the gallium oxide substrate, the source electrode forms an ohmic contact with the single crystal gallium oxide layer, and the gate electrode forms an ohmic contact with the p-type material layer.

[0024] Preferably, the gallium oxide substrate is a heavily doped n-type gallium oxide substrate with a doping concentration ranging from 10 18 ~10 20 cm -3 ;

[0025] The first gallium oxide drift layer is a lightly doped n-type gallium oxide drift layer with a doping concentration range of 10 15 ~10 17 cm -3 ;

[0026] The second gallium oxide drift layer is a lightly doped n-type gallium oxide drift layer with a doping concentration range of 10 15 ~10 17 cm -3 ;

[0027] The single crystal gallium oxide insulating layer is made of Fe-doped gallium oxide material;

[0028] The single-crystal gallium oxide layer is a heavily doped n-type single-crystal gallium oxide layer with a doping concentration range of 10 18 ~10 20 cm -3 .

[0029] Preferably, the gallium oxide field effect transistor is an enhancement mode device.

[0030] The present invention also provides a gallium oxide field effect transistor, comprising:

[0031] Drain electrode;

[0032] A gallium oxide substrate is disposed on the drain electrode;

[0033] A first gallium oxide drift layer is disposed on a gallium oxide substrate;

[0034] A single crystal gallium oxide insulating layer is disposed on both sides of the first gallium oxide drift layer;

[0035] A second gallium oxide drift layer is disposed on the first gallium oxide drift layer and the single crystal gallium oxide insulating layer;

[0036] A single crystal gallium oxide layer is formed by epitaxial growth on the single crystal gallium oxide insulating layer, and the single crystal gallium oxide layer is located on both sides of the second gallium oxide drift layer, and a source electrode is provided on the single crystal gallium oxide layer;

[0037] A p-type material layer is disposed on the second gallium oxide drift layer, and the p-type material layer and the second gallium oxide drift layer form a heterogeneous pn junction;

[0038] The gate insulating layer is arranged on the p-type material layer, and a gate electrode is arranged on the gate insulating layer.

[0039] Preferably, the p-type material layer is located in a groove in a central region of the second gallium oxide drift layer, and the groove penetrates a portion of the second gallium oxide drift layer from top to bottom.

[0040] Preferably, the p-type material layer is located in a central region of an upper surface of the second gallium oxide drift layer.

[0041] Compared with the prior art, the present invention has the following beneficial effects:

[0042] (1) The first gallium oxide drift layer and the single-crystal gallium oxide insulating layer of the present invention are both single-crystal thin films. The second gallium oxide drift layer grown by homoepitaxial growth on the first gallium oxide drift layer and the single-crystal gallium oxide layer grown by homoepitaxial growth on the single-crystal gallium oxide insulating layer are also high-quality Ga 2 O 3 Single crystal thin films, which previously did not have thermal mismatch and lattice mismatch, can reduce the power loss of gallium oxide field effect transistors and improve reliability.

[0043] (2) The first type of Ga with a current blocking layer 2 O 3The vertical MOSFET is a normally-on device and needs to be used in cascade with a normally-off MOSFET. To solve this problem, the present invention uses the depletion layer generated by the heterogeneous pn junction composed of a gallium oxide drift layer and a p-type material layer to close the channel, thereby forming a normally-off device. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solution of the present invention, the following will briefly introduce the drawings required for use in the embodiments or prior art descriptions. Obviously, the drawings described below are only some embodiments of the present invention, and the protection scope required by the present invention is not limited to the embodiments. For ordinary technicians in this field, other drawings can also be obtained based on these drawings without creative work.

[0045] Figure 1 The Ga of the existing current blocking layer 2 O 3 Schematic diagram of vertical MOSFET structure;

[0046] Figure 2 The Ga of the existing p-type metal oxide current blocking layer 2 O 3 Schematic diagram of the vertical MOSFET structure;

[0047] Figure 3 is a schematic diagram of a first embodiment of a gallium oxide field effect transistor of the present invention;

[0048] Figure 4 is a schematic diagram of a second embodiment of a gallium oxide field effect transistor of the present invention;

[0049] Figure 5 is a schematic diagram of a third embodiment of a gallium oxide field effect transistor of the present invention;

[0050] The technical features corresponding to the marks in the figure are:

[0051] 101 Gallium Oxide Substrate

[0052] 102 first gallium oxide drift layer

[0053] 103 Second gallium oxide drift layer

[0054] 104Single crystal gallium oxide insulating layer

[0055] 105Single crystal gallium oxide layer

[0056] 106p type material layer

[0057] 107 gate insulating layer

[0058] 108a Drain electrode

[0059] 108b source electrode

[0060] 108c gate electrode DETAILED DESCRIPTION

[0061] In the following description, for the purpose of illustration rather than limitation, specific details such as specific system structures and technologies are provided to provide a thorough understanding of the embodiments of the present invention. However, it should be clear to those skilled in the art that the present invention may also be implemented in other embodiments without these specific details.

[0062] First embodiment

[0063] refer to Figure 3 , Figure 3 Schematic diagram of a first embodiment of a gallium oxide field effect transistor of the present invention. The gallium oxide field effect transistor comprises: a heavily n-doped gallium oxide substrate 101, a lightly n-doped first gallium oxide drift layer 102, an Fe-doped single crystal gallium oxide insulating layer 104, a lightly n-doped second gallium oxide drift layer 103, a heavily n-doped single crystal gallium oxide layer 105, a p-type material layer 106, a gate insulating layer 107, a drain electrode 108a, a source electrode 108b, and a gate electrode 108c.

[0064] The gallium oxide substrate 101 is disposed on the drain electrode 108a, and the drain electrode 108a forms an ohmic contact with the gallium oxide substrate 101; the first gallium oxide drift layer 102 is disposed on the gallium oxide substrate 101, and the first gallium oxide drift layer 102 is a lightly doped n-type gallium oxide drift layer with a doping concentration range of 10 15 ~10 17 cm -3 The single-crystal gallium oxide insulating layer 104 is disposed on both sides of the first gallium oxide drift layer 102; the second gallium oxide drift layer 103 is disposed on the first gallium oxide drift layer 102 and the single-crystal gallium oxide insulating layer 104, and the second gallium oxide drift layer 103 is a lightly doped n-type gallium oxide drift layer with a doping concentration range of 10 15 ~10 17 cm -3 The single crystal gallium oxide layer 105 is formed by epitaxial growth on the single crystal gallium oxide insulating layer 104, and the single crystal gallium oxide layer 105 is located on both sides of the second gallium oxide drift layer 103. The doping concentration range of the gallium oxide substrate 101 and the single crystal gallium oxide layer 105 is 10 18 ~10 20 cm -3 , by heavy doping to reduce the contact resistance between the metal electrode and the semiconductor layer and improve the ohmic contact.

[0065] Attached Figure 3In the embodiment, the first gallium oxide drift layer 102 and the single crystal gallium oxide insulating layer 104 are both single crystal films. The second gallium oxide drift layer 103 and the single crystal gallium oxide layer 105 grown thereon by homoepitaxial growth are also high quality single crystal films, and there is no thermal mismatch and lattice mismatch between them.

[0066] The p-type material layer 106 is disposed on the first gallium oxide drift layer 102 , and the p-type material layer 106, the first gallium oxide drift layer 102 and the second gallium oxide drift layer 103 form a heterogeneous pn junction. The first gallium oxide drift layer 102 and the second gallium oxide drift layer 103 between the p-type material layer 106 and the single crystal gallium oxide insulating layer 104 are part of the conductive channel.

[0067] In this embodiment, the first gallium oxide drift layer 102 is provided with a groove (not labeled) in the central region, and the second gallium oxide drift layer 103 is provided with a through hole (not labeled) above the groove that is connected to the groove and penetrates the upper and lower surfaces of the second gallium oxide drift layer 103. The p-type material layer 106 is disposed in the groove of the first gallium oxide drift layer 102 and the through hole of the second gallium oxide drift layer 103. The p-type material layer 106 is any one of nickel oxide, tin oxide, cuprous oxide, iridium oxide, tungsten trioxide, molybdenum trioxide, and vanadium pentoxide. The doping concentration of the p-type material layer 106 ranges from 10 17 ~10 19 cm -3 .

[0068] The source electrode 108 b is disposed on the single crystal gallium oxide layer 105 , and the source electrode 108 b forms an ohmic contact with the single crystal gallium oxide layer 105 ; the gate insulating layer is disposed on the p-type material layer 106 , and a gate electrode 108 c is disposed on the gate insulating layer.

[0069] Attached Figure 3 In the gallium oxide field effect transistor, when the gate voltage is 0V, the free electrons in the conductive channel between the p-type material layer 106 and the single crystal gallium oxide insulating layer 104 are completely depleted by utilizing the heterogeneous pn junction formed by the p-type material layer 106 and the first gallium oxide drift layer 102, and the conductive channel is completely closed. At this time, a voltage is applied between the drain electrode 108a and the source electrode 108b, and no drain current flows in the conductive channel, thereby achieving a normally-off operation.

[0070] When a negative bias is applied between the gate electrode 108c and the source electrode 108b, due to the presence of the gate insulating layer 107, the gate electrode 108c and the p-type material layer 106 will not be directly connected, and the current of the gate electrode 108c is 0. However, due to the presence of the negative bias, negative charges will accumulate in the gate electrode 108c, which will repel the electrons on the side of the p-type material layer 106 close to the gate insulating layer 107, causing the electrons to gather in the other side of the p-type material layer 106 away from the gate insulating layer 107, resulting in increased electron accumulation, breaking the original equilibrium state of the pn junction, and causing the concentration difference to cause the diffusion movement of electrons, which diffuse into the conductive channel, causing free electrons to reappear in the conductive channel that was originally completely depleted of free electrons. At this time, when a voltage is applied between the drain electrode 108a and the source electrode 108b, current will flow through the conductive channel, and the device will be turned on.

[0071] Second embodiment

[0072] refer to Figure 4 , Figure 4 Schematic diagram of the second embodiment of the gallium oxide field effect transistor of the present invention. The gallium oxide field effect transistor comprises: a heavily n-doped gallium oxide substrate 101, a lightly n-doped first gallium oxide drift layer 102, an Fe-doped single crystal gallium oxide insulating layer 104, a lightly n-doped second gallium oxide drift layer 103, a heavily n-doped single crystal gallium oxide layer 105, a p-type material layer 106, a gate insulating layer 107, a drain electrode 108a, a source electrode 108b and a gate electrode 108c. The difference from the first embodiment is that in this embodiment, the p-type material layer 106 is arranged in a groove in the central area of ​​the second gallium oxide drift layer 103, and the groove penetrates a part of the second gallium oxide drift layer 103 from top to bottom. This embodiment can also achieve the effect of the first embodiment, which will not be described here.

[0073] Third embodiment

[0074] refer to Figure 5 , Figure 5 Schematic diagram of the third embodiment of the gallium oxide field effect transistor of the present invention. The gallium oxide field effect transistor comprises: a heavily n-doped gallium oxide substrate 101, a lightly n-doped first gallium oxide drift layer 102, an Fe-doped single crystal gallium oxide insulating layer 104, a lightly n-doped second gallium oxide drift layer 103, a heavily n-doped single crystal gallium oxide layer 105, a p-type material layer 106, a gate insulating layer 107, a drain electrode 108a, a source electrode 108b and a gate electrode 108c. The difference from the first embodiment is that in this embodiment, the p-type material layer 106 is disposed in the central region of the upper surface of the second gallium oxide drift layer 103. This embodiment can also achieve the effect of the first embodiment, which will not be described here.

[0075] It should be understood that the above-described embodiments and drawings are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included in the protection scope of the present invention.

Claims

1. A gallium oxide field effect transistor, comprising: It is characterized in that A drain electrode (108a); A gallium oxide substrate (101) is disposed on the drain electrode (108a); A first gallium oxide drift layer (102) is disposed on the gallium oxide substrate (101); A single crystal gallium oxide insulating layer (104) is disposed on both sides of the first gallium oxide drift layer (102); A second gallium oxide drift layer (103) is disposed on the first gallium oxide drift layer (102) and the single crystal gallium oxide insulating layer (104); a single crystal gallium oxide layer (105) formed by epitaxial growth on the single crystal gallium oxide insulating layer (104), the single crystal gallium oxide layer (105) being located on both sides of the second gallium oxide drift layer (103), and a source electrode (108b) being provided on the single crystal gallium oxide layer (105); A p-type material layer (106) is disposed on the first gallium oxide drift layer (102), wherein the p-type material layer (106) and the first gallium oxide drift layer (102) form a heterogeneous pn junction; A gate insulating layer (107) is disposed on the p-type material layer (106), and a gate electrode (108c) is disposed on the gate insulating layer (107).

2. The gallium oxide field effect transistor according to claim 1, characterized in that: The first gallium oxide drift layer (102) is provided with a groove in the central area, and the second gallium oxide drift layer (103) is provided with a through hole above the groove, which is connected with the groove and penetrates the upper and lower surfaces of the second gallium oxide drift layer (103); the p-type material layer (106) is arranged in the groove of the first gallium oxide drift layer (102) and the through hole of the second gallium oxide drift layer (103).

3. The gallium oxide field effect transistor according to claim 1, characterized in that: The p-type material layer (106) is made of a p-type metal oxide material, and the p-type metal oxide material is any one of nickel oxide, tin oxide, cuprous oxide, iridium oxide, tungsten trioxide, molybdenum trioxide, and vanadium pentoxide.

4. The gallium oxide field effect transistor according to claim 1, characterized in that: The drain electrode (108a) forms an ohmic contact with the gallium oxide substrate (101), and the source electrode (108b) forms an ohmic contact with the single crystal gallium oxide layer (105).

5. The gallium oxide field effect transistor according to claim 1, characterized in that: The gallium oxide substrate (101) is a heavily doped n-type gallium oxide substrate with a doping concentration ranging from 10 18 ~10 20 cm -3 ; The first gallium oxide drift layer (102) is a lightly doped n-type gallium oxide drift layer with a doping concentration ranging from 10 15 ~10 17 cm -3 ; The second gallium oxide drift layer (103) is a lightly doped n-type gallium oxide drift layer with a doping concentration ranging from 10 15 ~10 17 cm -3 ; The single crystal gallium oxide insulating layer (104) is made of Fe-doped gallium oxide material; The single crystal gallium oxide layer (105) is a heavily doped n-type single crystal gallium oxide layer, and the doping concentration ranges from 10 18 ~10 20 cm -3 .

6. The gallium oxide field effect transistor according to any one of claims 1 to 5, characterized in that: The gallium oxide field effect transistor is an enhancement mode device.

7. A gallium oxide field effect transistor, comprising: It is characterized in that A drain electrode (108a); A gallium oxide substrate (101) is disposed on the drain electrode (108a); A first gallium oxide drift layer (102) is disposed on the gallium oxide substrate (101); A single crystal gallium oxide insulating layer (104) is disposed on both sides of the first gallium oxide drift layer (102); A second gallium oxide drift layer (103) is disposed on the first gallium oxide drift layer (102) and the single crystal gallium oxide insulating layer (104); a single crystal gallium oxide layer (105) formed by epitaxial growth on the single crystal gallium oxide insulating layer (104), the single crystal gallium oxide layer (105) being located on both sides of the second gallium oxide drift layer (103), and a source electrode (108b) being provided on the single crystal gallium oxide layer (105); A p-type material layer (106) is disposed on the second gallium oxide drift layer (103), wherein the p-type material layer (106) and the second gallium oxide drift layer (103) form a heterogeneous pn junction; A gate insulating layer (107) is disposed on the p-type material layer (106), and a gate electrode (108c) is disposed on the gate insulating layer (107).

8. The gallium oxide field effect transistor according to claim 7, characterized in that: The p-type material layer (106) is located in a groove in the central area of ​​the second gallium oxide drift layer (103), and the groove penetrates a part of the second gallium oxide drift layer (103) from top to bottom.

9. The gallium oxide field effect transistor according to claim 7, characterized in that: The p-type material layer (106) is located in the central area of ​​the upper surface of the second gallium oxide drift layer (103).

10. The gallium oxide field effect transistor according to claim 7, characterized in that: The p-type material layer (106) is made of p-type metal oxide material; The gallium oxide substrate (101) is a heavily doped n-type gallium oxide substrate with a doping concentration ranging from 10 18 ~10 20 cm -3 ; The first gallium oxide drift layer (102) is a lightly doped n-type gallium oxide drift layer with a doping concentration ranging from 10 15 ~10 17 cm -3 ; The second gallium oxide drift layer (103) is a lightly doped n-type gallium oxide drift layer with a doping concentration ranging from 10 15 ~10 17 cm -3 ; The single crystal gallium oxide insulating layer (104) is made of Fe-doped gallium oxide material; The single crystal gallium oxide layer (105) is a heavily doped n-type single crystal gallium oxide layer, and the doping concentration ranges from 10 18 ~10 20 cm -3 .

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