A three-dimensional silicon magnetic sensitive triode with a planar electrode structure and a manufacturing process thereof

Abstract

The present invention provides a three-dimensional silicon magnetic-sensitive triode with a planarized electrode structure and a manufacturing method thereof. The structure includes an SOI device silicon layer inner lead, a SiO2 dielectric isolation ring, and a magnetically sensitive region. The emitter E is led from the lower surface of the device silicon layer to the upper surface of the device silicon layer via the device silicon layer inner lead, so that the base B, collector C, and emitter E are all located on the upper surface of the device silicon layer. Simultaneously, the SiO2 dielectric isolation ring isolates the inner lead region from the magnetically sensitive region, suppressing the effect of lateral diffusion of impurities in the inner lead region on the magnetically sensitive region. By combining SOI and CMOS processes, the three electrodes (E, B, and C) of the three-dimensional silicon magnetic-sensitive triode are planarized, overcoming the difficulties in manufacturing the inner lead in the device emitter region, laying the foundation for device integration, miniaturization, and mass production, while further improving the accuracy of the three-dimensional magnetic-sensitive triode in magnetic field measurement.

Description

Technical Field

[0001] The present invention relates to the field of magnetic sensitive devices, and in particular to a three-dimensional silicon magnetic sensitive triode with a planar electrode structure and a manufacturing process method thereof, which involves SOI process, CMOS process and dielectric isolation process. Background Art

[0002] Magnetic sensitive transistors are mainly used in magnetic field measurement. Due to their excellent sensitivity, stability and low temperature drift, they play an important role in geomagnetic surveys, mechanical testing, electronic compasses and other fields.

[0003] A three-dimensional magnetic-sensitive transistor (MNT) is a MNT with a three-dimensional structure within the silicon layer of an SOI device. The base and collector regions are located on the upper surface of the SOI device silicon layer, while the emitter region is located on the lower surface of the SOI device silicon layer, bordering the SiO2 insulating layer. This MNT exhibits excellent properties such as high magnetic sensitivity and a low temperature coefficient. However, due to the three-dimensional nature of the chip structure, a back electrode fabrication process is required when manufacturing the emitter. This process requires etching and ion implantation of the lower surface of the device silicon layer, resulting in low controllability and a significant impact on the device's sensitivity, accuracy, and yield. In particular, packaging affects the magnetic sensitivity, hindering the integration, miniaturization, and mass production of MNTs.

[0004] In order to break through the technical bottleneck of the back electrode manufacturing process, it is necessary to design a planar electrode structure of the three-dimensional silicon magnetic sensitive transistor to reduce the difficulty of the back electrode manufacturing process during device manufacturing, so that the device has better consistency and accuracy. Summary of the Invention

[0005] Based on the above technical background, the inventors have made great efforts and proposed a three-dimensional silicon magnetic-sensitive transistor with a planar electrode structure and a manufacturing method thereof. The three-dimensional silicon magnetic-sensitive transistor with a planar electrode structure leads the emitter from the lower surface of the device silicon layer to the upper surface of the device silicon layer through the internal lead of the SOI device silicon layer, so that the base, collector and emitter are all located on the upper surface of the device silicon layer, realizing the planarization of the three-dimensional silicon magnetic-sensitive transistor electrode; at the same time, a SiO2 dielectric isolation ring is provided to suppress the lateral diffusion of impurities in the internal lead area, breaking through the technical bottleneck of the back electrode process, improving the consistency of the three-dimensional structure magnetic-sensitive transistor and the accuracy of measuring the magnetic field, and having broad application prospects, thereby completing the present invention.

[0006] The first aspect of the present invention is to provide a three-dimensional silicon magnetic-sensitive triode with a planar electrode structure. The three-dimensional silicon magnetic-sensitive triode with a planar electrode structure includes a device silicon layer inner lead 5, a SiO2 dielectric isolation ring 6 and a magnetic sensitive area.

[0007] A second aspect of the present invention is to provide a method for manufacturing a three-dimensional silicon magnetic-sensitive triode with a planar electrode structure, the method comprising the following steps:

[0008] Step 1: Clean the silicon wafer, perform photolithography, and dry-etch alignment marks on the upper and lower surfaces of the silicon wafer;

[0009] Step 2: Clean the silicon wafer, perform photolithography once, photolithography the isolation groove window on the lower surface of the silicon wafer, deposit SiO2 isolation dielectric, make SiO2 dielectric isolation ring 6, and perform planarization process on the lower surface of the silicon wafer;

[0010] Step 3: Clean the silicon wafer and grow a SiO2 oxide layer on the lower surface of the silicon wafer by thermal oxidation to serve as an ion implantation buffer layer;

[0011] Step 4: Secondary photolithography, photolithography of inner lead window, ion implantation, forming n + Type heavy doping, making device silicon layer inner lead 5 and high temperature annealing, and performing planarization process on the lower surface of the silicon wafer;

[0012] Step 5: Three-time photolithography, photolithography emission window, ion implantation, forming n + Type heavy doping, making the emitter region 4 and high temperature annealing, and performing a planarization process on the lower surface of the silicon wafer;

[0013] Step 6: Clean the silicon wafer and the second silicon wafer 2, thermally grow SiO2 layers on the upper and lower surfaces of the second silicon wafer 2, and bond the upper surface of the second silicon wafer 2 to the lower surface of the silicon wafer;

[0014] Step 7, 0' photolithography, double-sided photolithography transfers the registration mark on the upper surface of the silicon wafer to the lower surface of the second silicon wafer 2;

[0015] Step 8: Thinning the upper surface of the silicon wafer to form an SOI wafer. The thinned silicon wafer is called the first silicon wafer 1, i.e., the device silicon layer.

[0016] Step 9: Photolithography four times to create the collector load resistor R L Window and base load resistors R b Window, ion implantation, forming n on the upper surface of the first silicon wafer 1 - Type doping, making the collector load resistor R L and the base load resistor R b ;

[0017] Step 10, five times of photolithography, photolithography collector window, ion implantation, forming n + Type heavy doping, forming collector region 7 and high temperature annealing;

[0018] Step 11, six times of photolithography, photolithography base window, ion implantation, forming p +Type heavy doping, forming base region 8 and high temperature annealing;

[0019] Step 12: Clean the first silicon wafer 1 and deposit a SiO2 layer on the upper surface of the first silicon wafer 1 as an insulating layer;

[0020] Step 13: Perform seven photolithography steps to etch lead holes on the upper surface of the first silicon wafer 1 and evaporate a metal Al layer;

[0021] Step 14: Eight photolithography steps to etch the metal to form the emitter E, collector C, base B, interconnects, and pads, followed by metal alloying to form ohmic contacts.

[0022] Step 15: Cleaning, and depositing silicon nitride (Si3N4) on the upper surface of the first silicon wafer 1 as a passivation layer;

[0023] Step 16: Photolithography nine times to etch the passivation layer and form a bonding pad;

[0024] Step 17: Clean the bonded wafer, perform intermediate testing, scribe the wafer, and perform non-magnetic packaging.

[0025] The three-dimensional silicon magnetic sensitive triode with a planar electrode structure and the manufacturing process provided by the present invention have the following advantages:

[0026] (1) The planarized electrode structure of the three-dimensional silicon magnetic sensitive transistor provided by the present invention reduces the influence of the emitter on the device characteristics during the packaging process by leading the emitter to the upper surface of the silicon layer of the SOI device, thereby improving the consistency and accuracy of the magnetic sensitive characteristics.

[0027] (2) The three-dimensional silicon magnetic-sensitive triode with a planar electrode structure provided by the present invention realizes the planarization of the electrodes of the three-dimensional silicon magnetic-sensitive triode and breaks through the technical bottleneck of the back electrode process.

[0028] (3) The present invention proposes a method for manufacturing a three-dimensional silicon magnetic sensitive transistor with a planar electrode structure based on SOI technology, which is easy to integrate into chips and provides broader prospects for miniaturization and mass production. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 A schematic diagram of a three-dimensional silicon magnetic-sensitive triode with a planar electrode structure according to a preferred embodiment of the present invention is shown;

[0030] Figure 2 A top view of a three-dimensional silicon magnetic-sensitive triode with a planar electrode structure according to a preferred embodiment of the present invention is shown;

[0031] Figure 3 An equivalent circuit diagram of a three-dimensional silicon magnetic-sensitive transistor with a planar electrode structure according to a preferred embodiment of the present invention is shown;

[0032] Figures 4-1 to 4-12A flowchart showing a process for manufacturing a three-dimensional silicon magnetic sensitive triode with a planar electrode structure according to a preferred embodiment of the present invention;

[0033] Figure 5-1 and Figure 5-2 A diagram showing a three-dimensional device simulation model of a three-dimensional silicon magnetic sensitive triode with a planar electrode structure according to a preferred embodiment of the present invention;

[0034] Figure 6 Shown along Figure 5-1 Sectional view of the mid-section line aa';

[0035] Figure 7-1 A three-dimensional silicon magnetic sensitive transistor I with a planar electrode structure according to a preferred embodiment of the present invention is shown. C -V CE Characteristic curve diagram;

[0036] Figure 7-2 A three-dimensional silicon magnetic sensitive transistor I is shown C -V CE Characteristic curve diagram;

[0037] Figure 8-1 A graph showing the magnetic sensitivity characteristics of a three-dimensional silicon magnetic sensitive transistor with a planar electrode structure according to a preferred embodiment of the present invention;

[0038] Figure 8-2 A magnetic sensitivity characteristic curve of a three-dimensional silicon magnetic sensitive triode is shown;

[0039] Figure 9-1 A temperature characteristic curve diagram of a three-dimensional silicon magnetic-sensitive transistor with a planar electrode structure according to a preferred embodiment of the present invention is shown;

[0040] Figure 9-2 A temperature characteristic curve of a three-dimensional silicon magnetic sensitive transistor is shown.

[0041] Explanation of Figure Numbers

[0042] 1-first silicon wafer;

[0043] 2- second silicon wafer;

[0044] 31-SiO2 insulating layer I;

[0045] 32-SiO2 insulation layer II;

[0046] 33-SiO2 insulation layer III;

[0047] 4-launching area;

[0048] 5-Device silicon layer inner lead;

[0049] 6-SiO2 dielectric isolation ring;

[0050] 7-collector area;

[0051] 8-base region;

[0052] E-emitter;

[0053] C-collector;

[0054] B-base;

[0055] R b - Base load resistor;

[0056] R L - Collector load resistor;

[0057] V DD -power supply;

[0058] GND-ground;

[0059] V out -Output voltage. DETAILED DESCRIPTION

[0060] The present invention will be described in detail below, and the characteristics and advantages of the present invention will become clearer and more distinct with the following description.

[0061] The first aspect of the present invention is to provide a three-dimensional silicon magnetic-sensitive transistor with a planar electrode structure. The three-dimensional silicon magnetic-sensitive transistor with a planar electrode structure is manufactured on an SOI wafer (i.e., an SOI device silicon layer) composed of a first silicon wafer 1 and a second silicon wafer 2. The second silicon wafer 2 is located below the first silicon wafer 1, and the upper surface of the second silicon wafer 2 is bonded to the lower surface of the first silicon wafer 1.

[0062] The thickness of the first silicon wafer 1 is 15-40 μm, preferably 15 μm.

[0063] The first silicon wafer 1 is preferably a near intrinsic p-type single crystal silicon wafer, more preferably having <100> Nearly intrinsic p-type single crystal silicon wafer with different crystal orientations.

[0064] The resistivity of the first silicon wafer 1 is greater than 100 Ω·cm, preferably 200 Ω·cm.

[0065] The thickness of the second silicon wafer 2 is 450-600 μm, preferably 500 μm.

[0066] Preferably, a SiO 2 insulating layer II 32 is provided between the first silicon wafer 1 and the second silicon wafer 2 , and the thickness of the SiO 2 insulating layer II 32 is 0.3-1.2 μm, preferably 1 μm.

[0067] The first silicon wafer 1 includes a SiO2 dielectric isolation ring 6, a magnetic sensitive area and a device silicon layer inner lead 5. A SiO2 insulating layer 131 is provided on the upper surface of the first silicon wafer 1. The thickness of the SiO2 insulating layer 131 is 0.1 to 0.2 μm, preferably 0.1 μm.

[0068] The SiO2 dielectric isolation ring 6 is located on the first silicon wafer 1 and passes through the first silicon wafer 1. The SiO2 dielectric isolation ring 6 forms a plurality of isolation regions in the first silicon wafer 1, such as Figure 1 and Figure 2 As shown, the magnetically sensitive region is located in the isolated area.

[0069] The SiO2 dielectric isolation ring 6 can suppress the lateral diffusion of impurities and isolate the magnetic sensitive area, which is beneficial to improving the performance of the magnetic sensitive transistor.

[0070] More preferably, a SiO2 dielectric isolation ring 6 is provided to separate the first silicon wafer 1 into four isolation regions, namely a first region, a second region, a third region and a fourth region.

[0071] Further arranging the magnetic sensitive areas in the above four areas respectively can avoid interference between the parts and further improve the magnetic sensitive characteristics of the magnetic sensitive triode.

[0072] According to a preferred embodiment of the present invention, the magnetic sensitive region includes a base B, a collector C, an emitter E, an emitter region 4 , a collector region 7 , and a base region 8 .

[0073] The base B, collector C and emitter E are located on the upper surface of the silicon layer of the SOI device (ie, the first silicon wafer 1 ).

[0074] In the present invention, the device silicon layer inner lead 5 is located within the SOI device silicon layer and penetrates the first silicon wafer 1. By providing the SOI device silicon layer inner lead 5, the emitter E is led to the upper surface of the device silicon layer, so that the base B, collector C, and emitter E are all located on the upper surface of the SOI device silicon layer, that is, the upper surface of the three-dimensional silicon magnetic-sensitive triode, and the base B, collector C, and emitter E are fabricated on the same plane. This effectively avoids the influence of the back electrode process on the magnetic-sensitive characteristics, improves the consistency and accuracy of the magnetic-sensitive triode characteristics, and simplifies the packaging process of the magnetic-sensitive device.

[0075] Specifically, the device silicon layer inner lead 5 is located between the emitter E and the emitter region 4, and the emitter region 4 is located at the junction of the lower surface of the first silicon wafer 1 and the SiO2 insulating layer II 32. The present invention achieves electrode planarization of the three-dimensional silicon magnetic sensitive transistor by providing the device silicon layer inner lead 5.

[0076] Preferably, the device silicon layer inner lead 5 is n + Type heavily doped, doping concentration is 1E19~1E20cm-3 , preferably 1E20cm -3 .

[0077] The doping type of the emitter region 4 is n + Type heavily doped, doping concentration is 1E19~1E20cm -3 , preferably 1E20cm -3 .

[0078] The collector region 7 is connected to the collector electrode C, is located on the upper surface of the first silicon wafer 1 and borders the SiO2 insulating layer 131.

[0079] Preferably, the doping type of the collector region 7 is n + Type heavily doped, doping concentration is 1E15~1E16cm -3 , preferably 1E15cm -3 .

[0080] The base region 8 is connected to the base electrode B, is located on the upper surface of the first silicon wafer 1 and borders the SiO2 insulating layer 131.

[0081] Preferably, the doping type of the base region 8 is p + Type heavily doped, doping concentration is 1E18~1E19cm -3 , the preferred doping concentration is 1E18cm -3 .

[0082] The magnetic sensitive area also includes a base load resistor R b , base load resistor R b Located on the upper surface of the first silicon wafer 1 and bordering the SiO2 insulating layer 131, the base load resistor R b One end is connected to the base B, and the other end is connected to the power supply V DD connected, such as Figure 1 、 Figure 2 and Figure 3 shown.

[0083] The magnetic sensitive area also includes a collector load resistor R L , collector load resistance R L Located on the upper surface of the first silicon wafer 1 and bordering the SiO2 insulating layer 131, the collector load resistor R L One end is connected to the collector C, and the other end is connected to the power supply V DD connected, such as Figure 1 、 Figure 2 and Figure 3 shown.

[0084] Preferably, the collector load resistor R L and the base load resistor R b Both are n -Type lightly doped region, the doping concentration is 5E14 ~ 5E15cm -3 , preferably 5E14cm -3 , the resistance value is 1.0~3.0kΩ, preferably 1.5kΩ.

[0085] According to a preferred embodiment of the present invention, the base B, collector C, collector region 7, base region 8 and emitter region 4 are located in the second region, the emitter E and the device silicon layer inner lead 5 are located in the third region, and the collector load resistor R L Located in the fourth region, the base load resistor R b Located in the first area.

[0086] By arranging SiO2 dielectric isolation rings 6 between the above parts, the lateral diffusion of the dielectrics in each part of the magnetic sensitive area can be further suppressed, and the mutual influence can be reduced, which is beneficial to improving the magnetic sensitivity of the magnetic sensitive transistor and reducing the temperature drift.

[0087] No SiO2 dielectric isolation ring 6 is provided in the region connecting the lead 5 and the emitter region 4 within the device silicon layer to prevent the SiO2 dielectric isolation ring 6 from blocking the connection between the lead 5 and the emitter region 4. The width of the region connecting the lead 5 and the emitter region 4 within the device silicon layer is 3 to 5 μm, preferably 3 μm.

[0088] The emitter E is grounded to GND, the collector C and the collector load resistor R L The connection is used as the output voltage V out end.

[0089] A SiO2 layer III 33 is provided on the lower surface of the second silicon wafer 2 to protect the three-dimensional silicon magnetic sensitive transistor with a planar electrode structure. The thickness of the SiO2 layer III 33 is 0.1 to 0.2 μm, preferably 0.1 μm.

[0090] The three-dimensional device simulation model of the three-dimensional silicon magnetic sensitive transistor with planar electrode structure of the present invention is shown in FIG. Figure 5-1 and Figure 5-2 As shown, along Figure 5-1 The cross-sectional view of the mid-section line aa' is as follows Figure 6 shown.

[0091] The second aspect of the present invention is to provide a method for manufacturing a three-dimensional silicon magnetic-sensitive triode having a planar electrode structure according to the first aspect of the present invention, the method comprising the following steps:

[0092] Step 1: Clean the silicon wafer, perform photolithography, and dry-etch the registration marks on the upper and lower surfaces of the silicon wafer. Figure 4-1 shown.

[0093] The silicon wafer is preferably a near intrinsic p-type single crystal silicon wafer, more preferably having <100> Nearly intrinsic p-type single crystal silicon wafer with different crystal orientations.

[0094] The resistivity of the silicon wafer is greater than 100 Ω·cm, preferably 200 Ω·cm.

[0095] The cleaning process preferably adopts the RCA standard cleaning method.

[0096] Step 2: Clean the silicon wafer, perform photolithography once, photolithography the isolation groove window on the lower surface of the silicon wafer, deposit SiO2 isolation dielectric, make SiO2 dielectric isolation ring 6, and perform flattening process on the lower surface of the silicon wafer. Figure 4-2 shown.

[0097] The dry process etches the silicon wafer, and the etching depth is preferably 15 to 40 μm, more preferably 15 μm.

[0098] The SiO 2 dielectric isolation ring 6 is located in the silicon wafer. Preferably, the magnetic sensitive area is located in the SiO 2 dielectric isolation ring 6 .

[0099] A SiO2 dielectric isolation ring 6 is provided to separate the silicon wafer into four isolation regions, namely the first region, the second region, the third region and the fourth region. Figure 1 、 Figure 2 and Figure 3 shown.

[0100] The SiO2 dielectric isolation ring 6 can not only suppress the lateral diffusion of impurities, but also isolate the magnetic sensitive area. By dividing it into four areas, the mutual interference caused by ion implantation in the subsequent manufacturing process can be avoided, thereby improving the performance of the magnetic sensitive transistor.

[0101] In a preferred embodiment of the present invention, a space is reserved in the dielectric isolation trench between the second region and the third region near the lower surface of the silicon wafer to form a connection area (please indicate the location of the reserved area in the attached drawings). Figure 1 As shown, the width of the reserved area is preferably 3-5 μm, more preferably 3 μm, to facilitate the connection between the lead 5 in the silicon layer of the device and the emitter region 4 to be manufactured later.

[0102] The width of the SiO2 dielectric isolation ring 6 is 1-3 μm, preferably 2 μm. The inventors have found that when the width of the SiO2 dielectric isolation ring 6 is within the above range, it can effectively play an isolation role.

[0103] Step 3: Clean the silicon wafer and grow a SiO2 layer on the lower surface of the silicon wafer by thermal oxidation method as an ion implantation buffer layer.

[0104] Preferably, the SiO2 oxide layer is produced by thermal oxidation, and the thickness of the SiO2 layer is 30 to 50 nm, preferably 30 nm.

[0105] Step 4: Secondary photolithography, photolithography of the lead window in the silicon layer of the device, ion implantation, forming n + The device is heavily doped, and the inner lead 5 of the silicon layer is made and annealed at high temperature, and the lower surface of the silicon wafer is flattened. Figure 4-3 shown.

[0106] Ion implantation is used to dope the silicon wafer from the bottom surface, which is beneficial to increasing the doping concentration of the leads 5 in the silicon layer of the device.

[0107] Preferably, phosphorus is implanted to form n + Type heavily doped, the doping concentration is 1E19~1E20cm -3 , preferably 1E20cm -3 .

[0108] After the doping is completed, high temperature annealing is performed in a vacuum environment. The high temperature annealing temperature is 900-1200°C, preferably 1000°C.

[0109] The annealing time is 20 to 50 seconds, preferably 30 to 40 seconds.

[0110] Step 5: Three-time photolithography, photolithography emission window, ion implantation, forming n + The emitter region 4 is made by heavy doping and high temperature annealing, and the lower surface of the silicon wafer is flattened. Figure 4-4 shown.

[0111] The lithography window includes the emitter area, the device silicon layer inner lead and the connection area between the two, that is, the production of the emitter area of ​​the three-dimensional silicon magnetic sensitive transistor and the connection between the emitter area and the device silicon layer inner lead are completed through the ion implantation process, thereby achieving a good connection between the emitter area 4 and the device silicon layer inner lead 5.

[0112] According to a preferred embodiment of the present invention, phosphorus is implanted to form n + Type heavily doped, the doping concentration is 1E19~1E20cm -3 , preferably 1E20cm -3 .

[0113] The annealing treatment after the doping is performed in a vacuum environment at a temperature of 1000-1200° C., preferably 1000° C.

[0114] The annealing time is 20 to 50 seconds, preferably 30 to 40 seconds.

[0115] Step 6: Clean the silicon wafer and the second silicon wafer 2, thermally grow SiO2 layers on the upper and lower surfaces of the second silicon wafer 2, and bond the upper surface of the second silicon wafer 2 to the lower surface of the silicon wafer. Figure 4-5 shown.

[0116] The thickness of the SiO2 insulating layer II 32 thermally grown on the upper surface of the second silicon wafer 2 is 0.3-1.2 μm, preferably 1 μm.

[0117] The thickness of the SiO2 insulating layer III 33 thermally grown on the lower surface of the second silicon wafer 2 is 0.1 to 0.2 μm, preferably 0.1 μm.

[0118] Step 7: 0′ photolithography: double-sided photolithography transfers the registration mark on the upper surface of the silicon wafer to the lower surface of the second silicon wafer 2.

[0119] Step 8: Thin the upper surface of the silicon wafer to form an SOI wafer (i.e., the silicon layer of the SOI device). The thinned silicon wafer is called the first silicon wafer 1. Figure 4-6 shown.

[0120] After thinning, the thickness of the first silicon wafer 1 is 15-40 μm, preferably 15 μm.

[0121] Step 9: Photolithography four times to create the collector load resistor R L Window and base load resistors R b Window, ion implantation, forming n on the upper surface of the first silicon wafer 1 - Type doping, making the collector load resistor R L and the base load resistor R b ,like Figure 4-7 shown.

[0122] The collector load resistor R L and the base load resistor R b Located on the right side of the lead 5 and one side of the base region 8 in the silicon layer of the device, the collector load resistor R L and the base load resistor R b They are respectively located in the SiO2 dielectric isolation ring 6.

[0123] According to a preferred embodiment of the present invention, phosphorus ions are implanted to form n - Type lightly doped region, the collector load resistor R L and the base load resistor R b The doping concentration is 5E14~5E15cm -3 , preferably 5E14cm -3 , the resistance value is 1.0~3.0kΩ, preferably 1.5kΩ.

[0124] Step 10, five times of photolithography, photolithography collector window, ion implantation, forming n + Type heavy doping, making collector region 7 and high temperature annealing. Figure 4-8 shown.

[0125] By phosphorus implantation, n+ The collector region 7 is heavily doped, with a doping concentration of 1E15 to 1E16 cm -3 , preferably 1E15cm -3 .

[0126] The annealing treatment after the doping is performed in a vacuum environment at a temperature of 1000-1200° C., preferably 1000° C.

[0127] The annealing time is 20 to 50 seconds, preferably 30 to 40 seconds.

[0128] Step 11, six times of photolithography, photolithography base window, ion implantation, forming p + Type heavy doping, making base region 8 and high temperature annealing. Figure 4-9 shown.

[0129] Preferably, boron is implanted to form p + Type heavily doped.

[0130] The doping concentration of base region 8 is 1E18~1E19cm -3 , preferably 1E18cm -3 .

[0131] The annealing treatment after the doping is performed in a vacuum environment at a temperature of 1000-1200° C., preferably 1000° C.

[0132] The annealing time is 20 to 50 seconds, preferably 30 to 40 seconds.

[0133] Step 12: clean the first silicon wafer 1 and deposit a SiO2 layer on the upper surface of the first silicon wafer 1 as an insulating layer.

[0134] The cleaning process preferably adopts the RCA standard cleaning method.

[0135] The SiO2 layer is preferably produced by chemical vapor deposition process, and its thickness is 0.1 to 0.2 μm, preferably 0.1 μm.

[0136] Step 13: Perform seven photolithography steps to etch lead holes on the upper surface of the first silicon wafer 1 and evaporate a metal Al layer.

[0137] Al is preferred as the metal layer.

[0138] Step 14: Eight times of photolithography, etching the metal to form the emitter E, collector C, base B, interconnection lines and bonding pads, and metal alloying process to form ohmic contacts. Figure 4-10 shown.

[0139] The alloying process is preferably carried out in a vacuum or nitrogen environment, the alloying temperature is 300-500° C., preferably 420° C., and the alloying time is 20-40 min, preferably 30 min.

[0140] Step 15: Cleaning, and depositing a passivation layer on the upper surface of the first silicon wafer 1. Figure 4-11 shown.

[0141] The passivation layer is preferably a Si3N4 layer, and the deposition method is preferably chemical vapor deposition.

[0142] The thickness of the passivation layer is 0.1 to 0.2 μm, preferably 0.1 μm.

[0143] Step 16: Photolithography is performed nine times to etch the passivation layer to form a bonding pad. Figure 4-12 As stated.

[0144] Step 17: Clean the bonded wafer, perform intermediate testing, scribe the wafer, and perform non-magnetic packaging.

[0145] The beneficial effects of the present invention are:

[0146] The three-dimensional silicon magnetic sensitive triode with a planar electrode structure and the manufacturing process method of the present invention not only has the advantages of the three-dimensional silicon magnetic sensitive triode, but also has the advantages of the three-dimensional silicon magnetic sensitive triode. C -V CE Characteristics, magnetic sensitivity characteristics and temperature characteristics, and improves the I C -V CE The 3D silicon magnetic-sensitive triode with a planar electrode structure and its process method solve the back electrode process problem, effectively improving the performance of the magnetic-sensitive triode and having important significance for the integration of 3D silicon magnetic-sensitive triode devices.

[0147] Example

[0148] The present invention is further described below through specific examples. These examples are only intended to illustrate the present invention and are not intended to limit the scope of the present invention.

[0149] Example 1

[0150] The following steps are used to manufacture a three-dimensional silicon magnetic sensitive transistor with a planar electrode structure:

[0151] Step 1: Clean using RCA standard cleaning method <100> Nearly intrinsic p-type single crystal silicon wafer with 0 photolithography, with dry etching on the upper and lower surfaces of the silicon wafer, and the impurity concentration of the silicon wafer is 1E11cm -3 .

[0152] Step 2: Clean the silicon wafer, perform photolithography once, and use a deep trench etching process to etch an isolation groove window on the lower surface of the silicon wafer with an etching depth of 15 μm. Deposit silicon dioxide isolation dielectric by chemical vapor deposition to make SiO2 dielectric isolation ring 6. The width of SiO2 dielectric isolation ring 6 is 2 μm.

[0153] A SiO2 dielectric isolation ring 6 is provided to separate the silicon wafer into four isolation areas, namely the first area, the second area, the third area and the fourth area from left to right. SiO2 is not deposited in the dielectric isolation groove between the second area and the third area near the lower surface of the silicon wafer, forming a reserved area with a width of 3 μm.

[0154] Step 3: Clean the silicon wafer and grow a SiO2 oxide layer on the lower surface of the silicon wafer by thermal oxidation. The thickness of the SiO2 layer is 30 nm.

[0155] Step 4: Secondary photolithography, photolithography of the lead window in the silicon layer of the device, and phosphorus injection to form n + Type doping, doping concentration is 1E20cm -3 , high temperature annealing at 1000℃ in a vacuum environment for 30 to 40s.

[0156] Step 5: Three-time photolithography, photolithography window, phosphorus implantation, forming n + Type heavily doped, with a doping concentration of 1E20cm -3 The emitter region is fabricated and subjected to high-temperature annealing in a vacuum environment at 1000°C for 30 to 40 seconds. After annealing, chemical mechanical planarization is used to remove the silicon dioxide layer on the lower surface of the silicon wafer.

[0157] Step 6: Clean the second silicon wafer 2, thermally grow a silicon dioxide layer on the upper surface of the second silicon wafer 2, that is, a SiO2 insulating layer II 32 with a thickness of 1 μm, and bond the lower surface of the silicon wafer and the upper surface of the second silicon wafer 2.

[0158] The thickness of the thermally grown SiO2 insulating layer III 33 on the lower surface of the second silicon wafer 2 is 0.1 μm.

[0159] Step 7: 0′ photolithography: double-sided photolithography transfers the registration mark on the upper surface of the silicon wafer to the lower surface of the second silicon wafer 2.

[0160] Step 8: Thinning the upper surface of the silicon wafer to form an SOI wafer. The thinned silicon wafer is called the first silicon wafer 1. The thickness of the first silicon wafer 1 is 15 μm.

[0161] Step 9: Four times of photolithography, by implanting phosphorus ions, n is formed on the upper surface of the first silicon wafer 1. - Type lightly doped region, making the collector load resistor R L and the base load resistor R b, the doping concentration is 5E14cm -3 , the resistance value is 1.5kΩ.

[0162] The collector load resistor R L Window and base load resistors R b They are respectively located on the right side of the lead 5 and the left side of the base region 8 in the silicon layer of the device.

[0163] Step 10: Photolithography five times to lithography the collector window and form n + Type heavily doped, with a doping concentration of 1E15cm -3 , make collector region 7, and anneal at 1000℃ for 30 to 40s after doping.

[0164] Step 11, six times of photolithography, photolithography base window, through boron implantation, form p + Type heavily doped, with a doping concentration of 1E18cm -3 , make the base region 8, and after doping, anneal at 1000℃ for 30 to 40 seconds.

[0165] Step 12: Clean the first silicon wafer 1 using the RCA standard cleaning method, and deposit a SiO2 oxide layer on the upper surface of the first silicon wafer 1 as an insulating layer with a thickness of 0.1 μm.

[0166] Step 13: Perform seven photolithography steps to etch lead holes on the upper surface of the first silicon wafer 1 and evaporate a metal Al layer.

[0167] Step 14: Perform eight photolithography steps to etch metal Al to form emitter E, collector C, base B, interconnects, and solder joints. Perform metal alloying in a vacuum environment at a temperature of 420° C. for 30 minutes to form ohmic contacts.

[0168] Step 15: Cleaning, depositing a Si3N4 layer on the upper surface of the first silicon wafer 1 by chemical vapor deposition as a passivation layer with a thickness of 0.1 μm.

[0169] Step 16: Photolithography is performed nine times to etch the passivation layer to form bonding pads.

[0170] Step 17: Clean the bonded wafer, perform intermediate testing, scribe the wafer, and perform non-magnetic packaging.

[0171] Comparative Example

[0172] A three-dimensional silicon magnetic-sensitive triode was fabricated for comparative analysis. The device, excluding the silicon layer inner leads and the SiO2 dielectric isolation ring, had the same process parameters as the device in Example 1. The emitter region was fabricated using the back electrode fabrication process.

[0173] Experimental example

[0174] Experimental Example 1IC -V CE Characteristic testing

[0175] The magnetic sensitive transistors of Example 1 of the present invention and the comparative example were subjected to I C -V CE Characteristic test, at room temperature (T = 300K) and without external magnetic field, set the following conditions: collector voltage V CE The range is 0~5V, the step size is 0.25V, and the base current I B The range is 0~5mA, and the step length is 1mA. The test results are as follows Figure 7-1 and Figure 7-2 shown.

[0176] Depend on Figure 7-1 and Figure 7-2 It can be seen that the collector current I c Lower than the base current I B , that is, the current amplification factor β of the three-dimensional silicon magnetic sensitive transistor is less than 1. B =5mA, V CE =5V, the collector current I of the three-dimensional silicon magnetic sensitive transistor with a planar electrode structure according to the first embodiment of the present invention is C The maximum value is 3.15mA. Under the same conditions, the collector current of the three-dimensional silicon magnetic sensitive transistor I C The three-dimensional silicon magnetic sensitive transistor I with a planar electrode structure according to embodiment 1 of the present invention C -V CE The characteristics are better than those of general three-dimensional silicon magnetic sensitive transistors.

[0177] Experimental Example 2 Magnetic Sensitivity Test

[0178] The magnetic sensitivity test was conducted on the three-dimensional silicon magnetic sensitive transistor with a planar electrode structure described in Example 1 of the present invention and the three-dimensional silicon magnetic sensitive transistor described in the comparative example. At room temperature (T=300K), the following conditions were set: the collector voltage V CE The range is 0~5V, the step size is 0.25V, and the base current I B The current is 5mA, and a magnetic field of ±0.3T is applied in the magnetic sensitive direction. The test results are as follows: Figure 8-1 and Figure 8-2 shown.

[0179] Depend on Figure 8-1 and Figure 8-2 It can be seen that the magnetic sensitivity of the three-dimensional silicon magnetic sensitive transistor with the planarized electrode structure described in Example 1 of the present invention is 0.41mA / T, and the magnetic sensitivity of the three-dimensional silicon magnetic sensitive transistor is 0.36mA / T. The electrode planarization method proposed in the present invention can effectively improve the magnetic sensitivity characteristics of the three-dimensional silicon magnetic sensitive transistor.

[0180] Experimental Example 3 Temperature Characteristics Test

[0181] Figure 9-1 and Figure 9-2 The temperature characteristics of the three-dimensional silicon magnetic sensitive transistor with a planar electrode structure according to Example 1 of the present invention and the three-dimensional silicon magnetic sensitive transistor according to the comparative example are shown respectively. When there is no external magnetic field, the setting conditions are as follows: the collector voltage V CE The range is 0~5V, the step size is 0.25V, and the base current I B The range is 0~5mA with a step size of 1mA, and the range of ambient temperature is -40℃~85℃ with a step size of 20℃.

[0182] Depend on Figure 9-1 and Figure 9-2 It can be seen that both the 3D silicon magnetic-sensitive transistor and the 3D silicon magnetic-sensitive transistor with a planar electrode structure described in Example 1 of the present invention have a negative temperature coefficient ɑ. The temperature coefficient of the 3D silicon magnetic-sensitive transistor with a planar electrode structure is -5235ppm / °C, and the temperature coefficient of the 3D silicon magnetic-sensitive transistor with a planar electrode structure is -5342ppm / °C. The 3D silicon magnetic-sensitive transistor with a planar electrode structure effectively reduces temperature drift.

[0183] In the description of the present invention, it should be noted that the terms "upper," "lower," "inner," "outer," "front," and "rear" and the like, indicating positions or locations, are based on the operating state of the present invention and are intended solely to facilitate and simplify the description of the present invention. They are not intended to indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation, and therefore should not be construed as limitations on the present invention. Furthermore, the terms "first," "second," "third," and "fourth" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0184] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed, detachable, or integral connections; mechanical or electrical connections; direct or indirect connections through an intermediate medium; and internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention in specific contexts.

[0185] The present invention has been described above with reference to preferred embodiments, but these embodiments are merely exemplary and serve only as illustrations. On this basis, various replacements and improvements can be made to the present invention, all of which fall within the scope of protection of the present invention.

Claims

1. A method for manufacturing a three-dimensional silicon magnetic sensitive triode with a planar electrode structure, characterized in that: The three-dimensional silicon magnetic sensitive triode with a planar electrode structure comprises an SOI device silicon layer inner lead (5), a SiO2 dielectric isolation ring (6) and a magnetic sensitive area. The SiO2 dielectric isolation ring (6) is located on the first silicon wafer (1) and penetrates the first silicon wafer (1). The SiO2 dielectric isolation ring (6) forms a plurality of isolation regions in the first silicon wafer (1). The device silicon layer inner leads (5) and the magnetic sensitive regions are distributed in the isolation regions. The method comprises the following steps: Step 1: Clean the silicon wafer, perform photolithography, and dry-etch alignment marks on the upper and lower surfaces of the silicon wafer; Step 2: Clean the silicon wafer, perform photolithography once, photolithography the isolation groove window on the lower surface of the silicon wafer, deposit SiO2 isolation dielectric, make SiO2 dielectric isolation ring (6), and perform flattening process on the lower surface of the silicon wafer; Step 3: Clean the silicon wafer and grow a SiO2 layer on the lower surface of the silicon wafer by thermal oxidation to serve as an ion implantation buffer layer; Step 4: Secondary photolithography, photolithography of inner lead window, ion implantation, forming n + The device is heavily doped to produce the inner lead (5) of the silicon layer, and is subjected to high temperature annealing, wherein the high temperature annealing temperature is 900-1200° C., and the lower surface of the silicon wafer is subjected to a flattening process; Step 5: Three-time photolithography, photolithography emission window, ion implantation, forming n + The silicon wafer is heavily doped to produce an emitter region (4), and subjected to high-temperature annealing to planarize the lower surface of the silicon wafer, wherein the high-temperature annealing temperature is 900 to 1200° C.; Step 6: Cleaning the silicon wafer and the second silicon wafer (2), thermally growing SiO2 layers on the upper and lower surfaces of the second silicon wafer (2), and bonding the upper surface of the second silicon wafer (2) to the lower surface of the silicon wafer; Step 7, 0' photolithography, double-sided photolithography transfer of the registration mark on the upper surface of the silicon wafer to the lower surface of the second silicon wafer (2); Step 8: Thinning the upper surface of the silicon wafer to form an SOI wafer. The thinned silicon wafer is called the first silicon wafer (1), i.e., the device silicon layer; Step 9: Photolithography four times to create the collector load resistor R L Window and base load resistors R b Window, ion implantation, forms n on the upper surface of the first silicon wafer (1) - Type doping, making collector load resistor R L and base load resistor R b ; Step 10, five times of photolithography, photolithography collector window, ion implantation, forming n + Type heavy doping to make collector region (7); Step 11, six times of photolithography, photolithography base window, ion implantation, forming p + Type heavy doping, making a base region (8), and high temperature annealing, the annealing temperature is 1000 ~ 1200 ℃; Step 12: cleaning the first silicon wafer (1), and depositing a SiO2 layer on the upper surface of the first silicon wafer (1) as an insulating layer; Step 13: perform seven photolithography steps to etch lead holes on the upper surface of the first silicon wafer (1) and evaporate a metal Al layer; Step 14: Eight photolithography steps to etch the metal layer to form interconnects and pads, and metal alloying to form ohmic contacts. Step 15: Clean the bonded silicon wafers and deposit a silicon nitride (Si3N4) layer on the upper surface of the first silicon wafer (1) as a passivation layer; Step 16: Photolithography nine times to etch the passivation layer and form a bonding pad; Step 17: Clean the bonded wafer, perform intermediate testing, scribe the wafer, and perform non-magnetic packaging.

2. The method according to claim 1, characterized in that The magnetic sensitive region comprises a base B, a collector C, an emitter E, an emitter region (4), a collector region (7), and a base region (8), wherein the base B, the collector C, and the emitter E are located on the upper surface of the first silicon wafer (1).

3. The method according to claim 2, characterized in that The device silicon layer inner lead (5) is located inside the first silicon wafer (1) and passes through the first silicon wafer (1). The device silicon layer inner lead (5) is located between the emitter E and the emitter region (4). The emitter region (4) is located on the lower surface of the first silicon wafer (1) and borders the SiO2 insulating layer II (32).

4. The method according to claim 3, characterized in that The lead wire (5) inside the silicon layer of the device is n + Type heavily doped, the doping concentration is 1E19~1E20 cm -3 .

5. The method according to claim 4, characterized in that The doping concentration is 1E20 cm -3 .

6. The method according to any one of claims 2 to 5, characterized in that The SiO2 dielectric isolation ring (6) separates the device silicon layer into four isolation regions, namely a first region, a second region, a third region and a fourth region; The base electrode B, the collector electrode C, the collector region (7), the base region (8) and the emitter region (4) are located in the second region, and the emitter electrode E and the device silicon layer inner lead (5) are located in the third region.

7. The method according to claim 6, characterized in that The magnetic sensitive area further includes a base load resistor R b and collector load resistance R L , collector load resistance R L Located in the fourth region, the base load resistor R b Located in the first area.

8. The method according to claim 6, characterized in that The SiO2 dielectric isolation ring (6) reserves space in the region where the lead (5) and the emitter region (4) are connected within the silicon layer of the device; The width of the region where the lead (5) and the emitter region (4) are connected in the silicon layer of the device is 3 to 5 μm.

9. The method according to claim 1, characterized in that In step 1, the silicon wafer is a nearly intrinsic p-type single crystal silicon wafer with a resistivity greater than 100 Ω·cm, and is used as the silicon layer of the SOI wafer device; In step 5, the ion implantation is used to make the inner lead (5) of the device silicon layer by doping from the lower surface of the silicon wafer, and phosphorus is implanted to form n + Type heavily doped, the doping concentration is 1E19~1E20 cm -3 ; In step 14, the metal alloying process is carried out at 300-500° C. for 20-40 minutes.

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