Chopper amplifier circuit and method for operating a chopper amplifier circuit

Abstract

Embodiments of the present disclosure relate to a chopper amplifier circuit and a method for operating a chopper amplifier circuit. The present disclosure relates to a chopper amplifier circuit with inherent chopper ripple rejection.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to circuits and methods for chopper amplifiers, and more specifically to circuits and methods for reducing chopper ripple. BACKGROUND

[0002] A chopper amplifier, also referred to as chopper amplifier circuit in the following, is an amplifier that modulates (chops), amplifies and demodulates again a signal to be amplified. By using this technique, the zero point error (or offset error) of the amplifier and the so-called 1 / f noise can be shifted into a frequency band that is irrelevant. Such a chopper amplifier can be used, for example, in a bandgap circuit that provides a defined reference voltage, but also in other applications in which a signal is to be amplified, for example for amplifying a measurement signal.

[0003] This modulation and demodulation, also referred to as chopping, causes a ripple in the output signal. This ripple can be caused, for example, by a voltage offset of the amplifier used for amplification in the chopper amplifier. The amplitude of the ripple corresponds to the offset amount, and the frequency of the ripple corresponds to the chopping frequency.

[0004] Various techniques have been used to reduce this ripple. At least in some cases, such conventional techniques are relatively expensive to implement, are disadvantageous in terms of current consumption, or are limited to a certain chopping frequency.

[0005] There is therefore a need to provide improved techniques for reducing chopper ripple. SUMMARY

[0006] The circuits and methods according to the present invention meet this requirement. Advantageous further developments are the following.

[0007] According to a first aspect of the present disclosure, a chopper amplifier circuit is proposed. The chopper amplifier can also be referred to as a Zerhacker amplifier. The chopper amplifier circuit comprises a modulator circuit that is switched at a chopping frequency, the modulator circuit being designed to convert a DC measurement voltage (DC = direct current) into an AC measurement voltage (AC = alternating current), i.e. an alternating voltage, at the chopping frequency. The chopper amplifier circuit further comprises an amplifier circuit having an inverting input and a non-inverting input for the AC measurement voltage, and an inverting output and a non-inverting output for the amplified AC measurement voltage. The chopper amplifier circuit further comprises a demodulator circuit that is switched at the chopping frequency, the demodulator circuit being designed to convert the amplified AC measurement voltage into an amplified DC measurement voltage. The demodulator circuit is designed for directly and capacitively coupling each inverting and non-inverting output of the amplifier circuit to each inverting and non-inverting input of a summing circuit during different switching phases (of the modulator or demodulator circuit).

[0008] The DC measurement voltage or the amplified DC measurement voltage can be a direct current voltage, respectively. However, it is also conceivable that only signals are considered which vary slowly with respect to the chopping frequency, so that the measurement voltage or the amplified DC measurement voltage can be considered as a quasi-direct current voltage during the switching phase.

[0009] The amplifier circuit may, for example, comprise a simple single-loop amplifier, an operational amplifier, an instrument amplifier, a comparator or an ADC input.

[0010] Compared to conventional chopping amplifier circuits, the structure of the demodulator circuit presented herein is able to reduce the chopping ripple present at the output of the chopping amplifier circuit. The chopping ripple refers to the offset voltage amplified by the amplifier circuit and demodulated by the demodulator circuit. The conventional demodulation of the offset direct current voltage then leads to an undesired alternating voltage (chopping ripple). The implementation and the functioning of the presented demodulator circuit can reduce the chopping ripple.

[0011] According to some embodiments, the demodulator circuit is designed to, during a first switching phase of the modulator (demodulator) circuit, directly couple the non-inverted output of the amplifier circuit to a first non-inverted input of the summing circuit (forming an average) and to capacitively couple the non-inverted output of the amplifier circuit to a second non-inverted input of the summing circuit, and to directly couple the inverted output of the amplifier circuit to a first inverted input of the summing circuit and to capacitively couple the inverted output of the amplifier circuit to a second inverted input of the summing circuit. The demodulator circuit is further designed to, during a second switching phase of the modulator (demodulator) circuit, directly couple the non-inverted output of the amplifier circuit to the second inverted input of the summing circuit and to capacitively couple the non-inverted output of the amplifier circuit to the first inverted input of the summing circuit, and to directly couple the non-inverted output of the amplifier circuit to the second inverted input of the summing circuit and to capacitively couple the non-inverted output of the amplifier circuit to the first inverted input of the summing circuit. By this alternating direct and capacitive coupling of the amplifier output to the inputs of the summing circuit for averaging, the chopping ripple can be smoothed.

[0012] According to some embodiments, the demodulator circuit is designed for directly coupling the non-inverting output of the amplifier circuit via a first signal path with a first non-inverting input of the summing circuit and for directly coupling the inverting output of the amplifier circuit via a second signal path with a first inverting input of the summing circuit during a first switching phase. The demodulator circuit is further designed for directly coupling the non-inverting output of the amplifier circuit via a third signal path with a second inverting input of the summing circuit and for directly coupling the inverting output of the amplifier circuit via a fourth signal path with a second non-inverting input of the summing circuit during a second switching phase of the modulator (demodulator) circuit. The first and fourth signal paths are coupled to each other via a first capacitor. The fourth signal path is coupled to ground via a second capacitor. The second and third signal paths are coupled to each other via a third capacitor. The third signal path is coupled to ground via a fourth capacitor. The first and second differential inputs of the summing circuit can thus be continuously equalized to each other. As a result, the summing circuit can form an average value with less ripple.

[0013] According to some embodiments, the first capacitor is larger than the second capacitor. Likewise, the third capacitor can be larger than the fourth capacitor. The first and second differential inputs of the summing circuit can thus be continuously equalized to each other during the successive switching phases.

[0014] According to some embodiments, the first and third capacitors each have the same size. Likewise, the second and fourth capacitors each have the same size.

[0015] According to some embodiments, the first capacitor is 10 to 20 times larger than the second capacitor. Likewise, the third capacitor can be 10 to 20 times larger than the fourth capacitor. This can result in a particularly advantageous equalization of the differential inputs of the summing circuit.

[0016] According to some embodiments, the demodulator circuit is designed for directly coupling the non-inverting output of the amplifier circuit via a first and a second signal path with a first non-inverting input of the summing circuit and for capacitive coupling the non-inverting output of the amplifier circuit via a third and a fourth signal path with a second non-inverting input of the summing circuit and for directly coupling the inverting output of the amplifier circuit via a fifth and a sixth signal path with a first inverting input of the summing circuit and for capacitive coupling the inverting output of the amplifier circuit via a seventh and an eighth signal path with a second inverting input of the summing circuit during a first switching phase. The demodulator circuit is designed for directly coupling the non-inverting output of the amplifier circuit via a ninth and a tenth signal path with the second inverting input of the summing circuit and for capacitive coupling the non-inverting output of the amplifier circuit via an eleventh and a twelfth signal path with the first inverting input of the summing circuit and for directly coupling the inverting output of the amplifier circuit via a thirteenth and a fourteenth signal path with the second non-inverting input of the summing circuit and for capacitive coupling the inverting output of the amplifier circuit via a fifteenth and a sixteenth signal path with the first non-inverting input of the summing circuit during a second switching phase of the modulator (demodulator) circuit. With this embodiment, the chopping ripple can be further reduced.

[0017] According to some embodiments, the demodulator circuit is designed for directly coupling the non-inverting output of the amplifier circuit with the first non-inverting input of the summing circuit via the first and second signal paths and for directly coupling the inverting output of the amplifier circuit with the first inverting input of the summing circuit via the third and fourth signal paths during a first switching phase. The demodulator circuit is further designed for directly coupling the non-inverting output of the amplifier circuit with the second inverting input of the summing circuit via the fifth and sixth signal paths and for directly coupling the inverting output of the amplifier circuit with the second non-inverting input of the summing circuit via the seventh and eighth signal paths during a second switching phase of the modulator (demodulator) circuit. The first and the eighth signal paths are coupled to each other via a first capacitor. The eighth signal path is coupled to ground via a second capacitor. The second and the seventh signal paths are coupled to each other via a third capacitor. The second signal path is coupled to ground via a fourth capacitor. The third and the fifth signal paths are coupled to each other via a fifth capacitor. The fifth signal path is coupled to ground via a sixth capacitor. The fourth and the sixth signal paths are coupled to each other via a seventh capacitor. The fourth signal path is coupled to ground via an eighth capacitor. The first and the second differential inputs of the summing circuit can thus be better balanced with each other during the successive switching phases.

[0018] According to some embodiments, a first output of the modulator circuit is directly connected with an inverting input of the amplifier circuit and a second output of the modulator circuit is directly connected with a non-inverting input of the amplifier circuit. According to some embodiments, additionally or alternatively, a non-inverting input of the modulator circuit is directly connected with a signal source and an inverting input of the modulator circuit is directly connected with the signal source. Thus, the input signal can be directly connected with the modulator circuit. The amplifier input can also be directly connected with the output of the modulator circuit. By the proposed demodulator circuit it is meant that a (large) input capacitor can be omitted.

[0019] According to some embodiments, the chopper amplifier circuit further comprises a Hall sensor designed for a spin current operation to provide a measurement voltage. A sensor based on the Hall effect, also known as a Hall sensor, is commonly used as a magnetic field sensor. A Hall sensor comprises one or more Hall effect sensor elements that measure the magnetic field strength and / or direction. These measurements are used to obtain parameters such as distance, position, and rotational speed. However, due to mechanical load, doping, and geometric errors, the Hall sensor elements can show an offset at their output. The Hall sensor elements also exhibit an offset drift, which can lead to an unpredictable and time-varying output error. This offset in the Hall sensor elements can be reduced by a three-phase electrical method or a spin current method, in which the bias current of the Hall sensor elements is spun spatially around the Hall sensor elements, while the output signal is simultaneously averaged over time. This can reduce the offset and the offset drift. The chopper amplifier circuit receives and amplifies the output signal of the Hall sensor elements. Embodiments of the present disclosure can further reduce the residual offset at the output of the chopper amplifier circuit.

[0020] According to another aspect of the present disclosure, a method for operating a chopper amplifier circuit is also presented. The method comprises directly coupling the non-inverting and inverting outputs of an amplifier of the chopper amplifier circuit during different switching phases, and capacitively coupling each of the inverting and non-inverting inputs of a summing circuit.

[0021] According to some embodiments, during a first switching phase, the non-inverting output of the amplifier circuit is directly coupled to a first non-inverting input of the summing circuit and capacitively coupled to a second non-inverting input of the summing circuit. During the first switching phase, the inverting output of the amplifier circuit is also directly coupled to a first inverting input of the summing circuit and capacitively coupled to a second inverting input of the summing circuit. During a second switching phase, the non-inverting output of the amplifier circuit is directly coupled to the second inverting input of the summing circuit and capacitively coupled to the first inverting input of the summing circuit. During the second switching phase, the non-inverting output of the amplifier circuit is directly coupled to the second inverting input of the summing circuit and capacitively coupled to the first inverting input of the summing circuit.

[0022] According to some embodiments, during the first switching phase, the non-inverting output of the amplifier circuit is directly coupled with the first non-inverting input of the summing circuit via a first signal path. During the first switching phase, the inverting output of the amplifier circuit is also directly coupled with the first inverting input of the summing circuit via a second signal path. During the second switching phase, the non-inverting output of the amplifier circuit is directly coupled with the second inverting input of the summing circuit via a third signal path. During the second switching phase, the inverting output of the amplifier circuit is also directly coupled with the second non-inverting input of the summing circuit via a fourth signal path. The first and fourth signal paths are coupled to each other via a first capacitor, the fourth signal path is coupled to ground via a second capacitor, the second and third signal paths are coupled to each other via a third capacitor, and the third signal path is coupled to ground via a fourth capacitor.

[0023] According to some embodiments, the first capacitor is larger than the second capacitor and the third capacitor is larger than the fourth capacitor.

[0024] According to some embodiments, the first and third capacitors are each the same size, and the second and fourth capacitors are each the same size.

[0025] According to some embodiments, the first capacitor is 10 to 20 times larger than the second capacitor, and the third capacitor is 10 to 20 times larger than the fourth capacitor.

[0026] Using an input modulator, an amplifier, an (grounded) output capacitor connected directly to the output of the amplifier for DC suppression, and a coupling capacitor (stacked capacitor) connected to the output capacitor, chopper ripple suppression can be achieved through the switching capacitor leakage effect of the stacked capacitor (capacitive voltage divider). Thus, a chopper amplifier with offset compensation can be provided with low chopper ripple noise, low jitter effects, low signal delay, and small chip area.

[0027] According to another aspect of the present disclosure, a chopper amplifier circuit is proposed, having a modulator circuit clocked at a chopper frequency, which is designed to convert a measurement voltage into an AC measurement voltage in dependence on the chopper frequency. The chopper amplifier circuit further comprises an amplifier circuit having an inverting input and a non-inverting input for the AC measurement voltage, and an inverting output and a non-inverting output for an amplified AC measurement voltage. A demodulator circuit clocked at the chopper frequency is designed to convert the amplified AC measurement voltage into an amplified measurement voltage. The inverting output of the amplifier circuit is coupled to a first input of the demodulator circuit via a first capacitor in a first signal path. The non-inverting output of the amplifier circuit is coupled to a second input of the demodulator circuit via a second capacitor in a second signal path. Furthermore, a discharge resistance circuit is provided, which is coupled between the first and the second signal path at the output side of the two capacitors. According to embodiments of this basic circuit arrangement, the chopper ripple can likewise be reduced by means of the discharge resistance circuit. Due to the coupling via the discharge resistance circuit, the differential voltage between the non-inverting and the inverting signal path can be reduced in a DC manner, thus also reducing the chopper ripple.

[0028] According to some embodiments, the resistance value of the discharge resistance circuit is in a range such that the time constant of the first or second capacitor together with the discharge resistance circuit is in the range of 10 / fchop to 200 / fchop, fchop denoting the chopper frequency. Thus, the resistance of the discharge resistance circuit can be designed to be high-ohmic in order to achieve a longer discharge period.

[0029] According to some embodiments, the discharge resistance circuit comprises a first discharge resistance device coupled between an output terminal of the first capacitor and a reference potential, and a second discharge resistance device coupled between an output terminal of the second capacitor and the reference potential. The reference potential may, for example, be a common mode or common mode potential.

[0030] According to some embodiments, the discharge resistance circuit comprises a switching device designed to connect the first discharge resistance device between the first capacitor and the reference potential and to connect the second discharge resistance device between the second capacitor and the reference potential during a discharge period. Thus, the discharge of the capacitors can be performed purposefully during the discharge period. According to some embodiments, the discharge period corresponds to a period between a first and a second switching phase of the modulator circuit.

[0031] According to some embodiments, the switching device is operated clocked such that the discharge period is located between the first and the second switching phase of the modulator circuit. The clock frequency of the discharge resistance circuit can be synchronous to the chopper frequency or generated pseudo-randomly. Thereby, the intermodulation effects with the input signal can be further reduced.

[0032] According to some embodiments, the duty cycle of the switching device is in the range from 0.1% to 5%.

[0033] According to some embodiments, the discharge resistance circuit can have one or more switched capacitors. For switched capacitors, a resistance of R = 1 / f s C can be implemented, wherein f s denotes the switching frequency of the switched capacitor. Compared to resistors of integrated circuits, capacitors can be manufactured more precisely and high resistance values can be achieved with small capacitors.

[0034] According to some embodiments, the discharge resistance circuit can have one or more voltage-controlled pseudo resistors comprising MOS transistors connected in series. The pseudo resistors can use diode-connected MOS elements, which work in the subthreshold region, and which take up less area compared to discrete elements.

[0035] According to some embodiments, a first output of the modulator circuit is directly connected to the inverting input of the amplifier circuit and a second output of the modulator circuit is directly connected to the non-inverting input of the amplifier circuit. According to some embodiments, additionally or alternatively, the non-inverting input of the modulator circuit is directly connected to a signal source and the inverting input of the modulator circuit is directly connected to the signal source. Thus, the input signal can be connected to the modulator circuit. The amplifier input can also be directly connected to the output of the modulator circuit. The proposed demodulator circuit means that a (large) input capacitor can be omitted.

[0036] According to some embodiments, the chopper amplifier circuit further comprises a low-pass or band-stop filter circuit of an order less than or equal to three, which is coupled on the output side to the demodulator circuit. Residual ripple can thus be precisely filtered out at the chopping frequency f chop . This type of filter can also be referred to as a twin-T filter, since R-C-R is arranged in one path and C-R-C in a parallel path like a T. A certain frequency is filtered out very selectively, here preferably f chop . Due to the advantageous design of the proposed demodulator circuit, a low-order low-pass filter circuit is already sufficient to sufficiently suppress the residual chopper ripple pulses (voltage peaks).

[0037] According to some embodiments, the chopper amplifier circuit further comprises a Hall sensor designed for a current-rotating operation to provide a measurement voltage.

[0038] According to another aspect of the present disclosure, a method for operating a chopper amplifier circuit is proposed, wherein the inverting output of the amplifier is coupled via a first capacitor to a first input of a demodulator circuit and the non-inverting output of the amplifier is coupled via a second capacitor to a second input of the demodulator circuit. A discharge resistance circuit is coupled to the output taps of the first and second capacitors.

[0039] According to some embodiments, the input terminal of the first capacitor is coupled with the inverting output of the amplifier, and the output terminal of the first capacitor is coupled with the first input of the demodulator circuit. The input terminal of the second capacitor is coupled with the non-inverting output of the amplifier, and the output terminal of the second capacitor is coupled with the second input of the demodulator circuit.

[0040] According to some embodiments, the output terminal of the first capacitor is coupled with a first terminal of a first discharge resistor arrangement, a second terminal of the first discharge resistor arrangement is coupled with a predetermined reference potential, the output terminal of the second capacitor is coupled with a first terminal of a second discharge resistor arrangement, and a second terminal of the second discharge resistor arrangement is coupled with the predetermined reference potential.

[0041] According to some embodiments, the first and second discharge resistor arrangements are coupled with the predetermined reference potential by means of clock switches during a discharge period, respectively.

[0042] According to some embodiments, the discharge period corresponds to a period between a first and a second switching phase of the demodulator circuit.

[0043] Using an input modulator, an amplifier, an output capacitor (AC-coupled) connected directly between the amplifier output and the demodulator, and a duty cycle resistor or a switched capacitor resistor or a pseudo resistor (with a MOS transistor connected in the blocking direction for voltage biasing), a chopper ripple rejection can be achieved. Thus, a chopper amplifier with offset compensation can be provided with low chopper ripple noise, low jitter effects, low signal delay (latency), and small chip area. BRIEF DESCRIPTION OF DRAWINGS

[0044] Some examples of devices and / or methods are explained in more detail below, by way of example only, with reference to the drawings. Herein:

[0045] Figure 1 The basic concept of a chopper amplifier according to embodiments of the present disclosure with a stacked capacitor demodulator and inherent chopper ripple rejection is shown in connection with a rotating Hall sensor;

[0046] Figure 2 The start-up behavior of a chopper amplifier according to Figure 1 embodiments of the present disclosure is shown.

[0047] Figure 3 The symmetric concept of a chopper amplifier according to another embodiment of the present disclosure with a stacked capacitor demodulator and inherent chopper ripple rejection is shown in connection with a rotating Hall sensor;

[0048] Figure 4A Fig. B shows the estimated and simulated attenuated chopper ripple caused by a switched capacitor divider of stacked and grounded capacitors;

[0049] Figure 5A comparison of various analog demodulation techniques with embodiments of the present disclosure is shown;

[0050] Figure 6 The basic concept of a chopper amplifier with inherent chopper ripple rejection according to another embodiment of the present disclosure is shown in connection with a rotating Hall sensor;

[0051] Figure 7 An illustration of a pseudo-random pulse used to suppress an offset DC voltage in front of a chopper demodulator during non-overlapping chopper phases is shown after several chopper phases;

[0052] Figure 8 An embodiment of an AC-coupled demodulation method using a switched capacitor as a discharge resistor is shown;

[0053] Figure 9 An embodiment of an AC-coupled demodulation method with a pseudo-resistor as a discharge resistor is shown.

[0054] Figure 10 Simulation waveforms of demodulation output signals from three different chopper amplifier topologies are shown;

[0055] Figure 11 The influence of different switching resistors on the settling time and residual ripple of the proposed chopper amplifier is shown. DETAILED DESCRIPTION

[0056] Some examples will now be described in more detail with reference to the drawings. Other possible examples are not limited to the features of these embodiments described in detail. These embodiments can have features in common with each other as well as with other examples. In addition, terminology used in connection with a particular example herein is not intended to be limiting but is for descriptive purposes only.

[0057] Throughout the description of the drawings, the same or similar reference numerals refer to the same or similar elements or features, which can be implemented identically or by modifications thereof, while providing the same or similar functionality. In the drawings, the thicknesses of lines, layers, and / or regions can be exaggerated for clarity.

[0058] It is to be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements can be present. If used, the transitional term “comprising” is to be construed as open and inclusive rather than limiting or exclusive. If used, the terms “comprises” or “comprising” are to be construed as open and inclusive rather than limiting or exclusive. If used herein, the term “and / or” is to be construed as an inclusive term meaning one, some, or all of the associated listed items. Similarly, the terms “one or more” and “at least one” are to be understood as including any one of or a combination of one or more items related to the term in the context of the term. Recitation of ranges of values herein are merely intended to serve as a shorthand method of referring individually to each separate value falling within the range, unless the context indicates otherwise. Similarly, the term “at least one of’ is to be understood as including any one of or a combination of one or more items related to the term in the context of the term.

[0059] When using a singular form such as "a", "an" and "the" and using only a single element, neither explicitly nor implicitly defined as mandatory, further examples can also implement the same functionality using multiple elements. When a functionality is later described as implemented using multiple elements, further examples can implement the same functionality using a single element or processing entity. It will be further understood that the terms "comprises", "comprising", "has", "having", "includes" and / or "including" when used, specify the presence of stated features, integers, steps, operations, processes, elements, components and / or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, processes, elements, components and / or groups thereof.

[0060] Figure 1 A chopper amplifier circuit 100 according to a first embodiment of the present disclosure is shown. The chopper amplifier circuit 100 comprises a modulator circuit 110 clocked at a chopper frequency fchop. The modulator circuit 110 is designed for converting a DC input voltage originating from a signal source 150 into an AC input voltage. During a switching phase (chopping phase) PHI or PH2 of the modulator circuit 110, the DC input voltage can be assumed to be approximately constant. However, the DC input voltage also varies over time, but with a frequency significantly lower than the chopper frequency fchop. chop In the shown embodiment, the signal source 150 is designed as a Hall sensor, which can be operated in a so-called rotating current operation. During a first switching phase PHI, a first current flows through the junctions 151, 152, so that a first Hall voltage can be tapped at the junctions 153, 154. During a subsequent second switching phase PH2, a second current flows through the junctions 153, 154, so that a second Hall voltage can be tapped at the junctions 151, 152, etc. It goes without saying that embodiments of the present disclosure can also be operated with other signal sources that can be combined with a chopper amplifier.

[0061] On the output side of the modulator circuit 110, the chopper amplifier circuit 100 further has an amplifier 120 with an inverting input 121 and a non-inverting input 122 for the AC input voltage, e.g. the Hall voltage. The inputs 121, 122 can also be referred to as negative and positive inputs and form a differential input. The amplifier 120 further has an inverting output 123 and a non-inverting output 124 for the amplified AC measurement voltage. Likewise, the outputs 123, 124 can be referred to as negative and positive outputs and form a differential output. For example, the amplifier 120 can be an operational amplifier. However, other common implementations of an amplifier are also conceivable.

[0062] The inverting output of modulator circuit 110 is directly connected to the inverting input 121 of amplifier 120 (e.g., without an intermediate connecting capacitor), and the non-inverting output of modulator circuit 110 is directly connected to the non-inverting input 122 of amplifier 120. The non-inverting input of modulator circuit 100 is directly connected to signal source 150 (connectors 151, 153), and the inverting input of modulator circuit 110 is directly connected to signal source 150 (connectors 152, 154).

[0063] On the output side of amplifier 120, chopper amplifier circuit 100 includes a chopper frequency f chop The demodulator circuit 130 is designed to convert the AC voltage amplified by amplifier 120 back to an amplified DC voltage. According to embodiments of this disclosure, the demodulator circuit 130 is designed to directly and capacitively couple each of the inverting and non-inverting outputs 123, 124 of amplifier 120 to each of the inverting and non-inverting inputs of averaging and summing circuit 140 during different switching phases PH1, PH2. The summing circuit 140 can be considered as part of the demodulator circuit 130.

[0064] exist Figure 1 In the illustrated embodiment, the summing circuit 140 is shown as a summing amplifier with two differential inputs. The summing circuit 140 has a first non-inverting input 141, a first inverting input 142, a second non-inverting input 143, and a second inverting input 144. Inputs 141 and 142 form the first differential inputs of the summing circuit, and inputs 143 and 144 form the second differential inputs of the summing circuit 140. It will be apparent to those skilled in the art that the differential inputs are used for averaging. It should be noted that the summing circuit 140 can also be implemented in different ways, for example, using comparators, amplifiers, or ADC inputs.

[0065] Modulator circuit 110 and demodulator circuit 130 each have multiple switches that open and close during different switching phases PH1 and PH2. The switching of modulator circuit 110 and demodulator circuit 130 is synchronized. Figure 1 In the illustrated embodiment, the demodulator circuit 130 is designed to: directly couple the non-inverting output 124 of the amplifier 120 to the first non-inverting input 141 of the summing circuit 140, and capacitively couple (via capacitor 135) to the second non-inverting input 143 of the summing circuit 140 during the first switching phase PH1. Furthermore, Figure 1The demodulator circuit 130 is designed to: during the first switching phase PH1, directly (closely) couple the inverting output 123 of amplifier 120 to the first inverting input 142 of summing circuit 140, and capacitively couple (via capacitor 137) to the second inverting input 144 of summing circuit 140. The differential outputs 123, 124 of amplifier 120 are therefore directly or closely coupled to the first differential inputs 141, 142 of summing circuit 140 during the first switching phase PH1, and capacitively coupled to the second differential inputs 143, 144 of summing circuit 140.

[0066] Demodulator circuit 130 is also designed to: during the second switching phase PH2, directly couple the non-inverting output 124 of amplifier 120 to the second inverting input 144 of summing circuit 140, and capacitively couple (via capacitor 137) to the first inverting input 142 of summing circuit 140. Demodulator circuit 130 is also designed to: during the second switching phase PH2, directly couple the inverting output 123 of amplifier circuit 120 to the second non-inverting input 143 of summing circuit 140, and capacitively couple (via capacitor 135) to the first non-inverting input 141 of summing circuit 140. In the second switching phase PH2, the differential output of amplifier 120 is therefore directly or indirectly coupled to the second differential inputs 143, 144 of summing circuit 140, and capacitively coupled to the first differential inputs 141, 142 of summing circuit 140.

[0067] exist Figure 1 In the illustrated embodiment, during the first switching phase PH1, demodulator circuit 130 directly couples the non-inverting output 124 of amplifier 120 to the first non-inverting input 141 of summing circuit 140 via a first signal path 131. Demodulator circuit 130 also directly couples the inverting output 123 of amplifier 120 to the first inverting input 142 of summing circuit 140 via a second signal path 132 during the first switching phase PH1. During the second switching phase PH2, demodulator circuit 130 directly couples the non-inverting output 124 of amplifier 120 to the second inverting input 144 of summing circuit 140 via a third signal path 133. During the second switching phase PH2, demodulator circuit 130 directly couples the inverting output 123 of amplifier 120 to the second non-inverting input 143 of summing circuit 140 via a fourth signal path 134. The first signal path 131 and the fourth signal path 134 are coupled to each other via coupling capacitor 135. The fourth signal path 134 is coupled to ground via output capacitor 136. The second signal path 132 and the third signal path 133 are coupled to each other via coupling capacitor 137. The third signal path 133 is coupled to ground via output capacitor 138.

[0068] The coupling capacitance 135 is designed to be larger than the output capacitance 136. Likewise, the coupling capacitance 137 is designed to be larger than the output capacitance 138. The size of the two coupling capacitances 135, 137 can be the same for the same signal ratio at the two differential inputs of 141, 142 and 143, 144 of the summing circuit 140. Likewise, the size of the two output capacitances 136, 138 can be the same. As Figure 1 shown, the coupling capacitances 135, 137 can be 10 to 20 times the size of the output capacitances 136, 138.

[0069] The operation of the chopper amplifier circuit 100 will now be described with reference to Figure 2 the timing diagram in Fig. 2.

[0070] After switching on the operating voltage, all the capacitor nodes +S1+O, +S2-O, -S1-O, -S2+O are at 0 V. The input signal from the signal source 150 also starts at 0 V here and rises only after many chopping cycles in this example, so as to then (after more chopping cycles) assume a constant value (different from 0 V). In the chopping phase PHI, the node +S1+O is charged to the amplification offset voltage of the amplifier 120 (the + offset voltage of the Hall sensor) by direct coupling. There is no signal voltage yet in the first phase PHI. The upper plate of the coupling capacitance 135 and the input of the summing circuit 140 forming the average value are directly electrically coupled with the positive amplifier output 124. The node +S2-O is decoupled from the amplifier output 124 in PHI, but also charged to the partial voltage of +S1+O together with the 0 V capacitor voltage division ratio. Thus, only a small part of this voltage at the node +S2-O is calculated as C st / (C st +C gnd ), for example, if the capacitance ratio C st / C gnd = 3, only 75% of the +S1+O voltage. Here, C st denotes the capacitance value of the coupling capacitance, and C gnd denotes the capacitance value of the output capacitance.

[0071] In the chopping phase PH2, the node +S2-O is charged to the negative value of the amplification offset of the amplifier 120 (+synchronous negative offset of the Hall plate), since this node is directly electrically connected to the negative output 123 of the amplifier 120. At the same time, however, in the input modulator 110 (chopping modulator), the input signal is inverted and connected to the differential amplifier inputs 121, 122. The differential inputs 121, 122 of the amplifier 120 thus see the offset as a DC value, while the input signal is received as an AC signal with the chopping frequency of the modulator 110 (and the synchronous chopping demodulator 130). Since during the transition from the phase PHI to the phase PH2, the node +S2-O is reloaded from +75% of the offset to -100% of the offset, a likewise large change signal follows at the node +S1+O, since the top plate of the coupling capacitor 135 is only loaded with a negligible large parasitic capacitance (i.e. there is no noteworthy capacitive voltage divider that reduces this dynamic capacitive voltage coupling).

[0072] The node +S1+O in the circuit is always charged to the positive offset in the PHI phase by direct coupling, while the node S2-O is always charged to the negative offset in the PH2 phase by direct coupling. Due to the capacitive voltage divider in the PHI phase, only a partial voltage change is taken over at the node S1+O. However, in the PH2 phase, the full voltage change is taken over from the node S2-O to the node S1+O. Ultimately, however, with the decay of the AC voltage, the positive offset voltage will occur at the node S1+O and the negative offset voltage will occur at the node S2-O if there is no further input signal. However, the average value of the two voltages is also 0 V and the follower circuit 140 that forms the average value (or sum) also only sees a 0 V input signal in the so-called steady state and without superimposed offset or offset ripple (ripple with chopping frequency).

[0073] If the input signal now changes, the amplifier 120 (and the nodes directly or dynamically via capacitive coupling) is able to follow the input signal. The delay time only depends on the amplifier bandwidth and not on the chopping frequency or the chopping phase with respect to the input signal. This means that the system can work continuously (continuous time) and without sampling effects (sampling effects) such as sampling and holding circuits or switched capacitor circuits. Although the capacitors in the circuit 100 are also switched on and off, any signal change is completely preserved at the output without any aliasing effects becoming effective, even in the middle of a chopping phase. Furthermore, by the time-continuous mode of operation, the switched capacitor also does not generate kT / C noise, which occurs in switched capacitor circuits, for example.

[0074] In the enlarged time representation of the signal curve, it can be seen that the division ratio is 75% in the phase PH2 of the previous voltage alternation. This causes the alternating voltage to decay. The asymmetry of the capacitive divider ratio in the phase PH1 (75%) and the phase PH2 (100%) still causes some side effects, which can be eliminated, however, by embodiments according to Figure 3 .

[0075] Figure 3 A chopper amplifier circuit 300 according to a further embodiment is shown.

[0076] In contrast to the chopper amplifier circuit 100 shown in Figure 1 , Figure 3 the chopper amplifier circuit 300 shown has a demodulator circuit 330, which is structured more symmetrically than Figure 1 .

[0077] The demodulator circuit 330 is designed for directly coupling the non-inverting output 124 of the amplifier 120 via a first signal path 331 and via a second signal path 332 with the first non-inverting input 141 of the summing circuit 140 during the first switching phase PH1. During the first switching phase PH1, the non-inverting amplifier output 124 is capacitively coupled via a third signal path 333 (via a capacitor 351) and via a fourth signal path 334 (via a capacitor 353) with the second non-inverting input 143 of the summing circuit 140. The demodulator circuit 330 is further designed for directly coupling the inverting amplifier output 123 via a fifth signal path 335 and via a sixth signal path 336 with the first inverting input 142 of the summing circuit 140 during the first switching phase PH1. The demodulator circuit 330 is further designed for capacitively coupling the inverting amplifier output 123 via a seventh signal path 337 (via a capacitor 355) and via an eighth signal path 338 (via a capacitor 357) with the second inverting input 144 of the summing circuit 140 during the first switching phase PH1. The differential outputs 123, 124 of the amplifier 120 are thus directly or immediately coupled with the first differential inputs 141, 142 of the summing circuit 140 and capacitively coupled with the second differential inputs 143, 144 of the summing circuit 140 in the first switching phase PH1. The signal guidance from each amplifier output to each summing circuit input always takes place through two different signal paths.

[0078] The demodulator circuit 330 is designed for directly coupling the non-inverted amplifier output 124 via a ninth signal path 339 and via a tenth signal path 340 with the second inverting input 141 of the summing circuit 140 during the second switching phase PH2, and for capacitively coupling the non-inverted amplifier output 124 via an eleventh signal path 341 (via the capacitor 355) and via a twelfth signal path 342 (via the capacitor 357) with the first inverting input 142 of the summing circuit 140. In the second switching phase PH2, the inverted amplifier output 123 is directly coupled via a thirteenth signal path 343 and via a fourteenth signal path 344 with the second non-inverting input 143 of the summing circuit 140. Furthermore, in the second switching phase PH2, the inverted amplifier output 123 is capacitively coupled via a fifteenth signal path 345 (via the capacitor 351) and via a sixteenth signal path 346 (via the capacitor 353) with the first non-inverting input 141 of the summing circuit 140. In the second switching phase PH2, the differential outputs of the amplifiers 120 are thus directly or immediately coupled with the second differential input 143, 144 of the summing circuit 140 and capacitively coupled with the first differential input 141, 142 of the summing circuit 140. The signal routing from each amplifier output to each summing circuit input always takes place through two different signal paths.

[0079] During the first switching phase PH1, the differential amplifier outputs 123, 124 are thus directly coupled with the first differential input 141, 142 of the summing circuit 140 and capacitively coupled with the second differential input 143, 144 of the summing circuit 140. In contrast to this, Figure 1 each amplifier output 123, 124 is directed to the inputs of the summing circuit 140 via two different signal paths, respectively. During the second switching phase PH2, the differential amplifier outputs 123, 124 are directly coupled with the second differential input 143, 143 of the summing circuit 140 and capacitively coupled with the first differential input 141, 142 of the summing circuit 140. Here, in contrast to this, Figure 1 each amplifier output 123, 124 is directed to the inputs of the summing circuit 140 via two different signal paths, respectively.

[0080] The demodulator circuit 330 is thus designed for directly coupling the non-inverting amplifier output 124 via signal paths 331 and 332 to the first non-inverting input 141 of the summing circuit 140 during the first switching phase PHi. The demodulator circuit 330 is designed for directly coupling the inverting amplifier output 123 via signal paths 335 and 336 to the first inverting input 142 of the summing circuit 140 during the first switching phase PHi. The demodulator circuit 330 is designed for directly coupling the non-inverting amplifier output 124 via signal paths 337 and 338 to the second inverting input 144 of the summing circuit 140 during the second switching phase PH2. The demodulator circuit 330 is further designed for directly coupling the inverting amplifier output 123 via signal paths 343 and 344 to the second non-inverting input 143 of the summing circuit during the second switching phase PH2. The signal path 331 and the signal path 343 are coupled to each other via a coupling capacitor 351. The signal path 343 is coupled to ground via an output capacitor 352. The signal path 332 and the signal path 344 are coupled to each other by a coupling capacitor 353. The signal path 32 is coupled to ground via an output capacitor 354. The signal path 335 and the signal path 337 are coupled to each other via a coupling capacitor 355. The signal path 337 is coupled to ground via an output capacitor 356. The signal path 338 and the signal path 336 are coupled to each other via a coupling capacitor 357. The signal path 336 is coupled to ground via an output capacitor 358.

[0081] Here, the coupling capacitors can each also have the same size. The output capacitors can likewise each have the same size. The coupling capacitors can be 10 to 20 times larger than the output capacitors.

[0082] In the embodiment of Figure 3 , the same capacitive divider ratio is produced in each switching phase PHi, PH2, since in each phase there is a direct connection of the upper plate (terminal) of the coupling capacitor C st to the output capacitor C gnd , and further to the lower plate of the coupling capacitor C st .

[0083] In each switching phase PH1, PH2, the same number of output capacitors are connected to the differential amplifier outputs 123, 124, and the same number of coupling capacitors are connected to the subsequent summing circuit 140 (e.g., a comparator, ADC, or output amplifier). The upper plate of the grounded output capacitor is adjusted according to the differential signal and negative offset from amplifier 120 (and the rotating Hall plate). The upper plate of the (floating) coupling capacitor is also adjusted according to the differential signal. However, these nodes contain a positive offset. In the (differential) summing circuit 140, the signal is averaged and the offset is eliminated. The summing circuit 140 can be a comparator, amplifier, or ADC input with dual differential inputs. The doubled offset voltage tends to stabilize after several chopping cycles, and the DC voltage is canceled out in the summing circuit 140, thus the chopping offset ripple decays after several chopping cycles. However, the signal remains fast at the input of the summing circuit 140 because, during one switching phase, the upper node of the coupling capacitor is directly connected to the output of amplifier 120 and simultaneously to the input of summing circuit 140; and during another switching phase, amplifier 120 capacitively and rapidly couples from the lower node of the coupling capacitor to the upper node, and finally to summing circuit 140. The settling time (Einschwingzeit) of the attenuated chopper offset ripple is defined by the ratio of the ground output capacitor to the coupling capacitor.

[0084] In the coupling capacitor (C st ) and grounded output capacitor (C gnd When the ratio of 1pF / 0.25pF is 1pF, the settling time of the offset ripple is given by the voltage divider effect of the switched capacitor: for each half-chop cycle, C st / (C gnd +C st When the coupling capacitors are symmetrically arranged: after the first half-chop cycle, 1pF / 1.25pF = 0.8 of the original offset step size; after two half-chop cycles, 0.8^2 = 0.64, and so on. This relationship is as follows: Figure 4A As shown in B.

[0085] After 20 half-chop cycles (= 10 full chopper cycles), the offset ripple decreases to about 1% after the theoretical offset step response. In reality, the offset changes very slowly compared to the chopper frequency, and ripple suppression is almost perfect during normal operation.

[0086] Figure 5 The diagram illustrates a performance comparison between embodiments of the present invention and conventional chopper amplifier implementations. Curve 510 shows a significant chopper offset ripple when using a conventional track-and-hold demodulator. Curve 520 shows the chopper offset ripple, which can be determined according to... Figure 1The embodiments implement a chopper offset ripple. The chopper offset ripple is indirectly proportional to the ratio of the coupling capacitor and the output capacitor to ground. The curve 530 shows that the chopper offset ripple can be implemented according to the embodiments of the present disclosure. Figure 3 The embodiments implement a chopper offset ripple. The chopper offset ripple is indirectly proportional to the ratio of the coupling capacitor and the output capacitor to ground. The curve 530 shows that the chopper offset ripple can be implemented according to the embodiments of the present disclosure.

[0087] In the case of using an input modulator 110, an amplifier 120, an (grounded) output capacitor directly connected to the output of the amplifier 120 for DC suppression, and a coupling capacitor (stacked capacitor) connected to the output capacitor, chopper ripple suppression can be achieved by the switched capacitor leakage effect of the coupling capacitor (capacitive voltage divider). Thus, an offset-compensated chopper amplifier with low chopper ripple noise, low jitter effect, low signal delay (latency), and small chip area can be provided.

[0088] Figure 6 Another embodiment of a chopper amplifier circuit 600 according to embodiments of the present disclosure is shown.

[0089] The chopper amplifier circuit 600 comprises again a modulator circuit 110 clocked at a chopper frequency, which is designed to convert a DC input voltage from a signal source 150 into an AC input voltage according to the chopper frequency. The chopper amplifier circuit further comprises an amplifier 120 arranged at the output side of the modulator circuit. The amplifier 120 has an inverting input 121 and a non-inverting input 122 for the AC input voltage obtained from the modulator 110. The inverting and non-inverting inputs 122 form a differential input.

[0090] The output of the modulator circuit 110 is directly or in other words immediately connected (e.g. without an intermediate connecting capacitor) to the inputs 121, 122 of the amplifier 120. The input of the modulator circuit 100 is directly connected to the output of the signal source 150.

[0091] The amplifier 120 has an inverting output 123 and a non-inverting output 124. The inverting output 123 and the non-inverting output 124 together form a differential output of the amplifier 120 for the amplified AC voltage. A demodulator circuit 630 clocked at the chopper frequency is provided at the differential amplifier output 123, 124, which is designed for converting the amplified AC voltage into an amplified DC output voltage. The inverting amplifier output 123 is coupled via a first capacitor 641 in a first signal path 642 to a first input 631 of the demodulator circuit 630. The non-inverting amplifier output 124 is coupled via a second capacitor 643 in a second signal path 644 to a second input 632 of the demodulator circuit. A discharge resistor circuit 650 coupled between the first signal path 642 and the second signal path 644 is located at the output side of the two capacitors 641, 643.

[0092] Figure 6The discharge resistor circuit 650 in the illustrated embodiment comprises a first discharge resistor 652 coupled between the output terminal of the first capacitor 641 and a reference potential 651. The discharge resistor circuit 650 further comprises a second discharge resistor 653 coupled between the output terminal of the second capacitor 643 and the reference potential 651. The input terminal of the first capacitor 641 is coupled with the inverting amplifier output 123. The input terminal of the second capacitor 643 is coupled with the non-inverting amplifier output 124. The discharge resistor circuit 650 further comprises a switching device 654 designed to connect the first discharge resistor 652 between the first capacitor 641 and the reference potential 651 and to connect the second discharge resistor between the second capacitor 643 and the reference potential 651 during at least one discharge period.

[0093] The reference potential 651 can be, for example, a common mode potential (common mode voltage) or can also be ground.

[0094] The discharge period preferably corresponds to the period between the first switching phase (chopping phase) PHI and the second switching phase PH2 of the modulator circuit 110. The two switching phases PHI and PH2 do not overlap. This is schematically shown in Figure 7 The two discharge resistors 652, 653 are thus connected with the reference potential 651 by means of the switching device 654 after the end of the switching phase PHI and before the start of the switching phase PH2. During the switching phases PHI and PH2, the discharge resistors 652, 653 are open, i.e. not connected with the reference potential 651. According to some embodiments, the duty cycle of the switching device 654 can be in the range from 0.1% to 5%. According to embodiments, the switch of the switching device 654 is closed in the period between the switching phases PHI and PH2 during the non-switching phases PHI and PH2. During the switching phases PHI and PH2, the switch of the switching device 654 is open. The switching points in time of the switching device 654 can, for example, also occur with the chopping frequency. However, in some embodiments, the clock frequency of the switching device 650 can also be chosen pseudo-randomly. The switching points in time of the switching device 650 are thus in any case arranged in the intermediate periods between two successive switching phases PHI and PH2, but not necessarily in each of these intermediate periods.

[0095] By means of the capacitive coupling of the amplifier outputs 123, 124 with the inputs of the demodulator circuit 630 and the discharge resistor circuit 650, the differential voltage between the non-inverting and inverting signal paths 644, 642 can be reduced in a DC manner, in turn also reducing the chopping ripple. A low-pass filter circuit 660 with a low order (here: first order) of less than or equal to three coupled on the output side with the demodulator circuit 630 is thus sufficient.

[0096] It has proven advantageous to design the discharge resistors 652, 653 relatively high ohmic, for example in the range of 1 MΩ, so that long discharge times occur. The clocked operation of the discharge resistors 652, 653 by the circuit arrangement 654 makes the resistors effectively become larger or have a higher resistance.

[0097] In particular when the discharge resistors 652, 653 are implemented in an integrated circuit, it can be problematic to implement very high ohmic resistors. Therefore, Figure 8 An embodiment of the chopper amplifier circuit 800 is shown, in which the discharge resistors 652, 653 are implemented by switched capacitors 852, 853. Switched-capacitor filters, or often abbreviated SC filters, are known as electronic filters in which ohmic resistors are replaced by switched capacitors. Time-discrete filters are involved. By changing the switching frequency f s of the capacitors 852, 853 used for conversion, the filter parameters of the SC filter can be changed very easily. The ohmic resistance R in a given circuit, for example a low-pass filter, is replaced by the capacitance C s operating at the conversion frequency f S . The resistance R is calculated from R = 1 / f s C S . The person skilled in the art will understand that the switching frequency f s of the capacitors 852, 853 does not necessarily have to correspond to the chopping frequency f chop .

[0098] A short limited charge equalization can take place during the non-overlapping period of the chopper demodulation phase, which only equalizes the time average to the differential 0 V after a number of (some) chopper phases. The continuous-time signal processing that also takes place here (the signal can also change during the chopper phases and is capacitively transferred to the output amplifier) differs from, for example, a sample-and-hold switched-capacitor circuit, because there is no full fast charge equalization exactly in one chopper phase. Rather, the charge equalization can only take place over a number of chopper phases, so that the actual useful signal remains substantially in amplitude (the discharge of the useful signal within the chopper phase can be neglected). A small partial discharge to the differential average = 0 V can take place by means of a small switched-capacitor circuit, which can be interpreted as a high-ohmic discharge resistor or functions as such. This partial discharge can also be done by means of a duty-cycle resistor during the short non-overlapping period.

[0099] Figure 9 Another possibility for implementing the discharge resistors 652, 653 is shown. Here the discharge resistors are implemented by so-called pseudo resistors 952, 953.

[0100] According to some embodiments, the discharge resistance circuit 950 can have one or more voltage-controlled pseudo-resistors 952, 953 comprising MOS transistors connected in series. The pseudo-resistors can use diode-connected MOS components that operate in the sub-threshold range and occupy a small area compared to discrete counterparts. As Figure 9 (bottom) shows that one or more sub-threshold biased MOSFETs 955 can act as linear resistors in a circuit whose resistance is controlled by the gate voltage. The voltage between the A, B terminals of the MOS pseudo-resistor is moved, for example, from -1 V to +1 V, and the corresponding resistance variation for different gate voltages is shown for different types of voltage-controlled pseudo-resistors. Figure 9 (bottom) shows one possible structure of a voltage-controlled PMOS pseudo-resistor. In addition to PMOS or NMOS, complementary MOS pseudo-resistors are also possible to consider.

[0101] Figure 10 Simulation waveforms of the demodulated output of different chopper amplifier topologies are shown. It can be seen that, Figure 1 and 3 Embodiments of (reference numeral 1010) and Figure 6 , 8 and 9 (reference numeral 1020) have lower delay and more continuous output waveforms compared to the conventional chopper amplifier topology (reference numeral 1030).

[0102] It can be seen from Figure 11 that a larger switching discharge resistance results in a longer offset ripple adjustment time, but lower chopper residual ripple.

[0103] In combination with the rotating Hall concept, chopper ripple suppression can be achieved with the use of an input modulator 110, an amplifier 120, output capacitors (AC coupled) 641, 643 directly connected between the amplifier output and the demodulator, and a duty cycle resistance or switching capacitor resistance or pseudo-resistance (with MOS transistors connected in the blocking direction for voltage biasing). Thus, an offset-compensated chopper amplifier can be provided that has low chopper ripple noise, low jitter effects, low signal delay (latency), and small chip area.

[0104] Aspects and features described in connection with one particular example of the previous examples can also be combined with one or more further examples to replace the same or similar features of that other example or to additionally introduce that feature into that example. Further examples.

[0105] It should also be understood that the disclosure of several steps, processes, operations or functions in the specification or claims, unless otherwise specified, does not necessarily imply that those steps, processes, operations or functions are necessarily carried out in the order in which they are described. Accordingly, the foregoing description does not limit the order of execution or performance of the individual steps or functions described in any particular order unless expressly stated or technically necessary. Further, in further examples, a single step, a single function, a single process or a single operation can include and / or be broken up into multiple sub-steps, functions, processes or operations.

[0106] If certain aspects are described in the preceding sections in connection with an apparatus or a system, these aspects should also be understood to describe a corresponding method. For example, a block, an apparatus or a functional aspect of an apparatus or system can correspond to a feature of a corresponding method, e.g. a method step. Correspondingly, aspects described in connection with a method should also be understood to describe an attribute or a functional feature of a corresponding block, a corresponding element, a corresponding apparatus or a corresponding system.

[0107] The following claims are hereby incorporated into the detailed description, each claim being separately independent of the others. It should also be noted that while the dependent claims refer to a specific combination of claims with one or more other claims, other examples can include combinations of the dependent claim with the subject matter of any other dependent or independent claim. Such combinations are expressly proposed here unless it is explicitly stated in the individual case that a specific combination is not intended. It is also intended to include the features of any other independent claim in a claim, even if the claim is not directly defined as dependent on this other independent claim.

Claims

1. A chopper amplifier circuit (100; 300), comprising: A modulator circuit (110) is switched at a chopping frequency, the modulator circuit being designed to convert voltage into AC voltage according to the chopping frequency; The amplifier circuit (120) has an inverting input (121) and a non-inverting input (122) for AC voltage, and an inverting output (123) and a non-inverting output (124) for amplifying AC measurement voltage; The demodulator circuit (130), switched at the chopping frequency, is designed to convert the amplified AC voltage into an amplified DC voltage. The demodulator circuit (130) described therein is designed to: During different switching phases (PH1; PH2), each of the inverted output (123) and the non-inverted output (124) of the amplifier circuit (120) is directly and capacitively coupled to each inverted input and non-inverted input of the summing circuit (140), wherein the two inverted inputs and two non-inverted inputs of the summing circuit are coupled to the demodulator circuit according to the different switching phases.

2. The chopper amplifier circuit (100; 300) according to claim 1, wherein the demodulator circuit (130) is designed to: During the first switching phase (PH1), The non-inverting output (124) of the amplifier circuit (120) is directly coupled to the first non-inverting input (141) of the summing circuit (140) and capacitively coupled to the second non-inverting input (143) of the summing circuit (140). The inverting output (123) of the amplifier circuit (140) is directly coupled to the first inverting input (142) of the summing circuit (140) and capacitively coupled to the second inverting input (144) of the summing circuit (140); During the second switching phase (PH2), The non-inverting output (124) of the amplifier circuit (120) is directly coupled to the second inverting input (144) of the summing circuit (140) and capacitively coupled to the first inverting input (142) of the summing circuit (140). The inverting output (123) of the amplifier circuit (120) is directly coupled to the second non-inverting input (143) of the summing circuit (140) and capacitively coupled to the first non-inverting input (141) of the summing circuit (140).

3. The chopper amplifier circuit (100; 300) according to claim 1 or 2, wherein the demodulator circuit (130) is designed to: During the first switching phase (PH1), The non-inverting output (124) of the amplifier circuit is directly coupled to the first non-inverting input (141) of the summing circuit via a first signal path. The inverted output (123) of the amplifier circuit is directly coupled to the first inverted input (142) of the summing amplifier via a second signal path; During the second switching phase (PH2), The non-inverting output (124) of the amplifier circuit is directly coupled to the second inverting input of the summing circuit via a third signal path. The inverting output (123) of the amplifier circuit is directly coupled to the second non-inverting input of the summing circuit via the fourth signal path. The first signal path and the fourth signal path are coupled to each other via a first capacitor (135). The fourth signal path is coupled to ground via the second capacitor (136). The second signal path and the third signal path are coupled to each other via a third capacitor (137). The third signal path is coupled to ground via a fourth capacitor (138).

4. The chopper amplifier circuit (100; 300) according to claim 3, wherein the first capacitor is larger than the second capacitor, and wherein the third capacitor is larger than the fourth capacitor.

5. The chopper amplifier circuit (100; 300) according to claim 3, wherein the first capacitor and the third capacitor each have the same size, and the second capacitor and the fourth capacitor each have the same size.

6. The chopper amplifier circuit (100; 300) according to claim 3, wherein the first capacitor is 10 to 20 times larger than the second capacitor, and wherein the third capacitor is 10 to 20 times larger than the fourth capacitor.

7. The chopper amplifier circuit (100; 300) according to claim 1 or 2, wherein the demodulator circuit (130) is designed to: During the first switching phase (PH1), The non-inverting output (124) of the amplifier circuit (120) is directly coupled to the first non-inverting input of the summing circuit via a first signal path and a second signal path, and capacitively coupled to the second non-inverting input of the summing circuit via a third signal path and a fourth signal path. The inverted output (123) of the amplifier circuit (120) is directly coupled to the first inverted input of the summing circuit via the fifth and sixth signal paths, and capacitively coupled to the second inverted input of the summing circuit via the seventh and eighth signal paths. During the second switching phase (PH2), The non-inverting output (124) of the amplifier circuit (120) is directly coupled to the second inverting input of the summing circuit via the ninth and tenth signal paths, and capacitively coupled to the first inverting input of the summing circuit via the eleventh and twelfth signal paths. The inverted output (123) of the amplifier circuit (120) is directly coupled to the second non-inverting input of the summing circuit via the 13th and 14th signal paths, and capacitively coupled to the first non-inverting input of the summing circuit via the 15th and 16th signal paths.

8. The chopper amplifier circuit (100; 300) according to claim 1 or 2, wherein the demodulator circuit (130) is designed to: During the first switching phase (PH1), The non-inverting output (124) of the amplifier circuit is directly coupled to the first non-inverting input of the summing circuit via a first signal path and a second signal path. The inverted output (123) of the amplifier circuit is directly coupled to the first inverted input of the summing amplifier via the third signal path and the fourth signal path; During the second switching phase (PH2), The non-inverting output (124) of the amplifier circuit is directly coupled to the second inverting input of the summing circuit via the fifth and sixth signal paths. The inverting output (123) of the amplifier circuit is directly coupled to the second non-inverting input of the summing circuit via the seventh and eighth signal paths. The first signal path and the eighth signal path are coupled to each other via a first capacitor. The eighth signal path is coupled to ground via a second capacitor. The second signal path and the seventh signal path are coupled to each other via a third capacitor. The second signal path is coupled to ground via the fourth capacitor. The third signal path and the fifth signal path are coupled to each other via a fifth capacitor. The fifth signal path is coupled to ground via a sixth capacitor. The fourth signal path and the sixth signal path are coupled to each other via a seventh capacitor. The fourth signal path is coupled to ground via an eighth capacitor.

9. The chopper amplifier circuit (100; 300) according to claim 1 or 2, wherein the first output of the modulator circuit (110) is directly connected to the inverting input (121) of the amplifier circuit (120), and the second output of the modulator circuit (110) is directly connected to the non-inverting input (122) of the amplifier circuit (120).

10. The chopper amplifier circuit (100; 300) according to claim 1 or 2, wherein the non-inverting input of the modulator circuit (110) is directly connected to the signal source (150), and the inverting input of the modulator circuit (110) is directly connected to the signal source (150).

11. The chopper amplifier circuit (100; 300) according to claim 1 or 2, further comprising: Hall sensors are designed for use in rotating current operation to provide measured voltage.

12. A method of operating the chopper amplifier circuit (100; 300) according to claim 1, comprising: During different transition phases The inverting and non-inverting outputs of the operational amplifier in the chopper amplifier circuit are directly and capacitively coupled to each inverting and non-inverting input of the summing amplifier.

13. The method of claim 12, comprising: During the first switching phase, The non-inverting output of the amplifier circuit is directly coupled to the first non-inverting input of the summing circuit, and capacitively coupled to the second non-inverting input of the summing circuit. The inverting output of the amplifier circuit is directly coupled to the first inverting input of the summing amplifier, and capacitively coupled to the second inverting input of the summing circuit. During the second switching phase, The non-inverting output of the amplifier circuit is directly coupled to the second inverting input of the summing circuit, and capacitively coupled to the first inverting input of the summing circuit. The non-inverting output of the amplifier circuit is directly coupled to the second inverting input of the summing circuit, and capacitively coupled to the first inverting input of the summing circuit.

14. The method according to claim 12 or 13, comprising: During the first switching phase, The non-inverting output of the amplifier circuit is directly coupled to the first non-inverting input of the summing circuit via a first signal path. The inverting output of the amplifier circuit is directly coupled to the first inverting input of the summing amplifier via a second signal path. During the second switching phase, The non-inverting output of the amplifier circuit is directly coupled to the second inverting input of the summing circuit via a third signal path. The inverting output of the amplifier circuit is directly coupled to the second non-inverting input of the summing circuit via a fourth signal path. The first signal path and the fourth signal path are coupled to each other via a first capacitor. The fourth signal path is coupled to ground via the second capacitor. The second signal path and the third signal path are coupled to each other via a third capacitor. The third signal path is coupled to ground via a fourth capacitor.

15. The method of claim 14, wherein the first capacitor is larger than the second capacitor, and wherein the third capacitor is larger than the fourth capacitor.

16. The method of claim 14, wherein the first capacitor and the third capacitor each have the same size, and the second capacitor and the fourth capacitor each have the same size.

17. The method of claim 14, wherein the first capacitor is 10 to 20 times larger than the second capacitor, and wherein the third capacitor is 10 to 20 times larger than the fourth capacitor.

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