Level conversion circuit, interface circuit, system on chip and level conversion method

Abstract

Provided are a level conversion circuit, an interface circuit, a system on chip, and a level conversion method. The level conversion circuit comprises: a boost circuit, whose power supply end receives a first reference voltage, and whose two output ends respectively output a first voltage signal obtained by boosting the first reference voltage and a second voltage signal obtained by boosting the first reference voltage, wherein the first voltage signal is inversely proportional to the second voltage signal; and a voltage conversion circuit, whose power supply end receives a second reference voltage, whose two input ends respectively receive the first voltage signal and the second voltage signal, and whose output end outputs a voltage signal obtained based on the second reference voltage. In the disclosed embodiment, the reference voltage is boosted by the boost circuit to obtain a voltage signal, and the voltage signal is used as a gate drive signal of each MOS tube in the voltage conversion circuit to turn on the MOS tube, so that the level conversion circuit can work normally even when the input reference voltage is extremely low.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular to a level conversion circuit, an interface circuit, a system on chip, and a level conversion method. Background Art

[0002] In the chip design of low-power applications, the power supply voltage of the chip is getting lower and lower. When the power supply voltage is lower than the threshold voltage of the interface circuit, the power supply voltage will not be able to drive the traditional level conversion circuit in the interface circuit to work properly, and the interface circuit will not work properly. Here, the level conversion circuit is used to convert the level of signals in two voltage domains.

[0003] Therefore, a newly designed level conversion circuit is needed to replace the traditional level conversion circuit working at a very low power supply voltage. Summary of the invention

[0004] In view of this, an object of the present disclosure is to provide a level conversion circuit, an interface circuit, a system on chip and a level conversion method to solve the problems existing in the prior art.

[0005] In a first aspect, an embodiment of the present disclosure provides a level conversion circuit, comprising:

[0006] A boost circuit, wherein a power supply end receives a first reference voltage, and two output ends respectively output a first voltage signal obtained by boosting the first reference voltage and a second voltage signal obtained by boosting the first reference voltage, wherein the first voltage signal is in antiphase with the second voltage signal;

[0007] A voltage conversion circuit has a power supply end receiving a second reference voltage, two input ends receiving the first voltage signal and the second voltage signal respectively, and an output end outputting a voltage signal obtained based on the second reference voltage.

[0008] Optionally, the level conversion circuit further comprises:

[0009] A first inverter, having a power supply terminal receiving the first reference voltage, an input terminal receiving a logic control signal, and an output terminal outputting a first voltage signal obtained based on the first reference voltage;

[0010] a second inverter, wherein a power supply terminal receives the first reference voltage, an input terminal receives the first voltage signal, and an output terminal outputs a second voltage signal obtained based on the first reference voltage;

[0011] The first voltage signal and the second voltage signal are provided to two input terminals of the boost circuit, respectively.

[0012] Optionally, the first inverter includes a first PMOS transistor and a first NMOS transistor connected in series between the first reference voltage and the ground terminal, and the second inverter includes a second PMOS transistor and a second NMOS transistor connected in series between the first reference voltage and the ground terminal.

[0013] Optionally, the voltage conversion circuit includes:

[0014] a fourth PMOS tube, whose source receives the second reference voltage, whose drain is coupled to the drain of the third NMOS tube, and whose gate is coupled to an intermediate node between the drain of the fifth PMOS tube and the drain of the fourth NMOS tube;

[0015] a fifth PMOS tube, whose source receives the second reference voltage, whose drain is coupled to the drain of the fourth NMOS tube, and whose gate is coupled to an intermediate node between the drain of the fourth PMOS tube and the drain of the third NMOS tube;

[0016] A third NMOS transistor, whose source is grounded and whose gate receives the first voltage signal;

[0017] The fourth NMOS tube has a source connected to the ground and a gate receiving the second voltage signal.

[0018] Optionally, the voltage conversion circuit includes:

[0019] a fourth PMOS tube, whose source receives the second reference voltage, whose drain is coupled to the source of the third PMOS tube, and whose gate is coupled to an intermediate node between the drain of the sixth PMOS tube and the drain of the fourth NMOS tube;

[0020] a fifth PMOS tube, whose source receives the second reference voltage, whose drain is coupled to the source of the sixth PMOS tube, and whose gate is coupled to an intermediate node between the drain of the third PMOS tube and the drain of the third NMOS tube;

[0021] a third PMOS tube, a drain of which is coupled to the drain of the third NMOS tube, and a gate of which receives the first voltage signal;

[0022] a sixth PMOS tube, a drain of which is coupled to the drain of the fourth NMOS tube, and a gate of which receives the second voltage signal;

[0023] A third NMOS transistor, whose source is grounded and whose gate receives the first voltage signal;

[0024] The fourth NMOS tube has a source connected to the ground and a gate receiving the second voltage signal.

[0025] Optionally, the voltage conversion circuit also includes: a third inverter, whose power supply end receives the second reference voltage, whose input end is connected to the middle node between the drain of the sixth PMOS tube and the drain of the fourth NMOS tube, and whose output end outputs the second reference voltage.

[0026] Optionally, a first voltage range of the first reference voltage is smaller than a second voltage range of the second reference voltage.

[0027] Optionally, the first reference voltage is a power supply voltage used inside the system, and the second reference voltage is an external interface voltage; or both the first reference voltage and the second reference voltage are power supply voltages used inside the system.

[0028] In a second aspect, an embodiment of the present disclosure provides an interface circuit, comprising any of the level conversion circuits described above.

[0029] Optionally, the interface circuit is one of the following interfaces: a digital-to-analog interface, an IO interface, a network interface, and a debugging interface.

[0030] In a third aspect, an embodiment of the present disclosure provides a system on chip, including:

[0031] Processing unit;

[0032] Storage devices;

[0033] The above-mentioned interface circuit;

[0034] An on-chip bus is used to couple the processing unit, the storage device and the interface circuit.

[0035] In a fourth aspect, an embodiment of the present disclosure provides an embedded system, including:

[0036] Processing unit;

[0037] Storage devices;

[0038] The above-mentioned interface circuit;

[0039] An on-chip bus is used to couple the processing unit, the storage device and the interface circuit.

[0040] In a fifth aspect, an embodiment of the present disclosure provides a level conversion method, including:

[0041] The first reference voltage is boosted by a boost circuit to obtain a first voltage signal and a second voltage signal, wherein the first voltage signal is in opposite phase to the second voltage signal;

[0042] A second reference voltage is received through the power supply terminal of the voltage conversion circuit, the first voltage signal and the second voltage signal are used as gate drive signals in the voltage conversion circuit, and a voltage signal obtained based on the second reference voltage is output.

[0043] Optionally, a first voltage range of the first reference voltage is smaller than a second voltage range of the second reference voltage.

[0044] The level conversion circuit provided by the embodiment of the present disclosure increases the reference voltage through a boost circuit to obtain an increased voltage signal, and uses the increased voltage signal as a gate drive signal of each MOS tube in the voltage conversion circuit to turn on each MOS tube, so that the level conversion circuit can work normally even when the input reference voltage is extremely low. Moreover, this level conversion circuit also has the advantages of small delay, low power consumption, and small area. Furthermore, since the boost circuit only needs two on-chip capacitors and several delay units, it has little impact on the manufacturing cost of the control level conversion circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] The above and other objects, features and advantages of the present disclosure will become more apparent through the description of the embodiments of the present disclosure with reference to the following drawings, in which:

[0046] Figure 1 is a circuit diagram of a conventional level conversion circuit 100;

[0047] Figure 2 is a circuit diagram of a level conversion circuit according to an embodiment of the present disclosure;

[0048] Figure 3 yes Figure 2 The waveform diagram of the level conversion circuit shown;

[0049] Figure 4 is a circuit diagram of a level conversion circuit according to an embodiment of the present disclosure;

[0050] Figure 5 is a circuit diagram of a level conversion circuit according to an embodiment of the present disclosure;

[0051] Figure 6 is a flow chart of a level conversion method according to an embodiment of the present disclosure;

[0052] Figure 7 It is a structural diagram of the embedded system used in the embodiment of the present disclosure. DETAILED DESCRIPTION

[0053] The present disclosure is described below based on embodiments, but the present disclosure is not limited to these embodiments. In the detailed description of the present disclosure below, some specific details are described in detail. It is possible for a person skilled in the art to fully understand the present disclosure without the description of these details. In order to avoid confusing the essence of the present disclosure, well-known methods, processes, and procedures are not described in detail. In addition, the drawings are not necessarily drawn to scale.

[0054] Before introducing various embodiments of the present disclosure, some terms or concepts used in the present disclosure are explained and clarified.

[0055] The term "including" mentioned throughout the specification and claims is an open-ended term and should be interpreted as "including but not limited to". In addition, the term "coupled" herein includes any direct and indirect electrical connection means. Therefore, if the text describes a first device coupled to a second device, it means that the first device can be directly electrically connected to the second device, or indirectly electrically connected to the second device through other devices or connection means.

[0056] Threshold voltage: The input voltage corresponding to the midpoint of the turning zone in the transfer characteristic curve where the output current changes sharply with the input voltage is usually called the threshold voltage.

[0057] Conventional voltage conversion circuit

[0058] Figure 1 1 is a circuit diagram of a conventional level conversion circuit 100. The level conversion circuit 100 may be a low-to-high level converter, which is used to receive an input signal with a predetermined level (e.g., a voltage of 0 volts to vddl volts) and pull up the input signal level to generate an output signal with a desired level (e.g., from a voltage of 0 volts to vddh volts), wherein vddl may be a low operating voltage for the operation of the entire system, and vddh may be a high operating voltage for the operation of the entire system. In one embodiment, vddl is a power supply voltage used internally in the system, and vddh is an external interface voltage, generally vddl is 0.8V, vddh is 1.8V, or vice versa. In another embodiment, vddl and vddh are two different voltage domains used internally in the system.

[0059] As shown in the figure, the level conversion circuit 100 includes a two-stage inverter 101 and a voltage conversion circuit 102 .

[0060] The two-stage inverter 101 includes a first inverter and a second inverter. The power supply terminal of the first inverter receives the first reference voltage vddl, the input terminal receives the logic control signal vin, the output terminal is coupled to the input terminal of the second inverter, and is coupled to the voltage conversion circuit 102. The power supply terminal of the second inverter receives the first reference voltage vddl, the input terminal is coupled to the output terminal of the first inverter, and the output terminal is coupled to the voltage conversion circuit 102.

[0061] More specifically, as shown in the figure, the first inverter includes a PMOS tube MP1 and an NMOS tube MN1. The gates of the PMOS tube MP1 and the NMOS tube MN1 receive an externally inputted logic control signal vin, the source of MP1 receives a first reference voltage Vddl, the drain of MP1 is coupled to the drain of MN1, the middle node between the drain of MP1 and the drain of MN1 is coupled to the gates of the PMOS tube MP2 and the NMOS tube MN2 in the second inverter, and is also coupled to the gates of the NMOS tube MMN4 and the PMOS tube MP6, and the source of the NMOS tube MN1 is grounded. The second inverter includes a PMOS tube MP2 and an NMOS tube MN2. The gates of the PMOS tube MP2 and the NMOS tube MN2 are coupled to the middle node between the drain of MP1 and the drain of MN1, the source of the PMOS tube MP2 receives the first reference voltage vddl, the drain of MP2 is coupled to the drain of MN2, the middle node between the drain of MP2 and the drain of MN2 is coupled to the gates of the PMOS tube MP3 and the NMOS tube MN3 in the voltage conversion circuit 102, and the source of MN2 is grounded.

[0062] The signal processing process of the two-stage inverter 101 is described in detail below based on the circuit structure of the two-stage inverter 101. For PMOS devices, the threshold voltage is less than zero, while for NMOS devices, the threshold voltage is greater than zero. When the logic control signal vin is at a low level (0 or a small positive voltage), the PMOS tube MP1 is turned on, and the NMOS tube MN1 is in a cut-off state. The output voltage inb is a high level (VDDL is used here to represent the high level of inb). When the input voltage vin is at a high level, the PMOS tube MP1 is in a cut-off state, and the NMOS tube MN1 is in a conducting state. The output voltage inb is equal to a low level (for example, 0).

[0063] The logic control signal of the second inverter is inb. When inb is high, the NMOS tube MN2 is turned on, the PMOS tube MP2 is in the off state, and the output voltage inbb is low (usually 0). When inb is low, the PMOS tube MP2 is turned on, and the NMOS tube MN2 is in the off state, so the output voltage inbb is high (i.e., VDDL).

[0064] The function of the inverter is to reverse the phase of the input signal by 180 degrees. Therefore, under the control of the logic control signal vin, the first inverter reverses the phase of the first reference voltage vddl by 180 degrees. Since the levels of vin and inb are opposite (when vin is high, inb is low, and vice versa), when the second inverter reverses the phase of the first reference voltage vddl by 180 degrees under the control of the logic control signal inb, the obtained inbb has the same phase as the first reference voltage and opposite phase to inb.

[0065] The voltage conversion circuit 102 is used for level conversion. As shown in the figure, the voltage conversion circuit 102 includes PMOS tubes MP3-MP7 and NMOS tubes MN3-MN5. The gates of the PMOS tubes MP3 and the NMOS tubes MN3 receive the output signal inbb of the two-stage inverter 101. The sources of the NMOS tubes MN3-MN5 are grounded. The drain of the NMOS tube MN3 is coupled to the drain of the PMOS tube MP3. The drain of the NMOS tube MN4 is coupled to the drain of the PMOS tube MP6. The drain of the NMOS tube MN5 is coupled to the drain of the PMOS tube MP7. The source of the PMOS tube MP3 is coupled to the drain of the PMOS tube MP4. The source of the PMOS tube MP6 is coupled to the drain of the PMOS tube MP5. The sources of the PMOS tubes MP4, MP5 and MP7 are coupled together and receive the second reference voltage vddh. The intermediate node between the drain of the NMOS tube MN3 and the drain of the PMOS tube MP3 is coupled to the gate of the PMOS tube MP5. The middle node between the drain of NMOS transistor MN4 and the drain of PMOS transistor MP6 is coupled to the gate of PMOS transistor MP4 and to the gates of PMOS transistor MP7 and NMOS transistor MN5. The middle node between the drain of PMOS transistor MP7 and the drain of NMOS transistor MN5 outputs a voltage signal vout.

[0066] The signal processing process of the voltage conversion circuit 102 is described in detail below based on the circuit structure of the voltage conversion circuit 102. The input signal of the voltage conversion circuit 102 is inbb. When inbb is high level (for example, VDDL), the NMOS tube MN3 is turned on, and the PMOS tube MP3 is in the cut-off state. At this time, the source and drain voltages of the NMOS tube MN3 are both ground voltage (0), and the PMOS tube MP5 is turned on. At the same time, it can be seen from the figure that since the gate of the PMOS tube MP6 receives inb (inb is low level at this time), the PMOS tube MP6 is turned on. Since the intermediate node between the drain of the PMOS tube MP6 and the drain of the NMOS tube MN4 outputs a high level (equal to VDDH), the high level drives MN5 to turn on, and the output voltage vout is low level (0).

[0067] When inbb is at a low level (for example, 0), the PMOS tube MP3 is turned on, and the NMOS tube MN3 is in a cut-off state. At this time, inb is at a high level (for example, VDDL). It can be seen from the figure that since the gate of the NMOS tube MN4 receives inb, the NMOS tube MN4 is turned on, and the middle node between the drains of MN4 and MP6 is the ground voltage (0) at this time. Since the middle node between the drains of MN4 and MP6 is coupled to the gate of the PMOS tube MP4 and the gate of the PMOS tube MP7, the PMOS tubes MP4 and MP7 are turned on, and the output voltage vout is equal to the voltage VDDH.

[0068] In this way, the input voltage vddl is converted into the power supply voltage vddh inside the chip through the two-stage inverter 101 and the voltage conversion circuit 102.

[0069] It should be noted that vddl and vddh both represent power supply voltages, but usually one is a low-level voltage and the other is a high-level voltage. The purpose of the level conversion circuit 100 is to convert the input vddl into vddh. However, correspondingly, even if the same devices in the circuits 101 and 102 need to withstand different power supply voltages, products with different power supply parameters will be used.

[0070] Based on the above Figure 1 As described in the background, in the chip design of low power consumption application, in order to reduce the chip power consumption, the power supply voltage vddl will become extremely small, so the voltages inbb and inb output by the two-stage inverter 101 are also correspondingly small, which may fail to drive the MOS tube of the voltage conversion circuit 102 to conduct, and further cause the voltage conversion circuit 102 to fail to work normally. In this way, the entire level conversion circuit 100 will not work normally.

[0071] In order to solve the above problems, the present disclosure provides Figure 2 As shown in the figure, the level conversion circuit 200 includes a two-stage inverter 201, a boost circuit 202 and a second voltage conversion circuit 203.

[0072] The two-stage inverter 201 in the figure and Figure 1 The structure of the two-stage inverter 101 in the level conversion circuit 100 is the same, and will not be repeated here. However, preferably, the MOS transistor in the two-stage inverter 201 in the embodiment of the present disclosure is an enhancement type field effect transistor.

[0073] As can be seen from the figure, the two output terminals of the two-stage inverter 201 output voltage signals inbb and inb respectively, and provide them to the two input terminals of the boost circuit 202 respectively. The boost circuit 202 includes a first boost circuit and a second boost circuit.

[0074] The input end of the first boost circuit receives a voltage signal inb, the power end receives a power voltage vddl, and the output end outputs a boosted voltage signal bst_bb, that is, a high level of bst_bb is greater than a high level of the power voltage vddl.

[0075] The first boost circuit includes a delay unit b1, a capacitor c1, a PMOS transistor MP10, a PMOS transistor MP11 and an NMOS transistor MN7. The input end of the delay unit b1 receives a voltage signal inb, and the output end is coupled to one end of the capacitor c1. The other end of the capacitor c1 is coupled to the drain of the PMOS transistor MP10. The source of the PMOS transistor MP10 receives a second reference voltage vddl, and the gate receives a voltage signal inb. The middle node between the drain of the PMOS transistor MP10 and the capacitor c1 is coupled to the source of the PMOS transistor MP11. The gate of the PMOS transistor MP11 is coupled to the gate of the NMOS transistor MN7 and receives the voltage signal inbb. The drain of the PMOS transistor MP11 is coupled to the drain of the NMOS transistor MN7, and the drain of the PMOS transistor MP11 is coupled to the drain of the NMOS transistor MN7, and is coupled to the first output end of the boost circuit and the gates of the PMOS transistors MP3 and the NMOS transistors MN3. The source of the NMOS transistor MN7 is grounded.

[0076] The input end of the second boost circuit receives the voltage signal inbb, the power end receives the power voltage vddl, and the output end outputs the boosted voltage signal bst_b, that is, the high level of bst_b is greater than the voltage range of the power voltage vddl.

[0077] The second boost circuit includes a delay unit b2, a capacitor c2, a PMOS tube MP8, a PMOS tube MP9 and an NMOS tube MN6. The delay unit b2 receives a voltage signal inbb, and an output terminal is coupled to one end of the capacitor c2, the other end of the capacitor c2 is coupled to the drain of the PMOS tube MP8, the source of the PMOS tube MP8 receives a power supply voltage vddl, and the gate of the PMOS tube MP8 receives the voltage signal inbb. The drain of the PMOS tube MP8 and the middle node of the capacitor c2 are coupled to the source of the PMOS tube MP9. The gate of the PMOS tube MP9 is coupled to the gate of the NMOS tube MN6 and receives the voltage signal inb, the drain of the PMOS tube MP9 is coupled to the drain of the NMOS tube MN6, and the drain of the PMOS tube MP9 is coupled to the drain of the NMOS tube MN6 and connected to the first output terminal of the boost circuit, and the first output terminal is coupled to the gates of the PMOS tube MP6 and the NMOS tube MN4. The source of the NMOS tube MN6 is grounded.

[0078] The voltage conversion circuit 203 and Figure 1 The circuit structure of the voltage conversion circuit 102 is the same as that of the voltage conversion circuit 102 in FIG. 1 , and will not be described in detail here.

[0079] The following is based on Figure 2 The circuit structure shown and Figure 3 The waveform diagram shown specifically describes the signal processing process of the level conversion circuit 200.

[0080] The working principle of the two-stage inverter 201 can be referred to in the above text. The two-stage inverter 201 outputs inbb. The waveform of inbb is the same as that of vddl, as shown in the figure.

[0081] The voltage signal inbb is provided to the second boost circuit. The delay unit b2 in the second boost circuit receives the voltage signal inbb, performs timing control on it, and outputs the signal inbb_dly. As shown in the figure, the rising edge of inbb_dly is delayed by a certain time length than the rising edge of inbb. The signal inbb is also provided to the PMOS tube MP8, and drives the PMOS tube MP8 to turn on. When MP8 is turned on, the intermediate node between the drain of the PMOS tube MP8 and the capacitor c2 outputs inbb_boost. Under the charging and discharging action of the capacitor c2, the voltage value of inbb_boost will rise from VDDL to VDDL+vboost. Vboost represents the voltage increment. The voltage signal bst_b is output at the intermediate node between the drain of the PMOS tube MP9 and the drain of the NMOS tube MN6. Through the joint action of the PMOS tube MP9 and the NMOS tube MN6, the voltage range of bst_bb is converted from [VDDL, VDDL+vboost] to [0, VDDL+vboost]. That is, through the PMOS transistor MP9 and the NMOS transistor MN6, the low level of the voltage signal bst_bb is grounded, so that the NMOS transistor MN4 can be completely turned off.

[0082] The first inverter outputs a voltage signal inb. As shown in the figure, the phase of the waveform of the voltage signal inb increases by 180 degrees compared with that of inbb.

[0083] The signal inb is provided to the first boost circuit. The delay unit b1 in the first boost circuit receives inb to perform timing control on the signal inb and outputs the signal inb_dly. As shown in the figure, the rising edge of inb_dly is delayed by a certain time length than the rising edge of inb. The signal inb is also provided to the PMOS tube MP10 and drives the PMOS tube MP10 to turn on. When MP10 is turned on, the middle node between the drain of the PMOS tube MP10 and the capacitor c1 outputs inb_boost. Under the action of the charge and discharge of the capacitor c1, the voltage range of inb_boost will rise to [VDDL, VDDL+vboost], where vboost represents the voltage increment. This process can be referred to Figure 3As shown. In the period from 0 to T1, the voltages of the signals inb and inb_dly are both 0. After the PMOS tube MP10 is turned on, inb_boost is pulled up to VDDL. In the period from T1 to T2, the PMOS tube MP10 is turned off, the lower plate of the capacitor c1 is 0, and inb_boost is maintained at VDDL. In the period from T2 to T3, MP10 is turned off, the lower plate voltage of the capacitor c1 is VDDL, and because the capacitor stores charge, inb_boost is pulled up to the level of VDDL+_vboost, and so on. In practice, due to the leakage of the capacitor, the high level of inb_boost will drop slightly.

[0084] The voltage signal bst_b is output at the middle node between the drain of the PMOS tube MP11 and the drain of the NMOS tube MN7. Under the joint action of the PMOS tube MP11 and the NMOS tube MN7, the voltage range of the output voltage signal bst_b is converted to [0, VDDL+vboost], where vboost represents a voltage increment. That is, through the PMOS tube MP11 and the NMOS tube MN7, the low level of the voltage signal bst_b is grounded, thereby completely turning off the NMOS tube MN3.

[0085] Figure 4 1 is a circuit diagram of a level conversion circuit according to an embodiment of the present disclosure. As shown in the figure, the level conversion circuit in the figure adopts and Figure 2 The two-stage inverter 201 and the boost circuit 202 are shown in FIG. Figure 2 The difference lies in the voltage conversion circuit 403 .

[0086] As shown in the figure, the voltage conversion circuit 403 includes: PMOS transistors MP4-MP5 and NMOS transistors MN3-MN4. The source of the PMOS transistor MP4 receives the second reference voltage vddh, the drain is coupled to the drain of the NMOS transistor MN3, and the gate is coupled to the middle node between the drain of the PMOS transistor MP5 and the drain of the NMOS transistor MN4. The source of the PMOS transistor MP5 receives the second reference voltage vddh, the drain is coupled to the drain of the NMOS transistor MN4, and the gate is coupled to the middle node between the drain of the PMOS transistor MP4 and the drain of the NMOS transistor MN3. The drain of the NMOS transistor MN3 is coupled to the drain of the PMOS transistor MP4, the source is grounded, and the gate receives the voltage signal bst_bb. The drain of the NMOS transistor MN4 is coupled to the drain of the PMOS transistor MP5, the source is grounded, and the gate receives the voltage signal bst_b. The middle node between the drain of the PMOS transistor MP5 and the drain of the NMOS transistor MN4 is coupled to the output end of the level conversion circuit 403.

[0087] Figure 5 1 is a circuit diagram of a level conversion circuit according to an embodiment of the present disclosure. As shown in the figure, the level conversion circuit in the figure adopts and Figure 2The two-stage inverter 201 and the boost circuit 202 are shown in FIG. Figure 2 The difference lies in the voltage conversion circuit 503 .

[0088] As shown in the figure, the voltage conversion circuit 503 includes: PMOS transistors MP3-MP6 and NMOS transistors MN3-MN4. The source of the PMOS transistor MP4 receives the second reference voltage vddh, the drain is coupled to the drain of the PMOS transistor MP3, and the gate is coupled to the middle node between the drain of the PMOS transistor MP6 and the drain of the NMOS transistor MN4. The source of the PMOS transistor MP5 receives the second reference voltage vddh, the drain is coupled to the drain of the PMOS transistor MP6, and the gate is coupled to the middle node between the drain of the PMOS transistor MP3 and the drain of the NMOS transistor MN3. The source of the PMOS transistor MP3 is coupled to the drain of the PMOS transistor MP4, the drain is coupled to the drain of the NMOS transistor MN3, and the gate receives the voltage signal bst_bb. The source of the PMOS transistor MP6 is coupled to the drain of the PMOS transistor MP5, the drain is coupled to the drain of the NMOS transistor MN4, and the gate receives the voltage signal bst_b. The drain of the NMOS transistor MN3 is coupled to the drain of the PMOS transistor MP3, the source is grounded, and the gate receives the voltage signal bst_bb. The drain of the NMOS transistor MN4 is coupled to the drain of the PMOS transistor MP6, the source is grounded, and the gate receives the voltage signal bst_b. The middle node between the drains of the PMOS transistor MP6 and the NMOS transistor MN4 is coupled to the output end of the level conversion circuit 503.

[0089] Figure 2 The voltage conversion circuit in Figure 4 and Figure 5 The voltage conversion circuit in Figure 4 and Figure 5 The high level of the final output voltage vout of the voltage conversion circuit provided may not reach VDDH (slightly smaller than VDDH), and Figure 2 Due to Figure 5 An inverter is added on the basis of VDDH to ensure that the high level of the output voltage is consistent with VDDH, avoiding leakage problems.

[0090] According to the above embodiments, it can be seen that the embodiments of the present disclosure do not require an additional DC module to generate a bias voltage. Only two on-chip capacitors and several delay units are needed to form a boost circuit to boost the reference voltage, so that a boosted voltage signal can be obtained. The voltage signal is used as a gate drive signal of each MOS tube in the voltage conversion circuit to turn on the MOS tube, so that the level conversion circuit can work normally, and then the entire system can work normally. In this way, even in the case of a very low reference voltage, the boosted voltage signal can enable the level conversion circuit to work normally. At the same time, this type of circuit itself also has the advantages of small delay, low power consumption, and small area.

[0091] The level conversion method provided by the embodiment of the present disclosure

[0092] Figure 6 1 is a flow chart of a level conversion method provided by an embodiment of the present disclosure. As shown in the figure, the method includes the following steps.

[0093] Step S601: The first reference voltage is boosted by a boost circuit to obtain a first voltage signal and a second voltage signal, wherein the first voltage signal is in opposite phase to the second voltage signal.

[0094] Step S602 receives a second reference voltage through the power supply terminal of the voltage conversion circuit, uses the first voltage signal and the second voltage signal as gate drive signals in the voltage conversion circuit, and outputs a voltage signal obtained based on the second reference voltage.

[0095] refer to Figure 2 , 4 As shown in FIG. 5 , the two terminals of the boost circuit 202 input voltage signals inb and inbb as control signals, respectively. The power supply terminal receives the first reference signal vddl. The first reference signal vddl is boosted by the boost circuit to obtain boosted voltage signals bst_b and bst_bb, respectively. The voltage signals bst_b and bst_bb are used as control signals of the voltage conversion circuit. Compared with the prior art, they have stronger driving capability and can drive each MOS tube in the power conversion circuit. The power supply terminal of the voltage conversion circuit receives the second reference voltage vddh. Through voltage conversion, a voltage signal based on the second reference voltage is output at the output terminal.

[0096] The boost circuit 202 can be implemented using a boost technology, so that even when the first reference voltage vddl is very small, the level conversion circuit can work normally. At the same time, the circuit itself has the advantages of small delay, low power consumption and small area.

[0097] Furthermore, as shown in the figure, the boost circuit can be implemented by using capacitors and delay units, and the product costs of the capacitors and delay units have little impact on the manufacturing cost of the entire level conversion circuit.

[0098] Furthermore, the voltage range [0, VDDL] of the first reference voltage vddl is smaller than the voltage range [0, VDDH] of the second reference voltage vddh. That is, the level conversion circuit is a level conversion circuit that converts a low level to a high level, and can be applied to the case where vddl is very small.

[0099] Embedded system and system on chip used in the embodiments of the present disclosure

[0100] An embedded system is a dedicated computer system that is completely embedded in a controlled device and designed for a specific application. According to the definition of the UK Institution of Electrical Engineers, an embedded system is a device that controls, monitors or assists equipment, machines or factory operations. Unlike general-purpose computer systems such as personal computers, embedded systems usually perform pre-defined tasks with specific requirements. Since embedded systems are only targeted at one specific task, designers can optimize it, reduce size and reduce costs. Embedded systems are usually mass-produced, so the cost savings of a single unit can be scaled up by hundreds or thousands as production increases.

[0101] Figure 7 It is a system architecture diagram of an embedded system 700 applied in an embodiment of the present disclosure.

[0102] Although the functions, appearance interfaces, operations, etc. of various specific embedded systems are different, or even vary greatly, the basic hardware structure is similar, and has a high degree of similarity with the hardware system of general-purpose computers. However, the characteristics of embedded system applications cause the embedded system to be quite different from general-purpose computer systems in terms of hardware composition and implementation.

[0103] First, in order to meet the requirements of the embedded system 700 in terms of speed, volume and power consumption, the operating system, application software, special data and other data that need to be stored for a long time usually do not use storage media such as disks with large capacity and slow speed, but mostly use random access memory 702 or flash memory (Flash Memory) 703, as shown in the figure above.

[0104] In addition, in the embedded system 700, an A / D (analog / digital conversion) interface 705 and a serial interface 706 are required for the needs of measurement and control, which are rarely used in general-purpose computers. The A / D interface 705 mainly completes the conversion of analog signals to digital signals and the conversion of digital signals to analog signals required in the test. When the embedded system 700 is applied to industrial production, it often needs to be tested. Since the single-chip microcomputer generates digital signals, it needs to be converted into analog signals for testing during testing. Therefore, unlike general-purpose computers, an A / D (analog / digital conversion) interface 705 is required to complete the relevant conversion. In addition, in industry, multiple embedded systems are often required to be connected in series to complete relevant functions, so a serial interface 706 is required for connecting multiple embedded systems in series, which is mostly not required in general-purpose computers.

[0105] In addition, as a basic processing unit, the embedded system 700 often needs to connect multiple embedded systems 700 into a network in industrial design, so a network interface 707 is needed to connect the embedded system 700 to the network. This is also not needed in most general-purpose computers. In addition, according to the actual application and scale, some embedded systems 700 need to use external buses 704. With the rapid expansion of the application field of embedded systems 700, embedded systems 700 are becoming more and more personalized, and more and more types of buses are used according to their own characteristics. In addition, in order to test the internal circuits of the embedded processor 701, the processor chip generally adopts boundary scan test technology. In order to adapt to this test, a debugging interface 708 is used. The processing core of the embedded system 700 is the embedded processor 701.

[0106] The level conversion circuit provided by the embodiment of the present disclosure can be applied to Figure 7 Among the various interfaces shown, for example, when the embodiment of the present disclosure is applied to the A / D interface, the first reference voltage can be the power supply voltage provided by the external system to the embedded system 700, and the second reference voltage is the power supply voltage inside the embedded system. The level conversion circuit enables the A / D interface to work normally even when the input voltage is extremely low.

[0107] With the rapid development of very large scale integration (VLSI) and semiconductor technology, part or all of the above embedded system can be implemented on a silicon chip, that is, an embedded system on chip (SoC). In other words, the level conversion circuit provided in the above embodiment can also be applied to various interfaces in the same chip.

[0108] The commercial value of the disclosed embodiments

[0109] The level conversion circuit provided in the embodiment of the present disclosure can work when the power supply voltage is extremely low. The system on chip and embedded system including the level conversion circuit can be used to form a computing device used in various scenarios, for example, electronic devices used in daily life, including terminal devices such as notebooks and mobile phones, Internet of Things devices as edge nodes, and certain consumer electronic products. In order to reduce energy consumption, the manufacturers of these devices are motivated to reduce the power supply voltage to an extremely low level, so the level conversion circuit provided in the embodiment of the present disclosure is required to perform level conversion. Based on this, the level conversion circuit, the system on chip and the computing device constructed by the system on chip of the embodiment of the present disclosure have commercial value and economic value on the basis of practical value.

[0110] Those skilled in the art will appreciate that the present disclosure may be implemented as systems, methods, and computer program products. Therefore, the present disclosure may be specifically implemented in the following forms, namely complete hardware, complete software (including firmware, resident software, microcode), and may also be implemented in the form of a combination of software and hardware. In addition, in some embodiments, the present disclosure may also be implemented in the form of a computer program product in one or more computer-readable media, which contains computer-readable program code.

[0111] Any combination of one or more computer-readable media may be used. A computer-readable medium may be a computer-readable signal medium or a computer-readable storage medium. A computer-readable storage medium may be, for example but not limited to, an electrical, magnetic, optical, electromagnetic, infrared or semiconductor system, device or device, or any combination thereof. More specific examples of computer-readable storage media include: electrical coupling of one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In this article, a computer-readable storage medium may be any tangible medium containing or storing a program that may be used by a processing unit, a device or a device, or used in combination with the processing unit, a device or a device.

[0112] Computer readable signal media may include data signals propagated in baseband or as part of a chopped wave, which carry computer readable program code. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any other suitable combination. Computer readable signal media may also be any computer readable medium other than a computer readable storage medium, which may send, propagate, or transmit a program for use by or in conjunction with an instruction system, apparatus, or device.

[0113] Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., and any suitable combination of the foregoing.

[0114] The computer program code for executing the disclosed embodiments may be written in one or more programming languages ​​or combinations thereof. The programming languages ​​include object-oriented programming languages, such as JAVA, C++, and may also include conventional procedural programming languages, such as C. The program code may be executed entirely on a user's computer, partially on a user's computer, as an independent software package, partially on a user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be coupled to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be coupled to an external computer (e.g., coupled via the Internet using an Internet service provider).

[0115] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the present disclosure. For those skilled in the art, the present disclosure may have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A level conversion circuit, comprising: A boost circuit, wherein a power supply end receives a first reference voltage, and two output ends respectively output a first voltage signal obtained by boosting the first reference voltage and a second voltage signal obtained by boosting the first reference voltage, wherein the first voltage signal is in antiphase with the second voltage signal; A voltage conversion circuit, wherein a power supply terminal receives a second reference voltage, two input terminals receive the first voltage signal and the second voltage signal respectively, and an output terminal outputs a voltage signal obtained based on the second reference voltage, The boost circuit includes a first boost circuit and a second boost circuit. The first boost circuit comprises: A first delay unit and a first capacitor connected in series in sequence, wherein an input end of the first delay unit receives the first voltage signal; a tenth PMOS transistor, whose source receives the second reference voltage, whose drain is coupled to the first capacitor, and whose gate receives the first voltage signal; The seventh NMOS tube has a source connected to the ground; an eleventh PMOS tube, a gate of which is coupled to the gate of the seventh NMOS tube and receives the second voltage signal, and a drain of which is coupled to the drain of the seventh NMOS tube and is coupled to the first output terminal; The second boost circuit comprises: A second delay unit and a second capacitor are sequentially connected in series, wherein an input end of the second delay unit receives the second voltage signal; an eighth PMOS tube, whose source receives the second reference voltage, whose drain is coupled to the second capacitor, and whose gate receives the second voltage signal; A sixth NMOS tube, whose source is grounded; A ninth PMOS tube has a gate coupled to the gate of the sixth NMOS tube and receives the first voltage signal, and a drain coupled to the drain of the sixth NMOS tube and coupled to the second output terminal.

2. The level conversion circuit according to claim 1, further comprising: A first inverter, having a power supply terminal receiving the first reference voltage, an input terminal receiving a logic control signal, and an output terminal outputting a first voltage signal obtained based on the first reference voltage; a second inverter, wherein a power supply terminal receives the first reference voltage, an input terminal receives the first voltage signal, and an output terminal outputs a second voltage signal obtained based on the first reference voltage; The first voltage signal and the second voltage signal are respectively provided to two input terminals of the boost circuit.

3. The level conversion circuit according to claim 2, wherein: The first inverter includes a first PMOS transistor and a first NMOS transistor connected in series between the first reference voltage and the ground terminal, and the second inverter includes a second PMOS transistor and a second NMOS transistor connected in series between the first reference voltage and the ground terminal.

4. The level conversion circuit according to claim 1, wherein: The voltage conversion circuit comprises: a fourth PMOS tube, whose source receives the second reference voltage, whose drain is coupled to the drain of the third NMOS tube, and whose gate is coupled to an intermediate node between the drain of the fifth PMOS tube and the drain of the fourth NMOS tube; a fifth PMOS tube, whose source receives the second reference voltage, whose drain is coupled to the drain of the fourth NMOS tube, and whose gate is coupled to an intermediate node between the drain of the fourth PMOS tube and the drain of the third NMOS tube; A third NMOS transistor, whose source is grounded and whose gate receives the first voltage signal; The fourth NMOS tube has a source connected to the ground and a gate receiving the second voltage signal.

5. The level conversion circuit according to claim 1, wherein: The voltage conversion circuit comprises: a fourth PMOS tube, whose source receives the second reference voltage, whose drain is coupled to the source of the third PMOS tube, and whose gate is coupled to an intermediate node between the drain of the sixth PMOS tube and the drain of the fourth NMOS tube; a fifth PMOS tube, whose source receives the second reference voltage, whose drain is coupled to the source of the sixth PMOS tube, and whose gate is coupled to an intermediate node between the drain of the third PMOS tube and the drain of the third NMOS tube; a third PMOS tube, a drain of which is coupled to the drain of the third NMOS tube, and a gate of which receives the first voltage signal; a sixth PMOS tube, a drain of which is coupled to the drain of the fourth NMOS tube, and a gate of which receives the second voltage signal; A third NMOS transistor, whose source is grounded and whose gate receives the first voltage signal; The fourth NMOS tube has a source connected to the ground and a gate receiving the second voltage signal.

6. The level conversion circuit according to claim 5, wherein: The voltage conversion circuit also includes: a third inverter, whose power supply end receives the second reference voltage, whose input end is connected to the middle node between the drain of the sixth PMOS tube and the drain of the fourth NMOS tube, and whose output end outputs the second reference voltage.

7. The level conversion circuit according to claim 1, wherein: A voltage range of the first reference voltage is smaller than a voltage range of the second reference voltage.

8. The level conversion circuit according to claim 1, wherein: The first reference voltage is a power supply voltage used inside the system, and the second reference voltage is an external interface voltage; or the first reference voltage and the second reference voltage are both power supply voltages used inside the system.

9. An interface circuit, comprising the level conversion circuit according to any one of claims 1 to 8. 10 . The interface circuit according to claim 9 , wherein the interface circuit is one of the following interfaces: a digital-analog interface, an IO interface, a network interface, and a debugging interface.

11. A system on chip, comprising: Processing unit; Storage devices; The interface circuit as claimed in claim 9 or 10; An on-chip bus is used to couple the processing unit, the storage device and the interface circuit.

12. An embedded system comprising: Processing unit; Storage devices; The interface circuit as claimed in claim 9 or 10; An on-chip bus is used to couple the processing unit, the storage device and the interface circuit.

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