A device output high impedance measurement circuit and method

Abstract

The present invention provides a device output high-impedance measurement circuit and method. An external test system connects the input of the device under test in the measurement circuit to the external test system output terminal GPIO1, the enable terminal to the external test system control terminal GPIO2, and the output terminal to the external test system acquisition terminal GPIO4 via a GPIO port. In a high-impedance test loading circuit, the input of the device under test is connected to the external test system output terminal GPIO3, the enable terminal is connected to the external test system control terminal GPIO2 via an inverter, and the output terminal is connected to the external test system acquisition terminal GPIO4. The present invention enables high-impedance measurement through simple GPIO port acquisition, significantly improving device testing efficiency.

Description

Technical Field

[0001] The present invention relates to the technical field of test circuits, and in particular to a circuit and method for measuring a device outputting a high-impedance state. Background Art

[0002] When verifying chip functionality, some devices may have a high-impedance output state. When the output is high-impedance, the output state is neither high nor low, but somewhere in between. This output state cannot be determined through simple logic state acquisition. It requires AD acquisition or an oscilloscope to determine whether it is in a high-impedance state. However, oscilloscopes or AD acquisition channels are often limited. For some multi-bit bus driver devices, there are insufficient acquisition channels, making it impossible to measure the high-impedance state of all device channels at once.

[0003] Therefore, how to provide a measurement circuit and a measurement method thereof that can improve the efficiency of high-resistance state testing of devices is an urgent problem that those skilled in the art need to solve. Summary of the Invention

[0004] In view of this, the present invention provides a device output high-impedance state measurement circuit and method, which can perform high-impedance measurement through simple GPIO port acquisition, and can greatly improve device testing efficiency.

[0005] In order to achieve the above object, the present invention adopts the following technical solutions:

[0006] On one hand, the present invention provides a device output high-impedance measurement circuit, wherein an external test system is connected to the measurement circuit via a GPIO port, comprising: a device under test test circuit and a high-impedance test loading circuit; wherein,

[0007] The device under test test circuit includes: a device under test; an input terminal of the device under test connected to an output terminal GPIO1 of an external test system, an enable terminal connected to a control terminal GPIO2 of an external test system, and an output terminal connected to an acquisition terminal GPIO4 of an external test system;

[0008] The high-resistance test loading circuit includes: an inverter and a test device; the input end of the test device is connected to the external test system output end GPIO3, the enable end is connected to the external test system control end GPIO2 through the inverter, and the output end is connected to the external test system acquisition end GPIO4.

[0009] Preferably, the device under test and the test device include unidirectional and bidirectional drivers / buffers.

[0010] Preferably, the output terminal of the test device is connected to the external test system acquisition terminal GPIO4 via a resistor. The resistor is used to control the on / off between the test circuit of the device under test and the high-resistance test loading circuit.

[0011] Another aspect of the present invention provides a measurement method for a device output high-impedance state measurement circuit based on the first aspect, which controls the states of GPIO1, GPIO2, and GPIO3 respectively, and compares the logic states of GPIO4 with those of GPIO1 and GPIO2 to determine whether the output of the device under test is in a high-impedance state, comprising the following steps:

[0012] When the GPIO2 signal received by the enable terminal of the device under test is at a low level, the GPIO4 signal of the acquisition terminal of the external test system changes following the change of the GPIO1 signal, and the device under test operates normally;

[0013] When the GPIO2 signal received by the enable terminal of the device under test is at a high level, the GPIO4 signal at the acquisition terminal of the external test system changes following the change of the GPIO3 signal, and is independent of the GPIO1 signal, and the device under test is in a high impedance state.

[0014] It can be seen from the above technical solution that, compared with the prior art, the beneficial effects of the present invention include:

[0015] Through circuit design, the present invention enables the test system to determine the high-impedance output state using only the GPIO port. This method simplifies the test method and allows for simultaneous high-impedance testing of all bus driver channels. This allows for simultaneous measurement of 8-bit and 16-bit unidirectional and bidirectional buffers / drivers, as well as high-impedance testing of multiple similar devices, significantly improving test efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only embodiments of the present invention. Those skilled in the art can also derive other drawings based on the provided drawings without inventive effort.

[0017] Figure 1 A principle block diagram of a measurement circuit for a device outputting a high-impedance state provided by an embodiment of the present invention;

[0018] Figure 2 This is a logic circuit diagram of a measurement circuit for a device outputting a high-impedance state provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0019] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0020] An embodiment of the present invention provides a device output high-impedance measurement circuit. An external test system is connected to the measurement circuit via a GPIO port. The output high-impedance measurement circuit includes a device under test test circuit and a high-impedance test loading circuit.

[0021] The test circuit of the device under test D2 includes: the device under test D2; the input end of the device under test D2 is connected to the output end GPIO1 of the external test system, the enable end is connected to the control end GPIO2 of the external test system, and the output end is connected to the acquisition end GPIO4 of the external test system.

[0022] The high-resistance test loading circuit includes: an inverter D1 and a test device D3; the input end of the test device D3 is connected to the external test system output end GPIO3, the enable end is connected to the external test system control end GPIO2 through the inverter D1, and the output end is connected to the external test system acquisition end GPIO4;

[0023] The device under test D2 and the test device D3 may be the same device or different devices;

[0024] In one embodiment, the device under test D2 and the test device D3 include unidirectional and bidirectional drivers / buffers.

[0025] In one embodiment, the output of test device D3 is connected to an external test system acquisition terminal GPIO4 via resistor R1. When the output of the device under test is not in a high-impedance state, the test device outputs a high-impedance state. Due to the presence of the resistor, the test system acquisition terminal GPIO4 and the test device are effectively disconnected, and the state of the test system acquisition terminal GPIO4 is determined by the test circuit. When the device under test outputs a high-impedance state, the test device outputs a non-high-impedance state. Due to the presence of the resistor, the test system acquisition terminal GPIO4 and the test device are effectively connected, and the state of the test system acquisition terminal GPIO4 is determined by the high-impedance test loading circuit.

[0026] The embodiments of the present invention are further described below in conjunction with specific working principles.

[0027] like Figure 1 and Figure 2As shown in the figure, the device under test D2 has a high-impedance output function, and its logical function is as follows: the high-impedance output is determined by the D2 enable terminal \OE. When the GPIO2 signal received by \OE is low, the output GPIO4 of the device under test changes with the changes of GPIO1. When the GPIO2 signal received by \OE is high, the output GPIO4 of the device under test is in a high-impedance state.

[0028] According to the logic function of the device under test, when the input GPIO2 of D2's enable terminal is low, the output GPIO4 of D2 changes with the changes of GPIO1. At this time, because the input GPIO2 of inverter D1 is low, its output is high. The enable terminal of test device D3 will input a high level. At this time, the output of D3 will be in a high-impedance state. Therefore, when device D2 is working normally, the output of the high-impedance test loading circuit is in a high-impedance state, which does not affect the test system's acquisition of D2's output GPIO4.

[0029] When the enable input GPIO2 of D2 is high, the output GPIO4 of D2 is in a high-impedance state. Since the input of the inverter D1 is high, its output is low. The enable terminal of the test device is enabled, and its output will change with the change of the test system input load control input GPIO3. After passing through the first resistor R1, the output is loaded to GPIO4. Since the output of the device under test D2 is in a high-impedance state, at this time, GPIO4 changes with the change of GPIO3, and is not related to the state of GPIO1.

[0030] From this, we can see that when GPIO2 is low, the device under test D1 works normally, and its output GPIO4 is related to the test system input GPIO1, but not to GPIO3. When GPIO2 is high, the device under test D1 enters a high-impedance state, and its output GPIO4 is related to the test system input GPIO3, but not to GPIO1. Therefore, the test system can determine whether the output of the device under test is in a high-impedance state by controlling the states of GPIO1, GPIO2, and GPIO3 respectively, and comparing the logical states of GPIO4 with GPIO1 and GPIO2.

[0031] This embodiment enables the external test system to complete the high-impedance output state determination using only the GPIO port, especially for one-time testing of bus driver devices. It has the characteristics of simple testing method and can complete the high-impedance test of all channels of the bus driver at one time.

[0032] The above is a detailed introduction to the device output high-impedance state measurement circuit and method provided by the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method and core ideas of the present invention. At the same time, for those skilled in the art, according to the ideas of the present invention, there may be changes in the specific implementation methods and application scopes. In summary, the contents of this specification should not be understood as limiting the present invention.

[0033] The above description of the disclosed embodiments is intended to enable one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be readily apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not limited to the embodiments shown herein but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for measuring a device outputting a high-impedance measurement circuit, characterized in that: The external test system is connected to the measurement circuit via the GPIO port, and includes: a device under test test circuit and a high-resistance test loading circuit; wherein, The device under test test circuit includes: a device under test; an input terminal of the device under test connected to an output terminal GPIO1 of an external test system, an enable terminal connected to a control terminal GPIO2 of an external test system, and an output terminal connected to an acquisition terminal GPIO4 of an external test system; The high-resistance test loading circuit includes: an inverter and a test device; the input end of the test device is connected to the output end GPIO3 of the external test system, the enable end is connected to the control end GPIO2 of the external test system through the inverter, and the output end is connected to the acquisition end GPIO4 of the external test system; Control the status of GPIO1, GPIO2, and GPIO3 respectively, and compare the logic status of GPIO4 with GPIO1 and GPIO2 to determine whether the output of the device under test is in a high-impedance state. The following steps are included: When the GPIO2 signal received by the enable terminal of the device under test is at a low level, the GPIO4 signal of the acquisition terminal of the external test system changes following the change of the GPIO1 signal, and the device under test operates normally; When the GPIO2 signal received by the enable terminal of the device under test is at a high level, the GPIO4 signal at the acquisition terminal of the external test system changes following the change of the GPIO3 signal, and is independent of the GPIO1 signal, and the device under test is in a high impedance state.

2. The method for measuring a device outputting a high-impedance state measurement circuit according to claim 1, wherein: The device under test and the test device include unidirectional and bidirectional buffers / drivers.

3. The method for measuring a device outputting a high-impedance state measurement circuit according to claim 1, wherein: The output terminal of the test device is connected to the external test system acquisition terminal GPIO4 through a resistor.

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