Memory controller and storage device including the same

Abstract

The present disclosure relates to a memory controller and a storage device including the memory controller. A memory controller includes: a command storage device including a first read command queue and a second read command queue; a command generation controller configured to provide an erase command, a suspend command, a resume command, and output a scheduling event signal after outputting the resume command; and a command scheduling controller configured to search a first physical address group, rearrange the output order of the first read command queue, and provide a read command based on the second read command queue to perform a read operation.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2020-0178166 filed in the Korean Intellectual Property Office on December 18, 2020, which is incorporated herein by reference in its entirety. Technical Field

[0003] One or more embodiments described herein relate to a memory controller and a memory device including the memory controller. Background Art

[0004] The memory controller may control storage of data in the memory device based on instructions from the host.

[0005] Volatile memory devices store data while power is supplied. When power is lost, the data is lost. Examples of volatile memory devices include static random access memory (SRAM) and dynamic random access memory (DRAM).

[0006] A nonvolatile memory device can store data even when power is interrupted. Examples of nonvolatile memory devices include a read only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable ROM (EEROM), and a flash memory. Summary of the invention

[0007] One or more embodiments described herein provide a memory controller capable of improving the performance of a read operation. One or more additional embodiments include a memory device that may be equipped with such a memory controller.

[0008] According to one aspect of the present disclosure, a memory controller is provided, comprising: a command storage device, comprising a first read command queue and a second read command queue, the first read command queue being configured to store a read command and a physical address according to an index number, the read command being used to read data stored in the memory device, and the physical address corresponding to the read command and comprising a plane number, a block number, and a page number; a command generation controller, configured to provide an erase command to perform an erase operation, the erase operation comprising erasing data stored in one of a plurality of memory blocks of the memory device; provide a suspend command in response to a request to suspend the erase operation; provide a resume command to resume the erase operation after completing the operation corresponding to the request; and output a scheduling event signal after outputting the resume command; and a command scheduling controller. A controller is configured to search for a first physical address group and a second physical address group among the physical addresses stored in a first read command queue in response to a scheduling event signal, the first physical address group including physical addresses with the same page number among the physical addresses stored in the first read command queue, and the second physical address group including all physical addresses whose plane numbers are different from the plane numbers of the first physical address group; rearrange the output order of the first read command queue by storing the physical addresses corresponding to the same page number in the first physical address group together at the same index number of the second read command queue, and storing the physical addresses in the second physical address group at the index numbers of the second read command queue respectively; and provide a read command based on the second read command queue to perform a read operation.

[0009] According to another aspect of the present disclosure, a memory controller is provided, comprising: a command storage device, comprising a first read command queue and a second read command queue, the first read command queue being configured to store a read command and a physical address according to an index number, the read command being used to read data stored in the memory device, and the physical address corresponding to the read command and comprising a plane number, a block number, and a page number; a command generation controller, configured to provide a command to the memory device to perform an erase operation or a write operation, the erase operation comprising erasing data stored in one of a plurality of memory blocks of the memory device, the write operation comprising storing data in one of a plurality of memory blocks, and configured to output a scheduling event signal after a predetermined period of time has passed since the time when the command is provided to the memory device ; and a command scheduling controller, configured to search for a first physical address group and a second physical address group among the physical addresses stored in the first read command queue in response to a scheduling event signal, the first physical address group including physical addresses with the same page number among the physical addresses stored in the first read command queue, and the second physical address group including all physical addresses whose plane numbers are different from the plane numbers of the first physical address group; rearrange the output order of the first read command queue by storing the physical addresses corresponding to the same page number in the first physical address group together at the same index number of the second read command queue, and storing the physical addresses in the second physical address group at the index numbers of the second read command queue respectively; and provide a read command based on the second read command queue to perform a read operation.

[0010] According to another aspect of the present disclosure, a storage device is provided, comprising: a memory device comprising a plurality of planes; and a memory controller configured to: store a read command and a physical address in a first read command queue according to an index number in response to a read request, the read command being used to perform a read operation including reading data stored in the memory device; when a scheduling event occurs, schedule the read command and the physical address stored in the first read command queue to a second read command queue; and provide the read command and the physical address stored in the second read command queue to the memory device according to a scheduling order, wherein the physical address comprises a plane number, a block number, and a page number, and wherein the memory controller is configured to: in the first read command queue, schedule the read command and the physical address stored in the second read command queue to the memory device according to a scheduling order, wherein the physical address comprises a plane number, a block number, and a page number, and wherein the memory controller is configured to: Searching for a first physical address group and a second physical address group among the physical addresses stored in the read command queue, the first physical address group includes physical addresses with the same page number among the physical addresses stored in the first read command queue, and the second physical address group includes all physical addresses whose plane numbers are different from the plane numbers of the first physical address group; rearranging the output order of the first read command queue by storing the physical addresses of the first physical address group corresponding to the same page number together at the same index number of the second read command queue, and storing the physical addresses of the second physical address group at the index numbers of the second read command queue respectively; and providing a read command based on the second read command queue to perform a read operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings; however, they may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the example embodiments to those skilled in the art.

[0012] In the accompanying drawings, the dimensions may be exaggerated for clarity of illustration. It will be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements, or one or more intermediate elements may also be present. Throughout the specification, the same reference numerals refer to the same elements.

[0013] Figure 1 An embodiment of a storage system is shown.

[0014] Figure 2 Multiple planar embodiments are shown.

[0015] Figure 3 An embodiment of a memory device is shown.

[0016] Figure 4 An embodiment of a memory controller is shown.

[0017] Figure 5 An embodiment of providing a scheduling event signal is shown.

[0018] Figure 6 An embodiment of providing a scheduling event signal is shown.

[0019] Figure 7 An embodiment of providing a scheduling event signal is shown.

[0020] Figure 8 is a diagram illustrating an embodiment of a command storage device.

[0021] Fig. 9 An embodiment of a read operation is shown.

[0022] Fig.10 An embodiment of scheduling read commands and physical addresses is shown.

[0023] Fig.11 An embodiment of a read operation is shown.

[0024] Fig.12 An embodiment of scheduling read commands and physical addresses is shown.

[0025] Fig.13 An embodiment of a read operation is shown.

[0026] Fig.14 An embodiment of a command storage device is shown.

[0027] Fig.15 An embodiment of a read operation is shown.

[0028] Fig.16 An embodiment of scheduling read commands and physical addresses is shown.

[0029] Fig.17 An embodiment of a read operation is shown.

[0030] Fig.18 An embodiment of a method of operating a memory controller is shown.

[0031] Fig.19 An embodiment of a memory controller is shown.

[0032] Fig. 20 An embodiment of a memory card system is shown.

[0033] Fig.21 An embodiment of a solid state drive system is shown.

[0034] Fig. 22 An embodiment of a user system is shown. DETAILED DESCRIPTION

[0035] The specific structural or functional descriptions disclosed herein are merely illustrative for the purpose of describing embodiments according to the concepts of the present disclosure. Embodiments according to the concepts of the present disclosure may be implemented in various forms and should not be construed as being limited to the embodiments set forth herein.

[0036] Figure 1 is a diagram showing a storage system according to an embodiment. The storage system may be implemented as a data processing system including, for example, a personal computer (PC), a data center, an enterprise data storage system, and a direct attached storage device (DAS), a data processing system including a storage area network (SAN), a data processing system including a network attached storage device, or other types of systems or devices.

[0037] Reference Figure 1 , the storage system may include a storage device 1000 and a host 400. The storage device 1000 may store data according to a request of the host 400 such as a mobile phone, smart phone, MP3 player, laptop computer, desktop computer, game console, TV, tablet computer, or in-vehicle infotainment system.

[0038] The storage device 1000 may be manufactured as any of various types of storage devices according to a host interface as a communication scheme with the host 400. Examples include a solid state drive (SSD), a multimedia card (MMC), an embedded MMC (eMMC), a reduced size MMC (RS-MMC), a micro MMC (micro-MMC), a secure digital (SD) card, a mini SD card, a micro SD card, a universal serial bus (USB) storage device, a universal flash memory (UFS) device, a compact flash (CF) card, a smart media card (SMC), a memory stick, etc.

[0039] The memory device 1000 may be manufactured in any of a variety of package types. Examples include: package on package (POP), system in package (SIP), system on chip (SOC), multi-chip package (MCP), chip on board (COB), wafer-level manufacturing package (WFP), and wafer-level stacked package (WSP).

[0040] In an embodiment, it can be Figure 1 As shown, one storage device 1000 is provided. However, the present disclosure is not limited thereto, and two or more storage devices 1000 may be provided. The plurality of storage devices 1000 may be operated by using a redundant array of independent disks (RAID) scheme or a redundant array of inexpensive disks (RAID) scheme, in which the plurality of storage devices 1000 operate as one storage device.

[0041] The memory device 1000 may include a memory device 100 and a memory controller 200. The memory device 100 may operate under the control of the memory controller 200. For example, the memory device 100 may receive a command and an address from the memory controller 200 and access a memory cell selected by the address among the memory cells. The memory device 100 may perform an operation indicated by the command on the memory cell selected by the address.

[0042] For example, the command may be a programming command, a read command, or an erase command. The programming command may instruct the memory device to perform a programming operation (or a write operation). The read command may instruct the memory device 100 to perform a read operation. The erase command may instruct the memory device 100 to perform an erase operation. Therefore, the operation indicated by the corresponding command in the command may be, for example, a programming operation (or a write operation), a read operation, or an erase operation.

[0043] In addition, the program operation may be an operation in which the memory device 100 stores data provided from the host 400 under the control of the memory controller 200. In one embodiment, the program operation may be an operation in which data is stored in any one of a plurality of memory blocks in the memory device 100.

[0044] For example, the memory device 100 may receive a programming command, an address, and data, and program the data to a memory cell selected by the address. The data to be programmed to the selected memory cell may be referred to as write data. The write data may include data (or user data) provided from the host 400 and metadata of the data.

[0045] The read operation may be an operation in which the memory device 100 reads read data stored in the memory device 100 under the control of the memory controller 200. For example, the memory device 100 may receive a read command and an address, and read data from a region selected by the address in the memory cell array. Data to be read from the selected region among the data stored in the memory device 100 may be defined as read data.

[0046] The erase operation may be an operation in which the memory device 100 erases data stored in the memory device 100 under the control of the memory controller 200. In one embodiment, the erase operation may erase data stored in any one of a plurality of memory blocks in the memory device 100. For example, the memory device 100 may receive an erase command and an address, and erase data stored in a region selected by the address.

[0047] The memory device 100 may be implemented as a volatile memory device or a non-volatile memory device. Examples of volatile memory devices include double data rate synchronous dynamic random access memory (DDR SDRAM), fourth generation low power double data rate (LPDDR4) SDRAM, graphic double data rate (GDDR) SRAM, low power DDR (LPDDR), Rambus dynamic random access memory (RDRAM), etc. Examples of non-volatile memory devices may include resistive random access memory (RRAM), phase change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), spin transfer torque random access memory (STT-RAM) and flash memory. Flash memory may include, for example, NAND flash memory, vertical NAND flash memory, NOR flash memory, etc. For illustration, it is assumed that the memory device 100 is a NAND flash memory.

[0048] The memory device 100 may store write data under the control of the memory controller 200 , or may read stored read data and provide the read data to the memory controller 200 .

[0049] The memory device 100 may include a plurality of planes 101, 102, 103, and 104. The number of planes may be as follows: Figure 1 4 as shown, but the present disclosure is not limited thereto. Each plane may include a memory cell array including memory cells for storing write data. The memory cell array may include a plurality of memory blocks. A memory block may be a unit for performing an erase operation to erase data. A memory block may include a plurality of pages, each of which corresponds to a unit for performing a program operation to store write data or a read operation to read stored read data.

[0050] The memory cell may be configured as any one of a single-level cell (SLC) storing one bit of data, a multi-level cell (MLC) storing two bits of data, a triple-level cell (TLC) storing three bits of data, and a quad-level cell (QLC) storing four bits of data. However, the present disclosure is not limited thereto, and the memory cell may store five or more bits of data.

[0051] In an embodiment, the memory device 100 may use, for example, a plane interleaving scheme to perform an operation indicated by a command. The plane interleaving scheme may be a scheme in which operations on corresponding planes of two or more planes at least partially overlap with each other. For example, the memory device 100 may perform a read operation on the zeroth plane 101 and a read operation on the first plane 102 to overlap with each other. However, the present disclosure is not limited thereto.

[0052] The memory controller 200 may control the overall operation of the memory device 1000. For example, when power is supplied to the memory device 1000, the memory controller 200 may execute instructions (e.g., firmware). When the memory device 100 is a flash memory device, the firmware may include a host interface layer, a flash translation layer, and a flash interface layer. Power may be supplied, for example, from an external power supply.

[0053] The host interface layer may control operations between the host 400 and the memory controller 200 .

[0054] The flash translation layer may convert a logical address provided from the host 400 into a physical address, and may control communication between the memory controller 200 and the memory device 100 .

[0055] The memory controller 200 may control the memory device 100 to perform a program operation, a read operation, and an erase operation, respectively, in response to a write request, a read request, and an erase request of the host 400 .

[0056] In a programming operation, the memory controller 200 may provide a programming command, a physical address, and write data to the memory device 100. In an embodiment, in a programming operation, the memory controller 200 may provide a programming command and a physical address to the memory device 100. Also, the memory controller 200 may provide a clear command to the buffer memory to provide (or clear) the data temporarily stored in the buffer memory to the memory device 100. When the data temporarily stored in the buffer memory is provided to the memory device 100, the data temporarily stored in the buffer memory may be erased.

[0057] In a read operation, the memory controller 200 may provide a read command and a physical address to the memory device 100 .

[0058] In an erase operation, the memory controller 200 may provide an erase command and a physical address to the memory device 100 .

[0059] In an embodiment, the physical address may include a plane number, a block number, a page number, and a sub-page number.

[0060] The memory controller 200 may autonomously generate commands, addresses, and data regardless of any request provided from the host 400. The memory controller 200 may transmit the autonomously generated commands, addresses, and data to the memory device 100. For example, the memory controller 200 may generate commands, addresses, and data for performing background operations. Moreover, the memory controller 200 may provide commands, addresses, and data to the memory device 100. For example, the command for performing background operations may be a program command or a read command.

[0061] The background operation may be at least one of wear leveling, read reclamation, and garbage collection.

[0062] For example, wear leveling may include static wear leveling, dynamic wear leveling, etc. Static wear leveling may include the following operations: storing the number of times a storage block is erased, and moving cold data that has hardly performed any erase operation or any write operation to the storage block with the most erase times. Dynamic wear leveling may include the following operations: storing the number of times a storage block is erased, and programming data to the storage block with the least erase times.

[0063] Read reclamation may include an operation of moving data stored in a memory block to another memory block before an uncorrectable error occurs in the data stored in the memory block.

[0064] Garbage collection may include the following operations: copying valid data included in a bad block among storage blocks to a free block and erasing invalid data in the bad block. Copying valid data in the bad block to the free block may include: moving valid data in the bad block to the free block.

[0065] In an embodiment, the memory controller 200 may control the memory device 100 to perform background operations within a predetermined period (e.g., an idle period or other period). For example, the idle period may include a period during which no request from the host 400 is provided. In an embodiment, the idle period may include a period corresponding to the following: a period from when a response to a request from the host 400 is provided to the host 400 to when a subsequent request from the host 400 is provided to the memory device 1000.

[0066] In an embodiment, the memory controller 200 may control two or more memory devices 100. The memory controller 200 may control the memory devices 100 according to, for example, an interleaving scheme to improve operation performance. The interleaving scheme may include controlling operations of two or more memory devices 100 to overlap with each other.

[0067] The memory controller 200 may sequentially store commands and physical addresses in at least one command queue, and may provide the commands and physical addresses stored in the command queue to the memory device according to the scheduling order. The commands and physical addresses stored in the command queue may be output according to a first-in-first-out (FIFO) scheme. However, the present disclosure is not limited thereto.

[0068] For example, the memory controller 200 may sequentially store the read command and the physical address in the read command queue, and sequentially provide the read command and the physical address stored in the read command queue to the memory device 100 .

[0069] In one example, the memory controller 200 may store the program command and the physical address in a program command queue, and store the read command and the physical address in a read command queue. Also, the memory controller 200 may first provide the program command and the physical address to the memory device 100, and then provide the read command and the physical address to the memory device 100.

[0070] The memory controller 200 may provide an erase command to the memory device 100. When the memory device 100 performs an erase operation in response to the erase command, the memory controller 200 may receive a request (e.g., a read request) from the host 400. The memory controller 200 may provide a suspend command in response to the request of the host 400. The suspend command may instruct the memory device 100 to suspend the erase operation. After providing the suspend command to the memory device 100, the memory controller 200 may provide a command (e.g., a read command) to the memory device 100 instructing the memory device 100 to perform an operation corresponding to the request of the host 400. The memory device 100 may suspend the erase operation in response to the suspend command, and perform an operation (e.g., a read operation) in response to the command (e.g., a read command). After completing the operation corresponding to the request, the memory controller 200 may provide a resume command to the memory device 100. The resume command may instruct the memory device 100 to resume the erase operation. The memory device 100 may resume the erase operation in response to the resume command.

[0071] When the erase operation is resumed in response to the resume command, there may be a certain preparation time before the erase operation is normally performed. This preparation time may be the time delayed before the erase operation is normally performed. When the host 400 provides a request (e.g., a read request) to the memory controller 200 during the preparation time, a command (e.g., a read command) instructing the memory device 100 to perform an operation corresponding to the request may be continuously stored in the command queue. When commands are continuously queued in the command queue, the response to the request of the host 400 may be delayed.

[0072] When commands indicating an operation on any one of the plurality of planes 101, 102, 103, and 104 are sequentially stored in the command queue, the next command to be outputted can be provided to the memory device 100 only when the operation indicated by the command outputted first is completed. For example, when the operation indicated by the command outputted first is performed, the next command to be outputted can be queued in the command queue. For example, when a program command indicating a program operation on the zeroth plane 101 and a read command indicating a read operation on the zeroth plane 101 are sequentially stored in each command queue, when the program operation is performed based on the program command, the read command can be queued in the command queue.

[0073] In a case where an operation indicated by a command output first is not completed, a read operation may be delayed when a read command and a physical address are continuously queued in a read command queue.

[0074] In response to a read request from the host 400, the memory controller 200 may store the read command and the physical address in the first read command queue according to the index number. Furthermore, when a scheduling event occurs, the memory controller 200 may schedule the read command and the physical address stored in the first read command queue to the second read command queue. Furthermore, the memory controller 200 may provide the memory device 100 with the scheduled read command and the scheduled physical address stored in the second read command queue according to the scheduling order.

[0075] In an embodiment, when a scheduling event occurs, the memory controller 200 may search for a first physical address group among the physical addresses stored in the first read command queue, the first physical address group including physical addresses with the same page number. Furthermore, the memory controller 200 may search for a second physical address group among the physical addresses stored in the first read command queue, the second physical address group including all physical addresses whose plane numbers are different from those of the first physical address group. Furthermore, the memory controller 200 may sequentially schedule the first physical address group and the second physical address group to the continuous index numbers of the second read command queue. The number of physical addresses in a physical address group may be one or more, and the number of physical address groups may be one or more.

[0076] The scheduling event may occur after the resume command is provided to the memory device 100. For example, the scheduling event may occur within a period corresponding to the period from the time when the resume command is provided to the memory device 100 to the time when the suspend command is provided to the memory device 100. For example, the scheduling event may occur before the completion of an erase operation or a program operation (or a write operation).

[0077] The memory controller 200 may include a command generation controller 210, a command storage device 220, and a command scheduling controller 230. The command generation controller 210 may generate a command in response to a request of the host 400. For example, the command generation controller 210 may generate a read command in response to a read request of the host 400. For example, the command generation controller 210 may generate a program command in response to a write request of the host 400. For example, the command generation controller 210 may generate an erase command in response to an erase request of the host 400. For example, the command generation controller 210 may generate a suspend command or a resume command.

[0078] The command generation controller 210 may convert a logical address from the host 400 into a physical address. The command generation controller 210 may be implemented as, for example, a flash translation layer.

[0079] The command generation controller 210 may provide the command and the physical address stored in the command storage device 220 to the memory device 100. In an embodiment, the command generation controller 210 may provide an erase command to the memory device 100, may provide a suspend command to the memory device 100 in response to a request provided by the host 400 during an erase operation, and may provide a resume command to the memory device 100 when an operation corresponding to the request is completed.

[0080] In an embodiment, after providing the restore command to the memory device 100, the command generation controller 210 may provide a scheduling event signal to the command scheduling controller 230. Figure 5 Embodiments are described.

[0081] In one embodiment, after a predetermined period of time has passed since a command instructing the memory device 100 to perform an erase operation or a write operation is provided to the memory device 100, the command generation controller 210 may provide a scheduling event signal to the command scheduling controller 230. Figure 6 and Figure 7 Embodiments are described.

[0082] The command storage device 220 may store commands and physical addresses, and may include at least one read command queue. For example, the command storage device 220 may include a read command queue, a program command queue, and / or an erase command queue.

[0083] The command scheduling controller 230 may compare the physical addresses stored in the command storage device 220 in response to the scheduling event signal. The command scheduling controller 230 may search for a physical address including the same page number among the physical addresses stored in the command storage device 220. A group including physical addresses having the same page number may be defined as a first physical address group. The command scheduling controller 230 may search for a second physical address group other than the first physical address group among the physical addresses stored in the command storage device 220. The second physical address group may be a group including physical addresses having a page number different from all plane numbers of the first physical address group.

[0084] The command scheduling controller 230 may sequentially schedule the first physical address group and the second physical address group into the second read command queue so that, for example, a read operation on the first physical address group and a read operation on the second physical address group are performed according to a plane interleaving scheme. Figures 10 to 13 Embodiments are described.

[0085] The physical addresses in the first physical address group may be scheduled to the same index number of the second read command queue. In an embodiment, when the first physical address group is not searched, the read commands and physical addresses stored in the command storage device 220 may be scheduled again so that the read operation is performed on the plane using the plane interleaving scheme as much as possible. Figures 14 to 17 Embodiments are described.

[0086] The memory device 1000 may include a buffer memory that stores data only when powered from a power source. The buffer memory may be in the memory controller 200. Alternatively, the buffer memory may be disposed outside the memory controller 200 and coupled to the memory controller 200. For example, the buffer memory may be a volatile memory device. Examples of the buffer memory include a double data rate synchronous dynamic random access memory (DDR SDRAM), a fourth generation low power double data rate (LPDDR4) SDRAM, a graphic double data rate (GDDR) SRAM, a low power DDR (LPDDR), and a Rambus dynamic random access memory (RDRAM).

[0087] The host 400 may communicate with the storage device 1000 through an interface. For example, the interface may be implemented as a serial advanced technology attachment (SATA) interface, a high-speed SATA (SATAe) interface, a serial small computer system interface (SAS) interface, a high-speed peripheral component interconnect (PCIe) interface, a high-speed non-volatile memory (NVMe) interface, an advanced host controller interface (AHCI) interface, or a multimedia card interface. However, the present disclosure is not limited thereto.

[0088] The host 400 may store data in the storage device 1000 , or may communicate with the storage device 1000 to acquire data stored in the storage device 1000 .

[0089] In an embodiment, the host 400 may provide the storage device 1000 with a write request for requesting the storage device 1000 to store data. Also, the host 400 may provide the storage device 1000 with the write request, the data, and a logical address for identifying the data.

[0090] The storage device 1000 may store write data in response to a write request provided from the host 400. The write data including the data and metadata provided by the host 400 may be stored in the memory device 100. The storage device 1000 may also provide a response to the host 400 indicating that storage of the write data has been completed.

[0091] In an embodiment, the host 400 may provide the memory device 1000 with a read request requesting the memory device 1000 to provide data stored in the memory device 1000 to the host 400. The host 400 may provide the memory device 1000 with the read request and a read address.

[0092] The storage device 1000 may read read data corresponding to a read address provided by the host 400 from the memory device 100, and may provide the read data to the host 400 as a response to the read request. The data may be read in response to the read request from the host 400.

[0093] Figure 2 is a diagram showing an embodiment of a plurality of planes PLANE0, PLANE1, PLANE2 and PLANE3, which may correspond to, for example, Figure 1 Shown are planes 101, 102, 103, and 104. Each of the planes PLANE0, PLANE1, PLANE2, and PLANE3 may include a plurality of memory blocks MB1, MB2, MB3, ..., and MBm, where m is a natural number of 2 or greater.

[0094] In an embodiment, the memory blocks MB1, MB2, MB3, ... and MBm may be divided into system blocks and user blocks. For example, the first memory block MB1 and the second memory block MB2 may be system blocks, and the third to mth memory blocks MB3 to MBm may be user blocks, but the present disclosure is not limited thereto.

[0095] The system block may store metadata, which includes mapping data, validity data, data of uncorrectable errors, operation data, and the like. The mapping data may be data indicating a mapping relationship between a logical address and a physical address. The validity data may be data indicating the validity of data (or user data) provided from the host 400. The data of uncorrectable errors may be data indicating that the data (or user data) provided from the host 400 has an uncorrectable error. The operation data may be data indicating whether the physical address stored in the command queue is an address converted from a logical address from the host 400 or an address generated to perform a background operation. However, the present disclosure is not limited thereto.

[0096] The user block may store data, for example, data and metadata provided from the host 400. A plurality of user blocks may be included.

[0097] Each of the storage blocks MB1, MB2, MB3, ... and MBm may include a plurality of pages PAGE1, PAGE2, ... and PAGEn, where n is a natural number of 2 or greater. Each of the pages PAGE1, PAGE2, ... and PAGEn may be divided into virtual subpages SP0, SP1, SP2 and SP3 according to a read unit, which is a unit for performing a read operation. In one embodiment, the read unit may be predetermined based on the size of the page and the number of subpages. For example, when the page size is 16KB and the number of subpages is 4, the read unit may be 4KB. However, the present disclosure is not limited thereto. In one embodiment, the terms "subpage", "slice", "segment", etc. may have the same meaning.

[0098] In an embodiment, a physical address may include a plane number, a block number, a page number, and a subpage number. The plane number may indicate any one of planes PLANE0, PLANE1, PLANE2, and PLANE3. The block number may indicate any one of a plurality of storage blocks MB1, MB2, MB3, ..., and MBm in a plane. The page number may indicate any one of a plurality of pages PAGE1, PAGE2, ..., and PAGEn in a storage block. The subpage number may indicate any one of subpages SP0, SP1, SP2, and SP3 in a page.

[0099] Figure 3 1 is a diagram showing an embodiment of a memory device 100, which may include a memory cell array 110, a peripheral circuit 120, and a control logic 130. The memory cell array 110 may include a plurality of memory blocks MB1 to MBk (k is a positive integer). The number of memory blocks MB1 to MBk shown is only an example, and may be a different number in another embodiment.

[0100] Each of the memory blocks MB1 to MBk may be connected to a local line LL and bit lines BL1 to BLn (n is a positive integer). The local line LL may be connected to the row decoder 122 and each of the memory blocks MB1 to MBk. The local line LL may include a first selection line, a second selection line, and a plurality of word lines arranged between the first selection line and the second selection line. The local line LL may further include a dummy line arranged between the first selection line and the word line, a dummy line arranged between the second selection line and the word line, and a pipeline.

[0101] The bit lines BL1 to BLn may be commonly connected to the memory blocks MB1 to MBk.

[0102] The memory blocks MB1 to MBk may be implemented in a two-dimensional or three-dimensional structure. In a two-dimensional structure, the memory cells in the memory blocks MB1 to MBk may be arranged in a direction parallel to the substrate. In a three-dimensional structure, the memory cells in the memory blocks MB1 to MBk may be stacked in a direction perpendicular to the substrate.

[0103] The peripheral circuit 120 may include a voltage generator 121, a row decoder 122, a page buffer group 123, a column decoder 124, an input / output circuit 125, and a sensing circuit 126. The voltage generator 121 may generate various operation voltages Vop for a program operation, a read operation, and an erase operation in response to an operation command OP_CMD. Moreover, the voltage generator 121 may selectively discharge the local line LL in response to the operation command OP_CMD. For example, the voltage generator 121 may generate a program voltage, a verification voltage, a pass voltage, a turn-on voltage, a read voltage, an erase voltage, a source line voltage, etc. under the control of the control logic 130.

[0104] In an embodiment, the voltage generator 121 may generate an internal power supply voltage by adjusting an external power supply voltage. The internal power supply voltage generated by the voltage generator 121 is used as an operating voltage of the memory device 100.

[0105] In an embodiment, the voltage generator 121 may generate a plurality of voltages using an external power supply voltage or an internal power supply voltage. For example, the voltage generator 121 may include a plurality of pumping capacitors for receiving the internal power supply voltage, and generate a plurality of voltages by selectively activating the pumping capacitors under the control of the control logic 130. The generated voltages may be supplied to the memory cell array 110 by the row decoder 122.

[0106] The row decoder 122 may transfer the operating voltage Vop to the local line LL in response to the row address RADD. The operating voltage Vop may be transferred to a selected memory block among the memory blocks MB1 to MBk through the local line LL.

[0107] For example, in a programming operation, the row decoder 122 may apply a program voltage to a selected word line, and may apply a program pass voltage (a level lower than the program voltage) to unselected word lines. In a program verification operation, the row decoder 122 may apply a verification voltage to a selected word line, and may apply a verification pass voltage (higher than the verification voltage) to unselected word lines.

[0108] In a read operation, the row decoder 122 may apply a read voltage to a selected word line, and may apply a read pass voltage (higher than the read voltage) to unselected word lines.

[0109] In an erase operation, the row decoder 122 may select a memory block according to the decoded address. In an erase operation, the row decoder 122 may apply a reference (eg, ground) voltage to a word line connected to the selected memory block.

[0110] The page buffer group 123 may include first to nth page buffers PB1 to PBn connected to the memory cell array 110 through first to nth bit lines BL1 to BLn, respectively. The first to nth page buffers PB1 to PBn operate under the control of the control logic 130. For example, the first to nth page buffers PB1 to PBn may operate in response to a page buffer control signal PBSIGNAL. For example, in a read operation or a verification operation, the first to nth page buffers PB1 to PBn may temporarily store data received through the first to nth bit lines BL1 to BLn, or may sense a voltage or current of the bit lines BL1 to BLn.

[0111] In a programming operation, when a programming voltage is applied to a selected word line, the first to nth page buffers PB1 to PBn may transmit data DATA received through the column decoder 124 and the input / output circuit 125 to the selected memory cell through the first to nth bit lines BL1 to BLn. The memory cells of the selected page are programmed according to the transmitted data DATA. The memory cells connected to the bit lines to which a programming enable voltage (e.g., a ground voltage) is applied may have an increased threshold voltage. The threshold voltage of the memory cells connected to the bit lines to which a programming inhibit voltage (e.g., a power supply voltage) is applied may be maintained.

[0112] In a verification operation, the first to nth page buffers PB1 to PBn may sense data stored in selected memory cells from the selected memory cells through the first to nth bit lines BL1 to BLn.

[0113] In a read operation, the first to nth page buffers PB1 to PBn may sense data DATA from memory cells of a selected page through the first to nth bit lines BL1 to BLn and may output the sensed data DATA to the input / output circuit 125 under the control of the column decoder 124 .

[0114] In an erase operation, the first to nth page buffers PB1 to PBn may float the first to nth bit lines BL1 to BLn.

[0115] The column decoder 124 may transfer data between the input / output circuit 125 and the page buffer group 123 in response to the column address CADD. For example, the column decoder 124 may exchange data with the page buffers PB1 to PBn through the data lines DL, or may exchange data with the input / output circuit 125 through the column lines CL. The input / output circuit 125 may transfer the command CMD and the address ADD transferred from the memory controller 200 to the control logic 130, or may exchange data DATA with the column decoder 124.

[0116] In a read operation or a verification operation, the sense circuit 126 may generate a reference current in response to the enable bit VRY_BIT<#> and may output a pass signal PASS or a fail signal FAIL by comparing a sense voltage VPB received from the page buffer group 123 with a reference voltage generated by the reference current.

[0117] The control logic 130 may control the peripheral circuit 120 by outputting an operation command OP_CMD, a row address RADD, a page buffer control signal PBSIGNAL, and an enable bit VRY_BIT<#> in response to a command CMD and an address ADD.

[0118] Figure 4 is a diagram illustrating an embodiment of a memory controller 200 , which may include a command generation controller 210 , a command storage 220 , and a command scheduling controller 230 .

[0119] The command generation controller 210 may receive a read request from the host 400 and may generate a read command instructing the memory device to read data stored in the memory device in response to the read request. For example, the read command may be generated in response to a current read request from the host 400.

[0120] The command generation controller 210 may convert a logical address from the host 400 into a physical address. The physical address may be provided together with the read command. In one embodiment, the physical address may be provided together with the read command stored in the command storage device 220.

[0121] The command generation controller 210 may input the read command and the physical address to the command storage 220. The command generation controller 210 may generate a scheduling event signal, and may provide the scheduling event signal to the command scheduling controller 230.

[0122] The command storage device 220 may sequentially store read commands instructing the memory device 100 to read data stored in the memory device 100 and a physical address corresponding to each read command. In an embodiment, the command storage device 220 may include a first read command queue and a second read command queue. The first read command queue may sequentially store read commands generated in response to a read request from the host 400 and a physical address corresponding to the read command. When a predetermined scheduling event occurs, the second read command queue may rearrange and store the read commands and physical addresses stored in the first read command queue.

[0123] The command scheduling controller 230 may receive a scheduling event signal. When the scheduling event signal is received, the command scheduling controller 230 may search for a first physical address group among the physical addresses stored in the first read command queue. Furthermore, the command scheduling controller 230 may search for a second physical address group among the physical addresses stored in the first read command queue. Furthermore, the command scheduling controller 230 may sequentially schedule the first physical address group and the second physical address group to consecutive index numbers of the second read command queue.

[0124] Figure 5 is a diagram showing an embodiment of providing a scheduling event signal. Figure 5 At time T1, the command generation controller 210 may provide an erase command ECMD to the memory device 100. The memory device 100 may start an erase operation in response to the erase command ECMD.

[0125] At time T2, the host 400 may provide a request to the command generation controller 210. For example, the request of the host 400 may be a write request or a read request. The command generation controller 210 may provide a suspend command SPD_CMD to the memory device 100. The memory device 100 may suspend the erase operation started at time T1 in response to the suspend command SPD_CMD.

[0126] At time T3, the command generation controller 210 may provide the memory device 100 with a command CMD corresponding to the request of the host 400 provided at time T2. When the request of the host 400 is a write request, the command CMD may be a program command. In one embodiment, when the request of the host 400 is a read request, the command CMD may be a read command. The memory device 100 may perform an operation indicated by the command CMD in response to the command CMD.

[0127] At time T4, the memory device 100 may complete the operation indicated by the command CMD. The command generation controller 210 may provide the memory device 100 with a resume command RSM_CMD. The memory device 100 may resume the erase operation suspended at time T2 in response to the resume command RSM_CMD. Before the memory device 100 normally performs the erase operation, a certain preparation time may be required. The preparation time may correspond to the recovery delay time. For example, when the erase operation is resumed at time T4, the erase operation may be performed normally from T6 after the recovery delay time.

[0128] During the recovery delay time, the host 400 may provide a read request to the command generation controller 210. Whenever a read request of the host 400 is provided to the command generation controller 210, the read command and the physical address may be sequentially stored in the first read command queue in the command storage 220. When the read commands and the physical addresses stored in the first read command queue are continuously queued in the first read command queue, a response to the read request of the host 400 may be delayed.

[0129] In an embodiment, at time T5 after providing the resume command RSM_CMD to the memory device 100 , the command generation controller 210 may provide the scheduling event signal EVT_SIG to the command scheduling controller 230 .

[0130] Figure 6 is a diagram showing an embodiment of providing a scheduling event signal. Figure 6 , the command generation controller 210 may not generate the suspend command SPD_CMD and the resume command RSM_CMD. Figure 5 The command generation controller 210 may output the scheduling event signal EVT_SIG after a predetermined period of time has passed since the command CMD is provided to the memory device 100 .

[0131] At time T1', the command generation controller 210 may provide a program command PCMD to the memory device 100. The memory device 100 may start a program operation (or a write operation) in response to the program command PCMD.

[0132] The time when the programming operation is normally completed may be the programming operation time tPROG. Information (or data) about the programming operation time tPROG may be stored in a memory block allocated as a CAM block among a plurality of memory blocks MB1, MB2, MB3, ..., and MBm in the memory device 100. At startup, the memory controller 200 may acquire information about the programming operation time tPROG from the memory device 100. For example, the programming operation time tPROG may be a period corresponding to a period from time T1' to time T3'.

[0133] The command generation controller 210 may provide the command scheduling controller 230 with a scheduling event signal EVT_SIG before a program operation time tPROG elapses after a time when the program command PCMD is provided to the memory device 100 .

[0134] In an embodiment, the command generation controller 210 may provide the command scheduling controller 230 with the scheduling event signal EVT_SIG at a time when the predetermined first reference time tSET1 elapses after the time when the program command PCMD is provided to the memory device 100. For example, the time when the predetermined first reference time tSET1 elapses after the time T1' may be T2'.

[0135] Information (or data) about the first reference time tSET1 may be stored in a memory block allocated as a CAM block among a plurality of memory blocks MB1, MB2, MB3, ..., and MBm in the memory device 100. At startup, the memory controller 200 may acquire information about the first reference time tSET1 from the memory device 100. In an embodiment, the first reference time tSET1 may be shorter than the program operation time tPROG. At time T3', the command generation controller 210 may provide a command for checking a result of the program operation to the memory device 100.

[0136] Figure 7 is a diagram showing an embodiment of providing a scheduling event signal. Figure 7 At time T1′, the command generation controller 210 may provide an erase command ECMD to the memory device 100. The memory device 100 may start an erase operation in response to the erase command ECMD.

[0137] The time for normally completing the erase operation may be the erase operation time tER. Information (or data) about the erase operation time tER may be stored in a memory block allocated as a CAM block among the plurality of memory blocks MB1, MB2, MB3, ..., and MBm in the memory device 100. At startup, the memory controller 200 may obtain information about the erase operation time tER from the memory device 100. For example, the erase operation time tER may be a period corresponding to a period from time T1' to time T5'. In one embodiment, the erase operation time tER may be longer than Figure 6 The programming operation time is tPROG.

[0138] The command generation controller 210 may provide the scheduling event signal EVT_SIG to the command scheduling controller 230 before the erase operation time tER elapses after the time when the erase command ECMD is provided to the memory device 100 .

[0139] In an embodiment, the command generation controller 210 may provide the command scheduling controller 230 with the scheduling event signal EVT_SIG after the predetermined second reference time tSET2 after the erase command ECMD is provided to the memory device 100. For example, the time after the predetermined second reference time tSET2 after the time T1' may be T4'.

[0140] Information (or data) about the second reference time tSET2 may be stored in a memory block allocated as a CAM block among a plurality of memory blocks MB1, MB2, MB3, ..., and MBm in the memory device 100. At startup, the memory controller 200 may acquire information about the second reference time tSET2 from the memory device 100. In an embodiment, the second reference time tSET2 may be shorter than the erase operation time tER. In an embodiment, the second reference time tSET2 may be equal to the first reference time tSET1 or longer than the first reference time tSET1.

[0141] Figure 8 is a diagram illustrating an embodiment of a command storage device 220 , which may include a first read command queue 221 and a second read command queue 222 .

[0142] Reference Figure 8 The first read command queue 221 may sequentially store the read command RCMD and the physical address Physical Address according to the index number. For example, the physical address including the plane number 0P0, the block number 100BLK100, the page number 5PG5 and the subpage number 0S0 and the read command RCMD1 may be stored in the index number 0Index0 of the first read command queue 221.

[0143] For example, a physical address including a plane number 0P0, a block number 200BLK200, a page number 10PG10, and a subpage number 3S3, and a read command RCMD2 may be stored in an index number 1Index1 of the first read command queue 221 .

[0144] For example, a physical address including a plane number 3P3 , a block number 303 BLK303 , a page number 50PG50 , and a subpage number 2S2 , and a read command RCMD3 may be stored in an index number 2Index2 of the first read command queue 221 .

[0145] For example, a physical address including a plane number 0P0, a block number 100BLK100, a page number 5PG5, and a subpage number 3S3, and a read command RCMD4 may be stored in an index number 3Index3 of the first read command queue 221 .

[0146] For example, a physical address including a plane number 2P2 , a block number 206 BLK206 , a page number 10PG10 , and a subpage number 2S2 , and a read command RCMD5 may be stored in an index number 4Index4 of the first read command queue 221 .

[0147] The read commands RCMD1, RCMD2, RCMD3, RCMD4, and RCMD5 and the physical addresses respectively stored in the index numbers Index0, Index1, Index2, Index3, and Index4 of the first read command queue 221 may be sequentially provided to the memory device 100. For example, the read commands RCMD1, RCMD2, RCMD3, RCMD4, and RCMD5 and the physical addresses may be sequentially provided starting from the lowest number among the index numbers Index0, Index1, Index2, Index3, and Index4 of the first read command queue 221. However, the present disclosure is not limited thereto.

[0148] Before the scheduling event occurs, the second read command queue 222 may be empty.

[0149] When the operation indicated by the command (currently executed in the memory device 100) is not completed, the read commands RCMD1, RCMD2, RCMD3, RCMD4, and RCMD5 and the physical address in the first read command queue 221 may continue to be on standby in the respective index numbers of the first read command queue 221 until the operation currently executed in the memory device 100 is completed. The time to perform the read operation in response to the read request of the host 400 (or the read busy time tR) increases, the performance of the read operation decreases, and the read response to the read request of the host 400 is delayed.

[0150] To alleviate this concern, the first read command queue 221 may be rescheduled according to whether the physical addresses stored in the first read command queue 221 are to be provided to the memory device 100 according to a specific output order.

[0151] Fig. 9 2 is a diagram exemplarily illustrating an embodiment of a read operation. Figure 8 and Fig. 9, the physical address stored in the index number 0Index0 of the first read command queue 221 and the read command RCMD1 may be provided to the memory device 100. The memory device 100 may perform a read operation PGS read on a sub-page corresponding to the physical address including the plane number 0P0, the block number 100BLK100, the page number 5PG5, and the sub-page number 0S0 in response to the read command RCMD1. The data stored in the sub-page may be output through the read operation PGS read (DATA OUT).

[0152] Next, the read command RCMD2 and the physical address stored in the index number 1Index1 of the first read command queue 221 may be provided to the memory device 100. The memory device 100 may perform a read operation PGS read on a subpage corresponding to the physical address including the plane number 0P0, the block number 200BLK200, the page number 10PG10, and the subpage number 3S3 in response to the read command RCMD2. The data stored in the subpage may be output through the read operation PGS read (DATA OUT).

[0153] After the read command RCMD2 stored in the index number 1Index1 of the first read command queue 221 is provided to the memory device 100, the read command RCMD3 (stored in the index number 2Index2 of the first read command queue 221) and the physical address may be provided to the memory device 100. The memory device 100 may perform a read operation PGS read on a subpage corresponding to the physical address including the plane number 3P3, the block number 303BLK303, the page number 50PG50, and the subpage number 2S2 in response to the read command RCMD3.

[0154] Since the plane numbers of the physical addresses stored in the index number 1Index1 of the first read command queue 221 and the plane numbers of the physical addresses stored in the index number 2Index2 of the first read command queue 221 are different from each other, the memory device 100 can perform a read operation on the zeroth plane 101 having the plane number 0P0 and the third plane 104 having the plane number 3P3, for example, using a plane interleaving scheme. For example, the read operation PGS read on the zeroth plane 101 and the read operation PGS read on the third plane 104 can partially overlap with each other.

[0155] Data (DATA OUT) may be output by a read operation PGS read performed on the third plane 104 having the plane number 3P3. After the data output by the read operation PGS read performed on the zeroth plane 101 is provided to the memory controller 200, the data (DATA OUT) output by the read operation PGS performed on the third plane 104 is output. This is because multiple planes (e.g., Figure 1 plane 101 to 104 or Figure 2 The planes PLANE0, PLANE1, PLANE2, and PLANE3) are connected to one channel.

[0156] Next, the read command RCMD4 and the physical address stored in the index number 3Index3 of the first read command queue 221 may be provided to the memory device 100. The memory device 100 may perform a read operation PGS read on a sub-page corresponding to the physical address including the plane number 0P0, the block number 100BLK100, the page number 5PG5, and the sub-page number 3S3 in response to the read command RCMD4. The data stored in the sub-page may be output through the read operation PGS read (DATA OUT).

[0157] After the read command RCMD4 stored in the index number 3Index3 of the first read command queue 221 is provided to the memory device 100, the read command RCMD5 (stored in the index number 4Index4 of the first read command queue 221) and the physical address may be provided to the memory device 100. The memory device 100 may perform a read operation PGS read on a subpage corresponding to the physical address including the plane number 2P2, the block number 206BLK206, the page number 10PG10, and the subpage number 2S2 in response to the read command RCMD5.

[0158] Since the plane numbers of the physical addresses stored in the index number 3Index3 and the index number 4Index4 of the first read command queue 221 are different from each other, the memory device 100 can use a plane interleaving scheme to perform a read operation on the zeroth plane 101 and the second plane 103. For example, the read operation PGS read on the zeroth plane 101 and the read operation PGS read on the second plane 103 may partially overlap with each other. Data (DATA OUT) may be output by the read operation performed on the second plane 103. After the data output by the read operation PGS read performed on the zeroth plane 101 is provided to the memory controller 200, the data (DATA OUT) output by the read operation PGS read performed on the second plane 103 is output. The reason is that multiple planes (for example, Figure 1 plane 101 to 104 or Figure 2 The planes PLANE0, PLANE1, PLANE2, and PLANE3) are connected to one channel.

[0159] A first time t1 may be required to complete the read operations regarding the read commands RCMD1, RCMD2, RCMD3, RCMD4, and RCMD5 stored in the respective index numbers of the first read command queue 221. When there are physical addresses to be simultaneously provided to the memory device 100 (among the physical addresses stored in the index numbers 0Index0 to 4Index4 of the first read command queue 221), or there are physical addresses to be read using the plane interleaving scheme (among the physical addresses stored in the index numbers 0Index0 to 4Index4 of the first read command queue 221), the time to complete the read operation may be shorter than the first time t1.

[0160] Fig.10 is a diagram illustrating an embodiment of scheduling a read command and a physical address stored in a first read command queue to a second read command queue.

[0161] Reference Fig.10 In an embodiment, the command scheduling controller 230 may search for a first physical address group including physical addresses having the same page number among the physical addresses stored in the first read command queue 221. In an embodiment, the first physical address group may include physical addresses having the same plane number, the same block number, and the same page number.

[0162] For example, since the physical addresses stored in index number 0Index0 and index number 3Index3 of the first read command queue 221 both include plane number 0P0, block number 100BLK100 and page number 5PG5, the physical addresses stored in index number 0Index0 and index number 3Index3 of the first read command queue 221 can be searched as the first physical address group.

[0163] The command scheduling controller 230 may schedule the read command corresponding to the first physical address group and the first physical address group to any one index number (e.g., index number 0 Index0) among index numbers Index0, Index1, Index2, Index3, Index4, Index5, Index6, and Index7 of the second read command queue 222. The number of read commands RCMD1 stored in index number 0 Index0 of the second read command queue 222 may be 1, which is equal to the number of plane numbers in the first physical address group.

[0164] In an embodiment, the first physical address group may include physical addresses having different plane numbers and the same page number. For example, the physical address stored in the index number 1Index1 of the first read command queue 221 includes the plane number 0P0, the block number 200BLK200, the page number 10PG10, and the sub-page number 3S3, while the physical address stored in the index number 4Index4 of the first read command queue 221 includes the plane number 2P2, the block number 206BLK206, the page number 10PG10, and the sub-page number 2S2.

[0165] Since the physical addresses stored in index number 1Index1 and index number 4Index4 of the first read command queue 221 are physical addresses including different plane numbers but the same page number, the physical addresses stored in index number 1Index1 and index number 4Index4 of the first read command queue 221 can be searched as the first physical address group.

[0166] The command scheduling controller 230 may schedule the read command corresponding to the first physical address group and the first physical address group to any one index number (e.g., index number 2Index2) among index numbers Index0, Index1, Index2, Index3, Index4, Index5, Index6, and Index7 of the second read command queue 222. The number of read commands RCMD3 stored in index number 2Index2 of the second read command queue 222 may be 2, which is equal to the number of plane numbers in the first physical address group.

[0167] The command scheduling controller 230 may search for the second physical address group among the physical addresses stored in the first read command queue 221. For example, when the physical addresses stored in the index number 1 Index1 and the index number 4 Index4 of the first read command queue 221 are in the first physical address group, the physical address stored in the index number 2 Index2 of the first read command queue 221 may be in the second physical address group.

[0168] The command scheduling controller 230 may sequentially schedule the first physical address group and the second physical address group to consecutive index numbers of the second read command queue 222. For example, the command scheduling controller 230 may schedule the physical addresses stored in the index number 0Index0 and the index number 3Index3 of the first read command queue 221 to the index number 0Index0. Moreover, the command scheduling controller 230 may schedule the physical addresses including the plane number 3P3, the block number 303BLK303, the page number 50PG50, and the subpage number 2S2 to the index number 1Index1 of the second read command queue 222. The command scheduling controller 230 may schedule the physical addresses stored in the index number 1Index1 and the index number 4Index4 of the first read command queue 221 to the index number 2Index2 of the second read command queue 222.

[0169] Fig.11 This is an example showing Fig.10 A diagram of an embodiment of a read operation performed by an embodiment of .

[0170] Reference Fig.10 and Fig.11 , the read command RCMD1 and the physical address stored in the index number 0Index0 of the second read command queue 222 may be provided to the memory device 100. The memory device 100 may, in response to the read command RCMD1, perform a read operation on a page in a single plane (e.g., the zeroth plane 101) having the physical address stored in the index number 0Index0 of the second read command queue 222. The read operation performed on the page in a single plane may correspond to a single-plane read operation SP read.

[0171] Next, the read command RCMD2 and the physical address stored in the index number 1Index1 of the second read command queue 222 may be provided to the memory device 100. The memory device 100 may perform a read operation PGSread on the subpage corresponding to the physical address stored in the index number 1Index1 of the second read command queue 222 in response to the read command RCMD2.

[0172] The memory device 100 may perform a read operation on the zeroth plane 101 having a plane number 0P0 and the third plane 104 having a plane number 3P3 using a plane interleaving scheme.

[0173] Data (DATA OUT) can be outputted by a read operation PGS read performed on the third plane 104. Next, data (DATA OUT) is outputted by a single plane read operation SP read performed on the zeroth plane 101. The reason is that multiple planes (e.g., Figure 1 planes 101 to 104 as shown, or Figure 2 The planes PLANE0, PLANE1, PLANE2 and PLANE3 shown are connected to one channel, and the read operation PGS read is faster than the single plane read operation SP read.

[0174] Next, the read command RCMD3 and the physical address stored in the index number 2Index2 of the second read command queue 222 may be provided to the memory device 100. In response to the read command RCMD3, the memory device 100 may simultaneously perform a read operation on the pages in each plane having the physical address stored in the index number 2Index2 of the second read command queue 222. The read operation performed on the pages in each plane at the same time may be defined as a multi-plane read operation MP read.

[0175] Data (DATA OUT) may be output through the multi-plane read operation MP read performed on the zeroth plane 101. Next, data (DATA OUT) may be output through the multi-plane read operation MP read performed on the second plane 103.

[0176] The second time t2 may be required to complete the read operations for the read commands RCMD1, RCMD2, and RCMD3 stored in the respective index numbers of the second read command queue 222. The second time t2 may be shorter than the above reference time t2. Fig. 9 The first time t1 is described.

[0177] As described above, since the read command queue is rearranged, the number of sensing operations used to perform a read operation on a read request of the host 400 can be reduced, and a phenomenon in which a response to a read request of the host 400 is delayed can be prevented. Therefore, the performance of the read operation can be improved.

[0178] Fig.12 is a diagram illustrating an embodiment of scheduling a read command and a physical address stored in a first read command queue to a second read command queue.

[0179] Reference Fig.12, the command scheduling controller 230 may schedule the first physical address group (including physical addresses with the same plane number, the same block number, and the same page number among the physical addresses stored in the first read command queue 221) to any index number among the index numbers of the second read command queue 222. For example, the command scheduling controller 230 may schedule the physical addresses stored in the index number 0Index0 and the index number 3Index3 of the first read command queue 221 to the index number 0Index0 of the second read command queue 222.

[0180] The command scheduling controller 230 may schedule the read command corresponding to the first physical address group into the index number 0Index0 of the second read command queue 222. The number of read commands stored in the index number 0Index0 of the second read command queue 222 may be one.

[0181] The command scheduling controller 230 may search for the second physical address group among the physical addresses stored in the first read command queue 221. For example, the first physical address group (including physical addresses having the same plane number, the same block number, and the same page number) may include the physical addresses stored in the index number 0 Index0 and the index number 3 Index3 of the first read command queue 221. The second physical address group may include the physical addresses stored in the index number 2 Index2 and the index number 4 Index4 of the first read command queue 221.

[0182] The command scheduling controller 230 may sequentially schedule the first physical address group and the second physical address group to consecutive index numbers of the second read command queue 222. For example, assume that the first physical address group is scheduled to index number 0Index0 of the second read command queue 222, and the second physical address group includes physical addresses stored in index number 2Index2 and index number 4Index4 of the first read command queue 221. The physical address stored in index number 2Index2 of the first read command queue 221 may be scheduled to index number 2Index2 of the second read command queue 222, and the physical address stored in index number 4Index4 of the first read command queue 221 may be scheduled to index number 1Index1 of the second read command queue 222.

[0183] The command scheduling controller 230 may sequentially schedule the read command to the index number 1 Index1 and the index number 2 Index2 of the second read command queue 222. The physical address stored in the index number 1 Index1 of the first read command queue 221 may be scheduled to the index number 3 Index3 of the second read command queue 222. The command scheduling controller 230 may schedule the read command to the index number 3 Index3 of the second read command queue 222.

[0184] Fig.13 This is an example showing Fig.12 A diagram of an embodiment of a read operation performed by an embodiment of .

[0185] Reference Fig.12 and Fig.13 , the read command RCMD1 and the physical address stored in the index number 0Index0 of the second read command queue 222 may be provided to the memory device 100. The memory device 100 may perform a single-plane read operation SPread.

[0186] Next, the read command RCMD2 and the physical address stored in the index number 1 Index1 of the second read command queue 222 may be provided to the memory device 100. The memory device 100 may perform the read operation PGS read.

[0187] A single plane read operation SP read on the zeroth plane 101 with plane number 0P0, a read operation PGS read on the second plane 103 with plane number 2P2, and a read operation PGS read on the third plane 104 with plane number 3P3 may be performed using a plane interleaving scheme.

[0188] The order of outputting data may be the order of performing a read operation PGS read on the second plane 103, performing a read operation PGS read on the third plane 104, and performing a single plane read operation SP read on the zeroth plane 101. This is because the speed of the read operation PGS read may be faster than the speed of the single plane read operation SP read.

[0189] Next, the read command RCMD4 and the physical address stored in the index number 3Index3 of the second read command queue 222 may be provided to the memory device 100. The memory device 100 performs the read operation PGS read and outputs data (DATA OUT).

[0190] There may be a third time t3 to complete the read operation for the read commands RCMD1, RCMD2, and RCMD3 stored in the respective index numbers of the second read command queue 222. The third time t3 may be shorter than the second time t2 described with reference to FIG.

[0191] As described above, the read commands and physical addresses stored in the first read command queue 221 are rearranged in the second read command queue 222 , so that the response time to the read request can be reduced and the read performance can be improved.

[0192] Fig.14 2 is a diagram showing an embodiment of a command storage device 220, which may include a first read command queue 221 and a second read command queue 222. Figure 8 Similarly, the first read command queue 221 can sequentially store the read command RCMD and the physical address Physical Address. However, different from Figure 8 As shown, physical addresses including different page numbers may be stored in the first read command queue 221. The first physical address group may not be searched among the physical addresses stored in the first read command queue 221.

[0193] In an embodiment, physical addresses for which a read operation can be performed using a plane interleaving scheme may be stored in the first read command queue 221. For example, the physical addresses stored in index number 1 Index1 and index number 2 Index2 of the first read command queue 221 are physical addresses for which a read operation can be performed using a plane interleaving scheme. For example, the physical addresses stored in index number 4 Index4 to index number 6 Index6 of the first read command queue 221 are physical addresses for which a read operation can be performed using a plane interleaving scheme. In an embodiment, the second read command queue 222 may correspond to Figure 8 A second read command queue 222 is shown.

[0194] Fig.15 This is an example showing Fig.14 A diagram of an embodiment of a read operation performed by an embodiment of .

[0195] Reference Fig.14 and Fig.15 , the read command RCMD1 and the physical address stored in the index number 0Index0 of the first read command queue 221 may be provided to the memory device 100. The memory device 100 may perform the read operation PGS, and may output the data stored in the page (DATA OUT).

[0196] Next, the read command RCMD2 and the physical address stored in the index number 1Index1 of the first read command queue 221 may be provided to the memory device 100. The memory device 100 may perform the read operation PGS, and may output the data stored in the page (DATA OUT).

[0197] After the read command RCMD2 stored in the index number 1Index1 of the first read command queue 221 is provided to the memory device 100, the read command RCMD3 stored in the index number 2Index2 of the first read command queue 221 and the physical address may be provided to the memory device 100. The memory device 100 may perform a read operation PGS read, and may output data stored in the page (DATA OUT).

[0198] The read operation PGS read indicated by the read command RCMD2 stored in the index number 1 Index1 of the first read command queue 221 and the read operation PGS read indicated by the read command RCMD3 stored in the index number 2 Index2 of the first read command queue 221 may be performed using the first plane interleaving scheme P11.

[0199] Next, the read command RCMD4 and the physical address stored in the index number 3Index3 of the first read command queue 221 may be provided to the memory device 100. The memory device 100 may perform the read operation PGS read, and may output the data stored in the page (DATA OUT).

[0200] Next, the read command RCMD5 and the physical address stored in the index number 4Index4 of the first read command queue 221 may be provided to the memory device 100. The memory device 100 may perform the read operation PGS read, and may output the data stored in the page (DATA OUT).

[0201] After the read command RCMD5 stored in the index number 4Index4 of the first read command queue 221 is provided to the memory device 100, the read command RCMD6 stored in the index number 5Index5 of the first read command queue 221 and the physical address may be provided to the memory device 100. The memory device 100 may perform a read operation PGS read, and may output data stored in the page (DATA OUT).

[0202] After the read command RCMD6 stored in the index number 5Index5 of the first read command queue 221 is provided to the memory device 100, the read command RCMD7 stored in the index number 6Index6 of the first read command queue 221 and the physical address may be provided to the memory device 100. The memory device 100 may perform the read operation PGS read, and may output the data stored in the page (DATAOUT).

[0203] The read operation PGS read indicated by the read command RCMD5 stored in index number 4Index4 of the first read command queue 221, the read operation PGS read indicated by the read command RCMD6 stored in index number 5Index5 of the first read command queue 221, and the read operation PGS read indicated by the read command RCMD7 stored in index number 6Index6 of the first read command queue 221 can be performed by using the second plane interleaving scheme P12.

[0204] The first time t1' may be required to complete the read operation regarding the read command RCMD1 stored in the index number 0 Index0 of the first read command queue 221 to the read command RCMD7 stored in the index number 6 Index6 of the first read command queue 221. When the physical address and the read command stored in the first read command queue 221 are scheduled again to the second read command queue 222 so that the number of planes operated using the plane interleaving scheme becomes the maximum, the time to complete the read operation may be shorter than the first time t1'.

[0205] Fig.16 is a diagram illustrating an embodiment of scheduling a read command and a physical address stored in a first read command queue to a second read command queue.

[0206] Reference Fig.16 When the first physical address group is not searched, the command scheduling controller 230 may search for a plane interleave group including all physical addresses having different plane numbers among the physical addresses stored in the first read command queue 221. For example, the physical addresses stored in index number 0Index0, index number 2Index2, index number 5Index5, and index number 6Index6 of the first read command queue 221 may be included in the plane interleave group.

[0207] The command scheduling controller 230 may sequentially schedule the physical addresses in the plane interleaving group into the consecutive index numbers of the second read command queue 222. Also, the command scheduling controller 230 may sequentially schedule the read commands corresponding to each of the physical addresses in the plane interleaving group into the consecutive index numbers of the second read command queue 222.

[0208] In an embodiment, the command scheduling controller 230 may sequentially schedule the physical addresses in the plane interleaving group to the index numbers of the second read command queue 222 starting from the index number corresponding to the first priority output order. Moreover, the command scheduling controller 230 may sequentially schedule the read commands corresponding to each of the physical addresses in the plane interleaving group to the index numbers of the second read command queue 222 starting from the index number corresponding to the first priority output order. For example, the physical addresses stored in the index number 0Index0, the index number 2Index2, the index number 5Index5, and the index number 6Index6 of the first read command queue 221 may be sequentially scheduled to the index number 0Index0 to the index number 3Index3 of the second read command queue 222. In addition, the read commands RCMD1, RCMD2, RCMD3, and RCMD4 may be sequentially scheduled to the index number 0Index0 to the index number 3Index3 of the second read command queue 222.

[0209] In addition to the plane interleaving group, the command scheduling controller 230 may also use other physical addresses to search for other plane interleaving groups among the physical addresses stored in the first read command queue 221. For example, the physical addresses stored in the index number 1Index1 and the index number 3Index3 of the first read command queue 221 may be in another plane interleaving group. The physical addresses in another plane interleaving group may be sequentially scheduled to the continuous index numbers of the second read command queue 222 to be output after the plane interleaving group. For example, the physical addresses stored in the index number 1Index1 and the index number 3Index3 of the first read command queue 221 may be sequentially scheduled to the index number 4Index4 and the index number 5Index5 of the second read command queue 222. The physical address stored in the index number 4Index4 of the first read command queue 221 may be scheduled to the index number 6Index6 of the second read command queue 222.

[0210] Fig.17 It shows that according to Fig.16 A diagram of an embodiment of a read operation performed by the illustrated embodiment.

[0211] Reference Fig.16 and Fig.17, the memory device 100 may perform a read operation in response to the physical address and the read command stored in the index number of the second read command queue 222. For example, the read operation PGS read indicated by the read command RCMD1 stored in the index number 0Index0 of the second read command queue 222, the read operation PGS read indicated by the read command RCMD2 stored in the index number 1Index1 of the second read command queue 222, the read operation PGS read indicated by the read command RCMD3 stored in the index number 2Index2 of the second read command queue 222, and the read operation PGS read indicated by the read command RCMD4 stored in the index number 3Index3 of the second read command queue 222 may be performed by using the first plane interleaving scheme P11'. The data stored in each plane may be sequentially output (DATAOUT).

[0212] For example, a read operation PGS read indicated by a read command RCMD5 stored in index number 4Index4 of the second read command queue 222 and a read operation PGS read indicated by a read command RCMD6 stored in index number 5Index5 of the second read command queue 222 may be performed by using the second plane interleaving scheme P12'. The data stored in each plane may be sequentially output (DATA OUT).

[0213] The second time t2′ may be required to complete the read operations on the read commands RCMD1, RCMD2, RCMD3, RCMD4, RCMD5, RCMD6, and RCMD7 stored in the respective index numbers of the second read command queue 222. The second time t2′ may be shorter than the reference time t2′. Fig.15 The first time t1' is described.

[0214] As described above, the read command queue is rearranged so that the number of planes operated using the plane interleaving scheme becomes the maximum. Therefore, the response time to the read request can be reduced and the read performance can be improved. Moreover, as described above, since the read command queue is rearranged, the number of all sensing operations used to perform the read operation with respect to the read request of the host 400 can be reduced, thereby preventing the phenomenon that the response to the read request of the host 400 is delayed, and the performance of the read operation can be improved.

[0215] Fig.18 is a diagram illustrating an embodiment of a method of operating a memory controller, which may be the memory controller 200 , for example.

[0216] Reference Fig.18The method includes, at S110, the memory controller 200 scans the read command queue. For example, the memory controller 200 may scan the physical addresses stored in the read command queue, and may compare the plane number, block number, and page number of the physical addresses with each other.

[0217] At S120, the memory controller 200 determines whether at least two physical addresses among the physical addresses stored in the read command queue are combinable. As described above, whether the physical addresses are combinable can be based on: determining whether the plane numbers of the physical addresses are different from each other and whether the page numbers of the physical addresses are the same, or determining whether the physical addresses all have the same plane number, the same block number, and the same page number.

[0218] At S130, when the physical addresses are combinable (S120, yes), the memory controller 200 rearranges the read command queue by combining the physical addresses. As described above, rearranging the read command queue by combining the physical addresses may correspond to scheduling the converted physical addresses to the index numbers of the physical addresses pre-stored in the read command queue, so that a multi-plane read operation MP read or a single-plane read operation SP read may be performed.

[0219] At S140 , when the physical addresses are not combinable ( S120 , No), the memory controller 200 determines whether there is a physical address operated using the plane interleaving scheme among the physical addresses stored in the read command queue.

[0220] At S150, when there are physical addresses operated using the plane interleaving scheme (S140, Yes), the memory controller 200 rearranges the read command queue so that the number of planes operated using the plane interleaving scheme becomes the maximum. This operation may be performed as previously described.

[0221] At S160, the memory controller 200 sequentially outputs the read commands and physical addresses stored in the read command queue according to the scheduling order. When there is no physical address operated using the plane interleaving scheme (S140, No), operation S160 may be performed.

[0222] Fig.19 is a diagram illustrating an embodiment of a memory controller 200 , which may include a processor 201 , a RAM 202 , an error correction code (ECC) circuit 203 , a host interface 204 , a ROM 205 , and a flash memory interface 206 .

[0223] The processor 201 may control the overall operations of the memory controller 200 .

[0224] The RAM 202 may be used as a buffer memory, a cache memory, a working memory, etc. of the memory controller 200. Exemplarily, the RAM 202 may be a buffer memory.

[0225] The ECC circuit 203 may generate ECC for correcting a fail bit or an error bit of data received from the memory device 100. The ECC circuit 203 may generate data to which a parity bit is added by performing ECC encoding on data provided to the memory device 100. The parity bit may be stored in the memory device 100.

[0226] The ECC circuit 203 may perform ECC decoding on data output from the memory device 100. The ECC circuit 203 may correct errors by using parity check. For example, the ECC circuit 203 may correct errors by using various coded modulations such as LDPC codes, BCH codes, turbo codes, Reed-Solomon codes, convolutional codes, RSC, TCM, and BCM.

[0227] The ECC circuit 203 may calculate an ECC value of data to be programmed to the memory device 100 in a programming operation. The ECC circuit 203 may perform an error correction operation on data read from the memory device 100 in a read operation based on the ECC value. The ECC circuit 203 may perform an error correction operation on data recovered from the memory device 100 in a recovery operation of failed data.

[0228] The memory controller 200 may communicate with an external device (eg, the host 400 , an application processor, etc.) through the host interface 204 .

[0229] The ROM 205 may store various information for controlling the operation of the memory controller 200 in the form of firmware or other types of instructions.

[0230] The memory controller 200 may communicate with the memory device 100 through the flash interface 206. The memory controller 200 may transmit commands CMD, addresses ADDR, control signals CTRL, etc. to the memory device 100 and receive data DATA through the flash interface 206. The flash interface 206 may include, for example, a NAND interface.

[0231] Fig. 20 is a block diagram illustrating an embodiment of a memory card system 2000 to which a memory device according to any one of the embodiments described herein may be applied.

[0232] Reference Fig. 20, the memory card system 2000 includes a memory device 2100, a memory controller 2200, and a connector 2300. For example, the memory device 2100 may be implemented using various nonvolatile memory devices such as an electrically erasable programmable ROM (EEPROM), a NAND flash memory, a NOR flash memory, a phase change RAM (PRAM), a resistive RAM (ReRAM), a ferroelectric RAM (FRAM), and a spin transfer torque magnetic RAM (STT-MRAM).

[0233] The memory controller 2200 is configured to access the memory device 2100. The memory controller 2200 may control the read operation, write operation, erase operation, and background operation of the memory device 2100. The memory controller 2200 serves as an interface between the memory device 2100 and the host. The memory controller 2200 drives firmware or other instructions to control the memory device 2100. The memory controller 2200 may be similar to Figure 1 The memory controller 200 is implemented as shown in FIG.

[0234] In addition, the memory controller 2200 may include components such as random access memory (RAM), a processing unit, a host interface, a memory interface, and an error corrector. The memory controller 2200 may communicate with an external device through a connector 2300. The memory controller 2200 may communicate with an external device (e.g., a host 400) according to a specific communication protocol. Examples of communication protocols include universal serial bus (USB), multimedia card (MMC), embedded MMC (eMMC), peripheral component interconnect (PCI), high-speed PCI (PCIe), advanced technology attachment (ATA), serial ATA (SATA), parallel ATA (PATA), small computer system interface (SCSI), enhanced small disk interface (ESDI), electronic integrated drive (IDE), FireWire, universal flash memory (UFS), Wi-Fi, Bluetooth, and NVMe. Exemplarily, the connector 2300 may be defined by at least one of the various communication protocols described above.

[0235] The memory device 2100 and the memory controller 2200 may be integrated into a single semiconductor device to constitute a memory card. Examples of memory cards include PC cards (Personal Computer Memory Card International Association (PCMCIA)), Compact Flash (CF) cards, Smart Media Cards (SM and SMC), Memory Sticks, Multimedia Cards (MMC, RS-MMC, Micro MMC, and eMMC), SD cards (SD, Mini SD, Micro SD, and SDHC), and Universal Flash Storage (UFS).

[0236] Fig.21is a block diagram illustrating an embodiment of a solid state drive (SSD) system 3000 to which a storage device according to the embodiments described herein may be applied.

[0237] Reference Fig.21 , the SSD system 3000 includes a host 4000 and an SSD 3000. In one embodiment, the SSD 3000 may exchange a signal SIG with the host 4000 through a signal connector 3001, and may receive power PWR through a power connector 3002. The SSD 3000 includes an SSD controller 3200, a plurality of flash memories 3100_1, 3100_2, and 3100_n, an auxiliary power supply 3300, and a buffer memory 3400. According to an embodiment, the SSD controller 3200 may perform operations with Figure 1 The memory controller 200 has the same function.

[0238] The SSD controller 3200 may control the plurality of flash memories 3100_1, 3100_2, and 3100_n in response to a signal SIG from the host 400. Exemplarily, the signal SIG may be a signal based on an interface between the host 400 and the SSD 3000. For example, the signal SIG may be a signal defined by at least one of interfaces such as a universal serial bus (USB), a multimedia card (MMC), an embedded MMC (eMMC), a peripheral component interconnect (PCI), PCI Express (PCIe), an advanced technology attachment (ATA), a serial ATA (SATA), a parallel ATA (PATA), a small computer system interface (SCSI), an enhanced small disk interface (ESDI), an integrated drive electronics (IDE), a firewire, a universal flash memory (UFS), WI-FI, Bluetooth, and NVMe.

[0239] The auxiliary power supply 3300 is connected to the host 400 through the power connector 3002. The auxiliary power supply 3300 can receive the power PWR input from the host 400 and be charged with the power PWR. When the power supply from the host 400 is not stable (or does not conform to a predetermined level or pattern), the auxiliary power supply 3300 can provide power to the SSD 3000. For example, the auxiliary power supply 3300 can be located in the SSD 3000, or can be located outside the SSD 3000 and connected to the SSD 3000. In one embodiment, the auxiliary power supply 3300 can be on the mainboard and / or can provide auxiliary power to the SSD 3000.

[0240] The buffer memory 3400 may temporarily store, for example, data from the host 400 and / or data received from the flash memories 3100_1, 3100_2, and 3100_n. In one embodiment, the buffer memory 3400 may temporarily store metadata (e.g., a mapping table) of the flash memories 3100_1, 3100_2, and 3100_n. The buffer memory 3400 may include a volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or a nonvolatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0241] Fig. 22 is a block diagram illustrating an embodiment of a user system 4000 to which a storage device as described herein may be applied.

[0242] Reference Fig. 22 , the user system 4000 includes an application processor 4100, a memory module 4200, a network module 4300, a storage module 4400, and a user interface 4500. The application processor 4100 may drive components, an operating system (OS), user programs, etc. in the user system 4000. For example, the application processor 4100 may include a controller for controlling components, interfaces, a graphic engine, etc. in the user system 4000. The application processor 4100 may be configured as a system on chip (SoC).

[0243] The memory module 4200 may operate as a main memory, a working memory, a buffer memory, or a cache memory of the user system 4000. The memory module 4200 may include a volatile random access memory such as DRAM, SDRAM, DDR SDRAM, DDR2SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, and LPDDR3 SDRAM, or a nonvolatile random access memory such as PRAM, ReRAM, MRAM, and FRAM. For example, the application processor 4100 and the memory module 4200 may be provided as one semiconductor package by packaging based on a stacked package (PoP).

[0244] The network module 4300 can communicate with external devices. For example, the network module 4300 can support wireless communications such as: code division multiple access (CDMA), global system for mobile communications (GSM), wideband CDMA (WCDMA), CDMA-2000, time division multiple access (TDMA), long term evolution (LTE), Wimax, WLAN, UWB, Bluetooth, and Wi-Fi. The network module 4300 can be located in the application processor 4100 or connected to the application processor 4100.

[0245] For example, the storage module 4400 may store data received from the application processor 4100 and / or may transmit the data stored therein to the application processor 4100. For example, the storage module 4400 may be implemented using a non-volatile semiconductor memory device such as a phase change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a NAND flash memory, a NOR flash memory, or a NAND flash memory having a three-dimensional structure. For example, the storage module 4400 may be provided as a removable drive such as a memory card or an external drive of the user system 4000.

[0246] For example, the storage module 4400 may be similar to Figure 1 The storage module 4400 may include a plurality of non-volatile memory devices, which may be operated in a manner similar to the reference Figure 1 The described memory device 100 operates in a similar manner.

[0247] The user interface 4500 may include one or more interfaces for inputting data or commands to the application processor 4100 or outputting data to an external device. The user interface 4500 may include one or more user input interfaces (e.g., a keyboard, a keypad, a button, a touch pad, a touch screen, a touch pad, a touch ball, a camera, a microphone, a gyro sensor, a vibration sensor, and a piezoelectric element) and / or one or more output interfaces (e.g., a liquid crystal display (LCD), an organic light emitting diode (OLED) display device, an active matrix OLED (AMOLED) display device, an LED, a speaker, and a monitor).

[0248] According to one or more of the aforementioned embodiments, a memory controller capable of improving the performance of a read operation is provided. According to one or more additional embodiments, a storage device including such a memory controller and a method of controlling a memory controller are provided, which method can achieve improved performance, for example.

[0249] Method described herein, process and / or operation can be performed by code or instruction to be run by computer, processor, controller or other signal processing device.Computer, processor, controller or other signal processing device can be those described herein or computer, processor, controller or other signal processing device except element described herein.Due to the algorithm formed based on method (or the operation of computer, processor, controller or other signal processing device) described in detail, therefore the code or instruction for implementing the operation of method embodiment can convert computer, processor, controller or other signal processing device into a special processor for performing the method herein.

[0250] When implemented at least in part with software, controllers, processors, devices, modules, units, multiplexers, generators, logic, interfaces, decoders, drivers and other signal generation and signal processing features may include, for example, a memory or other storage device for storing the code or instructions to be run by, for example, a computer, processor, microprocessor, controller or other signal processing device. The computer, processor, microprocessor, controller or other signal processing device may be those described herein or a computer, processor, microprocessor, controller or other signal processing device in addition to the elements described herein. Due to the algorithm forming the basis of the method (or the operation of a computer, processor, microprocessor, controller or other signal processing device) described in detail, the code or instructions for implementing the operation of the method embodiment can convert the computer, processor, controller or other signal processing device into a special processor for performing the method herein.

[0251] Although the present disclosure has been shown and described with reference to certain exemplary embodiments of the present disclosure, it will be understood by those skilled in the art that various changes may be made in form and details without departing from the spirit and scope of the present disclosure as defined by the appended claims and their equivalents. Therefore, the scope of the present disclosure should not be limited to the above exemplary embodiments, but should be determined not only by the appended claims, but also by their equivalents.

[0252] In the above-described embodiments, all steps may be performed, or a part of the steps may be selectively omitted. In each embodiment, the steps are not necessarily performed in the order described, and may be rearranged. The embodiments disclosed in this specification and the accompanying drawings are merely examples to simplify the understanding of the present disclosure, and the present disclosure is not limited thereto. That is, it is obvious to those skilled in the art that various modifications may be made based on the technical scope of the present disclosure.

[0253] Meanwhile, exemplary embodiments of the present disclosure have been described in the drawings and the specification. Although specific terms are used herein, those terms are only used to explain the embodiments of the present disclosure. Therefore, the present disclosure is not limited to the above-described embodiments, and many modifications can be made within the spirit and scope of the present disclosure. It should be clear to those skilled in the art that, in addition to the embodiments disclosed herein, various modifications can also be made on the basis of the technical scope of the present disclosure. The embodiments can be combined to form additional embodiments.

Claims

1. A memory controller, comprising: a command storage device, comprising a first read command queue and a second read command queue, wherein the first read command queue stores a read command and a physical address according to an index number, the read command indicating to read data stored in a memory device, and the physical address corresponds to the read command and includes a plane number, a block number, and a page number; a command generation controller that provides an erase command to perform an erase operation, the erase operation including erasing data stored in one of a plurality of memory blocks of the memory device, provides a suspend command to suspend the erase operation in response to a request, provides a resume command to resume the erase operation after the operation corresponding to the request is completed, and outputs a scheduling event signal after outputting the resume command; as well as The command scheduling controller, in response to the scheduling event signal: searching for a first physical address group and a second physical address group among the physical addresses stored in the first read command queue, the first physical address group including physical addresses having the same page number among the physical addresses stored in the first read command queue, the second physical address group including all physical addresses having a plane number different from the plane number of the first physical address group, The output order of the first read command queue is rearranged by storing the physical addresses corresponding to the same page number in the first physical address group together at the same index number of the second read command queue, and storing the physical addresses in the second physical address group at the index numbers of the second read command queue respectively, and The read command is provided based on the second read command queue to perform a read operation. 2 . The memory controller of claim 1 , wherein the first physical address group includes physical addresses having the same plane number, the same block number, and the same page number. 3 . The memory controller according to claim 2 , wherein the command scheduling controller schedules the first physical address group and the read command corresponding to the first physical address group to any one of the index numbers of the second read command queue. 4 . The memory controller of claim 1 , wherein the first physical address group includes physical addresses having different plane numbers and the same page number. 5 . The memory controller according to claim 4 , wherein the command scheduling controller schedules the first physical address group and the read command corresponding to the first physical address to any one of the index numbers of the second read command queue.

6. The memory controller according to claim 1, wherein when the first physical address group is not found, the command scheduling controller: searching among the physical addresses stored in the first read command queue for a plane interleave group including all physical addresses having different plane numbers; sequentially dispatching the physical addresses in the plane interleave group to consecutive index numbers of the second read command queue; and Read commands corresponding to each physical address in the plane interleave group are sequentially scheduled into the consecutive index numbers.

7. The memory controller according to claim 6, wherein the command scheduling controller: sequentially dispatching the physical addresses in the plane interleave group to the second read command queue in index numbers starting from the index number corresponding to the first priority output order; and The read commands corresponding to each physical address in the plane interleave group are sequentially scheduled to the second read command queue in index numbers starting from the index number corresponding to the first priority output order.

8. A memory controller comprising: a command storage device, comprising a first read command queue and a second read command queue, wherein the first read command queue stores a read command and a physical address according to an index number, the read command indicating to read data stored in a memory device, and the physical address corresponds to the read command and includes a plane number, a block number, and a page number; a command generation controller that provides a command to the memory device to perform an erase operation including erasing data stored in one of a plurality of memory blocks of the memory device or to perform a write operation including storing data in one of the plurality of memory blocks, and outputs a scheduling event signal after a predetermined period of time has passed from the time when the command is provided to the memory device; as well as The command scheduling controller, in response to the scheduling event signal: searching for a first physical address group and a second physical address group among the physical addresses stored in the first read command queue, the first physical address group including physical addresses having the same page number among the physical addresses stored in the first read command queue, the second physical address group including all physical addresses having a plane number different from the plane number of the first physical address group, The output order of the first read command queue is rearranged by storing the physical addresses corresponding to the same page number in the first physical address group together at the same index number of the second read command queue, and storing the physical addresses in the second physical address group at the index numbers of the second read command queue respectively, and The read command is provided based on the second read command queue to perform a read operation. 9 . The memory controller of claim 8 , wherein the first physical address group includes physical addresses having the same plane number, the same block number, and the same page number. 10 . The memory controller according to claim 9 , wherein the command scheduling controller schedules the first physical address group and the read command corresponding to the first physical address group to any one of the index numbers of the second read command queue. 11 . The memory controller of claim 8 , wherein the first physical address group includes physical addresses having different plane numbers and the same page number. 12 . The memory controller according to claim 11 , wherein the command scheduling controller schedules the first physical address group and the read command corresponding to the first physical address to any one of the index numbers of the second read command queue.

13. The memory controller according to claim 8, wherein when the first physical address group is not found, the command scheduling controller: searching among the physical addresses stored in the first read command queue for a plane interleave group including all physical addresses having different plane numbers; sequentially dispatching the physical addresses in the plane interleave group to consecutive index numbers of the second read command queue; and Read commands corresponding to each physical address in the plane interleave group are sequentially scheduled into the consecutive index numbers.

14. The memory controller according to claim 13, wherein the command scheduling controller: sequentially dispatching the physical addresses in the plane interleave group to the second read command queue in index numbers starting from the index number corresponding to the first priority output order; and The read commands corresponding to each physical address in the plane interleave group are sequentially scheduled to the second read command queue in index numbers starting from the index number corresponding to the first priority output order.

15. A storage device, comprising: A memory device comprising a plurality of planes; as well as The memory controller, in response to a read request: storing a read command and a physical address in a first read command queue according to an index number, the read command indicating execution of a read operation including reading data stored in the memory device, When a scheduling event occurs, the read command and the physical address stored in the first read command queue are scheduled to the second read command queue, and providing the read command and the physical address stored in the second read command queue to the memory device according to a scheduling order, wherein the physical address includes a plane number, a block number, and a page number, and wherein the memory controller: searching for a first physical address group and a second physical address group among the physical addresses stored in the first read command queue, the first physical address group including physical addresses having the same page number among the physical addresses stored in the first read command queue, and the second physical address group including all physical addresses having a plane number different from that of the first physical address group; Rearranging the output order of the first read command queue by storing the physical addresses of the first physical address group corresponding to the same page number together at the same index number of the second read command queue, and storing the physical addresses of the second physical address group at the index numbers of the second read command queue respectively; and The read command is provided based on the second read command queue to perform a read operation.

16. The storage device according to claim 15, wherein: The first physical address group includes physical addresses having the same plane number, the same block number, and the same page number, and The memory controller schedules the first physical address group and a read command corresponding to the first physical address group to one of the index numbers of the second read command queue.

17. The memory device according to claim 16, wherein in response to the first physical address group and a read command corresponding to the first physical address group, the memory device: performing a read operation on a page of a single plane having a physical address in the first physical address group, and Data stored in the pages of the single plane are provided to the memory controller.

18. The storage device according to claim 15, wherein: The first physical address group includes physical addresses having different plane numbers and the same page number, and The memory controller schedules the first physical address group and a read command corresponding to the first physical address group to one of the index numbers of the second read command queue.

19. The memory device according to claim 18, wherein in response to the first physical address group and a read command corresponding to the first physical address group, the memory device: performing read operations on pages of respective planes having physical addresses in the first physical address group simultaneously; and The data stored in the pages of the respective planes are provided to the memory controller.

20. The storage device of claim 15, wherein the memory device: In response to the first physical address group and at least one read command corresponding to the first physical address group, performing a first read operation on pages of at least one plane having physical addresses in the first physical address group; and In response to the second physical address group and at least one read command corresponding to the second physical address group, a second read operation is performed on pages of at least one plane having physical addresses in the second physical address group, wherein the first read operation and the second read operation partially overlap each other.

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