Processing systems, related integrated circuits and methods

Abstract

A processing system, a related integrated circuit and a method. The processing system includes a first subcircuit configured to be powered by a first power supply voltage and a second subcircuit configured to be powered by a second power supply voltage. The first subcircuit includes a general input / output register. The second subcircuit includes: a storage circuit configured to selectively store configuration data from the general input / output register; an input / output interface; at least one peripheral device; and a selection circuit for exchanging signals of the peripheral device and the stored configuration data with the input / output interface. The power management circuit is configured to manage a normal operating mode and a low power mode, and keeps the configuration data stored and turns off the first subcircuit during the low power mode. The power management circuit activates the low power mode in response to receiving a command, and resumes the normal operating mode in response to a wake-up event.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Italian Patent Application No. 102020000031235 filed on December 17, 2020, which is incorporated herein by reference. Technical Field

[0003] The present disclosure relates generally to electronic systems and methods and, in particular embodiments, to a processing system, related integrated circuits, and methods. Background Art

[0004] Digital processing systems, such as systems on a chip (SoC), comprising at least one digital processing unit are known in the art.

[0005] Figure 1 A block diagram of an exemplary digital processing system 10 (eg, SoC) is shown, namely, Figure 1 The processing system 10 may be integrated in an integrated circuit, such as a microcontroller or a digital signal processor (DSP). In the example considered, the processing system 10 comprises at least one programmable digital processing unit 102, such as a microprocessor, typically a central processing unit (CPU), programmed via software instructions.

[0006] A large number of microprocessor / CPU architectures are known. For example, as disclosed in U.S. Pat. No. US6,889,317B2, and incorporated herein by reference for this purpose, a microprocessor / CPU 102 typically includes:

[0007] - one or more arithmetic logic units (ALUs) configured to implement a plurality of arithmetic logic operations;

[0008] - Multiple registers;

[0009] - Routing circuitry, for example in the form of multiplexers and demultiplexers, configured to connect the ALU to the registers; and

[0010] - an instruction decoder configured to drive the routing circuit and the one or more ALUs according to the current software instruction, for example, to connect at least one register to the input of the ALU and to connect a register to the output of the ALU, to select an arithmetic operation to be performed by the one or more ALUs, to exchange data with a memory, etc.

[0011] Typically, the software executed by the processing unit / CPU 102 is stored in a program memory 104, such as a non-volatile memory, such as flash memory or EEPROM. Typically, the memory 104 can be integrated with the processing unit 102 in a single integrated circuit, or the memory 104 can be in the form of a separate integrated circuit and connected to the processing unit 102, such as via traces of a printed circuit board. Thus, typically, the memory 104 is configured to store the firmware / software of the processing unit 102.

[0012] Typically, the processing unit / CPU 102 is also associated with a volatile memory 100, such as a random access memory (RAM), for storing temporary results of calculations. In addition, the memory 100 can be integrated with the processing unit 102 in a single integrated circuit, or the memory 100 can be in the form of a separate integrated circuit and connected to the processing unit 102.

[0013] In the example considered, the processing unit / CPU 102 may be associated with one or more resources 106 selected from the following group:

[0014] - One or more general purpose input / output GPIOs;

[0015] one or more communication interfaces IF, e.g. for exchanging data via the communication system 20, e.g. via a Universal Asynchronous Receiver / Transmitter (UART), a Serial Peripheral Interface Bus (SPI), an Inter-Integrated Circuit (I2C), a Controller Area Network (CAN) bus and / or an Ethernet interface and / or a debug interface; and / or

[0016] - one or more analog-to-digital converters AD and / or digital-to-analog converters DA; and / or

[0017] - one or more dedicated digital components DC, such as hardware timers and / or counters, or cryptographic co-processors; and / or

[0018] - one or more analog components AC, such as comparators, sensors, such as temperature sensors, etc.; and / or

[0019] - One or more mixed signal components MSC, such as PWM (Pulse Width Modulation) drivers.

[0020] Thus, the digital processing system 10 may support different functionalities. For example, the behavior of the processing unit 102 is determined by firmware stored in the memory 104a, e.g., software instructions executed by the microprocessor / CPU 102 (such as a microcontroller or DSP) of the SoC 10. Thus, by installing different firmware, the same hardware (SoC) may be used for different applications.

[0021] In many applications, the processing system 10 may support a low power mode to reduce the power consumption of the processing system 10. This is particularly important in the case of a battery powered system or for implementing a standby mode of an electronic system including the processing system 10, for example.

[0022] For example, Figure 2 A second example of a processing system 10 is shown, of which only relevant portions are shown for simplicity. Specifically, Figure 2 It is shown that a typical processing system 10 may also include:

[0023] - an oscillator and reset circuit 114 configured to provide a clock signal CLK and a reset signal RST; and

[0024] A power supply circuit 112 , such as an electronic converter or a linear regulator, is configured to generate a supply voltage VDD of the processing system 10 from an input voltage VIN.

[0025] In general, these circuits 114 and / or 112 may be integrated in an integrated circuit / SoC including the processing unit 102, or may be (at least partially) external to the integrated circuit / SoC of the processing unit 102. For example, the control circuitry of the power circuit 112 may be integrated in the integrated circuit / SoC, while larger inductors and / or capacitors of the power circuit 112 may be externally connected to the integrated circuit.

[0026] For example, typically, the oscillator and reset circuit 114 is configured to generate a clock signal CLK of the processing system 10 once the power supply voltage VDD is provided, and then generate a reset via the reset signal RST so as to put the processing system into a reset state. For example, for this purpose, various registers of the processing system 10 are usually reset, such as the registers of the processing unit 102 and the resource 106.

[0027] In the example considered, the processing system 10 also includes a power management circuit 116. Specifically, the power management circuit 116 is configured to selectively activate a normal operating mode or a low power mode. Figure 2 As schematically shown in FIG. 1 , the power management circuit 116 may be configured to drive the oscillator and reset circuit 114 so as to reduce the frequency of the clock signal CLK or even switch off the generation of the clock signal CLK at least in the clock signal provided to the processing unit 102. Thus, in the low power mode, the processing unit 102 may operate at a reduced clock frequency, or may be paused. Conversely, when resuming the normal operating mode, the power management circuit 116 may be configured to drive the oscillator and reset circuit 114 so as to use the normal (higher) frequency of the clock signal CLK again.

[0028] Turning off the clock signal CLK may result in the processing unit 102 being unable to perform any operation. To this end, the power management circuit 116 may be configured to resume normal operating mode (with normal clock frequency) in response to one or more events. For example, these events typically correspond to one or more wake-up signals IRQ provided by one or more resources 106, such as a change in the logic level of an input pin or an interrupt generated by another resource P such as a timer, a comparator, etc. For example, although not in Figure 2 , but for this purpose, one or more resources 106 including sequential logic circuits may still receive the clock signal CLK or another (usually low-frequency) clock signal, or may asynchronously generate the wake-up signal IRQ.

[0029] Thus, typically, the power management circuit 116 is programmable / configurable via the processing unit 102, e.g., by executing one or more software instructions for programming one of a plurality of registers of the power management circuit 116. For example, for this purpose, the power management circuit 116 may be connected to the processing unit 102 similarly to the resources 106, e.g., via the bus system 108. For example, the power management circuit 116 is typically programmable in order to select a power saving mode and / or select a wake-up source, which should restore a normal operating mode.

[0030] To further reduce power, the power management circuit 116 may also be configured to deactivate the power supply to the processing system 10. However, this may cause the registers of the processing system to lose their contents.

[0031] Therefore, in order to avoid such information loss, the processing system 10 may use a so-called retention flip-flop for the registers, which must remain configured. Retention flip-flops are well known in the art and are disclosed, for example, in U.S. Patent Application No. US2018 / 0159513 A1, the contents of which are incorporated herein by reference for this purpose. For example, typically, the retention flip-flop is implemented with a master latch powered by a first power supply voltage and a slave latch powered by a second power supply voltage, and the control section is configured as follows:

[0032] - Before activating the low power mode, the information of the master latch is also stored in the slave latch;

[0033] - When exiting the low power mode, restoring the information from the slave latch.

[0034] Therefore, in the low power mode, the power supply voltage of the master latch and the control section may be deactivated while the slave latch still stores the original data. Summary of the invention

[0035] The inventors have observed that retention flip-flops have several disadvantages.

[0036] On the one hand, the retention flip-flop is complex and large due to the dual latch structure. Therefore, using such a retention flip-flop (in the processing unit / CPU 102 and the resource 106) may not be suitable for all applications.

[0037] On the other hand, the retention flip-flop continues to consume energy even in the low power mode. Therefore, using a retention flip-flop for the processing unit / CPU 102 may still result in excessive power consumption.

[0038] In addition, the retention flip-flop only allows information to be recovered from the latch at the end of the low power mode. Therefore, the data stored to the retention flip-flop cannot be used in the low power mode. For example, this problem may be particularly relevant in the context of CPUs and general input / outputs, where each pad of the die of an integrated circuit (including the processing system 10) may have several configuration bits associated with it. However, as previously mentioned, such a general input / output may directly be the source of a wake-up signal for resuming a normal working mode, or another resource 106 for generating a wake-up signal may still be able to send and / or receive data via the pads of the integrated circuit, such as a communication interface. In this regard, a modern system-on-chip may also include a large number of GPIO pads.

[0039] Some embodiments relate to management of general purpose input / output within a processing system such as a system on a chip (SoC).

[0040] Some embodiments provide solutions for managing general purpose input / output pads of an integrated circuit, particularly for implementing low power operating modes.

[0041] Some embodiments provide a solution for managing general purpose input / output pads of an integrated circuit by using a processing system having the features specifically set out in the appended claims. Some embodiments also relate to related integrated circuits and methods.

[0042] The claims are an integral part of the technical teaching of the present disclosure provided herein.

[0043] Various embodiments relate to a processing system, such as an integrated circuit, such as a system on a chip, comprising at least one pad.

[0044] Specifically, in various embodiments, the processing system includes a first subcircuit, a second subcircuit, and a power supply circuit. The power supply circuit is configured to receive an input voltage and generate a first power supply voltage for the first subcircuit and a second power supply voltage for the second subcircuit. In addition, the power supply circuit is configured to selectively turn off the first power supply voltage according to a first control signal, thereby turning off the first subcircuit.

[0045] In various embodiments, the first subcircuit comprises a digital processing unit, such as a microprocessor, preferably a CPU, configured to be programmed by software instructions, and a general purpose input / output register configured to be programmed by software instructions executed by the digital processing unit. Specifically, in various embodiments, the general purpose input / output register is configured to be connected to at least one pad. For this purpose, the general purpose input / output register can receive (at least) a first data input signal and provide configuration data including a first output enable signal, a first data output signal and a peripheral device selection signal, that is, the general purpose input / output register is configured to receive configuration data from the digital processing unit and provide the value of the first data input signal to the digital processing unit.

[0046] In various embodiments, the second subcircuit includes an input / output interface for the pad. Specifically, in various embodiments, the input / output interface includes an output driver, the output driver is configured to be enabled via an output enable signal, and when enabled, a voltage (typically a second power supply voltage or ground) is applied to the pad according to the logic level of the binary data output signal. In addition, the input / output interface includes an input buffer, the input buffer is configured to generate a binary data input signal according to the voltage at the pad.

[0047] In various embodiments, the configuration data stored in the general input / output register is not directly provided to the input / output interface. Specifically, in various embodiments, the second sub-circuit includes a storage circuit, which includes a plurality of latches, such as D-type latches, for providing the stored configuration data, the configuration data including the stored first output enable signal, the stored first data output signal, and the stored peripheral device selection signal. Specifically, the plurality of latches are configured to provide or maintain the configuration data applied to the corresponding input terminals of the plurality of latches according to the second control signal. Specifically, the latches are configured to:

[0048] - when the second control signal has a first logic level (e.g. high), the configuration data applied to the input terminal of the latch is provided at the output terminal of the latch, i.e. the latch is substantially transparent, and

[0049] - When the second control signal has a second logic level (eg, low), the latch holds the value of the configuration data at the output terminal of the latch.

[0050] In various embodiments, the storage circuit may further include a corresponding isolation unit for each of the plurality of latches. Specifically, the isolation units are configured to selectively connect the general input / output register to the input terminals of the plurality of latches according to a third control signal, thereby selectively providing configuration data to the inputs of the plurality of latches.

[0051] In various embodiments, the second subcircuit may further include at least one peripheral device, such as a communication interface, such as a CAN or SPI interface, configured to receive a second data input signal and provide a second output enable signal and a second data output signal. In this case, the second subcircuit may include a first selection circuit, the first selection circuit being configured to determine a logic level of a data output signal of the input / output interface based on the stored first data output signal, the second data output signal, and the stored peripheral device selection signal. For example, the first selection circuit may be configured to select the stored first data output signal or the second data output signal as the data output signal based on the stored peripheral device selection signal.

[0052] Similarly, the second selection circuit may be configured to determine the logic level of the output enable signal of the input / output interface according to the stored first output enable signal, the second output enable signal and the stored peripheral device selection signal. For example, the second selection circuit may be configured to select the stored first output enable signal or the second output enable signal as the output enable signal according to the stored peripheral device selection signal.

[0053] Similarly, the third selection circuit may be configured to provide the data input signal of the input / output interface as the first data input signal or the second data input signal according to the stored peripheral device selection signal.

[0054] In various embodiments, the second sub-circuit further includes a power management circuit configured to manage a normal operating mode and a low power mode. Specifically, in various embodiments, the power management circuit is configured to receive one or more commands for activating the low power mode from the digital processing unit. Specifically, in response to receiving one or more commands for activating the low power mode, the power management circuit may set a second control signal to indicate that the plurality of latches should hold configuration data, set a third control signal to disconnect the general purpose input / output register from the inputs of the plurality of latches, and set a first control signal to shut down the first power supply voltage.

[0055] Conversely, to resume the normal operating mode, the power management circuit may monitor one or more wake-up signals to determine a wake-up event. For example, for this purpose, the power management circuit may be configured to receive a plurality of wake-up signals, select a subset of the wake-up signals according to given configuration data, and monitor the selected subset of wake-up signals to determine a wake-up event. Specifically, in various embodiments, in response to determining a wake-up event, the power management circuit sets a first control signal to turn on the first power supply voltage, thereby activating the normal operating mode, and sets a third control signal to connect the general input / output register to the input of the plurality of latches.

[0056] Thus, in various embodiments, the power management circuitry does not directly set the second control signal in response to the wake-up event. In fact, in various embodiments, the power management circuitry is configured to receive a separate command from the digital processing unit to reactivate the plurality of latches. Thus, in response to receiving the command to reactivate the plurality of latches, the power management circuitry may set the second control signal to indicate that the plurality of latches should provide configuration data applied to the input terminals of the latches.

[0057] For example, to manage the above operations, the power management circuit may include another register configured to be programmed via a digital processing unit, wherein the other register includes first configuration data and second configuration data. Specifically, in various embodiments, the second control signal may be determined based on the first configuration data, and the first control signal and the third control signal may be determined based on the second configuration data. For example, in this case, one or more commands for activating the low power mode may include a first command for programming the first configuration data, thereby setting the second control signal to indicate that the plurality of latches should maintain the configuration data. The one or more commands may also include a second command for programming the second configuration data, thereby setting the third control signal to disconnect the general input / output register from the input of the plurality of latches, and setting the first control signal to turn off the first power supply voltage. Conversely, the command for reactivating the plurality of latches may include a third command for programming the first configuration data, thereby setting the second control signal to indicate that the plurality of latches should provide configuration data applied to the input terminals of the latches.

[0058] In fact, as previously mentioned, the digital processing unit and the general input / output registers are in the first subcircuit and are therefore turned off in the low power mode. Therefore, these circuits may lose their configuration during the low power mode. For example, in various embodiments, the processing system further includes an oscillator and a reset circuit, which are configured to generate a reset of the first subcircuit when the first power supply voltage is turned on. For example, in various embodiments, the digital processing unit can be a microprocessor, preferably a CPU, including a plurality of registers. In this case, a plurality of registers of the microprocessor and the general input / output registers can be reset in response to the reset signal.

[0059] Thus, directly setting the second control signal in response to a wake-up event may mean that the latches acquire unprogrammed / reset values ​​in the general purpose input / output registers. Thus, in case the configuration of the pads has to be changed, the software instructions executed by the digital processing unit include not only one or more commands for activating the low power mode, but also, after system startup, instructions for programming the general purpose input / output registers and, only thereafter, commands for reactivating the plurality of latches.

[0060] Thus, in various embodiments, a processing system according to the present disclosure may operate in the following manner.

[0061] First, an input voltage is supplied to the power supply circuit, whereby the power supply circuit generates a first power supply voltage for the first sub-circuit and a second power supply voltage for the second sub-circuit.

[0062] Next, the digital processing unit programs the first configuration data into the general purpose input / output register, and (for example, after executing a given task) sends one or more commands for activating the low power mode to the power management circuit. Accordingly, the power management circuit sets the second control signal to indicate that the plurality of latches should hold the configuration data, sets the third control signal to disconnect the general purpose input / output register from the inputs of the plurality of latches, and sets the first control signal to shut down the first power supply voltage.

[0063] Next, the power management circuit monitors the one or more wake-up signals to determine a wake-up event. In response to determining the wake-up event, the power management circuit sets a first control signal to turn on the first power supply voltage to activate the normal operation mode, and sets a third control signal to connect the general input / output register to the inputs of the plurality of latches.

[0064] Therefore, the power supply circuit again provides the first supply voltage to the first sub-circuit, and the processing unit and the general input / output register are turned on. Therefore, in response to activating the normal operating mode, the digital processing unit may program the second (same or different) configuration data to the general input / output register, and only then send a command for reactivating the plurality of latches to the power management circuit, whereby the power management circuit sets the second control signal to indicate that the plurality of latches should again provide the configuration data applied to the input terminals of the latches.

[0065] In the case where the contents of the microprocessor's registers must be maintained, the second subcircuit may include volatile memory and the microprocessor / CPU may be configured to perform:

[0066] - before sending one or more commands for activating the low power mode, executing instructions for storing the contents of a register of the microprocessor to a given location in the volatile memory, and

[0067] - After a reset of the microprocessor, an instruction is executed for reading the content of a given location in the volatile memory and storing this content in a register of the microprocessor. BRIEF DESCRIPTION OF THE DRAWINGS

[0068] Embodiments of the present disclosure will now be described with reference to the accompanying drawings, which are provided purely by way of non-limiting examples, and in which:

[0069] - Figure 1 An example of a processing system is shown;

[0070] - Figure 2 An example of a processing system including a power management circuit is shown;

[0071] - Figure 3 An embodiment of a processing system according to the present disclosure is shown;

[0072] - Figure 4 Shows Figure 3 Embodiments of a storage circuit of a processing system;

[0073] Figure 5 , Figure 6 and Figure 7 Shows Figure 3 Embodiments of a selector circuit for a processing system; and

[0074] Figure 8 and Fig. 9 Shows Figure 3 Embodiments of a power management circuit for a processing system. DETAILED DESCRIPTION

[0075] In the following description, numerous specific details are given to provide a thorough understanding of the embodiments. The embodiments may be practiced without one or several of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the embodiments.

[0076] Reference in this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout the specification are not necessarily all referring to the same embodiment. Furthermore, in one or more embodiments, the particular features, structures, or characteristics may be combined in any suitable manner.

[0077] The headings provided herein are for convenience only and do not interpret the scope or meaning of the embodiments.

[0078] In the following Figures 3 to 9 In, reference has been made Figure 1 and Figure 2 Described parts, elements or components are denoted by the same reference characters used previously in these figures; in order not to burden this detailed description, the description of these previously described elements will not be repeated below.

[0079] As mentioned above about Figure 1 and Figure 2As mentioned above, in many applications, the digital processing system 10 should be able to activate the normal mode and the low power mode. Preferably, the unused components of the digital processing system 10 should be able to be turned off in the low power mode, while the general purpose input / output GPIO should keep their configuration.

[0080] Figure 3 An embodiment of a processing system 10a according to the present disclosure is shown.

[0081] Specifically, in the embodiment under consideration, the processing system 10a comprises:

[0082] - a power supply circuit 112a, configured to generate a first power supply voltage VDD1 and a second power supply voltage VDD2;

[0083] - a reset and oscillator circuit 114 configured to generate at least one clock signal CLK and a reset signal RST;

[0084] - a first sub-circuit 30 powered by a first power supply voltage VDD1, wherein the first sub-circuit 30 comprises a processing unit 102 of a processing system, such as a microprocessor or CPU, and a general purpose input / output controller GPIO; and

[0085] - A second sub-circuit 32 powered by a second power supply voltage VDD2, wherein the second sub-circuit 30 comprises a plurality of n general purpose input / output pads PAD1, PADn of the integrated circuit.

[0086] Typically, these pads PAD1 , PADn of the die of the integrated circuit / SoC may be connected to respective pins of a package of the integrated circuit, or may be connected (eg, by wire bonding) to a PCB.

[0087] like Figure 3 As shown, each pad PAD1…PADn (in Figure 3 1 and 2, each of the general pads PADx) has an associated configurable input / output (I / O) circuit 130. Specifically, the input / output circuit 130 includes:

[0088] - an output driver 1300 configured to set a logic level of the pad PADx according to the binary data signal DOUT and the output enable signal OEN; and

[0089] An input buffer 1302 configured to set the logic level of the binary data signal DIN according to the voltage at the pad PADx.

[0090] For example, the output driver 1300 may be configured as:

[0091] - when the signal DOUT is set to a low level and the signal OEN has a first logic level (usually high), the pad PADx is connected to ground, i.e., a reference voltage of the power supply voltages VDD1 and VDD2;

[0092] - connecting the pad PADx to the power supply voltage VDD2 when the signal DOUT is set high and the signal OEN has a first logic level; and

[0093] - When the signal OEN has a second logic level (typically a low level), the output of the output driver 1300 is disabled.

[0094] Thus, in the embodiment considered, the output driver 1300 is configured as a three-state output driver (0 logic level and 1 logic level, and a high impedance state).

[0095] In contrast, the input buffer 1302, such as a Schmitt trigger, may be configured as:

[0096] - when the voltage at the pad PADx is greater than the upper threshold, the signal DIN is set high; and

[0097] - When the voltage at pad PADx is less than the low threshold, signal DIN is set low.

[0098] In various embodiments, the logic levels of the signals DOUT and OEN are determined according to a plurality of bits, which are programmable via the processing unit 102. For example, in the embodiment under consideration, the processing unit comprises a register interface GPIO, wherein the processing unit 102 is configured to read and / or write one or more bits of a register of the interface GPIO. For example, in various embodiments, the register GPIO is addressable in a memory space of the processing unit 102, for example in a so-called special function register (SFR) of the microprocessor / CPU 102. For example, as Figure 3 As schematically shown in FIG. 1 , the register interface GPIO may be connected to the processing unit 102 via a bus system 108 .

[0099] For example, each pad PADx may have associated:

[0100] - a bit ODR for setting the logic level of the signal DOUT; and

[0101] - One or more bits GPIOCONFIG to set the signal OEN.

[0102] Therefore, by programming the bits ODR and GPIOCONFIG of the interface GPIO, the processing unit 102 can set the logic level of the pad PADx. Similarly, the signal DIN can be stored in the bit IDR of the interface GPIO. Therefore, by reading the bit IDR, the processing unit 102 can determine / read the logic level of the pad PADx.

[0103] Specifically, as will be described in more detail below, in various embodiments, the processing system 10a includes a storage circuit 118, which is configured to store values ​​of configuration signals provided by the interface GPIO, such as GPIOCONF and ODR, and provide corresponding stored values, such as GPIOCONF' and ODR', to the I / O interface 130.

[0104] like Figure 3 As shown, signals DOUT and OEN may indeed be provided by selector circuits 124 and 126, respectively. Similarly, signal DIN may be provided to multiple circuits via selector circuit 128.

[0105] For example, circuits 124, 126, and 128 are useful where processing system 10 also includes one or more resources 106 configured to exchange data directly with input / output circuits 130. Figure 3 Two generic resources 120 and 122, such as communication interfaces, are shown.

[0106] For example, the circuit 120 is configured to:

[0107] - generating an output signal P1_OUT and an output enable signal P1_OEN; and / or

[0108] -Receive input signal P1_IN.

[0109] Similarly, circuit 122 is configured as:

[0110] - generating an output signal P2_OUT and an output enable signal P2_OEN; and / or

[0111] -Receive input signal P2_IN.

[0112] In general, the wording "and / or" emphasizes that the circuits 120 and 122 may also only receive data or only send data. For example, in this case, the corresponding output enable signals may also be hardwired.

[0113] Thus, in this case, selector circuit 124 may be configured to generate signal DOUT by selecting signal ODR′ (provided by storage circuit 118) or one of the output signals provided by resources 120 and 122. Similarly, selector circuit 126 may be configured to generate signal OEN based on one or more of configuration bits GPIOCONF′ (provided by storage circuit 118) or one of the output enable signals provided by resources 120 and 122. Finally, circuit 128 may be configured to provide signal DIN to storage circuit 118 (via signal IDR′, which is then provided to interface GPIO as signal IDR) or one of resources 120 and 122.

[0114] For example, in various embodiments, the selections performed within the circuits 124, 126, and 128 are controlled by one or more bits PERSEL in the register GPIO, and optionally by one or more bits GPIOCONFIG in the register GPIO. Specifically, also in this case, the storage circuit 118 may receive these signals and provide the signal PERSEL' and optionally the signal GPIOCONFIG'.

[0115] In the following, possible embodiments of the bits for each pad PADx in the controller register GPIO will now be described.

[0116] In various embodiments, two bits GPIOCONF[1:0]: are used to configure the corresponding PADx as an input or output, or as a pad connected to a peripheral device / resource. For example, the following bit mapping can be used:

[0117] 00:PADx is configured as input;

[0118] 01:PADx is configured as output;

[0119] 1x:PADx is configured as peripheral I / O, where "X" indicates that the corresponding bit can be either 1 or 0.

[0120] Therefore, in the considered embodiment, each PADx can be configured as input, output or peripheral I / O according to the value of the corresponding two bits GPIOCONF[1:0].

[0121] In various embodiments, a given number of bits is used for the peripheral selection bit PERSEL. For example, two possible peripheral devices 120 and 122 are used in the considered embodiment. Therefore, a single bit may be sufficient, for example:

[0122] 0: PADx is configured as a peripheral device 120; and

[0123] 1: PADx is configured as a peripheral device 122.

[0124] As mentioned before, the width of the register is one bit, because only two peripheral devices are considered in the embodiment. For example, for a number of y peripheral devices, the signal PERSEL should have at least log2(y) bits.

[0125] For example, Figure 5 , Figure 6 and Figure 7 Possible embodiments of selector circuits 124, 126, and 128 are shown, respectively.

[0126] For example, Figure 5 As shown, according to the signal PSEL, the first multiplexer 1240 can be used to select the output signal P_OUT from the output signals P1_OUT and P2_OUT provided by the peripheral devices 120 and 122. For example, the signal PSEL can correspond to the signal PERSEL' (provided by the storage circuit 118), or as shown in FIG. Figure 5 As shown, the signal PSEL corresponds to the signal PERSEL' only when the corresponding bit GPIOCONF'[1] (provided by the storage circuit 118) is also set high (i.e., PADx is configured as a peripheral I / O), as schematically shown via an electronic switch 1242. Therefore, another multiplexer 1244 can be used to select the signal ODR' (provided by the storage circuit 118) or the signal P_OUT as the signal DOUT according to the bit GPIOCONF'[1].

[0127] Similarly, if Figure 6 As shown, the selector circuit 126 may include a first multiplexer 1260 configured to select the output enable signal P_OEN from the output enable signals P1_OEN and P2_OEN provided by the peripheral devices 120 and 122 according to the signal PSEL. Therefore, another multiplexer 1262 may be used to select the bit GPIOCONF'[0] (set to 0 when PADx is configured as an input and set to 1 when PADx is configured as an output) or the signal P_OEN as the signal OEN according to the bit GPIOCONF'[1] (provided by the storage circuit 118).

[0128] In a complementary way, such as Figure 7 As shown, circuit 128 may include a demultiplexer 1280 configured to provide signal DIN as signal IDR (bit GPIOCONF'[1] is set to low) or as signal P_IN (bit GPIOCONF'[1] is set to high) according to bit GPIOCONF'[1]. In addition, a second multiplexer may be configured to provide signal P_ON as signal P1_ON or P2_ON to one of peripheral devices 120 or 122 according to signal PSEL.

[0129] Typically, based on the logic levels used for signals DIN, DOUT, and OEN, inversion of the logic levels of one or more signals may be performed when exchanging signals between circuits 118, 120, and 122 with I / O interface 130. For example, in various embodiments, multiplexer 1264 may not receive signal ODR′, but rather an inverted version of signal ODR′ provided by storage circuit 118.

[0130] Specifically, as described above, the processing system 10a includes a first sub-circuit 30 provided by a voltage VDD1 and a second sub-circuit 32 provided by a voltage VDD2. Figure 3 As shown:

[0131] - the first sub-circuit 30 comprises a microprocessor 102 and a register interface GPIO; and

[0132] The second sub-circuit 32 comprises an I / O interface 130 and blocks 120 , 122 , 124 , 126 and 128 .

[0133] like Figure 3 As schematically shown in FIG. 1 , in various embodiments, the processing system 10a includes a power management circuit 116a, which can be configured via software instructions executed by the processing unit 102. Specifically, the power management circuit 116a is located in the subcircuit 32 and is therefore powered by the power supply voltage VDD2. For example, in order to exchange data with the processing unit 102, the power management circuit 116a may include one or more registers that are programmable via the processing unit 102. For example, in Figure 3 In the embodiment, the power management circuit 116a is connected to the bus system 108.

[0134] For example, in various embodiments, the power management circuit 116a may be configured to:

[0135] - activating the low power mode as soon as the processing unit 102 sends a given command, for example programming a given bit of a register interface of the power management circuit 116a; and

[0136] - In response to one or more wake-up events, such as a change in logic level or a trigger in the wake-up signal IRQ, resuming the normal operating mode.

[0137] For example, when the low power mode is activated, the power management circuit 116a may set one or more signals POFF (e.g., high) that are provided to the power supply circuit 112a and optionally the oscillator and reset circuit 114 to perform at least one of the following operations:

[0138] - shut down the power supply voltage VDD1 of the sub-circuit 30;

[0139] - reducing the frequency of the clock signal CLK generated by the oscillator circuit 114;

[0140] - deactivating the clock signal provided to the sub-circuit 30 .

[0141] Specifically, in various embodiments, the processing system 10a may include:

[0142] - the first oscillator and reset circuit 114 in the subcircuit 30 and is therefore powered via the supply voltage VDD1;

[0143] - The second oscillator and reset circuit 114 in the subcircuit 32 are therefore powered via the supply voltage VDD2.

[0144] Therefore, in this case, when the power supply voltage VDD1 is turned off, the first oscillator and reset circuit 114 is also turned off, thereby deactivating the clock signal provided to the sequential logic circuit of the sub-circuit 30. In contrast, the sequential logic circuit of the sub-circuit 32 still receives the clock signal from the second oscillator and reset circuit 114. Therefore, in various embodiments, the oscillator of the second oscillator and reset circuit 114 has a lower frequency than the oscillator of the first oscillator and reset circuit 114.

[0145] In the case where the power management circuit 116a supports multiple modes, the register interface of the power management circuit 116a may include one or more bit patterns for selecting at least one of the above modes to be used in the low power mode (see also Fig. 9 , which will be described in more detail below).

[0146] Typically, in response to a wake-up event, the power management circuit 116a may thus resume a previous operating mode, for example:

[0147] - turning on the power supply voltage VDD1 of the sub-circuit 30; and

[0148] - Activate the clock signal provided to the sub-circuit 30 .

[0149] In various embodiments, the wake-up signal IRQ for resuming the normal working mode may be generated by any circuit within the sub-circuit 32, for example:

[0150] - the power management circuit 116a may be configured to determine whether one or more of the signal DIN provided by the I / O interface 130 or the signal IDR' provided by the circuit 128 changes logic level (eg, from high to low, or from low to high); and / or

[0151] The wake-up signal IRQ may be generated by one or more of the peripheral devices 120 and 122 .

[0152] In the case where the power management circuit 116a supports multiple wake-up sources, the register interface of the power management circuit 116a may include one or more bits WEN for selecting which wake-up signal should be enabled to resume normal operating mode (see also Fig. 9 , which will be described in more detail below).

[0153] Therefore, in various embodiments, peripheral devices that should remain turned on in the low power mode (eg, for generating the wake-up signal IRQ for resuming the normal operating mode) are powered by the power supply voltage VDD2 in the sub-circuit 32 .

[0154] like Figure 3 As shown, the register interface GPIO of the general input / output is in the subcircuit 30 and is therefore provided by the voltage VDD1. Therefore, when the power supply voltage VDD1 is turned off, the register interface GPIO loses its configuration. However, this also means that the various configuration signals provided by the circuit GPIO, such as the signals GPIOCONF, ODR and PRESEL will lose their values.

[0155] Thus, in various embodiments, the processing system 10a includes the aforementioned storage circuit 118, which is configured to store values ​​of configuration signals, such as GPIOCONF, ODR, and PRESEL, and to provide corresponding stored values, such as GPIOCONF', ODR', and PRESEL', to the I / O interface 130 and the selection circuits 124, 126, and 128. In particular, in the embodiment considered, the storage circuit 118 is located in the subcircuit 32 and is therefore powered via the power supply voltage VDD2.

[0156] For example, Figure 4 A possible embodiment of storage circuit 118 is shown.

[0157] As previously described, the register interface GPIO may be programmed via the processing unit 102. In various embodiments, the register interface GPIO may also be directly integrated in the processing unit 102. For example, as previously described, the register interface may include the following bits for each pad PAD1 ...PADn:

[0158] - a writable (and optionally readable) bit GPIOCONF for setting the mode of the corresponding pad PADx (input, output or optionally connected to a peripheral);

[0159] - a writable (and optionally readable) bit PERSEL for selecting the peripheral device 120 or 122 to be connected to the corresponding pad Padx;

[0160] - a writable (and optionally readable) bit ODR, used to set the value (high or low) of the corresponding pad PADx when the pad is configured as output; and

[0161] - A readable bit IDR indicating the logic level of the corresponding pad PADX.

[0162] In various embodiments, the storage circuit 118 is configured to store bits of the register interface GPIO, which bits are used to configure the I / O interface 130. For example, in the embodiment considered, the storage circuit 118 is configured to store the values ​​of the bits GPIOCONF, PERSEL and ODR, thereby providing stored versions of these bits GPIOCONF', PERSEL' and ODR.

[0163] Specifically, in various embodiments, the storage circuit 118 includes a corresponding storage element, such as a latch, such as a D-type latch, for each configuration bit to be stored. Specifically, in various embodiments, the storage element does not use a clock signal, thereby avoiding a significant delay between the programming of the bit in the register interface GPIO and the propagation to the I / O interface 130. For example, in Figure 4 , latches L1, L2, and L3 for storing bits of signals GPIOCONF, PERSEL, and ODR are shown, and wherein these latches provide signals GPIOCONF', PERSEL', and ODR'. In some embodiments, for example, latch L1 may include multiple latches (e.g., for GPIOCONF'[0], GPIOCONF'[1]).

[0164] Specifically, in the embodiment considered, the storage element is configured as:

[0165] - when the signal LCONF has a first logic level (eg, high), providing the logic level of the signal applied to the corresponding input; and

[0166] - When the signal LCONF has a second logic level (eg, low), the logic level is maintained.

[0167] Furthermore, in various embodiments, each configuration bit is provided to the input of the respective storage element (L1 ... L3) via a respective switch element / circuit configured to provide the configuration bit to the respective storage element (L1 ... L3) when the signal ISO has a given logic value (e.g. high). For example, in the embodiment under consideration, the switch elements are implemented with isolation cells, which are schematically shown as logic AND gates, i.e. isolation cells A1, A2 and A3 for storage elements L1, L2 and L3. Isolation cells are well known in the art and reference may be made, for example, to U.S. Pat. No. 7,167,017 B2 or US Pat. No. 6,977,833 B2, the contents of which are incorporated herein by reference. In general, isolation cells may also be implemented with electronic switches or transmission gates.

[0168] Thus, in the embodiment considered, each configuration bit can be selectively stored in a corresponding storage element (L1, L2, L3) according to the following two signals:

[0169] - a first signal LCONF selectively enabling or disabling storage of a signal provided to an input of a storage element; and

[0170] - a second signal ISO selectively providing a configuration bit to an input of a corresponding storage element.

[0171] Thus, in some embodiments, when the signal LCONF has a first logic level (e.g., high), the corresponding logic values ​​from the isolation cells (e.g., A1, A2, A3) are propagated by the corresponding storage elements (e.g., L1, L2, L3) to the circuits 124, 126, and 126; when the signal LCONF has a second logic level (e.g., low), the logic values ​​stored in the latches (e.g., L1, L2, L3) maintain their respective values, and the latches (e.g., L1, L2, L3) provide these stored values ​​to the circuits 124, 126, and 126. In some embodiments, the logic values ​​stored in the latches when the signal LCONF has the second logic level (e.g., low) correspond to the last logic values ​​at the corresponding inputs (e.g., L1, L2, L3) of the latches when the signal LCONF has the first logic level (e.g., high).

[0172] like Figure 4 As shown, the signal IDR′ provided by the circuit 128 can be directly provided to the corresponding bit IDR in the register interface GPIO.

[0173] Therefore, in the embodiment considered, the power management circuit 116a is configured to also generate the signals ISO and LCONF.

[0174] For example, Figure 8 A possible embodiment of the power management circuit 116a is shown.

[0175] In particular, in the embodiment considered, and as previously described, the power management circuit 116a is powered via the supply voltage VDD2 and comprises:

[0176] - a register interface 1162 programmable via the processing unit 102; and

[0177] -Control circuit 1164.

[0178] Specifically, in various embodiments, the control circuit 1164 is a sequential logic circuit (such as a finite state machine) or preferably a combinational logic circuit, configured to generate according to the configuration data stored in the register interface 1162 and one or more wake-up signals IRQ:

[0179] - a signal POFF of the power supply circuit 112a and optionally of the oscillator and reset circuit 114, and

[0180] - Signals ISO and LCONF of storage circuit 118.

[0181] For example, Fig. 9 As shown, register interface 1162 may include one or more of the following configuration data that may be programmed via processing unit 102:

[0182] - one or more bits MODE for activating a low power mode and optionally selecting the low power mode to be activated;

[0183] - one or more optional bits WEN for enabling wake-up sources for resuming normal working mode;

[0184] - a bit GPIORET indicating whether the storage circuit 118 should retain the configuration data of the register interface GPIO when activating the low power mode and exiting the low power mode;

[0185] - An optional bit GPIORETAC indicating whether the latches within circuit 118 should automatically become transparent (by setting signal LCONF) when resuming normal operating mode.

[0186] Thus, in various embodiments, the control circuit 1164 may be configured to monitor the bit GPIORET and, in normal operating mode, set the signals ISO and LCONF to provide configuration bits of the register interface GPIO, for example by setting the signals ISO and LCONF high.

[0187] Conversely, in response to determining that the configuration data pattern indicates that the low power mode should be activated, the control circuitry may set the signal POFF (e.g., high) to activate the (requested) low power mode, and:

[0188] - In case the signal GPIORET is set, the signals ISO and LCONF are set in order to keep the configuration bits and isolate the latches L1 - L3 from the interface GPIO, for example by setting the signals ISO and LCONF low.

[0189] Typically, in the case where the signal GPIORET is not set, the processing system 10a can be configured to perform other operations. For example, in various embodiments, in this case, the power management circuit is configured to set the signals ISO and LCONF so that the programming register value is passed from the interface GPIO to PADx, for example, by setting the signals ISO and LCONF high. However, in this case, the power management circuit sets the signal POFF so that only the clock signal CLK of the first sub-circuit 30 is turned off, while the power supply voltage VDD1 remains on. For example, this mode can be used for debugging purposes.

[0190] In various embodiments, in response to the enabled wake-up event IRQ, the control circuit 1164 may set the signal POFF (e.g., low) to activate the normal operating mode. In this case, the control circuit 1164 may also:

[0191] - without setting signal GPIORETAC, setting signals ISO and LCONF so as to retain the configuration bits in storage circuit 118, for example, by setting signal ISO high and signal LCONF low; or

[0192] In case the signal GPIORETAC is set, the storage circuit 118 is reset, for example by setting the signal ISO high and setting the signal LCONF high, whereby the reset configuration of the interface GPIO is provided by the latches L1 - L3 .

[0193] A possible operation of the processing system will now be described. After the processing system is started (activation of VIN), the power supply circuit 112a generates the power supply voltages VDD1 and VDD2. Typically, in the case where the voltages VDD1 and VDD2 correspond to the voltage VIN, the power supply circuit 112a can also be implemented via one or more electronic switches driven according to the signal POFF. As a result, the oscillator and reset circuit 114 is activated and generates a reset signal RST, thereby resetting the sub-circuit 30 of the processing system 10a. In addition, the oscillator and reset circuit 114 generates a clock signal CLK, whereby the processing unit 102 starts to execute the various firmware stored in the program memory 104.

[0194] Typically, such firmware comprises software instructions for configuring the various pads PAD1 ... PADn, ie the I / O interface 130. To this end, the firmware typically comprises software instructions for programming configuration bits in the register interface GPIO.

[0195] Furthermore, such firmware may include software instructions for activating a low power mode, for example by programming configuration data, particularly a data pattern, in register interface 1162 .

[0196] Specifically, it will be assumed hereinafter that the firmware includes software instructions for setting mode data MODE to indicate that the power supply voltage VDD1 (and optionally the oscillator and reset circuit 114) should be turned off, which will be referred to as DEEPSTOP mode hereinafter. Typically, DEEPSTOP mode may also be the only supported mode, and DEEPSTOP mode may be activated by setting a single mode bit pattern.

[0197] In various embodiments, the firmware includes one or more software instructions for setting one or more of these bits. Therefore, it will be assumed in the following that, before activating the low power mode, the firmware also programs the bit GPIORET.

[0198] In response to detecting that DEEPSTOP mode should be activated (by monitoring the configuration bit pattern), the control circuit verifies bit GPIORET and determines that the configuration data for the I / O pads should be stored.

[0199] Therefore, in this case, the control circuit 1164 can be configured to perform the following operations in sequence:

[0200] - setting signal LCONF (e.g., to low) to indicate that storage elements L1 . . . L3 should hold configuration data;

[0201] - setting the signal ISO (e.g. low) to disconnect the register interface GPIO from the elements L1 . . . L3;

[0202] - The signal POFF is set in order to switch off the supply voltage VDD1 (via the power supply circuit 112a).

[0203] Typically, the sequential operation of the control circuit 1164 can be implemented via a sequential logic circuit or by using a combinational logic circuit including a series of delay elements. Typically, the power management circuit 116a can also be a sequential logic circuit that operates in response to the clock signal CLK, and the clock signal CLK can also be turned off because the setting of the signal POFF is the last operation.

[0204] Furthermore, the sequence of operations may also be implicit due to the software instruction sequence, i.e., the processing unit 102 may first program the bit GPIORET, whereby the control circuit 1164 sets the signal LCONF (e.g., to low) to indicate that the storage elements L1 ... L3 should retain the configuration data, and then program the bit mode, whereby the control circuit 1164 sets the signal ISO (e.g., to low) to disconnect the register interface GPIO from the elements L1 ... L3. Thus, the signals LCONF and ISO may be determined from the signal GPIORET and the signal MODE, at least one or more corresponding bits indicating that the low power mode should start. For example, the bit may correspond to the CPU instruction WFI (wait for interrupt).

[0205] Thus, in response to signal POFF, power circuit 112 a switches voltage VDD1 and, optionally, oscillator and clock circuit 114 turns off clock signal CLK. However, storage circuit 118 still provides configuration data to I / O interface 130 .

[0206] For example, if the firmware has set register GPIOCONF (of a given pad PADx) to "01" and the corresponding bit ODR to "1", the storage circuit will provide the stored values ​​GPIOCONF'="01" and ODR'="1". Therefore, the selector circuits 1244 and 1262 will provide signals DOUT="1" and OEN'="1" to the output driver 1300, respectively, and the corresponding pad PADx is set high and will also maintain its value in DEEPSTOP mode. In the embodiment considered, the input comparator 1302 is always turned on, whereby the signal DIN is set to "1", and the selector circuit 1280 sets the signal IDR' to "1".

[0207] Conversely, where the firmware has set register GPIOCONF (for a given pad PADx) to "10" or "11", selector circuits 1244 and 1262 will provide signals DOUT=P_OUT and OEN'=P_OEN, and selector circuits 1240 and 1260 will:

[0208] - selecting one of the signals P1_OUT and P2_OUT as the signal P_OUT according to the signal PERSEL and optionally the signal GPIOCONF;

[0209] - Depending on the signal PERSEL and optionally the signal GPIOCONF, one of the signals P1_OEN and P2_OEN is selected as the signal P_OEN.

[0210] Furthermore, the selector circuit 1280 forwards the signal DIN to one of the signals P1_IN and P2_IN according to the signal PERSEL and optionally the signal GPIOCONF.

[0211] Thus, in this case, the selected peripheral device 120 or 122 may exchange data via the pad PADx, for example, set the logic value of the pad PADx or read the logic value of the pad PADx. For example, in order to exchange data, such a peripheral device may require a clock signal. Therefore, in various embodiments, the subcircuit 32 receives the clock signal, while the clock signal provided to the subcircuit 30 may be turned off. For example, for this purpose, the processing system 10a may include:

[0212] - two oscillators and reset circuit 114;

[0213] - an oscillator and a reset circuit 114 comprising two oscillators; or

[0214] - an oscillator and a reset circuit 114 including the oscillator (the oscillator preferably having a clock frequency settable according to the signal POFF), wherein the clock signal is always provided to the subcircuit 32 according to the signal POFF and selectively to the subcircuit 30 according to the signal POFF. As previously mentioned, in various embodiments, the operation of the clock and reset circuit 114 can be configured via a mode data pattern.

[0215] Once the low power mode is activated, the power management circuit 116a monitors for an enabled wake-up signal. As previously described, for this purpose the firmware may include instructions for programming configuration data WEN indicating which wake-up sources may reactivate the processing system 10a.

[0216] Thus, once the power management circuit 116a detects that a given enable wake-up event / signal IRQ is set, the control circuit 1164 may be configured to perform the following operations, which may be performed in parallel or sequentially:

[0217] - setting the signal POFF to switch on the power supply voltage VDD1 (via the power supply circuit 112a);

[0218] - Setting the signal ISO (eg high) in order to connect the register interface GPIO to the storage elements L1 . . . L3.

[0219] Thus, in the embodiment considered, when resuming the normal operating mode, the power management circuit 116 a does not change the logic level of the signal LCONF. For example, for this purpose, the signal LCONF may correspond to an inverted version of the bit GPIORET. In general, the signal LCONF may also correspond to the signal GPIORET by using the opposite logic level to the signal GPIORET.

[0220] Thus, in the embodiment considered, the register interface GPIO is powered via the supply voltage VDD1 and does not include a retention flip-flop. Thus, when the DEEPSTOP mode is activated, the corresponding configuration is lost. Conversely, the storage circuit 118 and the register 1162 of the power management circuit 116 a are within the subcircuit 32, which remains powered by the supply voltage VDD2 and therefore remains active.

[0221] Therefore, in various embodiments, the firmware executed by the processing unit 102 includes instructions for reprogramming the register interface GPIO and only includes instructions for changing the logic level of the bit GPIORET by programming the register interface 1162 .

[0222] For example, Figure 3 The processing circuit 10a shown has the advantage that the processing unit 102 also does not use a holding flip-flop.

[0223] For example, in response to resuming the normal operating mode, the oscillator and reset circuit 114 may generate a reset, thereby performing a new start of the processing unit 102. For example, in response to the reset, the firmware may include instructions for performing one or more tasks, such as reading data from a sensor and sending such data, and then reactivating the low power mode. Additionally or alternatively, the firmware may include instructions for determining which interrupt IRQ has been generated to resume the normal operating mode, and then performing one or more tasks based on the determined interrupt.

[0224] In the event that a given processing state of the processing unit must be maintained, the firmware may include instructions for storing data identifying the state of the processing unit 102 to a memory that is configured to maintain its configuration when the power supply voltage VDD1 is deactivated. For example, for this purpose, the memory may be a programmable non-volatile memory powered via the power supply voltage VDD2, such as the memory 104, or a volatile memory, such as the memory 100. Thus, in response to a reset generated by the circuit 114 when resuming a normal operating mode, the firmware may include instructions for reading data identifying the state of the processing unit 102 from the memory, and then performing one or more tasks based on the read data.

[0225] In various embodiments, the processing system 10a may also be configured via software instructions (executed via the processing unit 102) or via the hardware power management circuit 116a to store the complete context of the processing unit 102. In general, the term "context" refers to the contents of the registers of the processing unit 102 (in the subcircuit 30). In fact, as previously mentioned, in various embodiments, the memory 100 may be powered via the power supply voltage VDD2 and thus retain its data. Therefore, in response to resuming the normal operating mode, the processing system 10a (via firmware or via the hardware power management circuit 116a) may read the context from the memory again.

[0226] For example, restoring the complete context also includes restoring the configuration of the register interface GPIO. Therefore, in the event that the user wants to change the configuration of one or more pads, it is sufficient to reprogram the new configuration data to the register interface GPIO and then change the logic level of the configuration data GPIOORET.

[0227] On the contrary, in the embodiment considered, in case the configuration of the register interface GPIO is lost and the user wishes to change the configuration of the I / O interface, for example in order to change the logic level of a pad, the firmware must include instructions for providing the register interface GPIO with the new configuration of a given pad PADx and configuration data of the other pads PADx (which remain unchanged).

[0228] As previously mentioned, in various embodiments, the configuration register 1162 may further include a bit GPIORETAC. Specifically, when this bit is set, the power management circuit 116a may be configured to make the storage circuit 118 transparent when resuming the normal operating mode, for example, by setting the signal LCONF high according to the bit GPIORETAC. This behavior may be useful, for example, in the case where the processing system 10a is stuck for some reason during DEEPSTOP or during wakeup from DEEPSTOP, and the user wants to obtain dynamic control over one or more pads PAD1 ... PADn again, make the latch transparent again, and use JTAG or a single-wire interface for debugging.

[0229] Thus, with the configuration described herein, the processing system is able to process one or more general purpose input-outputs in and out of low power mode without losing their configuration, even if the controller GPIO does not include a retention trigger. Specifically, a combined solution is used for this purpose, which includes:

[0230] - storage circuit 118 and power management circuit 116a; and

[0231] - Software instructions for storing the configuration to the storage circuit 118, activating the DEEPSTOP mode, and in response to resuming the normal operating mode, reprogramming the I / O configuration and making the storage element circuit 118 transparent again.

[0232] Thus, power consumption in low power mode can be reduced, and the amount of area required for a retention flip-flop can be avoided. Furthermore, complex routing of two supply voltages to such a retention flip-flop can be avoided. In fact, in various embodiments, the register interface GPIO can be arranged near the microprocessor 102 (or even within the microprocessor 102), so the microprocessor 102 can be an existing integrated circuit layout, such as an IP core, and the sub-circuit 32 can be provided as an additional separate integrated circuit layout.

[0233] Of course, without prejudice to the principle of the invention, the details of construction and of the embodiments may vary widely with respect to what is described and illustrated herein purely by way of example, without thereby departing from the scope of the invention as defined by the appended claims.

Claims

1. A processing system comprising: A first pad; a first subcircuit and a second subcircuit; a power supply circuit configured to receive an input voltage and generate a first power supply voltage and a second power supply voltage, wherein the first subcircuit is configured to be powered by the first power supply voltage and the second subcircuit is configured to be powered by the second power supply voltage, wherein the power supply circuit is configured to selectively shut down the first power supply voltage according to a first control signal; The first sub-circuit comprises: a general purpose input / output register configured to receive a first data input signal and provide configuration data, the configuration data comprising a first output enable signal, a first data output signal, and a peripheral device select signal; and The second sub-circuit comprises: Input / output interfaces, including: an output driver configured to be enabled via an output enable signal, the output driver being configured to apply a voltage to the first pad according to a logic level of a binary data output signal when enabled, and an input buffer configured to generate a binary data input signal according to the voltage at the first pad, at least one peripheral device configured to receive a second data input signal and provide a second output enable signal and a second data output signal, A storage circuit comprising: a plurality of latches configured to provide stored configuration data, the stored configuration data comprising a stored first output enable signal, a stored first data output signal, and a stored peripheral device select signal, wherein the plurality of latches are configured to provide or maintain the configuration data applied to inputs of the plurality of latches according to a second control signal, and a corresponding isolation unit for each of the plurality of latches, configured to selectively connect the general purpose input / output register to input terminals of the plurality of latches according to a third control signal to selectively provide the configuration data to the inputs of the plurality of latches, a first selection circuit configured to determine a logic level of the data output signal according to the stored first data output signal, the second data output signal, and the stored peripheral device selection signal; a second selection circuit configured to determine a logic level of the output enable signal according to the stored first output enable signal, the second output enable signal, and the stored peripheral device selection signal; a third selection circuit configured to provide the data input signal as the first data input signal or the second data input signal according to the stored peripheral device selection signal, and A power management circuit is configured to manage a normal operating mode and a low power mode, wherein the power management circuit is configured to: receiving one or more commands for activating the low power mode; In response to receiving the one or more commands for activating the low power mode: setting the second control signal to a first state of the second control signal to indicate that the plurality of latches should hold the configuration data; setting the third control signal to a first state of the third control signal to disconnect the general purpose input / output register from the inputs of the plurality of latches, and setting the first control signal to a first state of the first control signal to turn off the first power supply voltage, monitoring one or more wake-up signals to determine a wake-up event, and In response to determining the wake-up event: setting the first control signal to a second state of the first control signal to switch on the first power supply voltage to activate the normal operating mode, setting the third control signal to a second state of the third control signal to connect the general purpose input / output register to the inputs of the plurality of latches, receiving a command for reactivating the plurality of latches, and In response to receiving the command to reactivate the plurality of latches, the second control signal is set to a second state of the second control signal to indicate that the plurality of latches should provide the configuration data. 2 . The processing system according to claim 1 , wherein the first selection circuit is configured to select the stored first data output signal or the second data output signal as the data output signal according to the stored peripheral device selection signal.

3. The processing system of claim 1, wherein: the at least one peripheral device comprising a first peripheral device and a second peripheral device, wherein the first peripheral device is configured to receive a third data input signal and provide a third output enable signal and a third data output signal, wherein the second peripheral device is configured to receive a fourth data input signal and provide a fourth output enable signal and a fourth data output signal; The first selection circuit is configured to select the third data output signal or the fourth data output signal as the second data output signal according to the stored peripheral device selection signal; and The second selection circuit is configured to select the third output enable signal or the fourth output enable signal as the second output enable signal according to the stored peripheral device selection signal. The processing system of claim 1 , wherein the at least one peripheral device comprises a communication interface.

5. The processing system of claim 1 , wherein the power management circuit comprises another register, the another register comprising first configuration data and second configuration data, wherein the second control signal is determined according to the first configuration data, and the first control signal and the third control signal are determined according to the second configuration data, and wherein, The one or more commands for activating the low power mode include: a first command for programming the first configuration data to set the second control signal to indicate that the plurality of latches should hold the configuration data; and a second command for programming the second configuration data to set the third control signal to disconnect the general purpose input / output register from the inputs of the plurality of latches and to set the first control signal to shut down the first power supply voltage, wherein the command for reactivating the plurality of latches comprises a third command for programming the first configuration data to set the second control signal to indicate that the plurality of latches should provide the configuration data. 6 . The processing system of claim 5 , wherein the first subcircuit further comprises a digital processing unit configured to be programmed via software instructions, and wherein the further register is configured to be programmed via the digital processing unit.

7. The processing system of claim 5, wherein the another register comprises third configuration data, and wherein the power management circuit is configured to: receiving multiple wake-up signals; selecting a subset of the wake-up signals according to the third configuration data; and A selected subset of the wake-up signals is monitored to determine the wake-up event.

8. The processing system of claim 1 , wherein the first subcircuit further comprises a digital processing unit, the digital processing unit being configured to be programmed via software instructions, wherein the general purpose input / output register is configured to be programmed via the digital processing unit, wherein receiving one or more commands for activating the low power mode comprises receiving one or more commands from the digital processing unit, and wherein receiving a command for reactivating the plurality of latches comprises receiving the command from the digital processing unit.

9. The processing system of claim 8, wherein the processing system comprises an oscillator and a reset circuit configured to generate a reset signal when the first power supply voltage is turned on, wherein the digital processing unit comprises a microprocessor, the microprocessor comprises a plurality of registers, and wherein the plurality of registers of the microprocessor and the general input / output register are reset in response to the reset signal.

10. The processing system of claim 9, wherein the processing system comprises a non-volatile program memory having stored software instructions executed by the digital processing unit, wherein the stored software instructions comprise: the one or more commands for activating the low power mode; Instructions for programming the general purpose input / output registers; as well as The command is used to reactivate the plurality of latches.

11. The processing system of claim 10, wherein the second subcircuit comprises a volatile memory, wherein the stored software instructions comprise: prior to the one or more commands for activating the low power mode, instructions for storing the contents of the plurality of registers of the microprocessor to given locations in the volatile memory; as well as Instructions for reading the contents of the given location in the volatile memory and storing the contents to the plurality of registers of the microprocessor after the microprocessor is reset.

12. The processing system of claim 1, wherein the processing system is integrated into an integrated circuit. 13 . The processing system of claim 1 , wherein the second selection circuit is configured to select the stored first output enable signal or the second output enable signal as the output enable signal according to the stored peripheral device selection signal.

14. A method of operating a processing system, the method comprising: generating a first power supply voltage for the first sub-circuit and a second power supply voltage for the second sub-circuit; controlling an input / output interface based on the contents of a general purpose input / output register of the first sub-circuit using a storage circuit of the second sub-circuit during a normal operating mode of the processing system, the storage circuit comprising a plurality of latches having inputs and outputs, the inputs being coupled to the outputs of the general purpose input / output registers, the outputs being coupled to a selection circuit of the second sub-circuit for controlling the input / output interface; receiving a request to enter a low power mode of the processing system; In response to receiving the request to enter the low power mode, setting a first control signal to a first state of the first control signal to maintain states of the outputs of the plurality of latches, setting a second control signal to a first state of the second control signal to disconnect the general purpose input / output register from the inputs of the plurality of latches, and turning off the first power supply voltage; During the low power mode, controlling the input / output interface based on contents of the plurality of latches and monitoring a wake-up signal to determine a wake-up event; and In response to determining the wake-up event: Turning on the first power supply voltage, setting the second control signal to a second state of the second control signal to connect the general purpose input / output register to the inputs of the plurality of latches, the second state of the second control signal being different from the first state of the second control signal, and Enter the normal working mode.

15. The method according to claim 14, further comprising: In response to entering the normal operating mode from the low power mode, changing the contents of the general purpose input / output register; as well as After changing the content of the general purpose input / output register, the first control signal is set to a second state of the first control signal, and the input / output interface is controlled via the plurality of latches based on the changed content of the general purpose input / output register, wherein the second state of the first control signal is different from the first state of the first control signal.

16. The method of claim 14 , wherein turning off the first power supply voltage comprises setting a third control signal to a first state of the third control signal, and wherein turning on the first power supply voltage comprises setting the third control signal to a second state of the third control signal, the second state of the third control signal being different from the first state of the third control signal.

17. The method of claim 14, further comprising providing an input voltage to a power supply circuit, wherein generating the first power supply voltage and the second power supply voltage comprises: The first power supply voltage for the first sub-circuit and the second power supply voltage for the second sub-circuit are generated from the input voltage using the power supply circuit.

18. An integrated circuit comprising: A first pad; a power supply circuit configured to receive an input voltage and generate a first power supply voltage and a second power supply voltage, wherein the power supply circuit is configured to selectively shut down the first power supply voltage according to a first control signal; a first subcircuit configured to be powered by the first supply voltage, the first subcircuit comprising a general purpose input / output register having outputs having respective states based on contents of the general purpose input / output register; as well as The second sub-circuit is configured to be powered by the second power supply voltage, the second sub-circuit comprising: An input / output interface is coupled to the first pad, the input / output interface having multiple working modes, A storage circuit comprising: Multiple latches, and a plurality of isolation units having: outputs respectively coupled to the inputs of the plurality of latches; and inputs respectively coupled to the outputs of the general purpose input / output register, wherein the plurality of isolation units are configured to disconnect the inputs of the plurality of latches from the outputs of the general purpose input / output register when a second control signal is in a first state of the second control signal, and to connect the inputs of the plurality of latches with the outputs of the general purpose input / output register when the second control signal is in a second state of the second control signal different from the first state of the second control signal, and wherein the plurality of latches are configured to: providing contents from the inputs of the plurality of latches at the outputs of the plurality of latches when a third control signal is in the first state of the third control signal, and maintaining and providing contents stored in the plurality of latches at the outputs of the plurality of latches when the third control signal is in a second state of the third control signal different from the first state of the third control signal, and A selection circuit is configured to select an operation mode of the input / output interface from the plurality of operation modes based on the outputs of the plurality of latches.

19. The integrated circuit of claim 18, further comprising a power management circuit configured to manage a normal operating mode and a low power mode, wherein the power management circuit is configured to: In response to receiving a request to enter the low power mode, setting the third control signal to the second state of the third control signal, setting the second control signal to the second state of the second control signal, and setting the first control signal to a first state of the first control signal to turn off the first power supply voltage; and During the low power mode, in response to determining a wake-up event, setting the first control signal to a second state of the first control signal to turn on the first power supply voltage, and The second control signal is set to the first state of the second control signal.

20. The integrated circuit according to claim 19 further includes a digital processing unit, which is configured to: change the content of the general input / output register when the third control signal is in the second state of the third control signal, and after changing the content of the general input / output register, set the third control signal to the first state of the third control signal.

21. The integrated circuit of claim 18, wherein: The second subcircuit also includes a first peripheral device; In a first operating mode among the plurality of operating modes, the input / output interface is configured to generate a binary data input signal according to a voltage at the first pad; In a second operating mode among the plurality of operating modes, the input / output interface is configured to apply a voltage to the first pad according to a logic level of a binary data output signal; and In a third operation mode among the plurality of operation modes, the input / output interface is configured to provide the binary data input signal to the first peripheral device or to apply a voltage to the first pad based on the first peripheral device.

22. The integrated circuit of claim 21, wherein the second sub-circuit further comprises a second peripheral device, and wherein the selection circuit comprises: a first multiplexer having: a first input coupled to an output of a first latch of the plurality of latches; an output coupled to the input / output interface; and a select input coupled to an output of a second latch of the plurality of latches; a second multiplexer having: a first input coupled to the first peripheral device; a second input coupled to the second peripheral device and an output coupled to the second input of the first multiplexer; a switch having: a first input coupled to an output of a third latch of the plurality of latches; and an output coupled to a select input of said second multiplexer, said switch having a control input coupled to said output of said second latch; a third multiplexer having: a first input coupled to an output of a fourth latch of the plurality of latches; an output coupled to the input / output interface; and a select input coupled to the output of the second latch of the plurality of latches; a fourth multiplexer having: a first input coupled to the first peripheral device; a second input coupled to the second peripheral device; an output coupled to a second input of the third multiplexer; and a select input coupled to said output of said switch; a first demultiplexer having: a first output coupled to the first peripheral device; a second output coupled to the second peripheral device; and a select input coupled to said output of said switch; as well as A second demultiplexer having: an input coupled to the input / output interface; a first output coupled to the storage circuit; a second output coupled to the first input of the first demultiplexer; and a select input coupled to the output of the second latch.

23. The integrated circuit of claim 22, wherein the input / output interface comprises: an output driver configured to be enabled by the output of the third multiplexer, the output driver being configured, when enabled, to: apply a voltage to the first pad according to the output of the first multiplexer; as well as An input buffer is configured to apply a binary data input signal to the input of the second demultiplexer based on the voltage at the first pad.

Images