Display Devices

Abstract

A display device is provided. The display device includes: a display area including a plurality of pixel rows and having a periphery including a curved section and a straight section; a non-display area surrounding the display area and having a periphery including a curved section and a straight section; a gate driver composed of a plurality of gate blocks corresponding to the pixel rows and arranged in the non-display area; and a low potential power supply line arranged between the gate driver and the periphery of the non-display area, wherein the gate block includes a plurality of stages.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2020-0177661 filed in the Korean Intellectual Property Office on December 17, 2020, and the disclosure of that patent application is incorporated into this application by reference. Technical Field

[0003] The present invention relates to a display device having a gate driver built in a display panel in which the shape of a substrate is not a rectangular but a free form. Background Art

[0004] Wearable devices, flexible devices, or vehicle display devices require free-form display devices with various shapes, rather than rectangular display devices of the related art. For example, in the case of a clock, the display panel can be processed into a disc. In addition, depending on the design of the display device, a smartphone with a rectangular display panel whose corners are processed into curves may be provided.

[0005] The driving circuit of the display panel includes: a pixel array, in which an image is displayed; a data driver, which provides data signals to data lines of the pixel array; a gate driver, which sequentially provides gate signals to gate lines of the pixel array; and a timing controller that controls the data driver and the gate driver.

[0006] In the related art, a display device is implemented by connecting a separate gate driver IC to a display panel. However, according to this method, the cost of the display device increases due to the cost of the IC, and the number of link lines connecting the gate driver and the gate line increases, which increases the width of the non-display area.

[0007] Recently, a technology is being adopted to build a gate driver into a display panel together with a pixel array. The gate driver built into the display panel is known as a gate-in-panel (GIP) circuit. The gate-in-panel circuit includes a shift register. The shift register includes a plurality of stages connected to a slave ground. These stages generate outputs in response to a start pulse and convert the outputs according to a shift clock. A start pulse, a shift clock, and a drive voltage are provided to the shift register.

[0008] When the gate driver is built into the display panel, the cost of the driver IC can be reduced, but it is difficult to reduce the size of the non-display area in which the gate driver is provided. This is because the number of gate stages increases, and the gate driver extends in the horizontal direction to ensure the space occupied by the wiring for providing the start pulse, shift clock and drive voltage to the level of the GIP circuit. In addition, in the case of a model that recently adopts more display devices by combining low-temperature polymer semiconductor (LTPS) transistors and oxide semiconductor transistors to drive the display device, more gate stages are required than normal display devices. For example, when a hetero thin film transistor is adopted, multiple gate stages will be further required to drive the low-temperature polymer semiconductor LTPS transistor as a p-type thin film transistor and the oxide semiconductor transistor as an n-type thin film transistor together. A circuit for generating a scan signal for the oxide semiconductor transistor and a circuit for generating a reset signal for the oxide semiconductor transistor will be separately required. In addition, there will be a GIP circuit for turning on and off the reset signal of the oxide semiconductor transistor.

[0009] There is a trend that display panels adopt special-shaped transistors to have higher performance, and users prefer displays with large display screens (in which the frame ratio of the non-display area is smaller than the screen of the display area) or free-form display devices with various shapes. Therefore, the gate level of the gate driver increases, thereby increasing the size of the non-display area.

[0010] In order to solve the above-mentioned problems, various methods for reducing the non-display area of ​​a free-form display panel with a built-in gate driver have been sought in recent years. Summary of the invention

[0011] As described above, when the gate driver is built into the display panel, the gate driver occupies a portion of the non-display area, so that the size of the non-display area increases. In order to reduce the size of the non-display area of ​​the display panel using the special-shaped transistor, the layout of the gate driver is optimized to reduce the area occupied by the gate driver, or the gate driver is set to be deformed in the remaining space of the free-form part to reduce the space of the non-display area. Therefore, in this specification, a method for optimizing the design of the gate driver will be described.

[0012] In the gate driver, a gate block formed by a plurality of stages is connected to correspond to a pixel array. The free-form display panel includes a curve so that a gate driver built into a free-form portion of the display panel can be arranged along the curve. However, a plurality of stages constituting the block are arranged in a rectangular space, making it difficult to arrange the gate driver in a curved portion of a free-form non-display area. Therefore, a gate driver arranged in a free-form non-display area can be arranged more irregularly than a gate driver arranged in a non-display area having a rectangular or straight frame, and the size of the non-display area increases.

[0013] Therefore, the inventors of the present invention recognized the above-mentioned problems and invented a wiring structure in which the size of the non-display area is reduced in the free-form portion and a display panel using the wiring structure.

[0014] An object to be achieved by the present invention is to provide a gate driver structure capable of reducing the size of a non-display area in a free-form portion and a display panel using the gate driver structure.

[0015] The objects of the present invention are not limited to the above objects, and those skilled in the art can clearly understand other objects not mentioned above based on the following description.

[0016] According to one aspect of the present invention, a display device includes: a display area, which includes a plurality of pixel rows and has a periphery including a curved segment and a straight segment; a non-display area, which surrounds the display area and has a periphery including a curved segment and a straight segment; a gate driver, which is composed of a plurality of gate blocks corresponding to the pixel rows and is arranged in the non-display area; and a low-potential power line, which is arranged between the gate driver and the periphery of the non-display area, wherein the gate block includes a plurality of stages.

[0017] According to another aspect of the present invention, a display device includes: a display area, which includes a plurality of pixel rows and has a periphery including a curved segment and a straight segment; a non-display area, which surrounds the display area and has a periphery including a curved segment and a straight segment; and a gate driver, which is composed of a plurality of gate blocks corresponding to the pixel rows and is arranged in the non-display area, wherein the gate blocks include a plurality of stages, wherein the plurality of stages include a first scanning drive circuit, a second scanning drive circuit, a light emitting drive circuit, a switch drive circuit and a reset drive circuit.

[0018] Additional details of exemplary embodiments are included in the detailed description and the accompanying drawings.

[0019] According to the exemplary embodiments of the present invention, the positioning of a gate driver including an increased number of gate stages by adopting a special-shaped thin film transistor is optimized, thereby minimizing the space of a free-form non-display area.

[0020] The effects according to the present invention are not limited to the above-exemplified contents, and more various effects are included in the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The above and other aspects, features and other advantages of the present invention will be more clearly understood through the following detailed description in conjunction with the accompanying drawings. In the accompanying drawings:

[0022] Figure 1 is a plan view illustrating a display panel according to an exemplary embodiment of the present invention;

[0023] Figure 2 It is a graphic Figure 1 Block diagram of the gate drive circuit when using heterotype transistors;

[0024] Figure 3 is a view illustrating a connection pattern of a gate driver and a gate line;

[0025] Figure 4 is a view illustrating another connection pattern of a gate driver and a gate line;

[0026] Figure 5 is a plan view of a gate driver disposed on a display panel according to an exemplary embodiment;

[0027] Figure 6 is a plan view illustrating area A, where area A is about the area set at Figure 5 a gate driver in a non-display area at a corner of a display panel;

[0028] Figure 7 is a plan view illustrating another example of area A, wherein area A is about a device set in Figure 5 A gate driver in a non-display area at a corner of a display panel. DETAILED DESCRIPTION

[0029] The advantages and features of the present invention and the methods for achieving these advantages and features are described in detail below and in the accompanying drawings. Figure 1 The exemplary embodiments described in detail will become clear. However, the present invention is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. The exemplary embodiments are provided only by way of example so that those skilled in the art can fully understand the disclosure of the present invention and the scope of the present invention. Therefore, the present invention will be limited only by the scope of the appended claims.

[0030] The shapes, sizes, proportions, angles, quantities, etc. shown in the accompanying drawings for describing exemplary embodiments of the present invention are merely examples, and the present invention is not limited thereto. Similar reference numerals denote similar elements throughout the application. In addition, in the following description of the present invention, detailed explanations of known related arts may be omitted to avoid unnecessarily obscuring the subject matter of the present invention. Terms such as "including", "having" and "comprising" used herein are generally intended to allow the addition of other components unless these terms are used together with the term "only".

[0031] Even if not explicitly stated, the components are interpreted as including the usual error range.

[0032] When terms such as "on", "over", "below", and "after" are used to describe the positional relationship between two parts, one or more parts may be set between the two parts unless these terms are used together with the terms "immediately" or "directly".

[0033] When an element or layer is referred to as being “on” another element or layer, the element or layer may be directly disposed on the other element or layer or other elements or layers may be interposed therebetween.

[0034] Although the terms "first", "second", etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from other components. Therefore, within the technical concept of the present invention, the first component mentioned below may be the second component.

[0035] When describing the components of the exemplary embodiments of the present invention, technical terms such as first, second, A, B, (a), (b), etc. may be used. These terms are used to distinguish one component from other components, but the nature, order or number of the components are not limited by these technical terms. If a component is described as being "connected to" or "joined to" another component, it will be understood that the component can be directly connected to or joined to the other component, or other components can be "connected to" or "joined to" between the two components.

[0036] In this specification, in a narrow sense, a "display device" may include a display device having a display panel and a driver for driving the display panel, such as a liquid crystal module (LCM), an organic light emitting diode module (OLED module), and a quantum dot (QD) module. In addition, a "display device" may further include a set electronic device or a set device (or set device) as a finished product or final product, such as an LCM, an OLED module, or a QD module such as a notebook computer, a television, or a computer monitor; an automobile display or an instrument display of other types of vehicles; and a mobile electronic device including a smart phone or an electronic pad.

[0037] Therefore, the display device of the present invention may include not only the display device itself in a narrow sense, such as LCM, OLED module or QD module, but also an application product or unit device as a final consumer device including LCM, OLED module or QD module.

[0038] In addition, as needed, an LCM, an OLED module, or a QD module consisting of a display panel and a driver is represented as a display device in a narrow sense, and an electronic device as a finished product including the LCM, the OLED module, and the QD module may be represented as a "set device". For example, a display device in a narrow sense includes a liquid crystal display (LCD) panel, an OLED display panel, or a quantum dot display panel, and a source PCB as a controller for driving the display panel. In contrast, a set device may be a concept that further includes a set PCB, wherein the set PCB is a set controller electrically connected to the source PCB to control the entire set device.

[0039] The display panel used in the exemplary embodiment of the present invention may use any type of display panel, such as a liquid crystal display panel, an organic light emitting diode (OLED) display panel, a quantum dot (QD) display panel, and an electroluminescent display panel. However, the display panel is not limited to a specific display panel, which can bend the frame and has a flexible substrate and a lower back-plate support structure for the OLED display panel of the present invention. In addition, the display panel used in the display device according to the exemplary embodiment of the present invention does not limit the shape or size of the display panel.

[0040] For example, when the display panel is an OLED display panel, the display panel includes a plurality of gate lines and a plurality of data lines, and pixels formed at the intersection of the gate lines and the data lines. In addition, the display panel may be configured to include an array having a thin film transistor (which is an element that selectively applies a voltage to each pixel), an organic light emitting diode (OLED) layer located on the array, and an encapsulation substrate or an encapsulation layer disposed on the array to cover the organic light emitting diode layer. The encapsulation layer protects the thin film transistor and the organic light emitting diode layer from external impacts and inhibits moisture or oxygen from penetrating into the organic light emitting diode layer. In addition, the layer formed on the array may include an inorganic light emitting layer, such as a nano-sized material layer or a quantum dot layer.

[0041] In this manual, Figure 1 An exemplary organic light emitting diode (OLED) display panel 100 is illustrated, which may be integrated in a display device.

[0042] Figure 1 An exemplary display device that may be included in an electronic device is illustrated.

[0043] Figure 1 is a view illustrating a display panel according to an exemplary embodiment of the present invention.

[0044] Reference Figure 1 , the display panel 100 may be divided into a pixel region 120 and a region other than the pixel region 120. The pixel region 120 is a region including a pixel array having a plurality of pixel rows and displaying a screen, also referred to as a display region. The region other than the pixel region 120 is a non-display region, and a gate driver 110, various wirings, and a pad unit for applying a signal to a pixel are disposed in the non-display region. Although in Figure 1 The data driver 200 is disposed outside the display panel 100 , but the location of the data driver 200 is not limited thereto.

[0045] The data driver 200 outputs a data signal in response to a data timing control signal provided from a timing controller. The data driver 200 samples and latches a digital data signal provided from the timing controller to convert the digital data signal into an analog data signal based on a gamma reference voltage. The output data signal is provided to a data line in the pixel area 120 via a data connection line 211. Specifically, the data driver 200 may be formed on the display panel 100 in the form of an integrated circuit (IC), or may be formed on the display panel 100 in the form of a chip on a film. In addition, depending on the product, the timing controller is combined with the data driver 200 to be implemented as a single chip.

[0046] The gate driver 110 outputs a gate signal in response to a gate timing control signal provided from a timing controller. The gate timing control signal includes, for example, gate clock signals GCLK1_L, GCLK2_L, GCLK1_R, GCLK2_R and a start signal. The gate driver 110 provides the gate signal to the gate line in the pixel area 120 via the gate connection 111. The gate driver 110 may be formed in the form of an integrated circuit (IC), but in the present invention, the gate driver 110 may be formed in the form of an intra-panel gate GIP built into the display panel. The gate driver 110 may be located on the left and right sides of the display panel 100, or may be arranged on either side.

[0047] The low potential power line 510 is disposed outside the gate driver 110 of the display panel 100. For example, the low potential power line 510 may be disposed between the gate driver 110 and the periphery of the non-display area. The low potential power line 510 may provide ground power to the organic light emitting diode of the pixel area 120.

[0048] As described above, the display panel 100 displays an image in response to the gate signal and the data signal supplied from the gate driver 110 and the data driver 200 and the power supply voltage supplied from the power supply unit.

[0049] Figure 2 It is a graphic Figure 1 A block diagram of a gate drive circuit (second gate driver) 110b when a special-type transistor is used in FIG. Figure 2 In the Figure 1 The gate signal of the pixel circuit.

[0050] The gate driver 110 includes a first scan drive circuit SP, a switch drive circuit SW, a light emitting drive circuit EM, a second scan drive circuit SN, and a reset drive circuit Dvini. The first scan drive circuit SP, the switch drive circuit CW, the light emitting drive circuit EM, the second scan drive circuit SN, and the reset drive circuit Dvini are multiple stages including a shift register, and the circuits are grouped together to form a block or a gate block. Figure 2 , the (n-2)th level, the (n-1)th level, the nth level, and the (n+1)th level among the multiple levels are shown as examples, where n is a natural number greater than or equal to 2.

[0051] The first scanning driving circuit SP includes first scanning stages SP(n-2) to SP(n+1) and wiring. The wiring is applied with the 1-1 gate clock signal G1CLK1, the 1-2 gate clock signal G1CLK2, the first clock signal CLK1, the second clock signal CLK2, the first gate low voltage VGL1, the first gate high voltage VGH1 and the first gate start voltage G1VST input to the first scanning stage. The first scanning stage outputs the output signal while shifting the first gate start voltage G1VST according to the 1-1 gate clock signal G1CLK1 and the 1-2 gate clock signal G1CLK2. Each stage outputs two output signals. For example, the nth first scanning stage SP(n) outputs the first output signal input as the start signal Vst of the (n+1)th first scanning stage SP(n+1), and the second output signal input to the gate line of the nth pixel row P(n). Specifically, the second output signal of the nth first scanning stage SP(n) may correspond to the first scanning signal of the nth pixel row P(n).

[0052] The first scan driving circuit SP may input a scan signal to the gate line to drive a low temperature polymer semiconductor (LTPS) transistor of the pixel circuit.

[0053] The second scan driving circuit SN includes second scan stages SN(n-2) to SN(n+1) and wirings to which a 2-1 gate clock signal SNCLK1, a 2-2 gate clock signal SNCLK2, a second gate low voltage VGL2, a second gate high voltage VGH2, and a second gate start voltage SNVST are applied.

[0054] The second scanning stage outputs two output signals while shifting the second gate start voltage SNVST according to the 2-1 gate clock signal SNCLK1 and the 2-2 gate clock signal SNCLK2. For example, one output signal of the nth second scanning stage SN(n) is input as the start signal Vst of the (n+1)th second scanning stage SN(n+1), and another output signal of the nth second scanning stage SN(n) is input to the gate line of the nth pixel row P(n). Specifically, another output signal of the nth second scanning stage SN(n) may correspond to the second scanning signal of the nth pixel row P(n).

[0055] The second scan driving circuit SN may input a scan signal to the gate line to drive the oxide semiconductor transistor of the pixel circuit.

[0056] The second scanning signal is input to the gate of the n-type transistor, and the first scanning signal is input to the gate of the p-type transistor. The gate conduction voltage VGH of the n-type transistor is the inverted voltage of the gate conduction voltage of the p-type transistor. In other words, the second scanning signal can be realized by inverting the first scanning signal. Therefore, the first scanning level can be realized by inverting the output signal of the second scanning level. In this case, the first output signal of the first scanning level can be the same as the output signal of the second scanning level, so that the first scanning level can be formed by using the circuit constituting the second scanning level. In addition, the first scanning level can generate an output signal obtained by inverting the signal output from the second scanning level using the first clock signal CLK1 and the second clock signal CLK2 additionally.

[0057] The light-emitting driving circuit EM includes light-emitting stages EM(n-2) to EM(n+1) and wiring. The wiring is applied with a first light-emitting clock signal EMCLK1, a second light-emitting clock signal EMCLK2, a light-emitting low voltage VEL, a light-emitting high voltage VEH, and a light-emitting start voltage EMVST input to the light-emitting stage. The light-emitting stage outputs two output signals while shifting the light-emitting start voltage EMVST according to the first light-emitting clock signal EMCLK1 and the second light-emitting clock signal EMCLK2. For example, the first output signal of the nth light-emitting stage EM(n) is input as the start signal Vst of the (n+1)th light-emitting stage EM(n+1), and the second output signal is input to the gate line of the nth pixel row P(n). Specifically, the output signal of the nth light-emitting stage EM(n) may correspond to the light-emitting signal of the nth pixel row P(n).

[0058] The reset drive circuit DVini includes reset stages DVini(n-2) to DVini(n+1) and wiring. The wiring is applied with a first reset clock signal DVCLK1, a second reset clock signal DVCLK2, a reset low voltage VGL3, a reset high voltage VGH3, and a reset start voltage DVVST input to the reset stage. The reset stage outputs two output signals while shifting the reset start voltage DVVST according to the first reset clock signal DVCLK1 and the second reset clock signal DVCLK2. For example, the first output signal of the nth reset stage DVini(n) is input as the start signal Vst of the (n+1)th reset stage DVini(n+1), and the second output signal is input to the gate line of the nth pixel row P(n). Specifically, the output signal of the nth reset stage DVini(n) may correspond to the reset signal of the nth pixel row P(n). When the reset signal is driven from the high-speed drive (120Hz to 60Hz) mode to the low-speed (1Hz) mode with low power consumption, the screen flicker or screen switching speed can be recognized relatively slowly compared with other display devices. To solve this problem, it is necessary to apply a high AC voltage and a low AC voltage to the driving transistor instead of a DC voltage. In order to apply an AC voltage to the driving transistor, a reset driving circuit DVini can be used.

[0059] The switch driving circuit SW may function as a switch to control whether a reset signal of the reset driving circuit DVini is input to the driving transistor.

[0060] Figure 3 and Figure 4 are views illustrating various connection patterns of a gate driver and a gate line.

[0061] Reference Figure 3 The gate driver includes a first gate driver 220a disposed at one edge (left side) of the display panel 100 and a second gate driver 220b disposed at the other edge (right side). The first gate driver 220a and the second gate driver 220b are connected to gate lines GL1 to GLn connected to all pixel rows located in the pixel area 120.

[0062] The first gate driver 220a and the second gate driver 220b are simultaneously applied with the start signal Vst to simultaneously output the gate signal. Therefore, the gate signals output from the first gate driver 220a and the second gate driver 220b are simultaneously applied to both ends of the same gate line. For example, when the pixels of the pixel area 120 are divided into a left half and a right half, the first gate driver 220a applies the gate signal to the pixels of the left half, and the second gate driver 220b applies the gate signal to the pixels of the right half. Thus, the gate signal is quickly applied to the pixels of the high-resolution display panel to drive the pixels.

[0063] Reference Figure 4 The first gate driver 330a is connected to the first group of gate lines to sequentially provide gate signals to the first group of gate lines. The second gate driver 330b is connected to the second group of gate lines to sequentially provide gate signals to the second group of gate lines.

[0064] The first group of gate lines may be odd-numbered gate lines (GL1, GL3 ... GLn-1). The second group of gate lines may be even-numbered gate lines (GL2, GL4 ... GLn). In this case, the start signal Vst may be applied to the first gate driver 330a and the second gate driver 330b according to a predetermined time difference. Therefore, there may be a predetermined time difference in the gate signal output timing and the carry signal output timing of the first gate driver 330a and the second gate driver 330b. For example, after the first gate signal is applied to the first gate line GL1 from the first gate driver 330a, the second gate signal may be provided to the second gate line GL2 from the second gate driver 330b after approximately one horizontal period. According to the design structure of the first gate driver 330a and the second gate driver 330b arranged on the left and right sides of the display panel, a margin is ensured in the arrangement space, so that the layout of the gate driver can be changed in various forms.

[0065] Figure 5 is a plan view in which a gate driver is disposed on the display panel 100 according to an exemplary embodiment.

[0066] Reference Figure 5 The data driver 200 may be disposed on the upper plane of the display panel 100 and transmit the data signal to the pixel region 120 via the data line 211. The first gate driver 110a and the second gate driver 110b (see Figure 1 ) may be disposed on the left and right sides of the non-display area surrounding the pixel area 120. Figure 5 As shown, the display area may include a plurality of pixel rows and have a periphery including a curved section and a straight section, and the non-display area may surround the display area and have a periphery including a curved section and a straight section. In addition, the gate blocks corresponding to the straight sections of the periphery of the display area may be arranged in a straight line form, and the gate blocks corresponding to the curved sections of the periphery of the display area may be in an atypical form.

[0067] like Figure 2As described in , the display panel 100 using heterogeneous transistors such as low temperature polymer semiconductor (LTPS) transistors and oxide semiconductor transistors may have a gate driver 110 as a complex to drive transistors with different characteristics. The more complex the structure of the gate driver, the more the area occupied by the gate driver should be increased, such as Figure 2 As described in , a gate driver having five stages may be provided for each pixel row. However, it may be difficult to provide a gate driver at a corner of the display panel 100.

[0068] In the corner of the pixel area 120, the curved area has the smallest radius of curvature to ensure the pixel area as wide as possible. In contrast, in order to minimize the non-display area, in the corner of the display panel 100, the radius of curvature of the curved area of ​​the corner needs to be formed to be larger than the radius of curvature of the pixel area 120. The non-display area in the corner may be relatively narrow. The non-display area of ​​the corner of the display panel 100 is narrower than other display areas, so that it can be limited to set the gate driver 110.

[0069] Similar to Figure 1 , not only the gate driver 110 but also the low potential power line 510 needs to be arranged in the non-display area of ​​the display panel 100. Therefore, the non-display area of ​​the corner of the display panel 100 can be a narrower space, so that in order to install the gate driver, the pixel area 120 needs to be reduced. In the non-display area of ​​the four corners of the display panel 100, there will be the problem of narrow space as described above. The gate driver 110 is arranged on the left and right sides of the pixel area 120 so as to correspond to the pixels one by one. For this purpose, it can be as follows Figure 2 The gate driver 110 is arranged as shown so that five stages are arranged in one row. In a non-display area at a corner of the display panel 100, the stages of the gate driver 110 may be separately arranged.

[0070] Figure 6 is a plan view illustrating area A, where area A is about the area set at Figure 5 The gate driver 110 is disposed in a non-display area at a corner of the display panel 100 .

[0071] Reference Figure 6 , the periphery of the pixel region 120 is indicated by a dotted line, and the periphery of the display panel 100 is indicated by a solid line. The pixels are arranged in the pixel region 120, and the gate driver 110 and the low potential power supply line 510 are arranged in a non-display area between the periphery of the pixel region 120 and the periphery of the display panel 100. Figure 2Similarly, the gate driver 110 includes a plurality of stages such as a first scan driving circuit SP, a second scan driving circuit SN, a light emitting driving circuit EM, a reset driving circuit DVini, and a switch driving circuit SW. In the case of the n-2 th pixel row P(n-2) and the n-1 th pixel row P(n-1) of the pixel region adjacent to the corner of the display panel 100, the space for disposing all the stages of the gate driver 110 may be insufficient in the non-display region.

[0072] Reference Figure 6 , the low potential power line 510 is arranged at the periphery of the gate driver 110 to surround the pixel area 120. At this time, due to the characteristics of the low potential power line 510, it is sensitive to the voltage drop caused by the resistance, which becomes a reason to arrange the low potential power line 510 in a short range to ensure the screen quality of the organic light emitting diode located in the pixel area 120. The low potential power line 510 is arranged in a straight line as much as possible to minimize the distance of the low resistance, and is also arranged at the corner of the display panel 100 in the same way. If the positioning of the low potential power line 510 and the positioning of the gate driver 110 are connected according to the shape of the gate driver of the related art, the level of the gate driver 110 corresponding to the n-2 pixel row P(n-2) and the n-1 pixel row P(n-1) and the low potential power line 510 may interfere with each other at the outer corner of the display panel 100.

[0073] Despite Figure 6 , only the upper right corner is illustrated, but the same problem may also be caused at the upper left corner, the lower right corner, and the lower left corner.

[0074] In order to avoid interference between the gate driver 110 and the low potential power line 510, the inventors consider separately setting the stages of the gate driver 110. For example, the reset driving circuit DVini and the first scanning driving circuit SP may not be arranged according to the standardized linear arrangement of the related art, but the gate blocks may be arranged according to an atypical arrangement such as "┘", "└" instead of a linear form.

[0075] Reference Figure 6, in the case of the gate driver 110 corresponding to the n-2 th pixel row P(n-2), a second scan drive circuit SN(n-2), a light emitting drive circuit EM(n-2) and a switch drive circuit SW(n-2) are provided. In addition, the reset drive circuit DVini(n-2) provided on one side of the light emitting drive circuit EM(n-2) and the switch drive circuit SW(n-2) may be provided above the switch drive circuit SW(n-2). When the first scan drive circuit SP(n-2) is provided above the reset drive circuit DVini(n-2), the positioning of the reset drive circuit DVini(n-2) and the first scan drive circuit SP(n-2) corresponding to the n-2 th pixel row P(n-2) of the related art is changed. Therefore, a free space may be ensured on one side of the light emitting drive circuit EM(n-2) and the switch drive circuit SW(n-2). In addition, there is an empty space above the switch driving circuit SW(n-2), so that the reset driving circuit DVini(n-2) and the first scanning driving circuit SP(n-2) can be disposed.

[0076] Next, in the gate driver 110 corresponding to the n-1th pixel row P(n-1), the second scan drive circuit SN(n-1), the light emitting drive circuit EM(n-1) and the reset drive circuit DVini(n-1) are arranged in the order closer to the pixel row P(n-1). In the case of the gate driver corresponding to the n-1th pixel row P(n-1), the first scan drive circuit SP(n-1) can be arranged above the reset drive circuit DVini(n-1), so that one side of the reset drive circuit DVini(n-1) can be an empty space. The first scan drive circuit SP(n-1) corresponding to the n-1th pixel row P(n-1) can be arranged on one side of the light emitting drive circuit EM(n-2) and the switch drive circuit SW(n-2) corresponding to the n-2th pixel row P(n-2). By moving the positions of the first scanning drive circuit SP(n-2) and the reset drive circuit DVini(n-2) corresponding to the n-2th pixel row P(n-2), consider preparing space for setting the first scanning drive circuit SP(n-1) corresponding to the n-1th pixel row P(n-1).

[0077] In the gate driver 110 corresponding to the nth pixel row P(n) and the n+1th pixel row P(n+1), Figure 2 The positioning is the same, and the second scanning driving circuit SN, the light emitting driving circuit EM, the switch driving circuit SW, the reset driving circuit DVini and the first scanning driving circuit SP are arranged in the order closer to each pixel row.

[0078] In addition, the gate driver 110 may be provided with various structures, but there may be a position reference that needs to be maintained. The reset drive circuit DVini and the switch drive circuit SW may be provided so that the switch drive circuit SW is closer to the pixel row P than the reset drive circuit DVini, or the output line passes through the switch drive circuit. Figure 2 It is described in that the switch driving circuit SW determines whether the driving transistor reset signal of the reset driving circuit DVini is input, so that the output signal of the reset driving circuit DVini can be necessarily connected to the pixel row P via the switch driving circuit SW.

[0079] Reference Figure 6 , the positions of the first scan drive circuit SP(n-2) and the reset drive circuit DVini(n-2) corresponding to the n-2th pixel row P(n-2) are moved, and the position of the first scan drive circuit SP(n-1) corresponding to the n-1th pixel row P(n-1) is moved. Therefore, a vacant space can be ensured at the corner of the display panel 100 corresponding to the n-2th pixel row P(n-2) and the n-1th pixel row P(n-1). The low potential power line 510 can be set in the ensured vacant space at the shortest distance that does not overlap with the gate driver 110.

[0080] The length of the gate block corresponding to the n-2th pixel row P(n-2) may be close to half the length of the gate block corresponding to the n+1th pixel row P(n+1). The length of the gate block may be regarded as the length extending from the periphery of the pixel area 120 to the periphery of the non-display area. The gate block in a straight line form may have a first length extending from the periphery of the straight section of the display area to the periphery of the non-display area, and the gate block in an atypical form may have a second length extending from the periphery of the curved section of the display area to the periphery of the non-display area. The first length may be greater than the second length.

[0081] Reference Figure 6 The low potential power line 510 extends in the horizontal direction and then turns near the first scan driving circuit SP(n-2) corresponding to the n-2 th pixel row P(n-2) to extend to form a diagonal line closest to the gate driver 110. The low potential power line 510 extends in the diagonal direction at the corner area of ​​the display panel 100 to extend in the vertical direction near the first scan driving circuit SP(n) corresponding to the n th pixel row P(n) to the lower corner of the display panel 100.

[0082] Figure 7 is a plan view illustrating another example of area A, wherein area A is about a device set in Figure 5 The gate driver 110 is disposed in a non-display area at a corner of the display panel 100 .

[0083] Reference Figure 7 , similar to Figure 6 , the periphery of the pixel area 120 is indicated by a dotted line, and the periphery of the display panel 100 is indicated by a solid line. The pixels are arranged in the pixel area 120, and the gate driver 110 and the low potential power supply line 510 are arranged in a non-display area between the periphery of the pixel area 120 and the periphery of the display panel 100. The gate driver 110 includes a plurality of stages such as a first scan drive circuit SP, a second scan drive circuit SN, a light emitting drive circuit EM, a reset drive circuit DVini, and a switch drive circuit SW. In the case of the n-2 pixel row P(n-2) and the n-1 pixel row P(n-1) of the pixel area 120 adjacent to the corner of the display panel 100, the space for setting all the stages of the gate driver 110 may be insufficient in the non-display area.

[0084] Reference Figure 7 , the low potential power line 510 is arranged at the periphery of the gate driver 110 to surround the pixel area 120. At this time, due to the characteristics of the low potential power line 510, it is sensitive to the voltage drop caused by the resistance, which becomes a reason for setting the low potential power line 510 in a shorter range to ensure the screen quality of the organic light emitting diode located in the pixel area 120. The low potential power line 510 is arranged in a straight line as much as possible to minimize the distance of the low resistance, and is also arranged at the corner of the display panel 100 in the same way. If the positioning of the low potential power line 510 and the positioning of the gate driver 110 are connected according to the shape of the gate driver of the related art, the level of the gate driver 110 corresponding to the n-2 pixel row P(n-2) and the n-1 pixel row P(n-1) and the low potential power line 510 may interfere with each other at the outer corner of the display panel 100.

[0085] Despite Figure 7 , only the upper right corner is illustrated, but the same problem may also be caused at the upper left corner, the lower right corner, and the lower left corner.

[0086] In order to avoid interference between the gate driver 110 and the low potential power line 510, the inventors consider separately setting the stages of the gate driver 110. For example, the reset driving circuit DVini and the first scanning driving circuit SP may not be arranged according to the standardized linear arrangement of the related art, but the gate blocks may be arranged according to an atypical arrangement such as "┘", "└" or "├" instead of a linear form.

[0087] Reference Figure 7, in the case of the gate driver 110 corresponding to the n-2th pixel row P(n-2), the light emitting drive circuit EM(n-2) and the switch drive circuit SW(n-2) are arranged above the second scan drive circuit SN(n-2). In addition, the reset drive circuit DVini(n-2) and the first scan drive circuit SP(n-2) are arranged on one side of the light emitting drive circuit EM(n-2) and the switch drive circuit SW(n-2). The first scan drive circuit SP(n-2) is arranged on the upper side of the reset drive circuit DVini(n-2) to arrange as many levels corresponding to the pixel row P(n-2) as possible in the upper area where the gate driver is not arranged according to the related art. That is, in a straight-form gate block, the first scan drive circuit can be arranged at the outermost periphery. The light emitting driving circuit EM(n-2), the switch driving circuit SW(n-2), the reset driving circuit DVini(n-2) and the first scanning driving circuit SP(n-2) are arranged above the second scanning driving circuit SN(n-2) to ensure a spare space on one side of the second scanning driving circuit SN(n-2).

[0088] Next, in the gate driver 110 corresponding to the n-1th pixel row P(n-1), the second scanning drive circuit SN(n-1), the light emitting drive circuit EM(n-1) and the switch drive circuit SW(n-1) are arranged in the order closer to the pixel row P(n-1). In the case of the gate driver corresponding to the n-1th pixel row P(n-1), the reset drive circuit DVini(n-1) is arranged above the switch drive circuit SW(n-1), and the first scanning drive circuit SP(n-1) is arranged on one side of the switch drive circuit SW(n-1) or the reset drive circuit DVini(n-1). Therefore, one side of the reset drive circuit DVini(n-1) can be a vacant space. The reset driving circuit DVini(n-1) corresponding to the n-1th pixel row P(n-1) can be set on one side of the second scanning driving circuit SN(n-2) corresponding to the n-2th pixel row P(n-2) and on the lower surface of the reset driving circuit DVini(n-2) corresponding to the n-2th pixel row P(n-2). By changing the positions of the light emitting driving circuit EM(n-2), the switch driving circuit SW(n-2), the reset driving circuit DVini(n-2) and the first scanning driving circuit SP(n-2) corresponding to the n-2th pixel row P(n-2), it is considered to prepare a space for setting the reset driving circuit DVini(n-1) corresponding to the n-1th pixel row P(n-1).

[0089] Reference Figure 7, in the gate driver 110 corresponding to the nth pixel row P(n), the second scan drive circuit SN(n), the light emitting drive circuit EM(n) and the reset drive circuit DVini(n) are arranged in the order closer to the pixel row P(n). In the case of the gate driver corresponding to the nth pixel row P(n), the first scan drive circuit SP(n) can be arranged above the reset drive circuit DVini(n), so that one side of the reset drive circuit DVini(n) can be a vacant space. That is, in the atypical form of the gate block, the reset drive circuit can be arranged at the outermost periphery. The first scan drive circuit SP(n) corresponding to the nth pixel row P(n) can be arranged on one side of the light emitting drive circuit EM(n-1) and the switch drive circuit SW(n-1) corresponding to the n-1th pixel row P(n-1). By moving the positions of the first scanning drive circuit SP(n-1) and the reset drive circuit DVini(n-1) corresponding to the n-1th pixel row P(n-1), consider preparing a space for setting the first scanning drive circuit SP(n) corresponding to the nth pixel row P(n).

[0090] In the gate driver 110 corresponding to the n+1-th pixel row P(n+1), Figure 2 The positioning is the same, and the second scanning driving circuit SN, the light emitting driving circuit EM, the switch driving circuit SW, the reset driving circuit DVini and the first scanning driving circuit SP are arranged in the order closer to each pixel row.

[0091] Reference Figure 7 , the positions of the light emitting drive circuit EM(n-2), the switch drive circuit SW(n-2), the first scan drive circuit SP(n-2) and the reset drive circuit DVini(n-2) corresponding to the n-2 pixel row P(n-2) are moved. In addition, the positions of the reset drive circuit DVini(n-1) and the first scan drive circuit SP(n-1) corresponding to the n-1 pixel row P(n-1) are moved. Therefore, a vacant space can be ensured at the corners of the display panel 100 corresponding to the n-2 pixel row P(n-2), the n-1 pixel row P(n-1) and the n pixel row P(n). The low potential power line 510 can be set in the ensured vacant space at the shortest distance that does not overlap with the gate driver 110.

[0092] The length of the gate block corresponding to the n-2th pixel row P(n-2) may be close to half the length of the gate block of the n+1th pixel row P(n+1). The length of the gate block may be considered as the length extending from the periphery of the pixel region 120 to the periphery of the non-display region.

[0093] Reference Figure 7, the low potential power line 510 extends in the horizontal direction and then turns near the first scan driving circuit SP(n-2) corresponding to the n-2 th pixel row P(n-2) to extend to form an oblique line closest to the gate driver 110. The low potential power line 510 extends in the oblique direction in the corner area of ​​the display panel 100 (i.e., the curved section of the non-display area) to extend in the vertical direction near the first scan driving circuit SP(n+1) corresponding to the n+1 th pixel row P(n+1) to the directly lower corner of the display panel 100 (i.e., the directly lower curved section of the non-display area).

[0094] The display apparatus according to the exemplary embodiment of the present invention includes a liquid crystal display device (LCD), a field luminescence display device (FED), an organic light emitting display device (OLED), and a quantum dot display device.

[0095] In addition, a display device according to an exemplary embodiment of the present invention may also include an assembly electronic device or assembly device (or assembly device) as a finished product or final product, which finished product or final product includes an LCM, OLED module or QD module such as a laptop computer, a television or a computer monitor; an automobile display or an instrument display of other types of vehicles; or a mobile electronic device including a smart phone or an electronic tablet.

[0096] The features, structures, effects, etc. described in the foregoing examples of the present application are included in at least one example of the present application, and are not necessarily limited to one example. Moreover, the features, structures, effects, etc. shown in at least one example of the present invention may be combined or modified by a person of ordinary skill in the art to implement other examples. Therefore, the combinations and modifications of the present invention are interpreted as being included within the scope of the present application.

[0097] The foregoing application is not limited to the foregoing examples and drawings. It will be clear to those skilled in the art that various modifications and variations can be made without departing from the scope and spirit of the application. The scope of the application is defined by the appended claims rather than the specific description, and should be interpreted as the meaning and scope of the claims and all changes and modifications obtained from their equivalents fall within the scope of the application.

[0098] Exemplary embodiments of the present invention may also be described as follows:

[0099] According to one aspect of the present invention, a display device is provided. The display device includes: a display area, the display area includes a plurality of pixel rows and has a periphery including a curved section and a straight section; a non-display area, the non-display area surrounds the display area and has a periphery including a curved section and a straight section; a gate driver, the gate driver is composed of a plurality of gate blocks corresponding to the pixel rows and is arranged in the non-display area; and a low potential power line, the low potential power line is arranged between the gate driver and the periphery of the non-display area, wherein the gate block includes a plurality of stages.

[0100] The low potential power line and the gate driver may not overlap.

[0101] The gate blocks corresponding to the straight sections of the periphery of the display area may be provided in a straight line form, and the gate blocks corresponding to the curved sections of the periphery of the display area may be in an atypical form.

[0102] The plurality of stages may include a first scan driving circuit, a second scan driving circuit, a light emitting driving circuit, and a reset driving circuit.

[0103] The plurality of stages may further include a switch driving circuit.

[0104] The straight-line form gate block may have a first length extending from the periphery of the straight section of the display area to the periphery of the non-display area, and the atypical form gate block may have a second length extending from the periphery of the curved section of the display area to the periphery of the non-display area.

[0105] The first length may be greater than the second length.

[0106] According to another aspect of the present invention, a display device is provided. The display device includes: a display area, the display area includes a plurality of pixel rows and has a periphery including a curved section and a straight section; a non-display area, the non-display area surrounds the display area and has a periphery including a curved section and a straight section; and a gate driver, the gate driver is composed of a plurality of gate blocks corresponding to the pixel rows and is arranged in the non-display area, wherein the gate blocks include a plurality of stages, wherein the plurality of stages include a first scan drive circuit, a second scan drive circuit, a light emitting drive circuit, a switch drive circuit, and a reset drive circuit.

[0107] The display device may further include a low potential power line disposed between the gate driver and the periphery of the non-display area. The low potential power line and the gate driver may not overlap.

[0108] The gate blocks corresponding to the straight sections of the periphery of the display area may be provided in a straight line form, and the gate blocks corresponding to the curved sections of the periphery of the display area may be in an atypical form.

[0109] In the atypical form of the gate block, the reset driving circuit may be provided at the outermost periphery.

[0110] In the straight form of the gate block, the first scan driving circuit may be disposed at an outermost periphery.

[0111] The switch driving circuit may be arranged closer to the display area than the reset driving circuit.

[0112] The atypical form of gate block may include an nth gate block and an n+1th gate block, wherein a first scan driving circuit of the n+1th gate block may be disposed on one side of a light emitting driving circuit of the nth gate block, wherein n is a natural number.

[0113] In the atypical form of the gate block, the first scan driving circuit may be disposed above the reset driving circuit.

[0114] Although the exemplary embodiments of the present invention have been described in detail with reference to the accompanying drawings, the present invention is not limited thereto, and the present invention can be implemented in many different forms without departing from the technical concept of the present invention. Therefore, the exemplary embodiments of the present invention are provided only for the purpose of illustration and are not intended to limit the technical concept of the present invention. The scope of the technical concept of the present invention is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are merely illustrative in all aspects and do not limit the present invention. The scope of protection of the present invention should be interpreted based on the attached claims, and all technical concepts within the equivalent scope thereof should be interpreted as falling within the scope of the present invention.

Claims

1. A display device, comprising: a display area including a plurality of pixel rows and having a periphery including curved segments and straight segments; a non-display area surrounding the display area and having a periphery including a curved section and a straight section; a gate driver, the gate driver being composed of a plurality of gate blocks corresponding to the pixel rows and being disposed in the non-display area; as well as a low potential power line, the low potential power line being arranged between the gate driver and the periphery of the non-display area, wherein the gate block includes a plurality of stages, wherein the plurality of stages include a first scanning driving circuit, a second scanning driving circuit, a light emitting driving circuit and a reset driving circuit, The plurality of pixel rows include an n-2th pixel row, an nth pixel row and an n+1th pixel row, wherein n is a natural number greater than or equal to 2, The low potential power line extends in a horizontal direction and then turns near the first scan driving circuit corresponding to the n-2 th pixel row to extend to form an oblique line closest to the gate driver. 2 . The display device according to claim 1 , wherein the low potential power supply line and the gate driver do not overlap. 3 . The display device according to claim 1 , wherein the gate blocks corresponding to the straight sections of the periphery of the display area are arranged in a straight line form, and the gate blocks corresponding to the curved sections of the periphery of the display area are in an atypical form. The display device according to claim 1 , wherein the plurality of stages further include a switch driving circuit.

5. The display device according to claim 3, wherein the gate block in the form of a straight line has a first length extending from the periphery of the straight section of the display area to the periphery of the non-display area, The atypical-form gate block has a second length extending from the periphery of the curved section of the display area to the periphery of the non-display area. The display device according to claim 5 , wherein the first length is greater than the second length. 7 . The display device according to claim 1 , wherein the gate driver comprises a first gate driver disposed in the one side non-display area and a second gate driver disposed in the other side non-display area. 8 . The display device of claim 7 , wherein the first gate driver and the second gate driver are simultaneously applied with a start signal to simultaneously output gate signals. 9 . The display device of claim 7 , wherein the first gate driver and the second gate driver are applied with a start signal at a predetermined time difference to output gate signals at a predetermined time difference.

10. The display device according to claim 3, wherein the atypical form is a "┘", "└" or "├" form.

11. A display device according to claim 1, wherein the low-potential power line extends in the curved section of the non-display area along an oblique direction so as to extend in the vertical direction to the curved section directly below the non-display area near the first scanning drive circuit corresponding to the n+1th pixel row.

12. A display device comprising: a display area including a plurality of pixel rows and having a periphery including curved segments and straight segments; a non-display area surrounding the display area and having a periphery including a curved section and a straight section; as well as a gate driver composed of a plurality of gate blocks corresponding to the pixel rows and disposed in the non-display area, and a low potential power line, the low potential power line being arranged between the gate driver and the periphery of the non-display area, wherein the gate block comprises a plurality of stages, wherein the plurality of stages include a first scan driving circuit, a second scan driving circuit, a light emitting driving circuit, a switch driving circuit and a reset driving circuit, The plurality of pixel rows include an n-2th pixel row, an nth pixel row and an n+1th pixel row, wherein n is a natural number greater than or equal to 2, The low potential power line extends in a horizontal direction and then turns near the first scan driving circuit corresponding to the n-2 th pixel row to extend to form an oblique line closest to the gate driver. 13 . The display device according to claim 12 , wherein the low potential power supply line and the gate driver do not overlap. 14 . The display device according to claim 12 , wherein the gate blocks corresponding to the straight sections of the periphery of the display area are arranged in a straight line form, and the gate blocks corresponding to the curved sections of the periphery of the display area are in an atypical form. 15 . The display device according to claim 14 , wherein in the atypical form of the gate block, the reset drive circuit is provided at an outermost periphery. 16 . The display device according to claim 14 , wherein in the gate block in the linear form, the first scan driving circuit is disposed at an outermost periphery. 17 . The display device according to claim 14 , wherein the switch driving circuit is provided closer to the display area than the reset driving circuit.

18. The display device according to claim 14, wherein the atypical form of gate block comprises an nth gate block and an n+1th gate block, wherein a first scanning driving circuit of the n+1th gate block is arranged on one side of a light emitting driving circuit of the nth gate block, wherein n is a natural number.

19. The display device according to claim 14, wherein in the atypical form of the gate block, the first scan driving circuit is disposed above the reset driving circuit.

20. The display device according to claim 14, wherein the atypical form is "┘", "└" or form.

21. A display device according to claim 12, wherein the low-potential power line extends in the curved section of the non-display area along an oblique direction so as to extend in the vertical direction to the curved section directly below the non-display area near the first scanning drive circuit corresponding to the n+1th pixel row.

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