Display device

Abstract

A display device includes a driving voltage line and a plurality of data lines extending in a first direction, a first driving transistor electrically connected to the driving voltage line, a first switching transistor electrically connected to the first driving transistor and including a first switching semiconductor layer extending in a second direction crossing the first direction and a first switching gate electrode overlapping a channel region of the first switching semiconductor layer, and a first storage capacitor electrically connected to the first driving transistor and the first switching transistor, wherein the first switching semiconductor layer is electrically connected to a first data line, the first switching semiconductor layer crosses a second data line between the channel region and the first data line, and an intersection region of an edge of the first switching semiconductor layer and an edge of the second data line overlaps a first protection layer.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2020-0177819, filed on December 17, 2020, and all benefits derived therefrom, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] One or more embodiments relate to a display device. Background Technology

[0003] With the rapid development of the display field that visually represents a wide variety of electrical signal information, various display devices with excellent characteristics such as being thinner and lighter and having low power consumption have been introduced.

[0004] Display devices may include liquid crystal display devices that do not emit light spontaneously and use light from a backlight unit, or light-emitting display devices that include light-emitting display elements. Light-emitting display devices may include display elements comprising an emitting layer. Summary of the Invention

[0005] One or more embodiments include a display device, and more specifically, a structure for a light-emitting display device.

[0006] Other features will be set forth in part in the description which follows and will be apparent in part from the description, or may be learned by practicing the embodiments presented in this invention.

[0007] In an embodiment of the present invention, a display device includes: a driving voltage line extending in a first direction; a plurality of data lines extending in the first direction; a first driving transistor electrically connected to the driving voltage line; a first switching transistor electrically connected to the first driving transistor and including a first switching semiconductor layer extending in a second direction intersecting the first direction and a first switching gate electrode overlapping a channel region of the first switching semiconductor layer; and a first storage capacitor electrically connected to the first driving transistor and the first switching transistor, wherein the first switching semiconductor layer is electrically connected to a first data line among the plurality of data lines, the first switching semiconductor layer intersects with a second data line disposed between the channel region and the first data line, and the intersection region of the edge of the first switching semiconductor layer and the edge of the second data line overlaps with a first protective layer.

[0008] In an embodiment, the first protective layer may include a first sublayer comprising an insulating material.

[0009] In an embodiment, the first protective layer may be further included on the first sublayer and include a second sublayer of metallic material.

[0010] In one embodiment, at least one of the first switching gate electrode of the first switching transistor, the first driving gate electrode of the first driving transistor, and the first capacitor electrode of the first storage capacitor is made of the same metal material as the second sublayer.

[0011] In an embodiment, the display device may further include a second driving transistor electrically connected to a driving voltage line and a second switching transistor electrically connected to the second driving transistor, wherein the second data line may be electrically connected to the second switching transistor.

[0012] In an embodiment, the first protective layer may have an isolated shape.

[0013] In an embodiment, the first driving transistor may include a first driving semiconductor layer and a first driving gate electrode that overlaps with a channel region of the first driving semiconductor layer, wherein the first driving semiconductor layer may overlap and intersect with one of the plurality of electrodes of the first storage capacitor, and the intersection region between the edge of the first driving semiconductor layer and the edge of the one of the plurality of electrodes of the first storage capacitor may overlap with a second protective layer.

[0014] In an embodiment, the second protective layer may include a first sub-layer containing an insulating material, and the material of the gate insulating layer between the channel region of the first driving semiconductor layer and the first driving gate electrode is the same as the insulating material of the first sub-layer.

[0015] In an embodiment, the second protective layer may be further included as a second sublayer on top of the first sublayer.

[0016] In one embodiment, the second sublayer may be integrated with the first driving gate electrode.

[0017] In an embodiment of the present invention, a display device includes: a driving voltage line extending in a first direction; a plurality of data lines extending in the first direction; a first driving transistor electrically connected to the driving voltage line and including a first driving semiconductor layer extending in a second direction intersecting the first direction and a first driving gate electrode overlapping a channel region of the first driving semiconductor layer; a first switching transistor electrically connected to the first driving transistor; and a first storage capacitor electrically connected to the first driving transistor and the first switching transistor, wherein the first driving semiconductor layer intersects at least one of the driving voltage line and the second capacitor electrode of the first storage capacitor, and the intersection region between the edge of the first driving semiconductor layer and the edge of the at least one overlaps with a protective layer.

[0018] In one embodiment, a portion of the first driving semiconductor layer may overlap and intersect with the driving voltage line, and the protective layer may include a first protective layer that overlaps with the intersection between the edge of the driving voltage line and the edge of that portion of the first driving semiconductor layer.

[0019] In an embodiment, the first protective layer may have an isolated shape.

[0020] In an embodiment, the first protective layer may include a first sublayer comprising an insulating material.

[0021] In an embodiment, the first protective layer may further include a second sublayer disposed on the first sublayer and comprising the same material as one of the first switching gate electrode of the first switching transistor, the first driving gate electrode of the first driving transistor, and the first capacitor electrode of the first storage capacitor.

[0022] In an embodiment, a portion of the first driving semiconductor layer may overlap and intersect with the second capacitor electrode of the first storage capacitor, and the protective layer may include a second protective layer that overlaps with the intersection area between the edge of the portion of the first driving semiconductor layer and the edge of the second capacitor electrode of the first storage capacitor.

[0023] In an embodiment, the second protective layer may include a first sub-layer containing an insulating material, and the material of the gate insulating layer between the channel region of the first driving semiconductor layer and the first driving gate electrode is the same as the insulating material of the first sub-layer.

[0024] In an embodiment, the second protective layer may be further included as a second sublayer on top of the first sublayer.

[0025] In one embodiment, the second sublayer may be integrated with the first driving gate electrode.

[0026] In an embodiment, the first switching transistor may include a first switching semiconductor layer extending in a second direction. The first switching semiconductor layer may be electrically connected to a first data line among a plurality of data lines and may intersect with a second data line disposed between a channel region of the first switching semiconductor layer and the first data line. The intersection region between the edge of the first switching semiconductor layer and the edge of the second data line may overlap with a third protective layer.

[0027] In an embodiment, the third protective layer may have an isolated shape.

[0028] In one embodiment, the first switching transistor may include a first switching semiconductor layer extending in a second direction and electrically connected to a first data line among a plurality of data lines, and the first switching semiconductor layer may be connected to a connector that intersects with a second data line disposed between the first data line and the first switching semiconductor layer.

[0029] In an embodiment of the present invention, a display device includes: a driving voltage line extending in a first direction; a plurality of data lines extending in the first direction; a first driving transistor electrically connected to the driving voltage line; a first switching transistor electrically connected to the first driving transistor and including a first switching semiconductor layer extending in a second direction intersecting the first direction and a first switching gate electrode overlapping a channel region of the first switching semiconductor layer; and a first storage capacitor electrically connected to the first driving transistor and the first switching transistor, wherein the first switching semiconductor layer is electrically connected to a first data line among the plurality of data lines and is electrically connected to the first data line via a connector intersecting a second data line disposed between the first data line and the first switching semiconductor layer.

[0030] These and / or other features will become apparent and more readily understood from the following description of the embodiments, the accompanying drawings, and the claims. Attached Figure Description

[0031] The above and other features and advantages of specific embodiments of the invention will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0032] Figure 1A This is a perspective view of an embodiment of the display device;

[0033] Figure 1B This is a cross-sectional view of an embodiment of the display device taken along line II-II';

[0034] Figure 1C yes Figure 1B A view of each section of the color-converting transmission layer;

[0035] Figure 2 This is an equivalent circuit diagram of an embodiment of a light-emitting diode included in the light-emitting panel of a display device and a pixel circuit electrically connected to the light-emitting diode;

[0036] Figure 3A This is a plan view of an embodiment of a pixel circuit, and Figure 3B yes Figure 3A A magnified view of a portion;

[0037] Figure 4A and Figure 4B It is along Figure 3A A cross-sectional view of an embodiment of the pixel circuit cut by line IVa-IVa';

[0038] Figure 4C It is along Figure 3A A cross-sectional view of an embodiment of the pixel circuit cut by line IVc-IVc';

[0039] Figure 5This is a cross-sectional view of a comparative example of a semiconductor layer without a protective layer and a bottom conductive layer;

[0040] Figures 6A to 6C This is a plan view of another embodiment of a pixel circuit that includes a semiconductor layer, a bottom conductive layer, and a protective layer;

[0041] Figure 7 This is a plan view of an embodiment of the pixel circuit of the light-emitting panel;

[0042] Figure 8 It is connected to Figure 7 A plan view of an embodiment of a pixel circuit light-emitting diode;

[0043] Figure 9 , Figure 10 and Figure 11 It shows the formation Figure 7 A plan view of an embodiment of the pixel circuit process shown;

[0044] Figure 12A and Figure 12B They are Figure 10 Enlarged plan view of the embodiments of regions XIIa and XIIb;

[0045] Figure 13A It is along Figure 9 A cross-sectional view of an embodiment of the pixel circuit intercepted by lines A-A' and B-B';

[0046] Figure 13B and Figure 13C Is with Figure 13A A cross-sectional view of the pixel corresponding to the process after the process;

[0047] Figure 13D It is set in Figure 13C A cross-sectional view of the organic light-emitting diodes on the pixel circuit;

[0048] Figure 14 This is a plan view of another embodiment of the pixel circuitry of the light-emitting panel;

[0049] Figure 15 It is connected to Figure 14 A plan view of another embodiment of the light-emitting diode of the pixel circuit;

[0050] Figure 16 yes Figure 14 A cross-sectional view of region XVI;

[0051] Figure 17 It is along Figure 16 A cross-sectional view of another embodiment of the region XVI intercepted by line C-C';

[0052] Figure 18 yes Figure 14 A cross-sectional view of another embodiment of region XVIII; and

[0053] Figure 19 It is along Figure 18 A cross-sectional view of another embodiment of region XVIII intercepted by line D-D'. Detailed Implementation

[0054] Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings, in which the same reference numerals consistently refer to the same elements. In this respect, embodiments may take different forms and should not be construed as limited to the description set forth herein. Therefore, the embodiments are described below solely by way of the accompanying drawings to illustrate the features described. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Throughout this disclosure, the expression “at least one of a, b, and c” indicates only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0055] Because this disclosure allows for various modifications and numerous embodiments, specific embodiments will be shown in the accompanying drawings and described in the written description. The effects and features of this disclosure, as well as methods for implementing them, will be illustrated by referring to the embodiments described in detail below with reference to the accompanying drawings. However, this disclosure is not limited to the following embodiments and can be embodied in various forms.

[0056] In the following description, embodiments will be referenced to the accompanying drawings, wherein the same reference numerals refer to the same elements throughout and repeated descriptions thereof are omitted.

[0057] Although terms such as "first" and "second" may be used to describe various components, such components should not be limited to these terms. The terms are used to distinguish one component from another.

[0058] The singular forms “a” and “the” used in this article are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0059] It will be understood that the terms “comprising” and / or “including” as used herein specify the presence of the stated features or components, but do not preclude the addition of one or more other features or components.

[0060] It will be further understood that when a layer, region, or component is referred to as being "on" another layer, region, or component, it can be directly or indirectly on that other layer, region, or component. That is, for example, there can be intermediate layers, regions, or components.

[0061] For ease of illustration, the dimensions of elements in the accompanying drawings may be exaggerated or reduced. For example, this disclosure is not limited thereto because the dimensions and thicknesses of elements in the drawings are arbitrarily shown for ease of illustration.

[0062] When embodiments can be implemented differently, a particular process sequence can be performed in a different order than that described. For example, two consecutively described processes can be performed substantially simultaneously or in the reverse order of their description.

[0063] It will be understood that when a layer, region, or component is referred to as being "connected" to another layer, region, or component, it can be "directly connected" to that other layer, region, or component, or it can be "indirectly connected" to that other layer, region, or component, with other layers, regions, or components inserted between them. For example, it will be understood that when a layer, region, or component is referred to as being "electrically connected" to another layer, region, or component, it can be "directly electrically connected" to that other layer, region, or component, or it can be "indirectly electrically connected" to that other layer, region, or component, with other layers, regions, or components inserted between them.

[0064] Figure 1A This is a perspective view of an embodiment of a display device (DV). Figure 1B This is a cross-sectional view of an embodiment of the display device DV, taken along line II-II', and Figure 1C yes Figure 1B A view of an embodiment of each part of the color conversion transmission layer.

[0065] refer to Figure 1A A display device (DV) may include a display area (DA) and a non-display area (NDA) outside the display area (DA). The display device (DV) can display an image by means of an array of multiple pixels arranged in two dimensions in the display area (DA).

[0066] Each pixel of the display device (DV) is an area capable of emitting light of a preset color. The display device (DV) can display images by emitting light from the pixels. In an embodiment, each pixel can emit red, green, or blue light. However, the invention is not limited to this, and each pixel can emit various other colors of light.

[0067] The non-display area NDA is an area that does not provide an image and can completely surround the display area DA. Drivers or main power lines can be arranged in the non-display area NDA, and these drivers or main power lines can provide electrical signals or power to the pixel circuitry. The non-display area NDA may include pads that can be electrically connected as electronic components or printed circuit boards.

[0068] like Figure 1AAs shown, the display area DA can have a polygonal shape, including quadrilaterals. In embodiments, the display area DA can have a rectangular shape with a horizontal length greater than its vertical length, a rectangular shape with a horizontal length less than its vertical length, or a square shape. In alternative embodiments, the display area DA can have various shapes such as elliptical or circular shapes.

[0069] In an embodiment, the display device DV may include a light-emitting panel 1 and a color panel 2 stacked in the thickness direction (e.g., the z-direction). Reference Figure 1B The light-emitting panel 1 may include first to third pixel circuits PC1, PC2 and PC3 on the first substrate 10, and first to third light-emitting diodes LED1, LED2 and LED3 respectively connected to the first to third pixel circuits PC1, PC2 and PC3.

[0070] The light emitted by the first to third light-emitting diodes LED1, LED2, and LED3 (e.g., blue light Lb) can be converted into green light Lg, red light Lr, and blue light Lb while passing through the color panel 2, or it can pass through the color panel 2 without conversion. The area from which it emits green light Lg can correspond to the green pixel Pg, the area from which it emits red light Lr can correspond to the red pixel Pr, and the area from which it emits blue light Lb can correspond to the blue pixel Pb.

[0071] The color panel 2 may include a second substrate 20 and a first light-shielding layer 21 on the second substrate 20. While removing portions corresponding to green pixels Pg, red pixels Pr, and blue pixels Pb, a plurality of holes may be defined in the first light-shielding layer 21. The first light-shielding layer 21 may include material portions disposed in non-pixel regions NPA. The material portions may include various materials capable of absorbing light.

[0072] The second light-shielding layer 22 may be disposed on top of the first light-shielding layer 21. The second light-shielding layer 22 may include a material portion disposed in the non-pixel region NPA. The second light-shielding layer 22 may include various materials capable of absorbing light. The second light-shielding layer 22 may include a material that is the same as or different from the material of the first light-shielding layer 21.

[0073] The first light-shielding layer 21 and / or the second light-shielding layer 22 may include an opaque inorganic insulating material such as chromium oxide or molybdenum oxide, or an opaque organic insulating material such as black resin.

[0074] The color layer can be disposed on the second substrate 20 and can include first to third color filters 30a, 30b and 30c. The first color filter 30a can include a pigment or dye of a first color (e.g., green). The second color filter 30b can include a pigment or dye of a second color (e.g., red). The third color filter 30c can include a pigment or dye of a third color (e.g., blue).

[0075] A color conversion and transmission layer can be disposed between a color layer and a light-emitting diode. The color conversion and transmission layer includes a first color conversion portion 40a, a second color conversion portion 40b, and a transmission portion 40c.

[0076] The first color conversion section 40a overlaps with the first color filter 30a and can convert blue light Lb incident on the first color conversion section 40a into green light Lg. For example... Figure 1C As shown, the first color conversion portion 40a may include a first photosensitive polymer 1161, a first quantum dot 1162 and a first scattering particle 1163, wherein the first quantum dot 1162 and the first scattering particle 1163 may be dispersed in the first photosensitive polymer 1161.

[0077] The first quantum dot 1162 can be excited by blue light Lb to isotropically emit green light Lg with a wavelength greater than that of blue light Lb. The first photosensitive polymer 1161 can be a transparent organic material.

[0078] The first scattering particle 1163 scatters blue light Lb that is not absorbed by the first quantum dot 1162, allowing more of the first quantum dot 1162 to be excited, thereby improving color conversion efficiency. The first scattering particle 1163 can be, for example, titanium oxide (TiO2) or metal particles. The first quantum dot 1162 can be one of group II-VI compounds, group III-V compounds, group IV-VI compounds, group IV elements, group IV compounds, and any combination thereof.

[0079] The second color conversion section 40b can overlap with the second color filter 30b and convert the blue light Lb incident on the second color conversion section 40b into red light Lr. For example... Figure 1C As shown, the second color conversion portion 40b may include a second photosensitive polymer 1151, a second quantum dot 1152, and a second scattering particle 1153, wherein the second quantum dot 1152 and the second scattering particle 1153 may be dispersed in the second photosensitive polymer 1151.

[0080] The second quantum dot 1152 can be excited by blue light Lb to isotropically emit red light Lr with a wavelength greater than that of blue light Lb. The second photosensitive polymer 1151 can be a transparent organic material. The second scattering particles 1153 scatter the blue light Lb that is not absorbed by the second quantum dot 1152 to allow more of the second quantum dot 1152 to be excited, thereby improving the color conversion efficiency. In an embodiment, for example, the second scattering particles 1153 can be, for example, titanium oxide (TiO2) or metal particles. The second quantum dot 1152 can be one of group II-VI compounds, group III-V compounds, group IV-VI compounds, group IV elements, and any combination thereof. The second quantum dot 1152 can include the same material as the first quantum dot 1162. In this case, the size of the second quantum dot 1152 can be larger than the size of the first quantum dot 1162.

[0081] The 40c transmissive portion can transmit blue light (Lb). For example... Figure 1C As shown, the transmissive portion 40c may include a third photosensitive polymer 1171 in which third scattering particles 1173 are dispersed. The third photosensitive polymer 1171 may include light-transmitting organic materials such as silicone resin and epoxy resin, and may include the same materials as the first photosensitive polymer 1161 and the second photosensitive polymer 1151. The third scattering particles 1173 may scatter blue light Lb to emit the blue light Lb, and may include the same materials as the first scattering particles 1163 and the second scattering particles 1153.

[0082] Blue light Lb emitted from the light-emitting panel 1 can have its color converted while passing through the color conversion transmission layer, or it can pass through the color conversion transmission layer without color conversion, and then its color purity can be improved while passing through the color layer. In an embodiment, blue light Lb emitted from the first light-emitting diode LED1 of the light-emitting panel 1 can pass through the first color region of the color panel 2. The blue light Lb can be converted and filtered into green light Lg by the color panel 2 while passing through the color panel 2. The first color region can have a stacked structure of a first color conversion portion 40a and a first color filter 30a.

[0083] Blue light Lb emitted from the second light-emitting diode LED2 of the light-emitting panel 1 can pass through the second color region of the color panel 2. While passing through the color panel 2, the blue light Lb is converted and filtered into red light Lr by the color panel 2. The second color region may have a stacked structure of a second color conversion section 40b and a second color filter 30b.

[0084] Blue light Lb emitted from the third light-emitting diode LED3 of the light-emitting panel 1 can pass through the third color region of the color panel 2. While passing through the color panel 2, the blue light Lb is also transmitted and filtered by the color panel 2. The third color region can have a stacked structure of a transmission portion 40c and a third color filter 30c.

[0085] The first to third light-emitting diodes LED1, LED2, and LED3 may each comprise an organic light-emitting diode containing organic materials. In another embodiment, the first to third light-emitting diodes LED1, LED2, and LED3 may each comprise an inorganic light-emitting diode containing inorganic materials. The inorganic light-emitting diode may comprise a PN junction diode containing inorganic semiconductor materials. When a voltage is forward-biased applied to the PN junction diode, holes and electrons can be injected, and light of a predetermined color can be emitted by converting the energy generated by the recombination of holes and electrons into light energy. The inorganic light-emitting diode may have a width of several micrometers to hundreds of micrometers or several nanometers to hundreds of nanometers. In an embodiment, the light-emitting diode LED may be a light-emitting diode comprising quantum dots. As described above, the emitting layer of the light-emitting diode LED may comprise organic materials, inorganic materials, quantum dots, organic materials and quantum dots, or inorganic materials and quantum dots.

[0086] Display devices having the above structure may include mobile phones, televisions, billboards, monitors, tablet PCs, and laptop computers.

[0087] Figure 2 This is an equivalent circuit diagram of an embodiment of a light-emitting diode included in the light-emitting panel of a display device and a pixel circuit electrically connected to the light-emitting diode.

[0088] refer to Figure 2 A light-emitting diode (e.g., the first electrode (e.g., the anode) of a light-emitting diode (LED) can be connected to a pixel circuit PC, and a second electrode (e.g., the cathode) of the LED can be connected to a common voltage line VSL that provides the common power voltage ELVSS. The LED can emit light with a brightness corresponding to the amount of current supplied from the pixel circuit PC.

[0089] Figure 2 The light-emitting diode (LED) can be used with the above-mentioned... Figure 1B Each of the first to third light-emitting diodes LED1, LED2 and LED3 shown corresponds to one of them. Figure 2 The pixel circuit PC can be used with the above in Figure 1B Each of the first to third pixel circuits PC1, PC2 and PC3 shown corresponds to the first to third pixel circuits.

[0090] The pixel circuit PC can control the amount of current flowing from the driving power voltage ELVDD through the light-emitting diode (LED) to the common power voltage ELVSS in response to a data signal. The pixel circuit PC may include a first transistor M1, a second transistor M2, a third transistor M3, and a storage capacitor Cst.

[0091] Each of the first transistor M1, the second transistor M2, and the third transistor M3 can be an oxide semiconductor thin-film transistor comprising a semiconductor layer containing an oxide semiconductor or a silicon semiconductor thin-film transistor comprising a semiconductor layer containing polycrystalline silicon. Depending on the type of transistor, the first electrode can be one of the source electrode and the drain electrode, and the second electrode can be the other of the source electrode and the drain electrode.

[0092] The first transistor M1 can be a driver transistor. The first electrode of the first transistor M1 can be connected to the drive voltage line VDL supplying the drive power voltage ELVDD, and the second electrode can be connected to the first electrode of the light-emitting diode (LED). The gate electrode of the first transistor M1 can be connected to the first node N1. The first transistor M1 can control the amount of current flowing from the drive power voltage ELVDD to the LED in response to the voltage at the first node N1.

[0093] The second transistor M2 can be a switching transistor. The first electrode of the second transistor M2 can be connected to the data line DL, and the second electrode of the second transistor M2 can be connected to the first node N1. The gate electrode of the second transistor M2 can be connected to the scan line SL. When a scan signal is supplied to the scan line SL, the second transistor M2 can be turned on to electrically connect the data line DL to the first node N1.

[0094] The third transistor M3 can be an initialization transistor and / or a sensing transistor. The first electrode of the third transistor M3 can be connected to the second node N2, and the second electrode of the third transistor M3 can be connected to the initialization sensing line ISL. The gate electrode of the third transistor M3 can be connected to the control line CL.

[0095] When a control signal is supplied to the control line CL, the third transistor M3 can be turned on to electrically connect the initialization sensing line ISL to the second node N2. In an embodiment, the third transistor M3 can be turned on according to the signal transmitted through the control line CL, and the first electrode of the light-emitting diode LED can be initialized by applying an initialization voltage from the initialization sensing line ISL to the first electrode of the light-emitting diode LED. In an embodiment, when a control signal is supplied to the control line CL, the third transistor M3 can be turned on to sense the characteristic information of the light-emitting diode LED. The third transistor M3 can have both the function of an initialization transistor and the function of a sensing transistor, or only one of these functions. In an embodiment, when the third transistor M3 has the function of an initialization transistor, the initialization sensing line ISL can be referred to as an initialization voltage line. When the third transistor M3 has the function of a sensing transistor, the initialization sensing line ISL can be referred to as a sensing line. The initialization operation and the sensing operation of the third transistor M3 can be performed individually or simultaneously. In the following description, for ease of description, the case where the third transistor M3 has both the function of an initialization transistor and the function of a sensing transistor is described.

[0096] The storage capacitor Cst can be connected between the first node N1 and the second node N2. In an embodiment, the first capacitor electrode of the storage capacitor Cst can be connected to the gate electrode of the first transistor M1, and the second capacitor electrode of the storage capacitor Cst can be connected to the first electrode of the light-emitting diode (LED).

[0097] although Figure 2 The first transistor M1, the second transistor M2, and the third transistor M3 are shown as n-channel metal-oxide semiconductors (“NMOS”), but the invention is not limited thereto. In embodiments, for example, at least one of the first transistor M1, the second transistor M2, and the third transistor M3 may be a p-channel metal-oxide semiconductor (“PMOS”).

[0098] although Figure 2 Three transistors are shown, but the invention is not limited thereto. The pixel circuit PC may include four or more transistors.

[0099] Figure 3A This is a plan view of an embodiment of a pixel circuit, showing the semiconductor layer Act, the bottom conductive layer BCL, and the protective layer PL. Figure 3B yes Figure 3A A magnified view of a portion of it. Figure 4A and Figure 4B It is along Figure 3A A cross-sectional view of an embodiment of the pixel circuit cut by line IVa-IVa'. Figure 4C It is along Figure 3AA cross-sectional view of an embodiment of the pixel circuit cut by line IVc-IVc'. Figure 5 This is a cross-sectional view of a comparative example of a semiconductor layer Act without a protective layer and a bottom conductive layer BCL.

[0100] refer to Figure 3A and Figure 3B The semiconductor layer Act may intersect with the bottom conductive layer BCL beneath it. In an embodiment, the semiconductor layer Act may extend in the x-direction, and the bottom conductive layer BCL may extend in the y-direction intersecting the x-direction. The semiconductor layer Act may be included in a reference... Figure 2 The semiconductor layer of at least one of the transistors in the described pixel circuit, and the bottom conductive layer BCL may be an element different from the transistor including the semiconductor layer Act, for example, wiring or electrode connected to another transistor or electrode of a storage capacitor.

[0101] The semiconductor layer Act may comprise oxide-based or silicon-based materials (e.g., amorphous silicon, polycrystalline silicon). In embodiments, for example, the semiconductor layer Act may comprise an oxide of at least one of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn). The semiconductor layer Act may comprise a channel region and low-resistance regions disposed on opposite sides, with the channel region between the low-resistance regions. The low-resistance regions are areas with a resistance lower than that of the channel region and may correspond to either the source or drain region.

[0102] The bottom conductive layer (BCL) may include a conductive material. In embodiments, for example, the bottom conductive layer (BCL) may include at least one of molybdenum (Mo), copper (Cu), and titanium (Ti), and has a single-layer or multi-layer structure comprising the aforementioned materials.

[0103] The protective layer PL can overlap with the intersection region CR where the edge Act-E of the semiconductor layer Act and the edge BCL-E of the bottom conductive layer BCL intersect. For example... Figure 4A As shown, the protective layer PL may include a first sublayer L1. (As illustrated...) Figure 4B and Figure 4C As shown, the protective layer PL may include a first sublayer L1 and a second sublayer L2 on the first sublayer L1. The first sublayer L1 may include an insulating material such as an inorganic insulating material. The second sublayer L2 may include a conductive material such as a metal.

[0104] refer to Figures 4A to 4CA bottom conductive layer (BCL) can be disposed on the first substrate 10. A semiconductor layer (Act) can be disposed above the bottom conductive layer (BCL). A buffer layer 201 is disposed between the semiconductor layer (Act) and the bottom conductive layer (BCL). The buffer layer 201 may include an inorganic insulating material, such as silicon nitride, silicon oxide, and / or silicon oxynitride. In embodiments, the semiconductor layer (Act) may include a silicon-based semiconductor such as polycrystalline silicon or an oxide-based semiconductor such as indium gallium zinc oxide (“IGZO”).

[0105] The protective layer PL can overlap with the intersection region CR of the edge of the semiconductor layer Act and the edge of the bottom conductive layer BCL, and can cover the intersection region CR. For example... Figures 4A to 4C As shown, the protective layer PL can directly contact the top surface of the semiconductor layer Act. Figure 3B As shown in the enlarged image, the edge Act-E of the semiconductor layer Act intersects with the edge BCL-E of the bottom conductive layer BCL. The protective layer PL can extend further outward in the y-direction than the edge Act-E of the semiconductor layer Act, and simultaneously, further outward in the x-direction than the edge BCL-E of the bottom conductive layer BCL. In this regard, Figures 4A to 4C The diagram shows the step difference between the protective layer PL covering the semiconductor layer Act and the bottom conductive layer BCL in the cross region CR, extending further outward than the edge BCL-E of the bottom conductive layer BCL (reference). Figure 4A and Figure 4B ), and extends outwards further than the edge Act-E of the semiconductor layer Act (reference). Figure 4C ).

[0106] The intermediate insulating layer 205 may be disposed on the semiconductor layer Act. In an embodiment, the intermediate insulating layer 205 may be disposed on the protective layer PL. The intermediate insulating layer 205 may comprise an inorganic insulating material such as silicon nitride, silicon oxide, and / or silicon oxynitride.

[0107] As a comparative example, such as Figure 5As shown, without a protective layer PL, the intermediate insulating layer 205 may include a cavity 205v disposed in the cross region CR. The portion of the intermediate insulating layer 205 with the cavity 205v is structurally thin and fragile. The cavity 205v can be provided due to the step difference between the semiconductor layer Act and the bottom conductive layer BCL and / or the stress of the intermediate insulating layer 205 itself. In the process of etching the layers disposed on the intermediate insulating layer 205, the intermediate insulating layer 205 can protect the underlying layers and structures. However, when the intermediate insulating layer 205 includes the cavity 205v, the etchant used during the etching process may damage the semiconductor layer Act. In an embodiment, the etchant may advance into the semiconductor layer Act through the portion with the cavity 205v and damage the semiconductor layer Act. The operating characteristics of the transistor with the damaged semiconductor layer Act may deteriorate and may result in damage to the display area DA (reference). Figure 1A Progressive white spots and / or dark spots appear. In contrast, in the embodiments, such as Figures 3A to 4B As shown, the above-mentioned problem can be prevented by arranging a protective layer PL corresponding to an etching blocker in the cross region CR.

[0108] Figures 6A to 6C This is a plan view of another embodiment of a pixel circuit that includes a semiconductor layer Act, a bottom conductive layer BCL, and a protective layer PL.

[0109] Refer to the above Figure 3A In the illustrated embodiment, two protective layers PL are shown overlapping with four intersection zones CR in a plan view. In this embodiment, one protective layer PL may overlap with and / or cover two adjacent intersection zones CR in the x-direction, and another protective layer PL may overlap with and / or cover two other intersection zones CR. In another embodiment, refer to... Figure 6A A protective layer PL can overlap with and / or cover one of the four cross zones CR.

[0110] Reference Figure 3A , Figure 3B and Figure 6A In the illustrated embodiment, although the first width W1 of the first portion of the semiconductor layer Act overlapping the bottom conductive layer BCL and the second width W2 of the second portion of the semiconductor layer Act not overlapping the bottom conductive layer BCL are substantially the same in the plan view, the invention is not limited thereto. In another embodiment, as Figure 6B As shown in the diagram, in the plan view, the first width W1 of the first portion of the semiconductor layer Act overlapping the bottom conductive layer BCL can be smaller than the second width W2 of the second portion of the semiconductor layer Act overlapping the bottom conductive layer BCL. In alternative embodiments, such as Figure 6C As shown in the diagram, in the plan view, the first width W1 of the first portion of the semiconductor layer Act that overlaps with the bottom conductive layer BCL can be greater than the second width W2 of the second portion of the semiconductor layer Act that overlaps with the bottom conductive layer BCL.

[0111] Figure 7 This is a plan view of an embodiment of the pixel circuit of the light-emitting panel, and Figure 8 It is connected to Figure 7 A plan view of an embodiment of a light-emitting diode in a pixel circuit. In the embodiment, Figure 8 Describe the case where the light-emitting diode is an organic light-emitting diode.

[0112] refer to Figure 7 The scan line SL and control line CL can extend in the x-direction. Multiple data lines (e.g., first to third data lines DL1, DL2, and DL3) can be arranged in the x-direction, intersecting the y-direction, and extend in the y-direction. The initialization sensing line ISL, drive voltage line VDL, and common voltage line VSL can extend in the y-direction.

[0113] In this embodiment, two adjacent common voltage lines VSL can be separated from each other. The first to third data lines DL1, DL2, and DL3, the initialization sensing line ISL, and the drive voltage line VDL can be arranged between the two adjacent common voltage lines VSL. The initialization sensing line ISL and the drive voltage line VDL are adjacent to each other and can be adjacent to one of the common voltage lines VSL. The first to third data lines DL1, DL2, and DL3 are adjacent to each other and can be adjacent to the other common voltage line VSL. In this embodiment, the initialization sensing line ISL and the drive voltage line VDL can be arranged on one side (e.g., the left side) of the first to third storage capacitors Cst1, Cst2, and Cst3 described below, and the first to third data lines DL1, DL2, and DL3 can be arranged on the other side (e.g., the right side). This structure allows for efficient use of the display panel space.

[0114] The auxiliary line AL can extend, for example, in the x-direction, such that it intersects the common voltage line VSL and the drive voltage line VDL. The auxiliary lines AL can be separated from each other, with the first to third storage capacitors Cst1, Cst2, and Cst3 located between the auxiliary lines AL. In an embodiment, one of the auxiliary lines AL can be adjacent to the scan line SL, and the other auxiliary line AL can be adjacent to the control line CL. One of the auxiliary lines AL can be electrically connected to the common voltage line VSL, and the other auxiliary line AL can be electrically connected to the drive voltage line VDL. The display panel may include... Figure 7The structure shown is a repeating structure in both the x and y directions. Therefore, the multiple auxiliary lines AL and multiple common voltage lines VSL provided to the display panel can form a mesh structure in a planar view. Similarly, the multiple auxiliary lines AL and multiple drive voltage lines VDL electrically connected can form a mesh structure in a planar view.

[0115] In a planar diagram, transistors and storage capacitors can be arranged in an approximately quadrilateral space surrounded by adjacent common voltage lines VSL and adjacent auxiliary lines AL. The transistors and storage capacitors can be electrically connected to their respective light-emitting diodes (LEDs). Figure 8 The first electrodes 211, 212 and 213 of the first to third organic light-emitting diodes OLED1, OLED2 and OLED3 are shown to be electrically connected to the relevant pixel circuits.

[0116] The first electrode 211 of the first organic light-emitting diode OLED1 can be electrically connected to the first pixel circuit. The first pixel circuit may include a first driving transistor M11, a first switching transistor M12, a first initialization sensing transistor M13, and a first storage capacitor Cst1.

[0117] The first electrode 212 of the second organic light-emitting diode OLED2 can be electrically connected to the second pixel circuit. The second pixel circuit may include a second driving transistor M21, a second switching transistor M22, a second initialization sensing transistor M23, and a second storage capacitor Cst2.

[0118] The first electrode 213 of the third organic light-emitting diode OLED3 can be electrically connected to the third pixel circuit. The third pixel circuit may include a third driving transistor M31, a third switching transistor M32, a third initialization sensing transistor M33, and a third storage capacitor Cst3.

[0119] The first to third storage capacitors Cst1, Cst2, and Cst3 can be arranged in one direction (e.g., the y-direction). The first storage capacitor Cst1 can be arranged relatively closest to the scan line SL, and the third storage capacitor Cst3 can be arranged relatively farthest from the scan line SL (or closest to the control line CL). The second storage capacitor Cst2 can be arranged between the first storage capacitor Cst1 and the third storage capacitor Cst3.

[0120] The first driving transistor M11 may include a first driving semiconductor layer A11 and a first driving gate electrode G11. The first driving semiconductor layer A11 may include a first low-resistance region B11 and a second low-resistance region C11. A first channel region may be disposed between the first low-resistance region B11 and the second low-resistance region C11. The first low-resistance region B11 and the second low-resistance region C11 are regions having a resistance lower than that of the first channel region, and may be provided by a process of doping impurities or a process of fabricating conductors. The first driving gate electrode G11 may overlap with the first channel region of the first driving semiconductor layer A11. One of the first low-resistance regions B11 and the second low-resistance region C11 may correspond to a source region, and the other may correspond to a drain region.

[0121] One of the first low-resistance region B11 and the second low-resistance region C11 of the first driving semiconductor layer A11 can be connected to the first storage capacitor Cst1, and the other can be connected to the driving voltage line VDL. In an embodiment, the first low-resistance region B11 can be connected to a portion of the second capacitor electrode CE2 of the first storage capacitor Cst1 (e.g., the second sub-electrode CE2t of the second capacitor electrode CE2) through the first contact hole CT1. The second low-resistance region C11 can be connected to the first connector NM1 through the second contact hole CT2. The first connector NM1 can be connected to the driving voltage line VDL through the eleventh contact hole CT11. The second low-resistance region C11 can be connected to the driving voltage line VDL through the first connector NM1.

[0122] The first switching transistor M12 may include a first switching semiconductor layer A12 and a first switching gate electrode G12. The first switching semiconductor layer A12 may include a first low-resistance region B12 and a second low-resistance region C12. A second channel region may be disposed between the first low-resistance region B12 and the second low-resistance region C12. The first switching gate electrode G12 may overlap with the second channel region of the first switching semiconductor layer A12. The first switching gate electrode G12 may correspond to a portion of a scan line SL (e.g., a portion of a branch SL-B (hereinafter also referred to as the first branch) extending in a direction intersecting the scan line SL).

[0123] The scan line SL may include the gate electrodes of the first to third switching transistors M12, M22, and M32. In an embodiment, the scan line SL may include a first branch SL-B extending in the y-direction. A portion of the first branch SL-B may correspond to the gate electrodes of the first to third switching transistors M12, M22, and M32. The first branch SL-B may extend between the first to third storage capacitors Cst1, Cst2, and Cst3 and the first to third data lines DL1, DL2, and DL3.

[0124] One of the first low-resistance regions B12 and C12 of the first switching semiconductor layer A12 can be electrically connected to the first data line DL1, and the other can be electrically connected to the first storage capacitor Cst1. In an embodiment, the first low-resistance region B12 can be connected to the second connector NM2 through the third contact hole CT3. The second connector NM2 can be connected to the first capacitor electrode CE1 of the first storage capacitor Cst1 through the fourth contact hole CT4. Therefore, the first low-resistance region B12 can be connected to the first capacitor electrode CE1 of the first storage capacitor Cst1 through the second connector NM2. The second low-resistance region C12 can be connected to the third connector NM3 through the fifth contact hole CT5. The third connector NM3 can be connected to the first data line DL1 through the sixth contact hole CT6. The second low-resistance region C12 can be connected to the first data line DL1 through the third connector NM3.

[0125] The first initialization sensing transistor M13 may include a first initialization sensing semiconductor layer A13 and a first initialization sensing gate electrode G13. The first initialization sensing semiconductor layer A13 may include a first low-resistance region B13 and a second low-resistance region C13. The first initialization sensing gate electrode G13 may overlap with the first initialization sensing semiconductor layer A13.

[0126] The control line CL may include the gate electrodes of the first to third initialization sensing transistors M13, M23, and M33. In an embodiment, the control line CL may include a branch CL-B (hereinafter also referred to as a second branch) extending in the y-direction. A portion of the second branch CL-B may correspond to the gate electrodes of the first to third initialization sensing transistors M13, M23, and M33. The second branch CL-B may extend between the drive voltage line VDL and the initialization sensing line ISL.

[0127] One of the first low-resistance region B13 and the second low-resistance region C13 of the first initialization sensing semiconductor layer A13 can be electrically connected to the initialization sensing line ISL, and the other can be electrically connected to the first storage capacitor Cst1. In an embodiment, the first low-resistance region B13 can be connected to the fourth connector NM4 through the seventh contact hole CT7. The fourth connector NM4 can be connected to the initialization sensing line ISL through the eighth contact hole CT8. Therefore, the first low-resistance region B13 can be electrically connected to the initialization sensing line ISL through the fourth connector NM4. The second low-resistance region C13 can be electrically connected to a portion of the second capacitor electrode CE2 of the first storage capacitor Cst1 through the ninth contact hole CT9, for example, the second sub-electrode CE2t of the second capacitor electrode CE2.

[0128] The first storage capacitor Cst1 may include at least two electrodes. In an embodiment, the first storage capacitor Cst1 may include a first capacitor electrode CE1 and a second capacitor electrode CE2.

[0129] The first capacitor electrode CE1 can be integrated with the first driving gate electrode G11 as a single unit. In other words, the first capacitor electrode CE1 can include the first driving gate electrode G11. In an alternative embodiment, the first driving gate electrode G11 can include the first capacitor electrode CE1.

[0130] The second capacitor electrode CE2 may include a first sub-electrode CE2b and a second sub-electrode CE2t. The first sub-electrode CE2b may be disposed below the first capacitor electrode CE1, and the second sub-electrode CE2t may be disposed on the first capacitor electrode CE1. The first sub-electrode CE2b may be connected to the second sub-electrode CE2t through the tenth contact hole CT10.

[0131] like Figure 8 As shown, the first organic light-emitting diode (OLED1) can be electrically connected to the first pixel circuit through the first via VH1. In an embodiment, the first electrode 211 of the first OLED1 can be connected to the second sub-electrode CE2t of the first storage capacitor Cst1 (see reference) through the first via VH1. Figure 7 ).

[0132] The second driving transistor M21, the second switching transistor M22, and the second initialization sensing transistor M23 of the second pixel circuit can have the same structure as the first driving transistor M11, the first switching transistor M12, and the first initialization sensing transistor M13 described above. Similarly, the second storage capacitor Cst2 can have the same structure as the first storage capacitor Cst1. For example... Figure 8 As shown, the second organic light-emitting diode OLED2 can be electrically connected to the second pixel circuit through the second via VH2. In an embodiment, the first electrode 212 of the second organic light-emitting diode OLED2 can be connected to the second sub-electrode of the second storage capacitor Cst2 through the second via VH2.

[0133] The third driving transistor M31, the third switching transistor M32, and the third initialization sensing transistor M33 of the third pixel circuit can have the same structure as the first driving transistor M11, the first switching transistor M12, and the first initialization sensing transistor M13 described above. Similarly, the third storage capacitor Cst3 can have the same structure as the first storage capacitor Cst1. For example... Figure 8As shown, the third organic light-emitting diode (OLED3) can be electrically connected to the third pixel circuit through the third via VH3. In an embodiment, the first electrode 213 of the third OLED3 can be connected to the second sub-electrode of the third storage capacitor Cst3 through the third via VH3.

[0134] Figure 7 In the transistors shown, the semiconductor layers of some transistors may overlap with lines and / or electrodes disposed beneath them. Cross-regions between the edges of the semiconductor layers and the edges of the lines and / or between the edges of the semiconductor layers and the edges of the electrodes may overlap with and / or be covered by a protective layer (hereinafter also referred to as the first protective layer PL). Figure 7 The diagram shows that the first switching semiconductor layer A12 of the first switching transistor M12 intersects with the second data line DL2, and the intersection area between the edge of the first switching semiconductor layer A12 and the edge of the second data line DL2 overlaps with and / or is covered by the first protective layer PL. Similarly, the third switching semiconductor layer of the third switching transistor M32 may intersect with the first data line DL1 and the second data line DL2. The intersection areas between the edge of the third switching semiconductor layer and the edge of the first data line DL1, and between the edge of the third switching semiconductor layer and the edge of the second data line DL2, may overlap with and / or be covered by the first protective layer PL. In the plan view, the first protective layer PL may have an isolated shape. The first protective layer PL may include the same material as the first capacitor electrode CE1 of the first storage capacitor Cst1, the first drive gate electrode G11 of the first drive transistor M11, the first branch SL-B, and / or the first switching gate electrode G12. In an embodiment, the first protective layer PL may include a sublayer. The sublayer is arranged in the same layer as the first capacitor electrode CE1 of the first storage capacitor Cst1, the first driving gate electrode G11 of the first driving transistor M11, the first branch SL-B and / or the first switching gate electrode G12, and includes the same material as the first capacitor electrode CE1 of the first storage capacitor Cst1, the first driving gate electrode G11 of the first driving transistor M11, the first branch SL-B and / or the first switching gate electrode G12.

[0135] The first driving semiconductor layer A11 of the first driving transistor M11 may intersect with the first sub-electrode CE2b of the first storage capacitor Cst1, and the intersection region CR between the edges may overlap with and / or be covered by the protective layer (hereinafter also referred to as the second protective layer PL'). The second protective layer PL' may be a portion of the first capacitor electrode CE1 of the first storage capacitor Cst1 and / or a portion of the first driving gate electrode G11. The second protective layer PL' may include the same material as the first capacitor electrode CE1 of the first storage capacitor Cst1, the first driving gate electrode G11 of the first driving transistor M11, the first branch SL-B, and / or the first switching gate electrode G12. In an embodiment, the second protective layer PL' may include a layer. This layer is disposed in the same layer as the first capacitor electrode CE1 of the first storage capacitor Cst1, the first driving gate electrode G11 of the first driving transistor M11, the first branch SL-B and / or the first switching gate electrode G12, and includes the same material as the first capacitor electrode CE1 of the first storage capacitor Cst1, the first driving gate electrode G11 of the first driving transistor M11, the first branch SL-B and / or the first switching gate electrode G12.

[0136] Similarly, the semiconductor layer of the second driving transistor M21 may intersect with the first sub-electrode of the second storage capacitor Cst2, and the intersection region CR between the edges may overlap with and / or be covered by a portion of the first capacitor electrode of the second storage capacitor Cst2 and / or the second protective layer PL', where the second protective layer PL' is part of the second driving gate electrode. Furthermore, the semiconductor layer of the third driving transistor M31 may intersect with the first sub-electrode of the third storage capacitor Cst3, and the intersection region CR between the edges may overlap with and / or be covered by a portion of the first capacitor electrode of the third storage capacitor Cst3 and / or the second protective layer PL', where the second protective layer PL' is part of the third driving gate electrode.

[0137] Figure 9 , Figure 10 and Figure 11 It shows the formation Figure 7 A plan view of an embodiment of the pixel circuit process shown. Figure 12A and Figure 12B They are Figure 10 Enlarged plan view of the embodiments of regions XIIa and XIIb. Figure 13A It is along Figure 9 A cross-sectional view of an embodiment of the pixel circuit intercepted by lines A-A' and B-B'. Figure 13B and Figure 13C Is with Figure 13AA cross-sectional view of the pixel embodiment corresponding to the process after the process, and Figure 13D It is set in Figure 13C A cross-sectional view of the organic light-emitting diodes on the pixel circuit. Figure 12A It shows Figure 10 Region XIIa, and can simultaneously with along Figure 13B The planar shape of the structure intercepted by line A-A' corresponds to that of the structure. Figure 12B It shows Figure 10 Region XIIb, and can simultaneously interact with along Figure 13B The planar shape of the structure intercepted by line B-B' corresponds to that of the structure.

[0138] refer to Figure 7 , Figure 9 and Figure 13A First, the first substrate 10 is prepared (reference). Figure 13A The first substrate 10 may include glass or resin material. The glass may include transparent glass containing SiO2 as a main component. The resin material may include polymer resins such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate. When the first substrate 10 includes a polymer resin, the first substrate 10 may be flexible, rollable, or bendable.

[0139] Then, lines in the y-direction (e.g., first to third data lines DL1, DL2, and DL3, a common voltage line VSL, a drive voltage line VDL, and an initialization sensing line ISL) can be provided on the first substrate 10. Furthermore, a first sub-electrode CE2b of each of the first to third storage capacitors Cst1, Cst2, and Cst3 can be provided. Figure 13A The first data line DL1, the second data line DL2, and the first sub-electrode CE2b are shown.

[0140] The first to third data lines DL1, DL2, and DL3, the common voltage line VSL, the drive voltage line VDL, and the initialization sensing line ISL, along with the first sub-electrode CE2b of each of the first to third storage capacitors Cst1, Cst2, and Cst3, may comprise the same material, such as a metallic material. In embodiments, the metallic material may, for example, comprise at least one of molybdenum (Mo), copper (Cu), and titanium (Ti).

[0141] Then, as Figure 13AAs shown, a buffer layer 201 is provided. The buffer layer 201 may cover the first to third data lines DL1, DL2 and DL3, the common voltage line VSL, the drive voltage line VDL, the initialization sensing line ISL, and the first sub-electrode CE2b. The buffer layer 201 may include an inorganic insulating material, such as silicon nitride, silicon oxide and / or silicon oxynitride.

[0142] Then, a semiconductor layer is formed on the buffer layer 201. In an embodiment, a first driving transistor M11 (reference) may be provided. Figure 7 The first driving semiconductor layer A11 and the first switching transistor M12 (reference) Figure 7 The first switching semiconductor layer A12 and the first initialization sensing transistor M13 (reference) Figure 7 The first initialization sensing semiconductor layer A13 is provided. Similarly, a second driving semiconductor layer A21, a second switching semiconductor layer A22, and a second initialization sensing semiconductor layer A23 can be provided, and a third driving semiconductor layer A31, a third switching semiconductor layer A32, and a third initialization sensing semiconductor layer A33 can also be provided. Figure 13A The first switching semiconductor layer A12 and the first driving semiconductor layer A11 are shown.

[0143] In one embodiment, semiconductor layers A11, A12, A13, A21, A22, A23, A31, A32, and A33 may be separated from each other and may comprise oxide-based semiconductor materials, such as IGZO. However, oxide-based semiconductor materials are not limited to IGZO. In another embodiment, the oxide-based semiconductor material may comprise an oxide of at least one of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn). In yet another embodiment, semiconductor layers A11, A12, A13, A21, A22, A23, A31, A32, and A33 may comprise silicon-based materials.

[0144] refer to Figure 7 , Figure 10 and Figure 13B A first capacitor electrode CE1, a first branch SL-B, and a second branch CL-B may be provided on the first substrate 10. In an embodiment, the first capacitor electrode CE1, the first branch SL-B, and the second branch CL-B may include at least one of molybdenum (Mo), copper (Cu), and titanium (Ti), and may include a single-layer structure or a multilayer structure containing the above materials.

[0145] The first to third storage capacitors Cst1, Cst2 and Cst3 (reference) Figure 7The first capacitor electrode CE1 can be separated from each other in the y-direction and can be connected to the first sub-electrode CE2b below it (see reference). Figure 9 )overlapping.

[0146] The first to third storage capacitors Cst1, Cst2 and Cst3 (reference) Figure 7 The first capacitor electrode CE1 can be connected to the first to third driving transistors M11, M21 and M31 (see reference). Figure 7 The first to third driving gate electrodes G11, G21, and G31 are integrated as a single unit. In other words, the first to third storage capacitors Cst1, Cst2, and Cst3 (refer to...) Figure 7 The first capacitor electrode CE1 may include first to third driving gate electrodes G11, G21 and G31, respectively. In an alternative embodiment, the first to third driving gate electrodes G11, G21 and G31 of the first to third driving transistors M11, M21 and M31 may each include the first capacitor electrode CE1.

[0147] like Figure 10 As shown, the first branch SL-B and the second branch CL-B can extend in the y-direction and include the gate electrodes of some transistors. In an embodiment, the first branch SL-B may include the first to third switching gate electrodes G12, G22, and G32 of the first to third switching transistors M12, M22, and M32. The second branch CL-B may include the first to third initialization sensing gate electrodes G13, G23, and G33 of the first to third initialization sensing transistors M13, M23, and M33. Figure 13B A portion of the first branch SL-B is shown, including the first switching gate electrode G12 and the first driving gate electrode G11.

[0148] Reference Figure 13B The pixel circuit cross-section is taken along line A-A'. The first switch gate electrode G12 may overlap with the first switch semiconductor layer A12, and the gate insulating layer 203 is below the first switch gate electrode G12. The region of the first switch semiconductor layer A12 that overlaps with the first switch gate electrode G12 may correspond to the first switch channel region. The left side of the first switch channel region may correspond to the first low resistance region B12, and the right side of the first switch channel region may correspond to the second low resistance region C12. The gate insulating layer 203 may include inorganic insulating materials such as silicon nitride, silicon oxide, and / or silicon oxynitride, and may include a single-layer structure or a multi-layer structure containing the above materials.

[0149] Reference Figure 13BThe cross-section of the pixel circuit along line B-B' is shown. The first driving gate electrode G11 can overlap with the first driving semiconductor layer A11, and the gate insulating layer 203 is between the first driving gate electrode G11 and the first driving semiconductor layer A11. The region of the first driving semiconductor layer A11 that overlaps with the first driving gate electrode G11 can correspond to the first driving channel region. The right side of the first driving channel region can correspond to the first low resistance region B11, and the left side of the first driving channel region can correspond to the second low resistance region C11.

[0150] like Figure 10 As shown, the first to third switching semiconductor layers A12, A22, and A32 of the first to third switching transistors M12, M22, and M32 can extend in the x-direction to intersect with the first branch SL-B. Some of the switching semiconductor layers can intersect with data lines.

[0151] In an embodiment, such as Figure 10 and Figure 12A As shown, the first switching semiconductor layer A12 may extend in the x-direction and intersect with the second data line DL2 disposed below the first switching semiconductor layer A12. The intersection region CR of the edge of the first switching semiconductor layer A12 and the edge of the second data line DL2 may overlap with or be covered by the first protective layer PL. Figure 12A As shown, the four intersection regions CR where the edge of the first switching semiconductor layer A12 intersects the edge of the second data line DL2 can overlap with or be covered by the first protective layer PL. (See reference...) Figure 3A and Figure 3B As described, Figure 12A The diagram shows that the first protective layer PL overlaps with and / or covers the two intersection regions CR. In another embodiment, as shown in the reference... Figure 6A As described, the four first protective layers PL may overlap with and / or cover the four intersection regions CR. In an alternative embodiment, the four intersection regions CR may overlap with and / or be covered by one first protective layer PL.

[0152] The first protective layer PL can also be arranged in the third switching transistor M32. For example... Figure 10As shown, the third switching semiconductor layer A32 can extend in the x-direction and intersect with the first data line DL1 and the second data line DL2 disposed beneath the third switching semiconductor layer A32. The intersection area between the edge of the third switching semiconductor layer A32 and the edges of the first data line DL1 and the second data line DL2 can overlap with or be covered by the first protective layer PL. The first protective layer PL can overlap with or cover the intersection area between the edge of the third switching semiconductor layer A32 and the edge of the first data line DL1, and also overlap with or cover the intersection area between the edge of the third switching semiconductor layer A32 and the edge of the second data line DL2.

[0153] In the plan view, the first protective layer PL can have an isolated shape. Each of the first protective layers PL can cover and overlap with the intersection of the edge of the first switching semiconductor layer A12 and the edge of the second data line DL2, the intersection of the edge of the third switching semiconductor layer A32 and the edge of the first data line DL1, and the intersection of the edge of the third switching semiconductor layer A32 and the edge of the second data line DL2.

[0154] The second protective layer PL' may overlap with or cover the intersection region between the edge of the first driving semiconductor layer A11 and the edge of the electrode disposed thereunder. In an embodiment, the second protective layer PL' may overlap with or cover the intersection region between the edge of the first driving semiconductor layer A11 and the edge of the first sub-electrode CE2b of the first storage capacitor Cst1.

[0155] refer to Figure 10 and Figure 12B The first driving semiconductor layer A11 can extend in the x direction and is connected to the second storage capacitor Cst2 (reference). Figure 7 The first driving gate electrode G11 is arranged below a portion of the first driving semiconductor layer A11 (e.g., the first sub-electrode CE2b), where the edge of the first driving semiconductor layer A11 intersects with the first sub-electrode CE2b. The intersection region of the first driving semiconductor layer A11 and the first sub-electrode CE2b may overlap with or be covered by the second protective layer PL'. The second protective layer PL' may be integrated with the first driving gate electrode G11 as a whole. In other words, a portion of the first driving gate electrode G11 may include the second protective layer PL'. When the intersection region of the edge of the first driving semiconductor layer A11 and the edge of the first sub-electrode CE2b overlaps with or is covered by the second protective layer PL', it may mean that the intersection region of the edge of the first driving semiconductor layer A11 and the edge of the first sub-electrode CE2b overlaps with or is covered by the first driving gate electrode G11.

[0156] Figure 12BThe structure shown is also applicable to the structure around the second driving semiconductor layer A21 and the structure around the third driving semiconductor layer A31. In the embodiment, as... Figure 10 As shown, the second driving semiconductor layer A21 can be electrically connected to the second driving transistor M21 (reference). Figure 7 The second storage capacitor Cst2 (reference) Figure 7 The first sub-electrode CE2b of the second driving semiconductor layer A21 intersects with the first sub-electrode CE2b of the second storage capacitor Cst2. The intersection region of the edge of the second driving semiconductor layer A21 and the edge of the first sub-electrode CE2b of the second storage capacitor Cst2 may also overlap with or be covered by the second protective layer PL'. Similarly, the second protective layer PL' may intersect with the third driving semiconductor layer A31 and be electrically connected to the third driving transistor M31 (see reference). Figure 7 The cross region of the first sub-electrode CE2b of the third storage capacitor Cst3 overlaps with or covers the cross region.

[0157] Figure 13B The first protective layer PL and the second protective layer PL' are shown arranged in the cross zone CR.

[0158] Reference Figure 13B Referring to a cross-section of the pixel circuit taken along line A-A', the first protective layer PL may overlap with or cover the intersection region CR of the edge of the first switching semiconductor layer A12 and the edge of the second data line DL2. The first protective layer PL may extend to traverse the edge DL2-E of the second data line DL2 in the extension direction (x direction) of the first switching semiconductor layer A12. Similarly, referring to a cross-section of the pixel circuit taken along line B-B', the second protective layer PL' may overlap with or cover the intersection region CR of the edge of the first driving semiconductor layer A11 and the edge of the first sub-electrode CE2b. The second protective layer PL' may extend to traverse the edge CE2b-E of the first sub-electrode CE2b in the extension direction (x direction) of the first driving semiconductor layer A11.

[0159] The first protective layer PL and the second protective layer PL' may each comprise two layers. In an embodiment, the first protective layer PL and the second protective layer PL' may each comprise a first sublayer L1 and L1' and a second sublayer L2 and L2' on top of the first sublayers L1 and L1'. The first sublayers L1 and L1' may comprise an insulating material such as an inorganic insulating material. The second sublayers L2 and L2' may comprise a conductive material such as a metal.

[0160] The first protective layer PL and the second protective layer PL' can be provided using the same masking process as that used to form the first branch SL-B, the second branch CL-B, and the first capacitor electrode CE1. In this case, the first sublayers L1 and L1' of the first protective layer PL and the second protective layer PL' may include the same material as the gate insulating layer 203. The second sublayers L2 and L2' of the first protective layer PL and the second protective layer PL' may include the same material as the gate electrode. In an embodiment, the first sublayers L1 and L1' may include inorganic insulating materials such as silicon nitride, silicon oxide, and / or silicon oxynitride and include a single-layer structure or a multilayer structure containing the aforementioned materials. In an embodiment, for example, the second sublayers L2 and L2' may include at least one of molybdenum (Mo), copper (Cu), and titanium (Ti) and include a single-layer structure or a multilayer structure containing the aforementioned materials.

[0161] The first protective layer PL may overlap with the second low-resistance region C12 of the first switching semiconductor layer A12. The first sub-layer L1 and the second sub-layer L2 of the first protective layer PL may each be separate from the gate insulating layer 203 and the first switching gate electrode G12. The first sub-layer L1 of the first protective layer PL may be disposed in the same layer as the gate insulating layer 203 and may comprise the same material as the gate insulating layer 203. (Reference) Figure 7 , Figure 10 and Figure 13B The second sublayer L2 of the first protective layer PL may include the same material as the first capacitor electrode CE1 of the first storage capacitor Cst1, the first drive gate electrode G11 of the first drive transistor M11, and / or the first switch gate electrode G12. Since the first switch gate electrode G12 is part of the first branch SL-B, the second sublayer L2 of the first protective layer PL may include the same material as the first branch SL-B.

[0162] The second protective layer PL' may overlap with the first driving channel region of the first driving semiconductor layer A11. The first sub-layer L1' and the second sub-layer L2' of the second protective layer PL' may be integrally provided with the gate insulating layer 203 and the first driving gate electrode G11, respectively. The first sub-layer L1' of the second protective layer PL' may be disposed in the same layer as the gate insulating layer 203 and may include the same material as the gate insulating layer 203. (Reference) Figure 7 , Figure 10 and Figure 13BThe second sublayer L2' of the second protective layer PL' may include the same material as the first capacitor electrode CE1 of the first storage capacitor Cst1, the first drive gate electrode G11 of the first drive transistor M11, and / or the first switch gate electrode G12. Since the first switch gate electrode G12 is part of the first branch SL-B, the second sublayer L2' of the second protective layer PL' may include the same material as the first branch SL-B.

[0163] Despite Figure 13B The diagram illustrates providing the first protective layer PL and the second protective layer PL' using the same masking process as that used to form the first branch SL-B, the second branch CL-B, and the first capacitor electrode CE1; however, the invention is not limited thereto. In another embodiment, the first protective layer PL and the second protective layer PL' can be provided using a different masking process than that used to form the first branch SL-B, the second branch CL-B, and the first capacitor electrode CE1. In this case, as shown in reference... Figure 4A As described, the first protective layer PL and the second protective layer PL' can be a single layer comprising first sublayers L1 and L1'. In embodiments, the first protective layer PL and the second protective layer PL' may comprise only an insulating material such as an inorganic insulating material.

[0164] refer to Figure 7 , Figure 11 and Figure 13C An intermediate insulating layer 205 is disposed on the first substrate 10. The intermediate insulating layer 205 may include an inorganic insulating material such as silicon nitride, silicon oxide, and / or silicon oxynitride.

[0165] Then, scan lines SL, control lines CL, auxiliary lines AL, the second sub-electrode CE2t of the second capacitor electrode CE2, and the first to ninth connectors NM1, NM2, NM3, NM4, NM5, NM6, NM7, NM8, and NM9 can be disposed on the intermediate insulating layer 205. In this regard, Figure 13C The diagram shows the second sub-electrode CE2t and the first to third connectors NM1, NM2, and NM3. In embodiments, for example, the scan line SL, control line CL, auxiliary line AL, the second sub-electrode CE2t of the second capacitor electrode CE2, and the first to ninth connectors NM1, NM2, NM3, NM4, NM5, NM6, NM7, NM8, and NM9 may include at least one of molybdenum (Mo), copper (Cu), and titanium (Ti), and may include a single-layer structure or a multi-layer structure comprising the aforementioned materials.

[0166] The scan line SL can be electrically connected to the first branch SL-B via the twelfth contact hole CT12 defined in the intermediate insulating layer 205. The control line CL can be electrically connected to the second branch CL-B via the thirteenth contact hole CT13 defined in the intermediate insulating layer 205.

[0167] The auxiliary line AL can be electrically connected to the drive voltage line VDL and the common voltage line VSL. In an embodiment, Figure 11 The auxiliary line AL arranged in the upper part can be connected to the drive voltage line VDL through the fourteenth contact hole CT14 defined in the intermediate insulating layer 205. The auxiliary line AL arranged in the lower part can be connected to the common voltage line VSL through the fifteenth contact hole CT15 defined in the intermediate insulating layer 205.

[0168] The second sub-electrode CE2t, corresponding to the first to third storage capacitors Cst1, Cst2, and Cst3, can be arranged in the y-direction. The second sub-electrode CE2t can overlap with the first sub-electrode CE2b and be connected to the first sub-electrode CE2b through the tenth contact hole CT10 defined in the intermediate insulating layer 205. The first sub-electrode CE2b and the second sub-electrode CE2t can have the same voltage level.

[0169] like Figure 11 and Figure 13C As shown, the first low-resistance region B11 of the first driving semiconductor layer A11 (reference) Figure 13C A portion of the second sub-electrode CE2t can be connected via a first contact hole CT1 defined in the intermediate insulating layer 205. A second low-resistance region C11 of the first driving semiconductor layer A11 can be connected to the first connector NM1 via a second contact hole CT2 defined in the intermediate insulating layer 205. Since the first connector NM1 is connected to the driving voltage line VDL via the eleventh contact hole CT11, the first connector NM1 can have the same voltage level as the driving voltage line VDL.

[0170] like Figure 11 and Figure 13C As shown, the first low-resistance region B12 of the first switching semiconductor layer A12 can be connected to a portion of the second connector NM2 via a third contact hole CT3 defined in the intermediate insulating layer 205. Another portion of the second connector NM2 can be connected to the first capacitor electrode CE1 via a fourth contact hole CT4. The second low-resistance region C12 of the first switching semiconductor layer A12 can be connected to a portion of the third connector NM3 via a fifth contact hole CT5 defined in the intermediate insulating layer 205. Another portion of the third connector NM3 can be connected to the first data line DL1 via a sixth contact hole CT6.

[0171] A first low-resistance region of the first initialization sensing semiconductor layer A13 can be connected to a portion of the fourth connector NM4 via a seventh contact hole CT7 defined in the intermediate insulating layer 205. The fourth connector NM4 can be connected to the initialization sensing line ISL via an eighth contact hole CT8. The fourth connector NM4 can have the same voltage level as the initialization sensing line ISL.

[0172] The second low-resistance region of the first initialization sensing semiconductor layer A13 can be connected to the second sub-electrode CE2t of the second capacitor electrode through the ninth contact hole CT9 defined in the intermediate insulating layer 205.

[0173] refer to Figure 11 and Figure 13C The predetermined structure of each of the first driving semiconductor layer A11, the first switching semiconductor layer A12, the first initialization sensing semiconductor layer A13, and the second sub-electrode CE2t of the first storage capacitor may be the same as the structure of each of the second driving semiconductor layer A21, the second switching semiconductor layer A22, the second initialization sensing semiconductor layer A23, and the second sub-electrode CE2t of the second storage capacitor.

[0174] In this embodiment, the first low-resistance region and the second low-resistance region of the second driving semiconductor layer A21 can be connected to the first connector NM1 and the second storage capacitor Cst2 (reference) respectively through contact holes. Figure 7 The second sub-electrode CE2t of the second switching semiconductor layer A22. The first low-resistance region and the second low-resistance region of the second switching semiconductor layer A22 can be connected to the fifth connector NM5 and the sixth connector NM6 respectively through contact holes. The fifth connector NM5 can be connected to the second storage capacitor Cst2 (reference) through contact holes. Figure 7 The first capacitor electrode CE1, and the sixth connector NM6 can be connected to the second data line DL2 through a contact hole. The first low-resistance region and the second low-resistance region of the second initialization sensing semiconductor layer A23 can be connected to the fourth connector NM4 and the second storage capacitor Cst2 (reference) through contact holes, respectively. Figure 7 The second sub-electrode CE2t.

[0175] Similarly, the structures of the third driving semiconductor layer A31, the third switching semiconductor layer A32, the third initialization sensing semiconductor layer A33, and the second sub-electrode CE2t of the third storage capacitor are the same as those referenced above. Figure 11 and Figure 13C The first driving semiconductor layer A11, the first switching semiconductor layer A12, the first initialization sensing semiconductor layer A13, and the second sub-electrode CE2t of the first storage capacitor have the same structure.

[0176] The first low-resistance region and the second low-resistance region of the third driving semiconductor layer A31 can be connected to the first connector NM1 and the third storage capacitor Cst3, respectively (see reference). Figure 7 The second sub-electrode CE2t of the third switching semiconductor layer A32. The first and second low-resistance regions of the third switching semiconductor layer A32 can be connected to the seventh connector NM7 and the eighth connector NM8 respectively through contact holes. The seventh connector NM7 can be connected to the third storage capacitor Cst3 (reference) through contact holes. Figure 7 The first capacitor electrode CE1, and the eighth connector NM8 can be connected to the third data line DL3 through a contact hole. The first low-resistance region and the second low-resistance region of the third initialization sensing semiconductor layer A33 can be connected to the fourth connector NM4 and the third storage capacitor Cst3 (see reference). Figure 7 The second sub-electrode CE2t.

[0177] The common voltage line VSL can be connected to the sub-line s-VSL to reduce the resistance of the common voltage line VSL itself. The sub-line s-VSL can be set at the reference... Figure 13C The intermediate insulating layer 205 described (reference) Figure 13C On, and Figure 11 The process duration shown is provided simultaneously.

[0178] refer to Figure 13D In reference Figure 11 and Figure 13C The described structure has a through-hole insulating layer 207, and an organic light-emitting diode can then be disposed on the through-hole insulating layer 207. In this regard, Figure 13D The first organic light-emitting diode OLED1 is shown on the through-hole insulating layer 207.

[0179] The through-hole insulating layer 207 may include an organic insulating material. In embodiments, the organic insulating material may include general polymers such as polymethyl methacrylate (“PMMA”) or polystyrene (“PS”), polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorinated polymers, p-xylene polymers, vinyl alcohol polymers, or combinations thereof.

[0180] In one embodiment, the first electrode 211 of the first organic light-emitting diode (OLED1) may include a transparent conductive oxide, such as indium tin oxide (“ITO”), indium zinc oxide (“IZO”), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (“IGO”), or aluminum zinc oxide (“AZO”). In another embodiment, the first electrode 211 of the first organic light-emitting diode (OLED1) may include a reflective layer comprising magnesium (Mg), silver (Ag), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or combinations thereof. In another embodiment, the first electrode 211 of the first organic light-emitting diode (OLED1) may further include a layer on / below the reflective layer, and for example, this layer may include ITO, IZO, ZnO, or In2O3. In another embodiment, the first electrode 211 of the first organic light-emitting diode (OLED1) may have a three-layer structure consisting of a stacked ITO layer, an Ag layer, and an ITO layer.

[0181] The edge of the first electrode 211 may overlap with or be covered by the top insulating layer 209. An opening 209op that overlaps with the first electrode 211 may be defined in the top insulating layer 209. The opening 209op of the top insulating layer 209 may define the emission region of the first organic light-emitting diode OLED1.

[0182] The emitting layer 221 can overlap with the first electrode 211 through the opening 209op. The emitting layer 221 may comprise a polymer or low molecular weight organic material that emits blue light. The emitting layer 221 may completely cover the first substrate 10. In an embodiment, the emitting layer 221 may be provided integrally to completely cover the reference electrode. Figure 8 The first to third organic light-emitting diodes OLED1, OLED2 and OLED3 described (refer to) Figure 8 ).

[0183] The second electrode 231 of the first organic light-emitting diode (OLED) 1 can be a semi-transparent or transmissive electrode. In embodiments, for example, the second electrode 231 can be a semi-transparent electrode comprising an ultrathin layer containing magnesium (Mg), silver (Ag), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or combinations thereof. In embodiments, the second electrode 231 of the first organic light-emitting diode (OLED) 1 can include a transparent conductive oxide such as ITO, IZO, zinc oxide (ZnO), indium oxide (In2O3), IGO, or AZO.

[0184] The second electrode 231 can be provided to completely cover the first substrate 10. In an embodiment, the second electrode 231 can be provided integrally to completely cover the reference. Figure 8The first to third organic light-emitting diodes OLED1, OLED2 and OLED3 described (refer to) Figure 8 ).

[0185] In the embodiments, although Figures 7 to 13D The first protective layer PL is shown in the intersection area of ​​the edge of the switching transistor (e.g., the first switching semiconductor layer A12 and the third switching semiconductor layer A32 of the first switching transistor M12 and the third switching transistor M32) and the edge of the data line below it, but it can be protected by the following Figure 14 and Figure 16 The connector shown solves the problem mentioned above. Figures 3A to 5 The formation of the cavity 205v in the intermediate insulating layer 205 and its problems are described.

[0186] Figure 14 This is a plan view of the pixel circuitry of another embodiment of the light-emitting panel, and Figure 15 It is connected to Figure 14 A plan view of another embodiment of the light-emitting diode in the pixel circuit. In this embodiment, Figure 15 Describe the case where the light-emitting diode is an organic light-emitting diode.

[0187] Figure 14 The pixel circuit shown can have the same characteristics as the reference. Figure 7 The pixel circuit described has the same structure. Scan lines SL, control lines CL, and auxiliary lines AL can extend in the x-direction. In the embodiment, the first to third data lines DL1, DL2, and DL3 can be arranged in the x-direction intersecting the y-direction and extending in the y-direction. Initialization sensing line ISL, drive voltage line VDL, and common voltage line VSL can extend in the y-direction.

[0188] Two adjacent common voltage lines VSL can be separated from each other. The first to third data lines DL1, DL2, and DL3, the initialization sensing line ISL, and the drive voltage line VDL can be arranged between the two adjacent common voltage lines VSL. The initialization sensing line ISL and the drive voltage line VDL can be adjacent to each other while also being adjacent to one of the common voltage lines VSL. The first to third data lines DL1, DL2, and DL3 can be adjacent to each other while also being adjacent to the other common voltage line VSL. The initialization sensing line ISL and the drive voltage line VDL can be arranged on one side (e.g., the left side) around the first to third storage capacitors Cst1, Cst2, and Cst3, and the first to third data lines DL1, DL2, and DL3 can be arranged on the other side (e.g., the right side).

[0189] refer to Figure 14 and Figure 15The first organic light-emitting diode OLED1 can be electrically connected to the first pixel circuit through the first through-hole VH1. The first pixel circuit may include a first driving transistor M11, a first switching transistor M12, a first initialization sensing transistor M13, and a first storage capacitor Cst1.

[0190] The first driving transistor M11 may include a first driving semiconductor layer A11 and a first driving gate electrode G11. The predetermined structure of the first driving transistor M11 may be similar to that described above. Figures 7 to 11 The first driving transistor M11 described has the same predetermined structure.

[0191] The first switching transistor M12 may include a first switching semiconductor layer A12 and a first switching gate electrode G12. The predetermined structure of the first switching transistor M12 may be similar to that described above. Figures 7 to 11 The first switching transistor M12 described has the same predetermined structure.

[0192] The first initialization sensing transistor M13 may include a first initialization sensing semiconductor layer A13 and a first initialization sensing gate electrode G13. The predetermined structure of the first initialization sensing transistor M13 may be similar to that described above. Figures 7 to 11 The first initialization sensing transistor M13 described has the same predetermined structure.

[0193] The first storage capacitor Cst1 may include a first capacitor electrode CE1 and a second capacitor electrode CE2. The second capacitor electrode CE2 may include a first sub-electrode CE2b and a second sub-electrode CE2t. The first sub-electrode CE2b may be disposed below the first capacitor electrode CE1, and the second sub-electrode CE2t may be disposed on the first capacitor electrode CE1. The electrical connection relationship between the electrodes of the first storage capacitor Cst1 and the transistor is the same as described above. Figures 7 to 11 The described electrical connections are the same.

[0194] The second organic light-emitting diode (OLED2) can be electrically connected to the second pixel circuit through the second via VH2. The second pixel circuit may include a second driving transistor M21, a second switching transistor M22, a second initialization sensing transistor M23, and a second storage capacitor Cst2. Similarly, the third organic light-emitting diode (OLED3) can be electrically connected to the third pixel circuit through the third via VH3. The third pixel circuit may include a third driving transistor M31, a third switching transistor M32, a third initialization sensing transistor M33, and a third storage capacitor Cst3.

[0195] The second driving transistor M21 and the third driving transistor M31 may have the same structure as the first driving transistor M11. The second switching transistor M22 and the third switching transistor M32 may have the same structure as the first switching transistor M12. The second initialization sensing transistor M23 and the third initialization sensing transistor M33 may have the same structure as the first initialization sensing transistor M13.

[0196] The electrical connection structure between the first to third driving transistors M11, M21, and M31, the first to third switching transistors M12, M22, and M32, the first to third initialization sensing transistors M13, M23, and M33 and adjacent electrodes (e.g., the first to eighth connectors NM1, NM2, NM3, NM4, NM5, NM6, NM7, and NM8, the first capacitor electrode CE1, the first sub-electrode CE2b, and the second sub-electrode CE2t) is the same as described above. Figures 7 to 13D The described electrical connection structures are the same.

[0197] and Figure 7 The structures shown are different. Figure 14 The diagram illustrates a structure in which multiple first connectors NM1 are connected to a drive voltage line VDL. Sub-drive voltage lines s-VDL can be electrically connected to the drive voltage line VDL while overlapping it to reduce the resistance of the drive voltage line VDL itself. To reduce the resistance of the common voltage line VSL itself, first sub-common voltage lines s-VSL and second sub-common voltage lines s'-VSL can be electrically connected to the common voltage line VSL while overlapping it. The sub-drive voltage lines s-VDL and second sub-common voltage lines s'-VSL can be provided simultaneously during the process of forming the gate electrode and / or the first capacitor electrode CE1, and can comprise the same material as the gate electrode and / or the first capacitor electrode CE1.

[0198] For reference Figure 14 The pixel circuit described is the same as the one referenced above. Figure 7 Unlike the pixel circuit described, the switching semiconductor layer may not intersect with one of the data lines arranged beneath it, and therefore, the above reference can be prevented. Figures 3A to 5 The formation of the cavity 205v in the intermediate insulating layer 205 and its problems are described. For this, refer to... Figure 16 Described in the relevant section.

[0199] For reference Figure 14The described pixel circuit allows the driving semiconductor layer to intersect with the driving voltage line VDL, and the intersection region between edges can overlap with or be covered by the protective layer PL. Furthermore, the driving semiconductor layer can intersect with a portion of the second capacitor electrode (e.g., the second sub-electrode CE2t), and the intersection region between edges can overlap with or be covered by the protective layer PL'. For this, see reference... Figure 18 Described in the relevant section.

[0200] Figure 16 yes Figure 14 A cross-sectional view of an embodiment of region XVI, and Figure 17 It is along Figure 16 A cross-sectional view of another embodiment of the region XVI intercepted by line C-C'.

[0201] refer to Figure 16 and Figure 17 The third switching semiconductor layer A32 of the third switching transistor M32 can extend in the x direction and overlap with the third switching gate electrode G32 corresponding to a portion of the first branch SL-B.

[0202] The third switch semiconductor layer A32 may include a channel region, a first low-resistance region B32, and a second low-resistance region C32. The channel region overlaps with the third switch gate electrode G32, and the first low-resistance region B32 and the second low-resistance region C32 may be respectively disposed on opposite sides of the channel region. The first low-resistance region B32 can be connected to the seventh connector NM7 through the contact hole of the intermediate insulating layer 205, and as... Figure 14 As shown, the seventh connector NM7 can be connected to the first capacitor electrode CE1 of the third storage capacitor Cst3. The second low-resistance region C32 can be connected to one side of the eighth connector NM8 through the contact hole of the intermediate insulating layer 205. The eighth connector NM8 can be connected to the third data line DL3 through the contact hole of the intermediate insulating layer 205 while extending in the x-direction to intersect with the first data line DL1 and the second data line DL2.

[0203] The switching semiconductor layer (e.g., the third switching semiconductor layer A32) can be separated from the third data line DL3. The first data line DL1 and the second data line DL2 are located between the switching semiconductor layer and the third data line DL3, and the switching semiconductor layer is electrically connected to the data line DL3 via the eighth connector NM8. Therefore, since the third switching semiconductor layer A32 does not cross other data lines (e.g., the first data line DL1 and the second data line DL2), the cavity 205v of the intermediate insulating layer 205 (refer to...) can be prevented. Figure 5 The appearance of ) and the above reference Figure 5 The description refers to damage to the semiconductor layer.

[0204] refer to Figure 16 and Figure 17 The described structure is also applicable to other switching transistors. In the embodiment, the connection structure of the second switching transistor M22 and the second data line DL2 can be the same as described above. Figure 16 and Figure 17 The structures described are basically the same.

[0205] Figure 18 yes Figure 14 A cross-sectional view of another embodiment of region XVIII, and Figure 19 It is along Figure 18 A cross-sectional view of another embodiment of region XVIII intercepted by line D-D'.

[0206] refer to Figure 18 and Figure 19 The first driving semiconductor layer A11 of the first driving transistor M11 may extend in the x direction and overlap with the first driving gate electrode G11 which is electrically connected and / or physically (integrally) connected to the first capacitor electrode CE1.

[0207] The first driving semiconductor layer A11 may include a channel region, a first low-resistance region B11, and a second low-resistance region C11. The channel region may overlap with the first driving gate electrode G11, and the first low-resistance region B11 and the second low-resistance region C11 may be respectively disposed on opposite sides of the channel region.

[0208] The first low-resistance region B11 can be connected to the second sub-electrode CE2t of the first storage capacitor Cst through the contact hole of the intermediate insulating layer 205. The second low-resistance region C11 can be connected to the first connector NM1 through the contact hole of the intermediate insulating layer 205. Figure 14 As shown, the first connector NM1 can be connected to the drive voltage line VDL.

[0209] The driving semiconductor layer (e.g., the first driving semiconductor layer A11) may intersect with the lines and / or electrodes disposed thereunder.

[0210] The first driving semiconductor layer A11 may intersect with the driving voltage line VDL, and the intersection area of ​​the edge of the first driving semiconductor layer A11 and the edge of the driving voltage line VDL may overlap with or be covered by the first protective layer PL, which has an isolated shape. Figure 19 As shown, the protective layer PL may have a stacked structure of a first sublayer L1 and a second sublayer L2. The first sublayer L1 comprises an insulating material such as an inorganic insulating material, and the second sublayer L2 comprises a metallic material. In an embodiment, the first sublayer L1 may comprise the same material as the gate insulating layer 203, and the second sublayer L2 may comprise the same material as the first driving gate electrode G11.

[0211] The first driving semiconductor layer A11 may intersect with the first sub-electrode CE2b of the first storage capacitor Cst1 disposed beneath the first driving semiconductor layer A11. The intersection region of the edge of the first driving semiconductor layer A11 and the edge of the first sub-electrode CE2b may overlap with or be covered by the second protective layer PL', which may have a stacked structure of the first sub-layer L1' and the second sub-layer L2'. In an embodiment, the first sub-layer L1' may include the same material as the gate insulating layer 203 and is integral with the gate insulating layer 203 beneath the first driving gate electrode G11 as a whole. The second sub-layer L2' may include the same material as the first driving gate electrode G11 and is integral with the first driving gate electrode G11 as a whole. In other words, the second sub-layer L2' of the second protective layer PL' may include the first driving gate electrode G11. In an alternative embodiment, the first driving gate electrode G11 may include the second sub-layer L2' of the second protective layer PL'. Since the first protective layer PL and the second protective layer PL' overlap with or cover the intersection region, the above reference can be prevented or reduced. Figure 5 The problem described.

[0212] refer to Figure 18 and Figure 19 The described structure is also applicable to other driving transistors. In the embodiment, the intersection region of the edge of the driving semiconductor layer of the second driving transistor M21 and the third driving transistor M31 and the edge of the driving voltage line VDL can overlap with or be covered by the first protective layer PL. Similarly, the intersection region of the edge of the driving semiconductor layer of the second driving transistor M21 and the third driving transistor M31 and the edge electrically connected to the first sub-electrode CE2b of the corresponding driving semiconductor layer can overlap with or be covered by the second protective layer PL'. Its predetermined structure is similar to... Figure 18 and Figure 19 The pre-defined structures described in the text are basically the same.

[0213] By means of embodiments, etchant can be prevented from advancing through cavities during the manufacturing process of pixel circuits electrically connected to display elements, and thus damage to the semiconductor layer of transistors can be prevented. However, the scope of the invention is not limited to this effect.

[0214] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for limiting purposes. The description of features or advantages within each embodiment should generally be considered applicable to other similar features or advantages in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the invention.

Claims

1. A display device, comprising: A driving voltage line extending in the first direction; Multiple data lines extending in the first direction; A first driving transistor electrically connected to the driving voltage line; A first switching transistor electrically connected to the first driving transistor, the first switching transistor including a first switching semiconductor layer extending in a second direction intersecting the first direction and a first switching gate electrode overlapping a channel region of the first switching semiconductor layer; as well as A first storage capacitor electrically connected to the first driving transistor and the first switching transistor. The first switching semiconductor layer is electrically connected to a first data line among the plurality of data lines, and the first switching semiconductor layer intersects with a second data line disposed between the channel region and the first data line. The intersection of the edge of the first switch semiconductor layer and the edge of the second data line overlaps with the first protective layer.

2. The display device according to claim 1, wherein, The first protective layer includes a first sublayer containing insulating material.

3. The display device according to claim 2, wherein, The first protective layer further includes a second sublayer on the first sublayer and includes a metallic material.

4. The display device according to claim 3, wherein, The material of at least one of the first switching gate electrode of the first switching transistor, the first driving gate electrode of the first driving transistor, and the first capacitor electrode of the first storage capacitor is the same as the metal material of the second sublayer.

5. The display device according to any one of claims 1-4, further comprising: A second driving transistor electrically connected to the driving voltage line; and The second switching transistor is electrically connected to the second driving transistor. The second data line is electrically connected to the second switching transistor.

6. The display device according to any one of claims 1-4, wherein, The first protective layer has an isolated shape.

7. The display device according to claim 1, wherein, The first driving transistor includes: First driving semiconductor layer; and The first driving gate electrode overlaps with the channel region of the first driving semiconductor layer. Wherein, the first driving semiconductor layer overlaps and intersects with one of the plurality of electrodes of the first storage capacitor, and The intersection region between the edge of the first driving semiconductor layer and the edge of one of the plurality of electrodes of the first storage capacitor overlaps with the second protective layer.

8. The display device according to claim 7, wherein, The second protective layer includes a first sublayer comprising an insulating material, and The material of the gate insulating layer between the channel region of the first driving semiconductor layer and the first driving gate electrode is the same as the insulating material of the first sublayer.

9. The display device according to claim 8, wherein, The second protective layer further includes a second sublayer on top of the first sublayer.

10. The display device according to claim 9, wherein, The second sub-layer is integrated with the first driving gate electrode.

11. A display device, comprising: A driving voltage line extending in the first direction; Multiple data lines extending in the first direction; A first driving transistor electrically connected to the driving voltage line, the first driving transistor including a first driving semiconductor layer extending in a second direction intersecting the first direction and a first driving gate electrode overlapping a channel region of the first driving semiconductor layer; A first switching transistor electrically connected to the first driving transistor; as well as A first storage capacitor electrically connected to the first driving transistor and the first switching transistor. Wherein, the first driving semiconductor layer intersects with at least one of the driving voltage line and the second capacitor electrode of the first storage capacitor, and The intersection area between the edge of the first driving semiconductor layer and the edge of the at least one of them overlaps with the protective layer.

12. The display device according to claim 11, wherein, A portion of the first driving semiconductor layer overlaps with and intersects the driving voltage line, and The protective layer includes a first protective layer that overlaps with the intersection region between the edge of the driving voltage line and the edge of the portion of the first driving semiconductor layer.

13. The display device according to claim 12, wherein, The first protective layer has an isolated shape.

14. The display device according to claim 13, wherein, The first protective layer includes a first sublayer containing insulating material.

15. The display device according to claim 14, wherein, The first protective layer further includes: The second sublayer is disposed on the first sublayer and comprises the same material as one of the first switching gate electrode of the first switching transistor, the first driving gate electrode of the first driving transistor, and the first capacitor electrode of the first storage capacitor.

16. The display device according to claim 11, wherein, A portion of the first driving semiconductor layer overlaps with and intersects with the second capacitor electrode of the first storage capacitor, and The protective layer includes a second protective layer that overlaps with the intersection region between the edge of the portion of the first driving semiconductor layer and the edge of the second capacitor electrode of the first storage capacitor.

17. The display device according to claim 16, wherein, The second protective layer includes a first sublayer comprising an insulating material, and The material of the gate insulating layer between the channel region of the first driving semiconductor layer and the first driving gate electrode is the same as the insulating material of the first sublayer.

18. The display device according to claim 17, wherein, The second protective layer further includes a second sublayer on top of the first sublayer.

19. The display device according to claim 18, wherein, The second sub-layer is integrated with the first driving gate electrode.

20. The display device according to claim 11, wherein, The first switching transistor includes a first switching semiconductor layer extending in the second direction. The first switching semiconductor layer is electrically connected to a first data line among the plurality of data lines, and intersects with a second data line disposed between the channel region of the first switching semiconductor layer and the first data line. The intersection area between the edge of the first switch semiconductor layer and the edge of the second data line overlaps with the third protective layer.

21. The display device according to claim 20, wherein, The third protective layer has an isolated shape.

22. The display device according to claim 11, wherein, The first switching transistor includes a first switching semiconductor layer extending in the second direction and electrically connected to a first data line among the plurality of data lines, and The first switching semiconductor layer is connected to a connector, which crosses a second data line disposed between the first data line and the first switching semiconductor layer.

23. A display device, comprising: A driving voltage line extending in the first direction; Multiple data lines extending in the first direction; A first driving transistor electrically connected to the driving voltage line; A first switching transistor electrically connected to the first driving transistor, the first switching transistor including a first switching semiconductor layer extending in a second direction intersecting the first direction and a first switching gate electrode overlapping a channel region of the first switching semiconductor layer; as well as A first storage capacitor electrically connected to the first driving transistor and the first switching transistor. The first switching semiconductor layer is electrically connected to a first data line among the plurality of data lines, and is electrically connected to the first data line via a connector that intersects with a second data line arranged between the first data line and the first switching semiconductor layer.

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