A display device

Abstract

The present application discloses a display device for avoiding uneven brightness of blocks and improving display effects. The display device provided by the present application includes: a display panel, a plurality of cascaded driver chips; each driver chip includes: a plurality of display signal input terminals, a display signal output terminal corresponding to the display signal input terminal, and at least one voltage compensation circuit; each voltage compensation circuit is electrically connected to a display signal input terminal and a display signal output terminal respectively; except for the last-level driver chip, each display signal output terminal of each driver chip is electrically connected to each display signal input terminal of the adjacent next level in a one-to-one correspondence; the voltage compensation circuit is used to: perform voltage compensation on the display signal according to the display signal received by the display signal input terminal, generate a compensated display signal, and output the compensated display signal to the display signal output terminal, so that the difference between the same compensated display signals output by any adjacent driver chips is less than a preset value.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display device. Background Art

[0002] In order to reduce the seams of spliced ​​display screens and improve the display effect of spliced ​​products, spliced ​​screen products usually adopt a narrow frame design. The prior art spliced ​​screen usually needs to set up multiple driver chips. The driver chip is bound to the display panel through a chip on flex film (COF), and a printed circuit board (PCB) is set at the edge of the display screen to provide signals to the driver chip. The display screen has edges extending along a first direction (X direction) and a second direction (Y direction). One of the prior art solutions requires PCBs to be set at the edges in the X direction and the edges in the Y direction, which is costly and has a complicated process flow. Another prior art solution removes the PCB at the edge in the Y direction, but it will cause some signal lines to have a larger impedance between different COFs, some signal voltage drops to be larger, and the signal voltage difference output by adjacent driver chips to be larger, which is prone to uneven block brightness and affects the display effect. Summary of the invention

[0003] The embodiment of the present application provides a display device to avoid uneven brightness of blocks and improve display effect.

[0004] An embodiment of the present application provides a display device, the display device comprising: a display panel, and a plurality of cascaded driver chips bound to one side of the display panel;

[0005] Each of the driving chips comprises: a plurality of display signal input terminals, display signal output terminals corresponding one to one to the display signal input terminals, and at least one voltage compensation circuit;

[0006] Each of the voltage compensation circuits is electrically connected to one of the display signal input terminals and one of the display signal output terminals respectively;

[0007] Except for the last-stage driving chip, each display signal output terminal of each driving chip is electrically connected to each display signal input terminal of the next adjacent stage in a one-to-one correspondence;

[0008] The voltage compensation circuit is used to: perform voltage compensation on the display signal according to the display signal received by the display signal input terminal to generate a compensated display signal, and output the compensated display signal to the display signal output terminal, so that the difference between the same compensated display signals output by any adjacent driving chips is less than a preset value.

[0009] In some embodiments, the voltage compensation circuit includes: a comparison unit;

[0010] The first input terminal of the comparison unit is electrically connected to one of the display signal input terminals, and the second input terminal of the comparison unit is electrically connected to the reference signal input terminal;

[0011] The comparison unit is used to determine the difference between the display signal and the reference signal according to the display signal received by the display signal input terminal and the reference signal received by the reference signal input terminal, and generate and output a voltage compensation signal of the display signal according to the difference between the display signal and the reference signal.

[0012] In some embodiments, the comparison unit includes: a comparator, and an operational amplifier;

[0013] The first input terminal of the comparator is electrically connected to one of the display signal input terminals, the second input terminal of the comparator is electrically connected to the reference signal input terminal, the output terminal of the comparator is electrically connected to the input terminal of the operational amplifier, and the output terminal of the operational amplifier outputs the voltage compensation value of the display signal.

[0014] In some embodiments, the voltage compensation circuit further includes: a low dropout linear regulator;

[0015] The input end of the low voltage difference linear regulator is electrically connected to the display signal input end, and the output end of the low voltage difference linear regulator is electrically connected to the first input end of the comparator.

[0016] In some embodiments, the voltage compensation circuit further includes: an adder;

[0017] The first input terminal of the adder is electrically connected to the output terminal of the comparison unit, the second input terminal of the adder is electrically connected to the display signal input terminal, and the output terminal of the adder is electrically connected to the display signal output terminal.

[0018] In some embodiments, the voltage compensation signals of each display signal generated by different driving chips have the same value.

[0019] In some embodiments, in different driving chips, the difference between the display signal input to the voltage compensation circuit and the signal input to the reference signal terminal is equal.

[0020] In some embodiments, the plurality of display signal input terminals include: a first power signal input terminal, a first voltage signal input terminal, and a second voltage signal input terminal;

[0021] At least one of the voltage compensation circuits includes: a first voltage compensation circuit electrically connected to the first power signal input terminal, a second voltage compensation circuit electrically connected to the first voltage signal input terminal, and a third voltage compensation circuit electrically connected to the second voltage signal input terminal.

[0022] In some embodiments, the display device further comprises: a chip-on-film circuit board; the driving chip is bound to the display panel via the chip-on-film circuit board;

[0023] The display panel includes: a display area, and a peripheral area outside the display area;

[0024] The peripheral area includes: a plurality of first binding terminals and a plurality of second binding terminals bound to each of the COF circuit boards, and a plurality of connecting leads;

[0025] The first binding terminals are electrically connected to the display signal input terminals in a one-to-one correspondence through the chip-on-film circuit board, and the second binding terminals are electrically connected to the display signal output terminals in a one-to-one correspondence through the chip-on-film circuit board;

[0026] The first binding terminal and the second binding terminal bound to the adjacent chip-on-film circuit board are electrically connected one-to-one through the connecting lead;

[0027] The connecting lead and the first binding terminal and the second binding terminal are located in different film layers.

[0028] In some embodiments, the display area includes: a source-drain electrode layer, a gate layer, and a transparent electrode layer;

[0029] The first binding terminal and the second binding terminal are arranged in the same layer as the source-drain electrode layer;

[0030] The connecting lead comprises: a first sub-lead arranged in the same layer as the gate layer, and a second sub-lead arranged in the same layer as the transparent electrode layer;

[0031] The extension direction of the first sub-lead intersects with the extension directions of the first binding terminal and the second binding terminal;

[0032] The first sub-lead is electrically connected to the first binding terminal and the second binding terminal respectively through the second sub-lead.

[0033] The display device provided in the embodiment of the present application has a plurality of driver chips cascaded, so that there is no need to provide signals to each driver chip by setting a printed circuit board, which can simplify the assembly process of the display device and save costs. In addition, a voltage compensation circuit is set in the driver chip. When a voltage drop occurs in the display signal during transmission, the voltage compensation circuit can compensate the voltage of the display signal, so that the difference in the voltage of the same display signal after compensation output by any adjacent driver chips is less than a preset value, avoiding a large difference in the voltage of the same display signal output by adjacent driver chips, avoiding uneven brightness of blocks, improving display effects, and enhancing user experience. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0035] Figure 1 A schematic diagram of a display device provided in an embodiment of the present application;

[0036] Figure 2 A schematic diagram of a driver chip in a display device provided in an embodiment of the present application;

[0037] Figure 3 A schematic diagram of another display device provided in an embodiment of the present application;

[0038] Figure 4 For example, the embodiments of the present application provide Figure 3 Cross-sectional view along line AA'. DETAILED DESCRIPTION

[0039] To make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme of the embodiments of the present application will be clearly and completely described below in conjunction with the drawings of the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all of the embodiments. And in the absence of conflict, the embodiments in the present application and the features in the embodiments can be combined with each other. Based on the described embodiments of the present application, all other embodiments obtained by ordinary technicians in the field without creative work belong to the scope of protection of this application.

[0040] Unless otherwise defined, the technical terms or scientific terms used in this application should be understood by people with ordinary skills in the field to which this application belongs. "First", "second" and similar words used in this application do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and other similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and other similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0041] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual proportions, but are only intended to illustrate the content of the present application. The same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions.

[0042] It should be noted that in the related art, during the transmission of the display signal, since the transmission lead is electrically connected to the driver chip, that is, the transmission lead is electrically connected to the load, there is current in the line, and thus there is impedance in the transmission lead, causing a voltage drop in the transmission process of the display signal through the transmission lead. When the voltage drop is too large, the display signal voltage value may be lower than the voltage range of the driver chip, resulting in abnormal display, and it may also cause a large difference in the voltage of the display signal output by adjacent driver chips, resulting in uneven brightness of the blocks, affecting the display effect.

[0043] In view of the above problems existing in the related art, the present application provides a display device, such as Figure 1 , Figure 2 As shown, the display device comprises: a display panel 1, and a plurality of cascaded driving chips 2 bound to one side of the display panel 1;

[0044] Each of the driving chips 2 comprises: a plurality of display signal input terminals 3, display signal output terminals 4 corresponding to the display signal input terminals 3, and at least one voltage compensation circuit 5;

[0045] Each of the voltage compensation circuits 5 is electrically connected to one of the display signal input terminals 3 and one of the display signal output terminals 4 respectively;

[0046] Except for the last stage of the driving chip 2, each display signal output terminal 3 of each driving chip 2 is electrically connected to each display signal input terminal 4 of the next adjacent stage in a one-to-one correspondence;

[0047] The voltage compensation circuit 5 is used to: perform voltage compensation on the display signal according to the display signal received by the display signal input terminal 3, generate a compensated display signal, and output the compensated display signal to the display signal output terminal 4, so that the difference in voltage of the same compensated display signal output by any adjacent driving chips 2 is less than a preset value.

[0048] In a specific implementation, the preset value may be: a theoretical value of the voltage difference between adjacent driving chips outputting the same display signal when uneven brightness of blocks of the display device occurs.

[0049] The display device provided in the embodiment of the present application has a plurality of driver chips cascaded, so that there is no need to provide signals to each driver chip by setting a printed circuit board, which can simplify the assembly process of the display device and save costs. In addition, a voltage compensation circuit is set in the driver chip. When a voltage drop occurs in the display signal during transmission, the voltage compensation circuit can compensate the voltage of the display signal, so that the difference in the voltage of the same display signal after compensation output by any adjacent driver chips is less than a preset value, avoiding a large difference in the voltage of the same display signal output by adjacent driver chips, avoiding uneven brightness of blocks, improving display effects, and enhancing user experience.

[0050] In a specific implementation, in the display device provided in the embodiment of the present application, the display panel includes a plurality of spliced ​​sub-display panels.

[0051] In some embodiments, Figure 2 As shown, the voltage compensation circuit 2 includes: a comparison unit 6;

[0052] The first input terminal of the comparison unit 6 is electrically connected to one of the display signal input terminals 3, and the second input terminal of the comparison unit 6 is electrically connected to the reference signal input terminal 20;

[0053] The comparison unit 6 is used to determine the difference between the display signal and the reference signal according to the display signal received by the display signal input terminal 3 and the reference signal received by the reference signal input terminal 20, and generate and output a voltage compensation signal δV of the display signal according to the difference between the display signal and the reference signal.

[0054] It should be noted that the display signal received by the display signal input terminal is a signal that undergoes a voltage drop through the transmission lead. The reference signal corresponds to the display signal received by the voltage compensation circuit. In a specific implementation, the reference signal can be received through a non-load lead. Even if the lead is thin, the reference signal will not produce a voltage drop, which can save the wiring space of the driver chip. The specific value of the reference signal can be set according to actual needs.

[0055] In some embodiments, Figure 2As shown, the comparison unit 6 includes: a comparator 7 and an operational amplifier 8;

[0056] The first input terminal of the comparator 7 is electrically connected to the display signal input terminal 3, the second input terminal of the comparator 7 is electrically connected to the reference signal input terminal 20, the output terminal of the comparator 7 is electrically connected to the input terminal of the operational amplifier 8, and the output terminal of the operational amplifier 8 outputs the voltage compensation value of the display signal.

[0057] In a specific implementation, the amplification factor of the operational amplifier can be adjusted as needed to adjust the voltage compensation value of the display signal.

[0058] In some embodiments, Figure 2 As shown, the voltage compensation circuit further includes: a low dropout linear regulator (LDO) 9;

[0059] The input end of the low voltage difference linear regulator is electrically connected to the display signal input end, and the output end of the low voltage difference linear regulator is electrically connected to the first input end of the comparator.

[0060] That is, the first input terminal of the comparator is electrically connected to the display signal input terminal through the LDO.

[0061] In a specific implementation, the LDO and the operational amplifier can be provided to isolate the load, thereby improving the load carrying capacity and impedance matching performance of the display signal.

[0062] In some embodiments, Figure 2 As shown, the voltage compensation circuit further includes: an adder 10;

[0063] The first input terminal of the adder 10 is electrically connected to the output terminal of the comparison unit 6 , the second input terminal of the adder 10 is electrically connected to the display signal input terminal 3 , and the output terminal of the adder 10 is electrically connected to the display signal output terminal 4 .

[0064] In some embodiments, the display panel includes a gate driving circuit, and a driving chip including a voltage compensation circuit is electrically connected to the gate driving circuit. In a specific implementation, the driving chip also includes an output unit electrically connected to the gate driving circuit, and the output unit is electrically connected to the output end of each voltage compensation circuit, so that the driving chip can provide a compensated display signal to the gate driving circuit.

[0065] In some embodiments, Figure 2 As shown, the plurality of display signal input terminals 3 include: a first power signal input terminal 11, a first voltage signal input terminal 12, and a second voltage signal input terminal 13;

[0066] The corresponding driving chip includes three voltage compensation circuits 5, and the three voltage compensation circuits 5 include: a first voltage compensation circuit 14 electrically connected to the first power signal input terminal 11, a second voltage compensation circuit 15 electrically connected to the first voltage signal input terminal 12, and a third voltage compensation circuit 16 electrically connected to the second voltage signal input terminal 13.

[0067] Correspondingly, the display signal output terminal includes: a first power signal output terminal 17 , a first voltage signal output terminal 18 , and a second voltage signal output terminal 19 .

[0068] In a specific implementation, the first power signal input terminal receives a first power signal (DVDD), the first voltage signal input terminal receives a first voltage signal (VGH), and the second voltage signal input terminal receives a second voltage signal (VGL). The first power signal may be, for example, a high-level voltage signal. The gate drive circuit includes a thin film transistor, the first voltage signal may be, for example, a voltage signal for controlling the thin film transistor to turn on, and the second voltage signal may be, for example, a voltage signal for controlling the thin film transistor to turn off. Thus, the display device provided in the embodiment of the present application, since the driving chip electrically connected to the gate drive circuit is provided with a voltage compensation circuit, can perform voltage compensation on VGH and VGL, thereby avoiding a large voltage drop between VGH and VGL affecting the turning on of the thin film transistor and avoiding display abnormalities.

[0069] In specific implementation, Figure 2 As shown, in the first voltage compensation circuit 14, the reference voltage signal terminal 20 receives a reference signal of the first voltage signal, and the voltage value of the reference signal of the first voltage signal is Vdd'. In the second voltage compensation circuit 15, the reference voltage signal terminal 20 receives a reference signal of the first voltage signal, and the voltage value of the reference signal of the first voltage signal is Vgh'. In the third voltage compensation circuit 16, the reference voltage signal terminal 20 receives a reference signal of the second voltage signal, and the voltage value of the reference signal of the second voltage signal is Vgl'.

[0070] It should be noted that, in the specific implementation, in addition to DVDD, VGH, and VGL, the gate drive circuit side also needs to provide display signals such as ground level signal (GND), vertical clock pulse signal (Clock Pulse Vertical, CPV), start signal (StartVertical, STV), output control signal (Output Enable, OE1), pull-up control signal (Output all-Oncontrol, XON), up and down control signal (Up and down control signal, UD), and common voltage signal (VCOM). The display signals other than DVDD, VGH, and VGL mentioned above may not be connected to the voltage compensation circuit, but the corresponding display signal input terminal and display signal output terminal still need to be set on the driver chip, and the output unit in the driver chip electrically connected to the gate drive circuit also needs to output other display signals except DVDD, VGH, and VGL.

[0071] In some embodiments, Figure 1 As shown, the display device further includes: a chip-on-film circuit board (COF) 21 ; the driving chip 2 is bound to the display panel 1 through the chip-on-film circuit board 21 .

[0072] In specific implementation, Figure 1 As shown, the display panel 1 includes: a display area 22, and a peripheral area 23 outside the display area 22. Since the display device provided in the embodiment of the present application does not have a printed circuit board (PCB) on the side of the gate drive circuit to provide signals to each driver chip, the multiple driver chips arranged in the Y direction are electrically connected in sequence. Since the driver chip is bound to the display panel through the COF, Figure 1 As shown in FIG. 1 , it is necessary to set connection signal lines in the peripheral area of ​​the COF and the display panel to provide display signals to each driver chip. Figure 1 As shown, multiple source COFs 24 need to be arranged in the X direction and bound to the edge of the display panel. The display device also includes a timing controller (TCON). The display signal generated by the timing controller is transmitted through the source COF 24, and is transmitted to the display signal input terminal of the first driver chip 2 arranged in the Y direction through the first connection signal line 25 electrically connected to the source COF 24. The transmission of the display signal is realized between adjacent driver chips 2 through the second connection signal line 26. It should be noted that Figure 1 Only a portion of the display device is shown, and Figure 1 Only the transmission of DVDD, VGH, and VGL is taken as an example.

[0073] In a specific implementation, taking eight cascaded driver chips arranged in the Y direction as an example, the voltage compensation of DVDD, VGH, and VGL by the display device provided in the embodiment of the present application is illustrated.

[0074] The voltage of DVDD generated by TCON is Vdd, the voltage of VGH generated by TCON is Vgh, the voltage of VGL generated by TCON is Vgl, and the voltage drops of Vdd, Vgh, and Vgl transmitted to the display signal input end of the first driver chip through the first connecting signal line are a, b, and c, respectively. Therefore, the voltages of DVDD, VGH, and VGL received by the display signal input end of the first driver chip are Vdd-a, Vgh-b, and Vgl-c, respectively. The voltage compensation value generated by the first voltage compensation circuit is δV1, the voltage compensation value generated by the second voltage compensation circuit is δV2, and the voltage compensation value generated by the third voltage compensation circuit is δV3. Therefore, the compensated DVDD, VGH, and VGL voltages output by the display signal output end of the first driver chip are Vdd-a+δV1, Vgh-b+δV2, and Vgl-c+δV3, respectively.

[0075] For any two adjacent driver chips, the display signals outputted from the output terminals of DVDD, VGH and VGL are transmitted to the display signal input terminal of the next driver chip through the second connecting signal line. The voltage drops of DVDD, VGH and VGL during the transmission process are ▽V1, ▽V2 and ▽V3 respectively. Therefore, the voltages of DVDD, VGH and VGL received by the display signal input terminal of the second driver chip are Vdd+δV1-a-▽V1, Vgh+δV2-b-▽V2 and Vgl+δV3-c-▽V3 respectively. In the second driver chip, the voltage compensation value generated by the first voltage compensation circuit is δV1', the voltage compensation value generated by the second voltage compensation circuit is δV2', and the voltage compensation value generated by the third voltage compensation circuit is δV3'. Therefore, the voltages of DVDD, VGH and VGL after compensation outputted from the display signal output terminal of the second driver chip are respectively Vdd-a+δV1-▽V1+δV1', Vgh-b+δV2-▽V2+δV2', Vgl-c+δV3-▽V3+δV3', therefore, the voltage difference of DVDD, the voltage difference of VGH, and the voltage difference of VGL output by the first driver chip and the second driver chip are δV1'-▽V1, δV2'-▽V2, δV3'-▽V3 respectively, wherein the preset value of the difference of display signal voltages output by adjacent driver chips is V0, therefore δV1'-▽V1<V0, δV2'-▽V2<V0, δV3'-▽V3<V0.

[0076] By analogy, in the n+1th driver chip, the voltage compensation value generated by the first voltage compensation circuit is δV1 n', the voltage compensation value generated by the second voltage compensation circuit is δV2 n ', the voltage compensation value generated by the third voltage compensation circuit is δV3 n '. The voltage difference between the output of the n+1th driver chip and the output of the nth driver chip is δV1 n '-▽V1、δV2 n '-▽V2, δV n 3'-▽V3, so δV1 n '-▽V1<V0、δV2 n '-▽V2<V0、δV n 3'-▽V3<V0. In this way, the voltage difference of DVDD, VGH and VGL output by the first driver chip and the last driver chip are δV1'+δV1"+…+δV1 respectively. 7’ -7▽V1,δV2'+δV2”+…+δV2 7’ -7▽V2,δV3'+δV3”+…+δV3 7’ -▽7V3, and δV1'+δV1"+…+δV1 7’ -7▽V1<V0,δV2'+δV2”+…+δV2 7’ -7▽V2<V0,δV3'+δV3”+…+δV3 7’ -▽7V3<V0, thereby satisfying that the difference in display signal voltage after the same compensation output by any adjacent driver chips is less than the preset value, and at the same time ensuring that the voltage difference between the voltage signals output by the first driver chip and the last driver chip meets the specifications (SPEC) of the driver chip, thereby avoiding the display signal voltage value being lower than the voltage range of the driver chip and avoiding display abnormalities.

[0077] In some embodiments, the voltage compensation signals of each display signal generated by different driving chips have the same value.

[0078] In specific implementation, driver chips with the same specifications are usually used on the same side of the display panel, and the values ​​of the voltage compensation signals of each display signal generated by different driver chips are the same, so that the voltage compensation multiples of the display signal by each driver chip with the same specifications are consistent. Taking the example of setting 8 cascaded driver chips in the Y direction, it is necessary to satisfy δV1'=δV1"=……=δV1 7 ', δV2'=δV2”=……=δV2 7 ', δV3'=δV3”=……=δV3 7 '.

[0079] In order to ensure that different driver chips have the same compensation multiples for the display signal, in some embodiments, in different driver chips, the difference between the display signal input to the voltage compensation circuit and the signal input to the reference signal terminal is equal.

[0080] Still taking the example of setting 8 cascaded driver chips in the Y direction, in the first driver chip, the voltage differences of DVDD, VGH, and VGL relative to their respective reference voltages are: a, b, and c respectively; in the second driver chip, the voltage differences of DVDD, VGH, and VGL relative to their respective reference voltages are: δV1-▽V1, δV2-▽V2, and δV3-▽V3 respectively; in the third driver chip, the voltage differences of DVDD, VGH, and VGL relative to their respective reference voltages are: δV1-▽V1, δV2-▽V2, and δV3-▽V3 respectively, and so on. In order to ensure that the voltage compensation multiples of the display signal of each driver chip are consistent, the voltage difference of the display signal received by the compensation modules of different driver chips and the reference voltage needs to be equal. That is, it needs to satisfy δV1-▽V1=a, δV2-▽V2=b, and δV3-▽V3=c.

[0081] In a specific implementation, the wiring space of each first connection signal line electrically connected to the first driver chip is relatively large, and the line width of the first connection signal line can be adjusted so that the values ​​of a, b, and c are very small, thereby reducing the impedance of the first connection signal line and further reducing the display signal voltage drop.

[0082] In some embodiments, Figure 3 , Figure 4 As shown, Figure 4 For along Figure 3 In the cross-sectional view taken along line AA', the peripheral area 23 includes: a plurality of first binding terminals 26 and a plurality of second binding terminals 27 bound to each of the COF circuit boards 21, and a plurality of connecting leads 28;

[0083] The first binding terminals 26 are electrically connected to the display signal input terminals in a one-to-one correspondence through the chip-on-film circuit board 21, and the second binding terminals 27 are electrically connected to the display signal output terminals in a one-to-one correspondence through the chip-on-film circuit board 21;

[0084] The first binding terminal 26 and the second binding terminal 27 bound to the adjacent COF PCB 21 are electrically connected in a one-to-one correspondence via the connecting lead 28;

[0085] The connecting lead 28 and the first binding terminal 26 and the second binding terminal 27 are located in different film layers.

[0086] It should be noted that the first binding terminal, the second binding terminal and the connecting lead may be the portion of the second connecting signal line on the display panel.

[0087] In the display device provided in the embodiment of the present application, a first binding terminal, a second binding terminal and a connecting lead for electrically connecting adjacent driving chips are arranged at the edge of the display panel, the connecting lead and the first binding terminal and the second binding terminal are located in different film layers, and the connecting leads located in different film layers do not conflict with the wiring space of the first binding terminal and the second binding terminal, thereby increasing the line width of the first binding terminal, the second binding terminal and the connecting lead, further reducing the impedance of the second connecting signal line electrically connecting the adjacent driving chips, and further reducing the voltage difference between the display signals output by the adjacent driving chips, thereby avoiding display defects such as uneven block brightness, and improving the display effect.

[0088] In a specific implementation, since the connection leads located in different film layers do not conflict with the wiring space of the first binding terminal and the second binding terminal, the width of the first binding terminal and the second binding terminal bound to the COF circuit board can be increased, thereby reducing the binding impedance.

[0089] In some embodiments, the display area includes: a source-drain electrode layer, a gate layer, and a transparent electrode layer;

[0090] like Figure 3 , Figure 4 As shown, the first binding terminal 26 and the second binding terminal 27 are arranged in the same layer as the source-drain electrode layer;

[0091] The connecting lead comprises: a first sub-lead 29 disposed in the same layer as the gate layer, and a second sub-lead 30 disposed in the same layer as the transparent electrode layer;

[0092] An extension direction Y of the first sub-lead 29 intersects with an extension direction X of the first binding terminal 26 and the second binding terminal 27;

[0093] The first sub-lead 29 is electrically connected to the first binding terminal 26 and the second binding terminal 27 through the second sub-lead 30 .

[0094] In specific implementation, Figure 4 As shown, the display panel further includes: a base substrate 31, a first insulating layer 32 located between the first binding terminal 26 and the first sub-lead 29, and a second insulating layer 33 located between the first binding terminal 26 and the second sub-lead 30. The second sub-lead 30 is electrically connected to the first binding terminal 26 through a via hole penetrating the second insulating layer 33, and the second sub-lead 30 is electrically connected to the first sub-lead 29 through a via hole penetrating the second insulating layer 33 and the first insulating layer 32.

[0095] In a specific implementation, the overall impedance of the connecting lead, the first binding terminal, and the second binding terminal can be adjusted by adjusting the line width of the first sub-lead.

[0096] In a specific implementation, the diameter of the via hole may be, for example, 3 micrometers to 5 micrometers.

[0097] In a specific implementation, the display panel provided in the embodiment of the present application may be a liquid crystal display panel, and the liquid crystal display panel includes: an array substrate and an opposing substrate arranged opposite to each other, and a liquid crystal layer located between the array substrate and the opposing substrate. In a specific implementation, the array substrate includes: a thin film transistor, a pixel electrode; the source-drain electrode layer includes, for example, a source and a drain of a thin film transistor, the gate layer includes, for example, a gate of a thin film transistor, and the transparent electrode layer includes, for example, a pixel electrode. The material of the transparent electrode layer may include, for example, indium tin oxide (ITO). In a specific implementation, the thin film transistor may, for example, be a bottom gate structure, the first insulating layer includes a gate insulating layer, and the second insulating layer includes a passivation layer. Of course, the thin film transistor may also be a top gate structure, the first insulating layer includes an interlayer insulating layer, and the second insulating layer includes a passivation layer.

[0098] The display device provided in the embodiment of the present application is any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a laptop computer, a digital photo frame, a navigator, etc. Other essential components of the display device should be understood by ordinary technicians in the field, and will not be described in detail here, nor should they be used as limitations to the present application.

[0099] In summary, the display device provided by the embodiment of the present application has multiple driver chips cascaded, so there is no need to provide signals to each driver chip by setting a printed circuit board, which can simplify the assembly process of the display device and save costs. In addition, a voltage compensation circuit is set in the driver chip. When a voltage drop occurs in the display signal during transmission, the voltage compensation circuit can compensate the voltage of the display signal, so that the difference in the voltage of the same display signal after compensation output by any adjacent driver chips is less than a preset value, avoiding a large difference in the voltage of the same display signal output by adjacent driver chips, avoiding uneven brightness of blocks, improving display effects, and enhancing user experience.

[0100] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A display device, characterized in that: The display device comprises: a display panel, and a plurality of cascaded driving chips bound to one side of the display panel; Each of the driving chips comprises: a plurality of display signal input terminals, display signal output terminals corresponding one to one to the display signal input terminals, and at least one voltage compensation circuit; Each of the voltage compensation circuits is electrically connected to one of the display signal input terminals and one of the display signal output terminals respectively; Except for the last-stage driving chip, each display signal output terminal of each driving chip is electrically connected to each display signal input terminal of the next adjacent stage in a one-to-one correspondence; The voltage compensation circuit is used to: perform voltage compensation on the display signal according to the display signal received by the display signal input terminal to generate a compensated display signal, and output the compensated display signal to the display signal output terminal, so that the difference between the same compensated display signals output by any adjacent driving chips is less than a preset value; The voltage compensation circuit comprises: a comparison unit; The first input terminal of the comparison unit is electrically connected to one of the display signal input terminals, and the second input terminal of the comparison unit is electrically connected to the reference signal input terminal; The comparison unit is used to: determine the difference between the display signal and the reference signal according to the display signal received by the display signal input terminal and the reference signal received by the reference signal input terminal, and generate and output a voltage compensation signal of the display signal according to the difference between the display signal and the reference signal; The reference signal is received through a non-load lead, that is, the lead has a thin line width and will not produce a voltage drop.

2. The display device according to claim 1, characterized in that The comparison unit includes: a comparator and an operational amplifier; The first input terminal of the comparator is electrically connected to one of the display signal input terminals, the second input terminal of the comparator is electrically connected to the reference signal input terminal, the output terminal of the comparator is electrically connected to the input terminal of the operational amplifier, and the output terminal of the operational amplifier outputs the voltage compensation value of the display signal.

3. The display device according to claim 2, characterized in that: The voltage compensation circuit further includes: a low voltage dropout linear regulator; The input end of the low voltage difference linear regulator is electrically connected to the display signal input end, and the output end of the low voltage difference linear regulator is electrically connected to the first input end of the comparator.

4. The display device according to claim 1, characterized in that The voltage compensation circuit further includes: an adder; The first input terminal of the adder is electrically connected to the output terminal of the comparison unit, the second input terminal of the adder is electrically connected to the display signal input terminal, and the output terminal of the adder is electrically connected to the display signal output terminal.

5. The display device according to claim 1, characterized in that The voltage compensation signals of each display signal generated by different driving chips have the same value.

6. The display device according to claim 5, characterized in that: In different driving chips, the difference between the display signal input to the voltage compensation circuit and the signal input to the reference signal terminal is equal.

7. The display device according to claim 1, characterized in that: The plurality of display signal input terminals include: a first power signal input terminal, a first voltage signal input terminal, and a second voltage signal input terminal; At least one of the voltage compensation circuits includes: a first voltage compensation circuit electrically connected to the first power signal input terminal, a second voltage compensation circuit electrically connected to the first voltage signal input terminal, and a third voltage compensation circuit electrically connected to the second voltage signal input terminal.

8. The display device according to claim 1, characterized in that: The display device further comprises: a chip-on-film circuit board; the driving chip is bound to the display panel via the chip-on-film circuit board; The display panel includes: a display area, and a peripheral area outside the display area; The peripheral area includes: a plurality of first binding terminals and a plurality of second binding terminals bound to each of the COF circuit boards, and a plurality of connecting leads; The first binding terminals are electrically connected to the display signal input terminals in a one-to-one correspondence through the chip-on-film circuit board, and the second binding terminals are electrically connected to the display signal output terminals in a one-to-one correspondence through the chip-on-film circuit board; The first binding terminal and the second binding terminal bound to the adjacent chip-on-film circuit board are electrically connected one-to-one through the connecting lead; The connecting lead and the first binding terminal and the second binding terminal are located in different film layers.

9. The display device according to claim 8, characterized in that: The display area includes: a source-drain electrode layer, a gate layer, and a transparent electrode layer; The first binding terminal and the second binding terminal are arranged in the same layer as the source-drain electrode layer; The connecting lead comprises: a first sub-lead arranged in the same layer as the gate layer, and a second sub-lead arranged in the same layer as the transparent electrode layer; The extension direction of the first sub-lead intersects with the extension directions of the first binding terminal and the second binding terminal; The first sub-lead is electrically connected to the first binding terminal and the second binding terminal respectively through the second sub-lead.

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