Apparatus and method for redundant match control to disable word line activation on refresh

Abstract

Devices and methods for redundant match control to disable word line activation at refresh are described. An example method includes, during a refresh operation, determining a respective row of memory cells that is scheduled for refresh in each section of a plurality of sections of a bank of a memory device; and determining whether the respective row of memory cells that is scheduled for refresh of a particular section of the plurality of sections of the bank has been repaired. The example method further includes, in response to determining that the row of memory cells that is scheduled for refresh has been repaired, causing refresh within the particular section of the bank to be skipped while performing refresh of the row of memory cells that is scheduled for refresh in other sections of the plurality of sections of the bank that are to be refreshed.

Description

TECHNICAL FIELD

[0001] The present application relates generally to dynamic random access memory (DRAM), including volatile memory cells that can be used to store data. BACKGROUND

[0002] Dynamic random access memory (DRAM) includes volatile memory cells that can be used to store data. However, to maintain stored data, memory cells are periodically refreshed to restore the data that is stored. Memory cells are typically refreshed by sequencing groups of memory cells associated with respective refresh addresses. Refresh addresses can be generated internally and refresh operations are performed on memory cells corresponding to refresh addresses in response to refresh commands. In some instances, refreshing defective memory cells can result in unpredictable behavior. Accordingly, it can be desirable to mitigate unpredictable behavior associated with defective memory cells. SUMMARY

[0003] In one aspect, the present application provides an apparatus comprising a bank having a plurality of sections, a row address control circuit configured to determine, during a refresh operation, whether a predetermined refresh-eligible respective row of memory cells in each of the plurality of sections has been repaired and, in response to determining that the respective row of memory cells in a particular section of the plurality of sections has been repaired, cause the bank to skip refresh in the particular section while performing refresh in the respective row of memory cells of each of the plurality of sections detected to be operational during the refresh operation.

[0004] In another aspect, the present application provides an apparatus comprising a row decoder configured to decode a row address corresponding to a plurality of rows of memory cells of a bank that are predetermined to be refreshed concurrently during a refresh operation based on a row match signal, a register circuit configured to store a repair row address corresponding to a row of memory cells that has been repaired, wherein the register circuit is configured to compare a row address corresponding to the plurality of rows of memory cells of the bank that are predetermined to be refreshed concurrently to the repair row address and provide a match signal when a match is detected, a latch circuit configured to latch a bit of the row match signal in response to the match signal being set, wherein the bit of the row match signal corresponds to a row of memory cells that has been repaired of the plurality of rows of memory cells that are predetermined to be refreshed concurrently during the refresh operation, wherein the row decoder is configured to skip decoding a row of memory cells of the plurality of rows of memory cells of the bank that are predetermined to be refreshed concurrently during a refresh operation in response to the latched bit of the row match signal.

[0005] In another aspect, the present application provides a method comprising, during a refresh operation: determining a respective row of memory cells in each of a plurality of sections of a bank of a memory device that are scheduled for refresh; determining whether the respective row of memory cells scheduled for refresh in a particular section of the plurality of sections of the bank has been repaired; and responsive to determining that the row of memory cells scheduled for refresh has been repaired, causing refresh within the particular section of the bank to be skipped while performing refresh of the rows of memory cells scheduled for refresh in other sections of the plurality of sections of the bank that are to be refreshed. BRIEF DESCRIPTION OF DRAWINGS

[0006] Figure 1 is a block diagram of a device according to embodiments of the present disclosure.

[0007] Figure 2 is an exemplary block diagram of a row address control circuit according to embodiments of the present disclosure.

[0008] Figure 3 depicts a layout diagram of an exemplary memory pad for a bank according to embodiments of the present disclosure.

[0009] Figure 4 is a timing diagram for a first embodiment for performing a refresh operation according to embodiments of the present disclosure.

[0010] Figure 5 is a timing diagram for a second embodiment for performing a refresh operation according to embodiments of the present disclosure.

[0011] Figure 6 depicts a flowchart of an exemplary method for performing a refresh operation according to embodiments of the present disclosure. DETAILED DESCRIPTION

[0012] The present disclosure describes instances of skipping word line activation of defective memory rows during refresh operations that involve simultaneous refreshing of multiple segments of a memory bank. In other words, a memory bank can be divided into multiple segments that can have word lines activated simultaneously. During some refresh operations, memory cell rows from two or more segments of a memory bank can be refreshed simultaneously by simultaneously activating the corresponding word lines. A counter can be used to systematically step through each row over time so that the same row in each segment is refreshed (e.g., starting with the first row in each segment, then refreshing the second row in each segment, and so on). However, in some instances, as the refresh counter increments through the rows of each segment, it can land on a defective row in one or more particular segments and cause the defective row to be refreshed. Refreshing a defective row can cause problems with subsequent memory operations because the defective row can respond to word line activation in an unpredictable manner. For example, when a word line of a defective row is activated for a refresh operation and then deactivated after the refresh operation, the row can discharge more slowly than a non-defective row, causing the charged word line to bleed into subsequent memory operations. Thus, to mitigate the unpredictable behavior, refresh control logic can detect a defective word line and cause the activation of the word line corresponding to the defective row to be skipped during a refresh operation.

[0013] In some instances, detection of a defective memory cell row can be performed during a refresh operation prior to word line activation. In other instances of refresh operations that include a row hammer refresh (RHR), followed by an automatic refresh (e.g., a double pump refresh), a defective word line can be detected during the RHR operation. By skipping refreshing a defective memory cell row, the unpredictable behavior of subsequent memory operations can be mitigated.

[0014] Certain details are set forth below to provide a sufficient understanding of examples of the present disclosure. However, it will be clear to one skilled in the art that examples of the present disclosure can be practiced without such specific details. Moreover, the particular examples of the present disclosure described herein are by way of example only and are not intended to limit the scope of the present disclosure. In other instances, well-known circuits, control signals, timing diagrams, and software operations have not been shown in detail in order to avoid unnecessarily obscuring examples of the present disclosure. Additionally, the terms "couples" and "coupled" are intended to mean either a direct electrical or magnetic coupling between two components or an indirect coupling between two components by way of one or more intermediate components. Indirect coupling can imply that two components are coupled by way of one or more intermediate components.

[0015] Figure 1is a block diagram of a device according to embodiments of the present disclosure. The device can include a semiconductor device 100 and will be so referred to. In some embodiments, the semiconductor device 100 can include, but is not limited to, a DRAM device such as, for example, a double data rate (DDR) memory or a low power DDR (LPDDR) memory integrated into a single semiconductor chip. The semiconductor device 100 includes a memory array 150. The memory array 150 includes a plurality of memory banks, each memory bank including a plurality of word lines WL, a plurality of bit lines BL and / BL, and a plurality of memory cells MC arranged at intersections of the plurality of word lines WL and the plurality of bit lines BL. The memory cells MC are volatile memory cells that require periodic refresh to maintain data stored in the memory array.

[0016] Selection of the word lines WL is performed by a row address control circuit 140, and selection of the bit lines BL and / BL is performed by a column decoder 145. Sense amplifiers (SAMPs) are positioned for their corresponding bit lines BL and / BL, coupled to at least one respective local I / O line pair (LIOT / B), which in turn is coupled to at least one respective main I / O line pair (MIOT / B) through a pass gate (TG) acting as a switch.

[0017] The memory array 150 can be divided into memory banks BANK0-7, with each memory bank having a regular array and a redundant array. The regular array includes memory cells that are typically used to store data, with the memory cells corresponding to respective memory addresses. The redundant array includes memory cells that can be used to “repair” defective memory cells of the regular array. The memory cells can be configured as redundant rows of memory and redundant columns of memory. The redundant rows of memory can be used to repair memory rows of the regular array, and the redundant columns of memory can be used to repair memory columns of the regular array. Redundant memory is used to repair defective memory cells of the regular array by mapping memory addresses corresponding to the defective memory cells to memory cells of the redundant array. Thus, when a memory address of a defective memory location is provided to the semiconductor device 100, the memory location in the redundant array to which the memory address is mapped is accessed instead of the defective memory location in the regular array corresponding to the memory address.

[0018] The semiconductor device 100 can employ a plurality of external terminals including command and / address termination terminals CA coupled to a command bus and an address bus to receive commands and addresses. The plurality of external terminals further include clock terminals CK and CK / to receive a clock signal, data terminals DQ and data mask terminals DM, and power supply terminals VDD, VSS, VDDQ, and VSSQ.

[0019] A memory address, e.g., from a memory controller, can be supplied to the command / address terminals CA. The memory address supplied to the command / address terminals CA is transmitted to the address decoder 112 through the command / address input circuit 105. The address decoder 112 receives the memory address and supplies a decoded row address XADD to the row address control circuit 140 and a decoded column address YADD to the column decoder 145.

[0020] A command, e.g., from a memory controller, can further be supplied to the command / address terminals CA. The command can be provided in the form of an internal command signal ICMD to the command decoder 115 through the command / address input circuit 105. The command decoder 115 includes circuitry for decoding the internal command ICMD to generate internal commands and signals for performing operations. For example, the command decoder 115 can provide an activate command ACT and a refresh command AREF to the row address control circuit 140 to select a word line and can provide a read / write command R / W to the column decoder 145 to select a bit line. The refresh command AREF can be provided by the command decoder 115 to the row control circuit 140 when a refresh operation is to be performed. The refresh command AREF can represent an auto-refresh command generated from receiving a refresh command by the semiconductor device 100, and can also represent a self-refresh command internally generated when the semiconductor device 100 is set to a self-refresh mode.

[0021] When a read command is received and a memory address is supplied in time with the read command, read data can be read from a memory cell in the memory array 150 specified by the memory address. The read data is output from the data terminals DQ to the outside through the read / write amplifiers 155 and the input / output circuit 160. When a write command is received and a memory address is supplied in time with the write command, write data and a data mask (when applicable) are supplied to the data terminals DQ and DM, and the write data is written to a memory cell in the memory array 150 specified by the memory address. The write data is received by a data receiver in the input / output circuit 160 and is supplied to the memory array 150 through the input / output circuit 160 and the read / write amplifiers 155.

[0022] During access operations for read and write commands, the row address control circuit 140 can include circuitry to determine whether a memory address has been mapped to a memory location in the redundant array, for example, when a memory address corresponding to a defective memory location in the regular array has been mapped to a memory location of the redundant array (e.g., a redundant row of memory). The memory addresses that have been remapped are stored and the memory address associated with an access operation is compared to the stored memory addresses. Memory addresses that have been mapped to redundant memory can be stored in a non-volatile storage device. An example of a non-volatile storage device is a fuse circuit (and anti-fuse circuit) that is programmed with the memory addresses to be stored. When the memory address associated with an access operation matches a stored memory address, the memory location in the redundant array is accessed instead of the memory location in the regular array.

[0023] As previously described, volatile memory cells are periodically refreshed to maintain the data stored by the memory array. The memory cells are typically refreshed as rows of memory cells. The row address control circuit 140 can include refresh control circuitry used during refresh operations. Refresh operations are performed when an active refresh command AREF is provided to the row address control circuit 140. Each refresh command AREF generates a memory location associated with a refresh address to be refreshed. In some embodiments of the present disclosure, the refresh address can be generated internally within the semiconductor device 100. In some embodiments of the present disclosure, similar circuitry and operations can be included in the column decoder 145.

[0024] The refresh address can have a number of memory locations associated therewith. For example, a plurality of rows of memory can be associated with a refresh address, where each of the rows of memory corresponds to a value that, when combined with the refresh address, identifies a particular row of memory. For example, a memory bank BANK0-7 can be divided into a plurality of sections capable of simultaneously activating a word line. During some refresh operations, memory cell rows from two or more sections of a memory bank can be refreshed simultaneously by simultaneously activating the corresponding word lines. Such an arrangement can facilitate faster access and refresh operations.

[0025] When refreshing memory, a determination is made whether the refresh address is to be mapped to a redundant memory location in the redundant array. The determination can be performed during a refresh operation associated with a defective row. In some instances, the refresh operation can be performed immediately prior to activating a set of word lines corresponding to the refresh address. In a double pump refresh operation (e.g., RHR, followed by an auto-refresh), the determination can be made during the RHR portion of the refresh operation. In cases where the refresh address has been mapped to a redundant memory, the memory location in the regular array corresponding to the refresh address is not refreshed, thereby avoiding unpredictable behavior associated with a necessary refresh operation of an unused memory location, for example, when the regular memory location is defective and the corresponding memory address has been mapped to a redundant memory location. Skipping refresh operations for unused memory locations can avoid unpredictable behavior, such as interference with activation of word lines, because the segment contains rows of defective memory cells resulting from slow discharge of activated word lines. Skipping such refreshes, as compared to performing refresh operations for all memory locations regardless of their use, can also reduce power consumption.

[0026] Turning to the explanation of the external terminals included in semiconductor device 100, clock terminals CK and / CK are supplied with complementary external clock signals. The external clock signals can be supplied to clock input circuit 120. Clock input circuit 120 can generate an internal clock signal ICLK. The internal clock signal ICLK is supplied to internal clock generator circuit 130 and command decoder 115. When enabled by a clock enable CKE from command / address input circuit 105, the circuitry of internal clock generator circuit 130 provides various internal clock signals LCLK based on the internal clock signal ICLK. The internal clock signals LCLK can be used to time the operation of various internal circuits. For example, the LCLK signals can be provided to input / output circuit 160 for timing the operation of input / output circuit 160 to provide and receive data on data terminals DQ.

[0027] Power supply terminals VDD and VSS are supplied with power supply potentials. These power supply potentials are supplied to internal voltage generator circuit 170. Internal voltage generator circuit 170 generates various internal potentials VPP, VOD, VARY, VPERI, etc. based on the power supply potentials provided to power supply terminals VDD and VSS. Internal potential VPP is primarily used in row address control circuit 140, internal potentials VOD and VARY are primarily used in sense amplifiers SAMP included in memory array 150, and internal potential VPERI is used in many other peripheral circuit blocks.

[0028] A power potential is also supplied to power terminals VDDQ and VSSQ. This power potential is also supplied to input / output circuitry 160. In some embodiments of this disclosure, the power potential supplied to power terminals VDDQ and VSSQ may be the same as the power potential supplied to power terminals VDD and VSS. Providing a dedicated power potential to power terminals VDDQ and VSSQ prevents power supply noise generated by input / output circuitry 160 from propagating to other circuit blocks.

[0029] Figure 2 This is an exemplary block diagram of a row address control circuit 200 according to an embodiment of the present disclosure. In some embodiments, Figure 1 The row address control circuit 140 can implement the row address control circuit 200. The row address control circuit 200 may include an address latch 210, a pre-decoder 212, a refresh area counter circuit 220, a buffer circuit 222, a buffer circuit 224, a redundant match register 230, a latch 232, a row selector 240, an OR gate 242, a delay circuit 250, a flip-flop 252, an OR gate 254, an AND gate 256, and a row decoder 258.

[0030] Address latch 210 can be configured to receive global row address GRA<15:0> and, in response to row address latch signal RXLATCH, can be configured to latch row address RA<15:0> to provide to pre-decoder 212 and latch redundant row address RRP0-3<15:0> to provide to buffer circuit 222 and buffer circuit 224.

[0031] The refresh counter circuit 220 can be configured to provide the refresh address RX0-3<15:14> and the refresh address selection signal SelRA to the buffer circuit 224 based on the refresh signal REFRESHST. It can respond to refresh commands (e.g., from a command decoder, such as...). Figure 1 The REFRESHST signal is set using the command decoder 115. In some instances, it can be based on the AREF command (e.g., Figure 1 The REFRESHST signal is set using either the AREF command or a self-refresh command. The refresh area counter circuit 220 may include a two-bit counter configured to provide each count value (e.g., b00, b01, b10, and b11) as a corresponding address in the RX0-3<15:14> address set.

[0032] Buffer circuit 222 and buffer circuit 224 can collectively provide the RR0-3<15:0> address to redundant match register 230. Buffer circuit 222 can provide the RRP<13:0> bits as the RR<13:0> bits. Buffer circuit 224 can selectively provide one of the RRP0-3<15:14> address or the RXR0-3<15:14> address as the RR0-3<15:14> address based on the SelRA signal. During normal access operations, buffer circuit 222 and buffer circuit 224 can provide the RRP0-3<15:0> address to redundant match register 230 (e.g., based on the SelRA signal indicating a non-refresh operation). During a refresh operation, buffer circuit 222 can be configured to provide the RRP<13:0> bits and buffer circuit 224 can be configured to provide the RX0-3<15:14> address from refresh zone counter circuit 220 to collectively make up the RR0-3<15:0> address (e.g., based on the SelRA signal indicating a refresh operation).

[0033] Pre-decoder 212 can decode the RA<15:0> address to provide a pre-decoded row address (e.g., the RXP0-3<15:14> address bits each combined with the RX<13:0> address bits). Pre-decoder 212 can also receive a redundant row address RRAdd<8:0> from redundant match register 230, which can be used to replace some or all of the decoded RA<15:0> with a replacement row (e.g., during normal access operations).

[0034] Redundancy match register 230 can compare RR0-3<15:0> addresses to addresses stored at redundancy match register 230 to determine whether any of the RR0-3<15:0> addresses have been replaced by a redundant address. Responsive to determining that a particular one of the RR0-3<15:0> addresses has been replaced by a redundant address, a redundancy match signal RMATCH can be set. Further responsive to determining that a particular one of the RR0-3<15:0> addresses has been replaced by a redundant address, redundancy match register 230 can also provide a redundant row address RRAdd<8:0> to predecoder 212. Latches 232 can latch a particular RMATCH signal for activating a corresponding one of low redundancy match latch signals RMLF<3:0> to indicate a match. During a refresh operation, refresh region counter circuit 220 can set RMLATCH signals to cause each of the RMLF<3:0> signals to indicate a match with a corresponding one of the RXR0-3<15:14> signals. For example, RMLF<0> signal can indicate whether an address corresponding to RXR0<15:14> address has been replaced by a redundant address, RMLF1<1> signal can indicate whether an address corresponding to RXR1<15:14> has been replaced by a redundant address, etc. Each of the RMLF<3:0> signals can correspond to a particular section of a memory bank.

[0035] Or gate 242 can receive AREF signal and self refresh SR signal, and responsive to one of the signals being set (e.g., indicating a refresh operation), can cause row selector 240 to selectively provide RMLF<3:0> signals as RX1514<3:0> signals. For non-refresh access operations (e.g., when neither AREF or SR signals are set), row selector 240 can provide RXP1514<3:0> signals as RX1514<3:0> signals. The provided RX1514<3:0> signals are decoded by row decoder 258 to determine whether to perform or skip an access operation for a particular section of a corresponding memory bank.

[0036] The delay circuit (e.g., delay circuit 250, flip-flop 252, or gate 254 and AND gate 256) can be configured to provide a row decoder enable signal RDEN to row decoder 258 to initiate decoding of the provided RX1514<3:0> signal and RX<13:0> address to activate a word line associated with the word line address WORDRX1514<3:0>. Because it takes a period of time for the refresh address to be checked for redundancy by refresh zone counter circuit 220, buffer circuit 224, redundancy match register 230, latch 232, and row selector 240 after the refresh REFRESHST signal is set and after the GRA<15:0> address is latched by address latch 210, delay circuit 250, flip-flop 252, and or gate 254 can delay setting the RDEN signal to enable row decoder 258 to allow those components to determine whether any particular row has been replaced by a redundant row.

[0037] In operation, a refresh operation can be performed simultaneously on a plurality of rows of a memory bank. To avoid activating a word line on a defective memory row, row address control circuit 200 can be configured to determine whether any of the plurality of rows has been replaced by a redundant row (e.g., by redundancy match register 230), and if so, can prevent activation of the row (e.g., by row selector 240).

[0038] At the start of a refresh operation, address latch 210 can receive the GRA<15:0> address, and in response to the RXLATCH signal, can latch the RA<15:0> address for provision to predecoder 212 and can latch the RRP<15:0> address for provision to buffer circuit 222 and buffer circuit 224. Refresh zone counter circuit 220 can be configured to provide the RXR0-3<15:14> addresses and the SelRA signal to buffer circuit 224 in response to the REFRESHST signal. Once the REFRESHST signal is set, refresh zone counter circuit 220 can provide the RXR0-3<15:14> addresses and the SelRA signal. The RX0-3<15:14> addresses can collectively represent each two-bit count value (e.g., bOO, bOl, blO, and bl l).

[0039] Buffer circuit 222 and buffer circuit 224 can provide the RR0-3<15:0> address to the redundant match register 230, with buffer circuit 224 selectively providing one of the RRP0-3<15:14> address or the RXR0-3<15:14> address as the RR0-3<15:14> address based on the SelRA signal. During normal access operations, buffer circuit 222 and buffer circuit 224 can provide the RRP0-3<15:0> address to the redundant match register 230 (e.g., based on the SelRA signal indicating a non-refresh operation). During a refresh operation, buffer circuit 222 can be configured to provide the RRP<13:0> bits and buffer circuit 224 can be configured to provide the RX0-3<15:14> address from the refresh zone counter circuit 220 to collectively make up the RR0-3<15:0> address (e.g., based on the SelRA signal indicating a refresh operation).

[0040] The predecoder 212 can decode the RA<15:0> address to provide a predecoded row address (e.g., the RXP0-3<15:14> address bits each combined with the RX<13:0> address bits). The predecoder 212 can also receive a redundant row address RRAdd<8:0> from the redundant match register 230, which can be used to replace some or all of the decoded RA<15:0> with a replacement row (e.g., during normal access operations).

[0041] The redundant match register 230 can compare the RR0-3<15:0> address to the redundant replacement addresses stored at the redundant match register 230 to determine whether the RR0-3<15:0> address has been replaced by a redundant address. Responsive to determining that the RR0-3<15:0> address has been replaced by a redundant address, a redundant match signal RMATCH can be set. Further responsive to determining that a particular one of the RR0-3<15:0> address has been replaced by a redundant address, the redundant match register 230 can also provide a redundant row address RRAdd<8:0> to the predecoder 212. Latches 232 can latch the particular RMATCH signal for activating a corresponding one of low redundant match latch signals RMLF<3:0> to indicate a match. Each of the RMLF<3:0> signals can correspond to a particular section of the memory bank. For example, the RMLF<0> signal can indicate whether the address corresponding to the RXR0<15:14> address has been replaced by a redundant address, the RMLF1<1> signal can indicate whether the address corresponding to the RXR1<15:14> has been replaced by a redundant address, etc. Figure 3A layout diagram of an example memory pad 300 for a bank in accordance with embodiments of the present disclosure is depicted. If a refresh operation is to be performed on a row address corresponding to memory cell rows 310, 320, 330, and 340, the redundancy match register 230 can determine whether any of the row addresses have been replaced by a redundant row. As shown in the memory pad 300, row 330 has been replaced by row 332. Thus, the redundancy match register 230 can store the row address corresponding to row 330, and can generate an RMATCH signal to be set for the row when the RR<15:0> in combination with the RRP<8:0> address matches the row address of row 330, which can be latched as the RMLF<2> signal.

[0042] Based on one of the set AREF or SR signals, the OR gate 242 can cause the row selector 240 to selectively provide the RMLF<3:0> signals as the RX1514<3:0> signals. For non-refresh access operations, the row selector 240 can provide the RXP1514<3:0> signals. The provided RX1514<3:0> signals can be decoded by the row decoder 258 to determine whether to perform or skip an access operation on a particular section of the corresponding bank.

[0043] The delay circuit 250, flip-flop 252, OR gate 254, and AND gate 256 can be configured to delay the provision of the RDEN signal based on the RDENP, SelRA, and SR signals, which results in the row decoder 258 initiating the decoding of the provided RX1514<3:0> signals and RX<13:0> address to activate a word line associated with the word line address WORDRX1514<3:0> in order to allow the completion of the redundancy check of the refresh address by the refresh region counter circuit 220, buffer circuit 224, redundancy match register 230, latch 232, and row selector 240.

[0044] Figure 2 The row address control circuit 200 depicted in FIG. 3 is configured for simultaneous refreshing of 4 memory cell rows based on four row addresses (e.g., by four two-bit RHR0-3<15:14> address bits and RHR0-3<15:14> address bits). It should be appreciated that the row address control circuit 200 can be modified to accommodate simultaneous refreshing of more or less than four memory cell rows without departing from the scope of the present disclosure. The ability of the row address control circuit 200 to detect defective row addresses and prevent word line activation of defective row addresses can mitigate adverse effects caused by unpredictable behavior of activated defective rows.

[0045] Figure 4 is a timing diagram 400 for a first embodiment of performing a refresh operation in accordance with embodiments of the present disclosure. In some embodiments of the present disclosure,Figure 4 The refresh operation can be used to refresh. Figure 1 The memory locations of the memory array 150 of the semiconductor device 100. In some instances, timing diagram 400 may correspond to... Figure 1 Row address control circuit 140 and / or Figure 2 The operation of the row address control circuit 200.

[0046] At time T0, the SR or AREF signal can become active to initiate a refresh operation. The SR or AREF signal can be set based on a self-refresh or automatic refresh command. At time T1, a pulse can be provided on the REFRESH signal, and in response, the REFRESHST signal can become active at time T2. The transition of the REFRESHST signal can trigger... Figure 2 The refresh counter circuit 220 is used to initially provide the RXR0-3<15:14> address (e.g., b00, b01, b10, and b11), the SelRA signal, and the RMLATCH signal.

[0047] In response to the SR / AREF signal, at time T3, it is used for BANKX (e.g., Figure 1 The bank row address strobe signal RAS_BANKX (from any of the banks BANK0-7) can be activated to indicate the bank on which a refresh operation should be performed. Similarly, at time T3, a pulse can be provided on the RXLATCH signal to cause the address latch 210 to latch the received GRA<15:0> address.

[0048] At time T4, the RXR0-3<15:14> address begins to be evaluated, and in response to a hit detection (e.g., a matched address at redundant match register 230), a pulse can be provided on the RMATCH signal. For example, in timing diagram 400, a matched address is detected with the RXR1<15:14> address, and therefore a pulse is provided on the RMATCH signal. The pulse on the RMATCH signal corresponding to the RXR1<15:14> address may result in RMLF. <1> The bit is cleared in the RMLF<3:0> signal (e.g., RMLF<3:0> changes from hF to hD). In response to the RMLF<3:0> signal changing to hD, the RX1514<3:0> signal can also be cleared at time T6. Figure 2 The row selector 240 and OR gate 242 are transformed into hD.

[0049] At time T7, the line decoder 258 can activate the word line associated with the WORDRX1514<3:0> segment of the memory bank based on the RX1514<3:0> signal. The delay between time T3 and T7 can be partially based on... Figure 2The delay circuit 250, flip-flop 252, OR gate 254, and AND gate 256 are used. Therefore, as shown in timing diagram 400, the word lines in the WORDRX1514<3, 2, and 0> segment of the memory bank can be activated, and WORDRX1514... <1> No word lines are active in the segment. Between time T7 and T8, the RAS_BANKX and WORDRX1514<3:0> signals can be cleared to terminate the refresh operation.

[0050] Time intervals T8-T11 depict subsequent refresh operations where no repair line was detected, and thus, at time T11, each word line in the WORDRX1514<3:0> word line is activated for the refresh operation. After time T11, the RAS_BANKX and WORDRX1514<3:0> signals can be cleared to terminate subsequent refresh operations.

[0051] Figure 5 This is a timing diagram 500 for performing a refresh operation according to a second embodiment of the present disclosure. In some embodiments of the present disclosure, Figure 5 The refresh operation can be used to refresh. Figure 1 The memory locations of the memory array 150 of the semiconductor device 100. In some instances, the timing diagram 500 may correspond to... Figure 1 Row address control circuit 140 and / or Figure 2 The operation of the row address control circuit 200 is described in timing diagram 500, which depicts the dual-pump refresh operation, including RHR and subsequent normal refresh. RHR begins at time T1 and normal refresh begins at time T4.

[0052] At time T0, the REFRESHST signal can become active at time T2. The transition of the REFRESH signal can trigger... Figure 2 The refresh counter circuit 220 begins by providing the RXR0-3<15:14> address, the SelRA signal, and the RMLATCH signal. RHR can be started at time T1.

[0053] At time T2, the RXR0-3<15:14> addresses (e.g., bOO, bOl, b10, and bl l) begin to be evaluated, and in response to a detection of a hit (e.g., a matching address at the redundant match register 230), a pulse can be provided on the RMATCH signal. For example, in the timing diagram 500, a matching address is detected with the RXR1<15:14> address, and thus a pulse is provided on the RMATCH signal at time T3. The pulse on the RMATCH signal corresponding to the RXR1<15:14> address can cause the RMLF<1> bit to clear in the RMLF<3:0> signal (e.g., RMLF<3:0> transitions from hF to hD). However, since neither the AREF signal nor the SR signal is set during the RHR, the row selector 240 can provide the RXP1514<3:0> signal as RX1514<3:0> to trigger a target refresh.

[0054] At time T4, a normal refresh can begin, where the GRA<15:0> signal is latched in response to a pulse on the RXLATCH signal at time T5. Thus, the RX1514<3:0> signal can transition from the RXR1514<3:0> signal (e.g., h l) to the RMLF<3:0> signal (e.g., hD). At time T6, the row decoder 258 can activate the word lines associated with the WORDRX1514<3:0> segments of the memory bank based on the RX1514<3:0> signal. Thus, as shown in the timing diagram 500, the word lines in the WORDRX1514<3:2> and 0> segments of the memory bank can be activated, while no word lines in the WORDRX1514<1> segment are activated. Times T8-T11 depict subsequent refresh operations in which a repair row is not detected, and as such, at time Tl l, each of the WORDRX1514<3:0> word lines are activated for a refresh operation.

[0055] Applicants note that the relative timing between the signals, pulse lengths, etc. in the timing diagrams 400 and 500 of Figure 4 and 5 are exemplary, and the actual relative timing can vary from that described without departing from the scope of the present disclosure.

[0056] Figure 6 A flow diagram of an exemplary method 600 for performing a refresh operation according to embodiments of the present disclosure is depicted. The method 600 can be performed by the row address control circuit 140 of Figure 1 and / or the row address control circuit 200 of Figure 2 .

[0057] Method 600 can be performed during a refresh operation. Method 600 can include determining, at 610, a respective row of memory cells in each of a plurality of sections of a bank of a memory device that are scheduled for refresh. The determination can be made by refresh section counter circuit 220, address latch 210, and predecoder 212 of FIG. 1. Figure 2 In some examples, method 600 can further include latching a global row address (e.g., by address latch 210 of FIG. 1). The respective row of memory cells in each of the plurality of sections that are scheduled for refresh can be based on the global row address. In some examples, method 600 can further include decoding the global row address to provide a predecoded row address (e.g., by predecoder 212 of FIG. 1). The respective row of memory cells in each of the plurality of sections that are scheduled for refresh can be based on the predecoded row address. Figure 2 Figure 2

[0058] Method 600 can further include determining, at 620, whether the respective row of memory cells in a particular section of the plurality of sections of the bank that are scheduled for refresh has been repaired. In some examples, method 600 can further include comparing an address associated with the respective row of memory cells that are scheduled for refresh to an address corresponding to a repaired row stored in a register. The determination and comparison can be made by redundancy match register 230 of FIG. 1. Figure 2

[0059] Method 600 can further include, at 630, in response to determining that the row of memory cells that are scheduled for refresh has been repaired, causing refresh within the particular section of the bank to be skipped while performing refresh of the row of memory cells that are scheduled for refresh in other sections of the plurality of sections of the bank that are to be refreshed. The skip activation can be based on a signal provided from row selector 240 to row decoder 258 of FIG. 1. In some examples, method 600 can further include delaying activation of word lines in the plurality of sections until after determining whether the respective row of memory cells in the particular section of the plurality of sections that are scheduled for refresh has been repaired. In some examples, the activation of the word lines in the plurality of sections is delayed until after determining whether the respective row of memory cells in the particular section of the plurality of sections that are scheduled for refresh has been repaired by a delay circuit (e.g., delay circuit 250, flip-flop 252, OR gate 254, and AND gate 256 of FIG. 1). Figure 2 Figure 2 In some examples, method 600 can further include decoding, by a row decoder, the row address detected as operational that corresponds to the respective row of memory cells in each of the plurality of sections that are scheduled for refresh.​​​​

[0060] In some examples, the refresh operation includes a row hammer refresh, followed by a normal refresh. In some examples, the method 600 can further include determining whether the respective memory cell rows of the particular section of the plurality of sections that are scheduled to be refreshed have been repaired during the row hammer refresh portion of the refresh operation.

[0061] From the foregoing, it will be appreciated that, although specific embodiments of the disclosure have been described herein for purposes of illustration, various modifications can be made without deviating from the spirit and scope of the disclosure. Accordingly, the scope of the disclosure should not be limited to the specific embodiments described herein.

Claims

1. A memory device comprising: a memory bank having a plurality of sections; a row address control circuit, during a refresh operation at the memory bank, wherein the refresh operation includes a row hammer refresh, followed by a normal refresh, the row address control circuit configured to determine, during the row hammer refresh, whether a respective row of memory cells in each section of the plurality of sections that is scheduled for refresh has been repaired, and in response to determining that the respective row of memory cells in a particular section of the plurality of sections has been repaired, cause the memory bank to skip refresh in the particular section, while performing refresh in the respective row of each section of the plurality of sections that is detected to be operational during the normal refresh.

2. The memory device of claim 1, wherein the row address control circuit includes a register configured to compare the respective rows of memory cells that are scheduled for refresh to rows of memory cells that have been repaired to determine whether any of the respective rows of memory cells that are scheduled for refresh have been repaired.

3. The memory device of claim 1, wherein the row address control circuit further includes a delay circuit for delaying activation of word lines in the plurality of sections until after determining whether the respective row of memory cells in each section of the plurality of sections that is scheduled for refresh has been repaired.

4. The memory device of claim 3, wherein the delay circuit includes a flip-flop configured to delay a row decoder enable signal in response to a control signal set based on initiation of the refresh operation.

5. The memory device of claim 1, wherein the row address control circuit further comprises a row decoder configured to decode row addresses that are detected to be operational, the row addresses corresponding to the respective rows of memory cells in each section of the plurality of sections that are scheduled for refresh.

6. The memory device of claim 1, wherein the row address control circuit further comprises an address latch configured to latch a global row address, wherein the respective rows of memory cells in each section of the plurality of sections that are scheduled for refresh are based on the global row address.

7. The memory device of claim 6, wherein the row address control circuit further comprises a predecoder circuit configured to determine predecoded row addresses from the global row address, wherein the respective rows of memory cells in each section of the plurality of sections that are scheduled for refresh are based on the predecoded row addresses.

8. A memory device comprising: a row decoder configured to decode, during a refresh operation, row addresses corresponding to a plurality of rows of memory cells of a memory bank that are scheduled for simultaneous refresh based on a row match signal, the refresh operation including a row hammer refresh, followed by a normal refresh; a register circuit configured to store a repair row address corresponding to a memory cell row that has been repaired, wherein the register circuit is configured to compare a row address corresponding to the plurality of memory cell rows scheduled to be refreshed concurrently with the memory bank during the row hammer refresh to the repair row address and provide a match signal when a match is detected; a latch circuit configured to latch a bit of the row match signal in response to the match signal being set, wherein the bit of the row match signal corresponds to a memory cell row that has been repaired of the plurality of memory cell rows scheduled to be refreshed concurrently during the normal refresh, wherein the row decoder is configured to skip decoding a memory cell row of the plurality of memory cell rows scheduled to be refreshed concurrently of the memory bank during the normal refresh in response to the latched bit of the row match signal.

9. The memory device of claim 8, further comprising a delay circuit configured to delay enabling the row decoder until after the register circuit has compared the row address corresponding to the plurality of memory cell rows scheduled to be refreshed concurrently of the memory bank to the repair row address.

10. The memory device of claim 9, wherein the delay circuit includes a flip-flop configured to delay providing an enable signal to the row decoder.

11. The memory device of claim 8, further comprising a memory array including a plurality of memory banks including the memory bank.

12. A method for a memory device, comprising: during a refresh operation including a row hammer refresh, followed by a normal refresh: determining a respective memory cell row scheduled to be refreshed in each section of a plurality of sections of a memory bank of the memory device; determining whether the respective memory cell row scheduled to be refreshed of a particular section of the plurality of sections of the memory bank has been repaired during the row hammer refresh; and in response to determining that the memory cell row scheduled to be refreshed has been repaired, skipping refresh within the particular section of the memory bank while performing refresh of the memory cell row scheduled to be refreshed in other sections of the plurality of sections of the memory bank to be refreshed during the normal refresh.

13. The method of claim 12, further comprising comparing an address associated with the respective memory cell row scheduled to be refreshed and an address corresponding to a repair row stored in a register.

14. The method of claim 12, further comprising delaying activation of a word line of the plurality of sections until after determining whether the respective memory cell row scheduled to be refreshed in the particular section of the plurality of sections has been repaired.

15. The method of claim 14, further comprising delaying activation of the word lines in the plurality of sections by a flip-flop until after determining whether the respective rows of memory cells in the particular section of the plurality of sections that are scheduled to be refreshed have been repaired.

16. The method of claim 12, further comprising decoding, by a row decoder, row addresses detected as operable that correspond to the respective rows of memory cells in each section of the plurality of sections that are scheduled to be refreshed.

17. The method of claim 12, further comprising latching a global row address, wherein the respective rows of memory cells in each section of the plurality of sections that are scheduled to be refreshed are based on the global row address.

18. The method of claim 17, further comprising decoding the global row address to provide a pre-decoded row address, wherein the respective rows of memory cells in each section of the plurality of sections that are scheduled to be refreshed are based on the pre-decoded row address.

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