Host refresh control

Abstract

This application relates to host refresh control. A memory device can be operated using a set of refresh control features. A host can access the memory device to discover the set of refresh control features. The host can command the memory device to change at least one of the set of refresh control features. The memory device can be operated using the original and / or changed set of refresh control features.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to memory devices, and more particularly to apparatuses and methods related to host refresh control. BACKGROUND

[0002] Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including volatile and non-volatile memory. Volatile memory can require power to maintain its data and includes random access memory (RAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM), among others. Non-volatile memory can provide persistent data by retaining stored data when not powered and can include NAND flash memory, NOR flash memory, read only memory (ROM), Electrically Erasable Programmable ROM (EEPROM), Erasable Programmable ROM (EPROM), and resistance variable memory such as phase change random access memory (PCRAM), resistive random access memory (RRAM), and magnetoresistive random access memory (MRAM), among others.

[0003] Memory is also used as volatile and non-volatile data storage devices for a wide range of electronic applications. Non-volatile memory can be used, for example, in personal computers, portable memory sticks, digital cameras, cellular telephones, portable music players such as MP3 players, video players, and other electronic devices. Memory cells can be arranged in arrays, where the arrays are used in memory devices.

[0004] Various computing systems include a number of processing resources coupled to memory (e.g., a memory system) that is accessed in association with executing instruction sets (e.g., programs, applications, etc.). Data stored in the memory can be of various types and can often include sensitive data such as passwords and personal information. Due to degradation mechanisms such as charge leakage and / or disturbance mechanisms associated with access units (e.g., read, write, erase, etc.), data stored in the memory becomes less reliable over time. Additionally, data stored in the memory can be intentionally altered by an unauthorized entity (e.g., a hacker) via a row hammer attack, for example. Such unauthorized entities can also attempt to gain or corrupt data stored in the memory that can include sensitive data. SUMMARY

[0005] One aspect of the disclosure provides a method for host refresh control, where the method includes operating a memory device using a set of refresh control features; reading a mode register storing an identifier of a version of the set of refresh control features; transmitting the identifier to a host; receiving a command from the host to change at least one of the set of refresh control features; and operating the memory device using the changed set of refresh control features.

[0006] Another aspect of the disclosure provides an apparatus for host refresh control, comprising: a memory array; and a control circuit coupled to the memory array, and where the control circuit is configured to: refresh the memory array according to a predefined set of refresh control features; and change at least one of the predefined set of refresh control features in response to a command from a host.

[0007] Another aspect of the disclosure provides a non-transitory machine-readable medium storing instructions executable to cause a machine to: access an identifier indicative of a refresh control version of a memory device; look up features supported by the refresh control version based on the identifier; and command the memory device to use a particular feature supported by the refresh control version. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 A block diagram of an apparatus in the form of a computing system including a memory system having a memory device with refresh control circuitry, in accordance with the present disclosure.

[0009] Figure 2 A block diagram of an apparatus in the form of a memory device having refresh control circuitry, in accordance with the present disclosure.

[0010] Figure 3 A block diagram of refresh control circuitry, in accordance with the present disclosure.

[0011] Figure 4A A block diagram of a number of mode registers on a memory device having refresh control circuitry, in accordance with the present disclosure.

[0012] Figure 4B A block diagram of a number of mode registers on a memory device having refresh control circuitry, in accordance with the present disclosure.

[0013] Figure 5 A flow diagram to illustrate a method for host refresh control, in accordance with the present disclosure.

[0014] Figure 6 A flow diagram to illustrate an example host refresh control process, in accordance with the present disclosure.

[0015] Figure 7 A flow diagram to illustrate another example host refresh control process, in accordance with the present disclosure. DETAILED DESCRIPTION

[0016] The present disclosure includes devices and methods related to host refresh control. Host refresh control refers to a host of a memory device that has some ability to control how the memory device conducts refresh operations. Refresh operations are a common background operation for DRAM memory devices. In DRAM, each data value (e.g., bit) is stored as the presence or absence of an electrical charge on a capacitor. Over time, the electrical charge can leak away and can be lost without a refresh operation. For example, a DRAM cell can be refreshed by charging a capacitor that acts as the cell’s charge storage structure to a particular voltage. Typically, refresh operations are controlled entirely by the memory device itself without the host. Typically, the host is not able to control or change anything about the refresh operations.

[0017] Row hammering refers to undesired changes in the capacitor voltage of a DRAM cell of a given row in response to the given row or an adjacent row being frequently accessed. As an example, a hacker can employ a row hammering attack to intentionally alter data stored in memory by repeatedly accessing a particular row quickly in succession. Refreshing the cells at a faster rate (e.g., more frequently) can improve the reliability of the data stored in the memory cells by reducing the row hammering effect. However, increasing the refresh rate involves increasing power consumption. Prior to deployment of a memory device, the memory device is typically preconfigured with a predefined set of refresh control features. However, future security vulnerabilities cannot always be predicted.

[0018] To address these and other issues associated with some previous approaches, at least one embodiment of the present disclosure provides a host of a memory device with some control measures over refresh operations of the memory device. Refresh operations can be implemented with different parameters, referred to herein as refresh control features. Refresh operations can be defined by a set of refresh control features. According to at least one embodiment of the present disclosure, the host can command the memory device to change at least one of the set of refresh control features. The changed refresh control feature can address, for example, a newly discovered security vulnerability of the memory device associated with a row hammering attack. Additional embodiments and advantages are described in greater detail below.

[0019] As used herein, the singular forms “a,” “an,” and “the” include both singular and plural referents unless the context clearly dictates otherwise. Additionally, the word “may” is used herein in a permissive sense (i.e., having the potential to), rather than in a mandatory sense (i.e., must). The term “include” and its derivatives mean “including, but not limited to.” The term “coupled” means directly or indirectly connected.

[0020] The drawings herein follow a numbering convention in which the first numeral or numerals correspond to the drawing figure number and the remaining numerals identify an element or component within the drawing figure. Similar elements or components between different figures can be identified by the use of similar numerals. For example, 210 can represent element "10" in Figure 2 , and similar elements can be represented as 310 in Figure 3 . Similar elements within a figure can be generally referred to without the use of a hyphen and additional numbers or letters. For example, elements 108-1, 108-2, 108-3, and 108-M in Figure 1 may be collectively referred to as 108. As used herein, the designators "N" and "M", particularly with respect to reference numerals in the drawings, indicate that a number of the particular feature (e.g., elements, components, members, steps, operations, etc.) can be included. As will be understood by those of skill in the art, elements shown in various embodiments herein can be added, exchanged, and / or eliminated so as to provide a number of additional embodiments of the present disclosure. In addition, as will be appreciated, the proportion and the relative scale of the elements provided in the figures are intended to illustrate certain embodiments of the application and should not be taken in a limiting sense.

[0021] Figure 1A block diagram of a device in the form of a computing system 100 including a host 102 and a memory system 104 having memory devices 108-1, 108-2, 108-3,... 108-M with refresh control circuits 110-1, 110-2, 110-3,... 110-M in accordance with the present disclosure. As used herein, a computing system 100, a host 102, a memory system 104, or a memory device 108, for example, can also be considered individually as an “device.” In this example, the computing system 100 includes a host 102 coupled to a memory system 104 via an interface. The interface can pass control signals, address signals, data signals, and other signals between the memory system 104 and the host 102. The interface can include a command / address bus 112 and a data bus 116-1,... 116-N. In some embodiments, the command / address bus 112 can be made up of separate command and address buses. In some embodiments, the command / address bus 112 and the data bus 116 can be part of a common bus. The command / address bus 112 can pass signals from the host 102 to the controller 106, such as a clock signal for timing, a reset signal, a chip select, an address of a memory device 108, parity information, etc. The command / address bus 112 can be used by the controller 106 to send warning signals to the host 102. The command / address bus 112 can be operated in accordance with a protocol. The interface can be a physical interface that employs a suitable protocol. This protocol can be custom or proprietary, or the interface can employ a standardized protocol, such as Peripheral Component Interconnect Express (PCIe), Gen-Z interconnect, Cache Coherent Interconnect for Accelerators (CCIX), etc. In some cases, the controller 106 is a register clock driver (RCD), such as an RCD employed on an RDIMM or LRDIMM. In some embodiments, the memory system 104 includes a serial presence detect (SPD) hub 115 or just “hub,” which can include temperature sensors, clock functionality, isolation circuitry (e.g., the ability to isolate the bus on a module, such as one or more buses 114, from other buses or the host 102 (e.g., via bus 112 or buses 116).

[0022] The computing system 100 can be a personal laptop computer, a desktop computer, a digital camera, a mobile telephone, a memory card reader, or an Internet of Things (IoT) enabled device, among various other types of systems. The computing system 100 has been simplified for clarity to focus on features relevant to the present disclosure. The host 102 can include one or more processing resources (e.g., one or more processors, microprocessors, or some other type of controlling circuitry) capable of accessing the memory system 104. In some embodiments, the memory system 104 and / or the memory devices 108 can be preconfigured with a predefined set of refresh control features prior to deployment of the memory system 104 (e.g., prior to sale, shipping, or use of the memory system 104). For example, the memory devices 108, each of which can be configured with a respective set of refresh control features and an identifier of a version of the set of refresh control features, can be stored in the SPD hub 115, one or more fuses associated with the memory devices 108, and / or one or more mode registers associated with the memory devices 108, as described in greater detail herein. The host 102 can be configured to read the version information from the SPD hub 115 and / or to command the memory devices 108 to read the version information from the fuses or mode registers therein. In contrast to some previous approaches, the host 102 can be configured to command the memory system 104 and / or the memory devices 108 to change at least one of the set of refresh control features. Giving the host 102 some control over refresh operations allows for updating refresh operations after the memory devices 108 have been deployed in the field (e.g., by a customer), for example, in response to a newly detected vulnerability associated with a default refresh operation of the memory devices 108.

[0023] The memory system 104 can provide main memory for the computing system 100 or can be used as additional memory or storage throughout the computing system 100. Each memory device 108 can be a separate memory die, which can also be referred to as a chip. Each memory device 108 can include one or more arrays of memory cells. By way of example, the memory system 104 can be a dual in-line memory module (DIMM) that includes memory devices 108 operating as double data rate (DDR) DRAM, such as DDR5, graphics DDR DRAM, such as GDDR6, or another type of memory system. Embodiments are not limited to a particular type of memory system 104. Other examples of memory devices 108 include RAM, ROM, SDRAM, PCRAM, RRAM, flash memory, and three-dimensional cross-point, among others. Cross-point arrays of non-volatile memory can store bits based on changes in bulk resistance in conjunction with stackable cross-gridded data access arrays. Additionally, cross-point non-volatile memory can perform in-situ write operations, where a non-volatile memory cell can be programmed without previously erasing the non-volatile memory cell, as compared to many flash-based memories. Memory devices 108-1, 108-2 are coupled to a first data bus 116-1. Memory devices 108-3, 108-M are coupled to a second data bus 116N. The data buses 116 can provide data for read / write operations between the host 102 and the memory system 104.

[0024] The memory system 104 can include a controller 106 coupled to the memory devices 108 via respective buses 114-1, 114-2, 114-3, 114-M. The buses 114 can be referred to as internal command / address buses 114 (e.g., internal to the memory system 104, as opposed to the command / address bus 112 between the host 102 and the memory system 104). The controller 106 can be implemented as hardware, firmware, and / or software. For example, the controller 106 can be an application specific integrated circuit (ASIC) coupled to a printed circuit board that includes physical interfaces. The controller 106 can thereby relay command and / or address signals from the host 102 to the memory devices 108. In some embodiments, the controller 106 can perform command and / or address translation before relaying the command and / or address signals from the host 102 to the memory devices 108. The controller 106 can operate the buses 114 in the same or different protocol as the protocol in which the command / address bus 112 is operated between the host 102 and the memory system 104. The controller 106 can use the buses 114 to send command and / or address signals, clock signals, select signals, and other related signals to the memory devices 108. The memory devices 108 can use the buses 114 to send error signals, reset signals, and other related signals to the controller 106. The controller 106 thus provides access to the memory devices 108 for the host 102. Examples of commands for the memory devices 108 include read commands, write commands, and erase commands for data on the memory devices 108, among other commands. The memory system 104 can include separate integrated circuits, or both the controller 106 and the memory devices 108 can be on the same integrated circuit.

[0025] The memory devices 108 are each illustrated as including a refresh control circuit 110. The refresh control circuit 110 can control refresh operations on the respective memory device 108 with which it is associated. Different refresh operations can be defined by different sets of refresh control features. The different refresh operations can be completely different (e.g., every one of the sets of refresh control features is different) or similar (e.g., one or a few of the sets of refresh control features are different). Similar refresh operations with one or a few different refresh control features can be referred to as different versions of a refresh operation when the memory device is configured to operate in different versions of the refresh operation (and different sets of refresh control features). An identifier of a version of a set of refresh control features can be stored in association with the memory device 108, such as in a mode register or a fuse of the memory device 108 and / or in the SPD hub 115 of the memory system 104 that includes the memory device 108. The different versions of the refresh operation can be referred to with respect to the different sets of refresh control features. Figures 2-3 The refresh control circuit 110 is described in more detail.

[0026] Figure 2A block diagram of a device in the form of a memory device 208 having refresh control circuit 210, in accordance with the present disclosure. Memory device 208 is similar to any of the memory devices 108 described in Figure 1

[0027] Data can be provided to and / or from the memory array 226 via data lines that couple the memory array 226 to input / output (I / O) circuitry 222 via read / write circuitry 230. The I / O circuitry 222 can be used for bidirectional data communication between the host 202 through the interface. The read / write circuitry 230 is used to write data to and read data from the memory array 226. As examples, the read / write circuitry 230 can include various drivers, latching circuitry, and the like. In some embodiments, the data path can bypass the controller (e.g., controller 106 described in Figure 1

[0028] ​​The memory device 208 includes an address circuit 220 to latch address signals provided over the interface. A row decoder 224 and a column decoder 232 receive address signals and decode them to access the memory array 226. Data from the memory array 226 can be read in by using the sense circuit 228 to sense voltage and / or current changes on the sense lines. The sense circuit 228 can be coupled to the memory array 226. Each memory array 226 and corresponding sense circuit 228 can constitute a bank of the memory device 208. The sense circuit 228 can include, for example, a sense amplifier that can read and latch a page (e.g., a row) of data from the memory array 226. Sensing (e.g., reading) a bit stored in a memory cell can involve sensing a relatively small voltage difference on a pair of sense lines, which can be referred to as digit lines or data lines. Thus, it can be beneficial to provide an increased voltage difference to be sensed. For example, more than one storage structure (e.g., a capacitor) can be used to store a particular bit value. As one example, in a transistor-capacitor (1T1C) DRAM cell, a charge corresponding to a bit value is stored on (and sensed from) a single capacitor. In contrast, in a 2T2C DRAM cell, a charge is stored on (and sensed from) two capacitors via differential digit lines coupled to a sense amplifier. Thus, for example, as compared to a 1T1C memory cell, a 2T2C memory cell can have increased sensing margin and can be less susceptible to adverse effects due to charge leakage. However, a memory array employing 2T2C cells has a reduced storage density as compared to a memory array employing 1T1C cells.

[0029] The memory array 226 can include memory cells arranged in rows coupled by access lines (which can be referred to herein as word lines or select lines) and columns coupled by sense lines (which can be referred to herein as digit lines or data lines). Although the memory array 226 is shown as a single memory array, the memory array 226 can represent a plurality of memory arrays arranged in banks of the memory device 208. The memory array 226 can include a number of memory cells, such as volatile memory cells (e.g., DRAM memory cells, among other types of volatile memory cells) and / or non-volatile memory cells (e.g., RRAM memory cells, among other types of non-volatile memory cells).

[0030] According to at least one embodiment of the present disclosure, the control circuit 218 also includes a refresh control circuit 210. However, embodiments are not so limited as some embodiments include a refresh control circuit 210 separate from the control circuit 218. As illustrated, the refresh control circuit 210 is coupled to the address circuit 220, the I / O circuit 222, and the column decode 232 and the row decode 224. Commands by the control circuit 218 (e.g., from the host 202) can also pass through the refresh control circuit 210. Relative to the refresh control circuit 210, the refresh control circuit 210 is configured to refresh the memory array 226 according to a predefined set of refresh control features. The refresh control circuit 210 is also configured to change at least one of the predefined set of refresh control features in response to a command from the host. Figure 3 The refresh control circuit 210 is described in more detail.

[0031] Access commands from the host 202 can include one or more commands such as a precharge command, an activate command, a read command, and / or a write command, among other possible commands. In various embodiments, an access command can propagate into multiple access commands. For example, an access command can be a read command that can propagate into access commands including a precharge command, an activate command, and a read command. According to the present disclosure, the host 202 can be configured to provide a new type of access command to read version information and / or change at least one of a set of refresh control features of the refresh control circuit 210. In at least one embodiment, the version information is merely an identifier of a version of the set of refresh control features that the memory device operates using. In at least one embodiment, the version information includes specific details identifying a value of the set of refresh control features that the memory device 208 operates using.

[0032] In some embodiments, the version information and / or the set of refresh control features can be protected by the memory device 208. In such embodiments, if the host 202 sends a valid key input sequence prior to sending an access command of the refresh control circuit 210, the access command can be verified. The key input sequence can be a specific sequence of commands that can be verified against a sequence identifier stored in the memory device 208 (e.g., in a mode register). If the key input sequence matches the stored sequence identifier, the memory device 208 can proceed with the command issued by the host 202. If the key input sequence does not match the stored sequence identifier, the memory device will not proceed with the command issued by the host 202.

[0033] In at least one embodiment, the refresh control circuit 210 is configured to refresh the memory array 226 according to a predefined set of refresh control features. The refresh control circuit 210 is also configured to change at least one of the predefined set of refresh control features in response to a command from the host.

[0034] Figure 3 A block diagram of a refresh control circuit 310 according to the present disclosure. The refresh control circuit 310 can be similar to the refresh control circuit 210 as described above with respect to the memory device 208. The refresh control circuit 310 is configured to refresh the memory array 226 according to a predefined set of refresh control features. The refresh control circuit 310 is also configured to change at least one of the predefined set of refresh control features in response to a command from the host. Figure 2The control circuitry of the memory device illustrated in FIG. 1 can be integrated with, or can include one or more ASICs separate from, the control circuitry of the memory device. The refresh control circuit 310 can be coupled to the command / address bus (Cmd / Addr bus) 314, the memory array 326, and the I / O circuit 322 (e.g., via a data bus). The command / address bus 314 can be coupled to a controller (e.g., the controller 106 illustrated in FIG. 1) or a host (e.g., the host 102 illustrated in FIG. 1), while the I / O circuit 322 can be coupled to the host. Figure 1 The controller 106 illustrated in FIG. 1) or a host (e.g., the host 102 illustrated in FIG. 1), while the I / O circuit 322 can be coupled to the host. Figure 1 The controller 106 illustrated in FIG. 1) or a host (e.g., the host 102 illustrated in FIG. 1), while the I / O circuit 322 can be coupled to the host.

[0035] The refresh control circuit 310 can include a refresh circuit 334 responsible for controlling refresh operations of the memory array 326. The refresh control circuit 310 can also include a fuse option 336 and several mode registers, such as a test mode / default "TM / DFT" register 338, a write register 340, a read-only register 342, and / or an on-die memory array (not specifically illustrated). The fuse option 336 block represents a fuse or antifuse (e.g., read-only memory) that stores default settings for the memory array 326. Embodiments are not limited to the refresh control circuit 310 including any particular number of registers. The refresh control circuit 310 can include more or fewer registers than those illustrated in FIG. 1. Figure 3 The refresh control circuit 310 can include more or fewer registers than those illustrated in FIG. 1.

[0036] The TM / DFT register 338 includes control logic for a test mode and configurable default settings for the memory array 326. The memory array 326 operates at least with respect to refresh operations based on information stored in the TM / DFT register 338 and controlled by the refresh circuit 334. The fuse option 336 can be coupled to the TM / DFT register 338. The TM / DFT register 338 can store configurable default settings based at least in part on a state of the fuse option 336. The state of the fuse option 336 can represent default refresh control features of the memory array 326. Based on reading the fuse option 336 and / or receiving information from the fuse option 336, the TM / DFT register 338 can at least initially store values indicating the same default refresh control features as the fuse option 336.

[0037] Write register 340 can be accessed and written by the host. In some embodiments, the host can access write register 340 via refresh circuit 334 (as illustrated). In some embodiments, write register 340 can be accessed by the host without passing through refresh circuit 334 (not specifically illustrated). Ultimately, whether or not via refresh circuit 334, the host can access write register 340 via command / address bus 314. The host can cause a change in at least one of the set of refresh control features by causing the memory device to write a value to write register 340 that indicates the changed refresh control feature. Write register 340 can communicate information to TM / DFT register 338 in order to update the control of refresh operations of memory array 326 by refresh circuit 334 using the changed refresh control feature.

[0038] Read-only register 342 can be accessed by the host to read an identifier of a version of the set of refresh control features used by the memory device. A command from the host to read the version identifier can be received via command / address bus 314 via refresh circuit 334 (as illustrated) or directly (not specifically illustrated). The version identifier can be transmitted to the host via I / O circuit 322. In the alternative or in addition to storing the version identifier in an SPD hub (e.g., SPD hub 115 illustrated in Figure 1 Fuses option 336 can be coupled to read-only register 342. Based on reading fuses option 336 and / or receiving information from fuses option 336, read-only register 342 can at least initially store a value that indicates the same default refresh control features as fuses option 336.

[0039] As described in greater detail herein, in some embodiments, the host can track memory access diagnostic data for memory array 326. In some embodiments, the memory device can track such diagnostic data. Although not specifically illustrated, refresh control circuit 310 can include registers that can be written by the memory device and can be read by the host. Refresh control circuit 310 can be configured to write values indicating memory access diagnostic data to the registers for later reading by the host such that the host can analyze the diagnostic data to detect suspicious access patterns and adjust new control features used by the memory device accordingly.

[0040] Figures 4A-4B A block diagram illustrating a number of mode registers 444 on a memory device having refresh control circuitry in accordance with the present disclosure is illustrated. Due to space limitations, the diagram is split into two sheets of paper. Figures 4A-4BThe mode register 444 described herein is used for DDR5 DRAM memory. Mode register 444 can be read and / or written based on commands from the host, controller, and / or control circuitry. Mode register 446, marked "RFU," indicates that it is reserved for future use. This mode register 446 can be used to fill in the blanks in the above description. Figure 3 The function of the described mode registers (e.g., TM / DFT register 338, write register 340, read-only register 342, etc.) is explained.

[0041] Figure 5 A flowchart illustrating a method for host refresh control according to this disclosure. Figure 5 The method described herein can, for example, refresh the control circuit (e.g., Figure 3 The refresh control circuit 310 described herein is used for this purpose. At block 550, the method may include operating the memory device using a set of refresh control features. At block 552, the method may include the memory device reading a mode register (e.g., a register storing an identifier of the refresh control version) from the memory device. Figure 3 The TM / DFT register 338 and / or read-only mode register 342 described herein. At box 554, the method may include transmitting an identifier to a host. At box 556, the method may include receiving a command from the host to change at least one of the refresh control feature sets. At box 558, the method may include operating the memory device using the changed refresh control feature set. As described above, the prior approach does not provide the host with the ability to read and / or change refresh control features. The memory device may also change the refresh control feature set independently of any command from the host. For example, these changes may be implemented periodically to keep an eye on attempts to exploit a specific refresh control feature set with a well-designed line hammer attack. The identifier may be written to the mode register before the memory device is deployed (e.g., by the manufacturer of the memory device).

[0042] Although not specifically stated, the method may include writing a value indicating the changed refresh control feature to a mode register in response to receiving a command to change at least one refresh control feature (e.g., Figure 3(Write register 340 as described herein). In at least one embodiment, the value can be written in response to receiving a valid key input sequence from the host before (e.g., immediately before) receiving a command to change at least one refresh control feature. As described herein, such embodiments are advantageous because the key input sequence can be known or provided to an authorized host to the memory device to allow those hosts to change the refresh control feature, while helping to prevent unauthorized entities (e.g., users, hackers, etc.) from changing the refresh control feature. In at least one embodiment, if another command is subsequently received from the host without a valid key input sequence being received, the memory device will not execute the subsequently received command. Similarly, if the original change command is received without a valid key input sequence being received, the original command will not be executed. Not all embodiments employ such additional security features; this can be implemented through programmable options in the memory device.

[0043] Figure 6 A flowchart illustrating the instance host refresh control process according to this disclosure. Figure 6 At least a portion of the process described herein can be executed by a host, for example, by executing instructions stored in a machine-readable medium (e.g., software, firmware, etc.). At 660, the process begins at a computing system (e.g., Figure 1 The computing system 100 described herein is powered on. At 662, the computing system can read the refresh control circuit version, which is similar to the version of the refresh control feature set. The host can access the version information, which is embodied in the instruction memory device (e.g., Figure 2 The refresh control version identifier of the memory device 208 described herein. This information can be obtained by the host from the SPD hub (e.g., Figure 1 The SPD hub 115 described herein) or from the refresh control circuit (e.g., Figure 3 The refresh control circuit 310 described herein reads the read-only register.

[0044] At 664, the computing system can look up based on the version bits received from the memory. The host can look up the features supported by the refresh control version based on the identifier. Such information (features supported by the refresh control version) can be provided by the manufacturer of the memory device and used by the host to make changes to it. Such changes can be made, for example, with intent to configure the memory to a particular host self-select setting, to prevent future security risks, or for reasons other than security. By way of example, the manufacturer of the memory device can implement the refresh control function using different refresh control circuitry, different versions of refresh control circuitry, or different versions of the refresh control function implemented by different memory devices. The manufacturer can make the memory refresh features used by different memory devices, circuitry, or versions of it available to select (e.g., trusted) development partners. In some embodiments, the lookup information is provided by the manufacturer of the memory device to the entity that manufactures the host. In some embodiments, the lookup information can be stored in the firmware of the memory device itself and accessed by the host during operation of the memory device. In such embodiments, the host can select a particular feature from among the features supported by the refresh control version of the memory device.

[0045] At 665, the computing system can write the desired refresh control circuitry settings to the memory (e.g., DRAM). The host can command the memory device to use a particular feature supported by the refresh control version. Another reason for the host to reference the lookup information is to confirm that the desired refresh control feature is actually supported by the memory device before commanding the memory device to implement it. At 667, the memory device updates its behavior according to the settings written by the host.

[0046] Figure 7 To illustrate a flowchart of another example host refresh control process according to the present disclosure. Figure 7 The process illustrated in Figure 6 The process illustrated in can be implemented together with the process illustrated in. At 770, upon power up of the computing system, the refresh control circuitry of the memory device is initialized. At 772, the system can monitor the access behavior of the memory device. For example, the access pattern can be monitored in order to detect suspicious access patterns or suspicious behavior, as illustrated at 774. If no suspicious behavior is detected, the memory device can continue to operate using the current or default refresh control version and / or features, and the host can continue to monitor. However, if suspicious behavior is detected, the host can command the memory device to use more restrictive features supported by the refresh control version based on the detected suspicious access pattern. Examples of suspicious behavior include a large amount of activity to a limited set of addresses of the memory array, extensive use of a particular address of the memory array, and a particular sequence or pattern of address accesses, among others. At 776, the host can write the more stringent refresh control circuitry settings to the write registers of the memory device. The memory device can then be operated using the new settings.

[0047] After a period of time, the suspicious behavior can subside, as indicated at 778. The host can determine that the suspicious access pattern has subsided after further monitoring of the access pattern. In response thereto, the host can command the memory device to use less restrictive features supported by the refresh control version. At 779, the host can write a less stringent refresh control circuit setting to a write register of the memory device. In at least one embodiment, the host can command the memory device to revert to a previous refresh control feature setting in response to the suspicious activity subsiding. The memory device can then be operated using the new setting.

[0048] Embodiments can include a tangible machine-readable storage medium (also known as computer-readable medium), on which is stored one or more sets of instructions or software embodying any one or more of the methodologies or functions described herein. In some embodiments, a memory device or a processing device constitutes a machine-readable medium. The term "machine-readable storage medium" includes a single medium or multiple media, storing the one or more sets of instructions. The term "machine-readable storage medium" includes any medium that is capable of storing or encoding a set of instructions for execution by the machine and that cause the machine to perform any one or more of the methodologies of the present disclosure. The term "machine-readable storage medium" can include, but is not limited to, solid-state memories, optical media, and magnetic media.

[0049] While specific embodiments have been illustrated and described herein, it will be appreciated that various arrangements can be devised in the implementation of an arrangement calculated to implement the same. The disclosure is intended to cover any adaptations or variations of various embodiments of the disclosure. It should be understood that the above description is illustrative only and not restrictive. Combinations of the above embodiments, and other embodiments not specifically described herein, will be apparent to those of ordinary skill in the art upon reviewing the above description. The scope of various embodiments of the disclosure includes other applications in which the above structures and methods are used. Accordingly, the scope of various embodiments of the disclosure should be determined with reference to the appended claims, along with the full range of equivalents to which such claims are entitled. The disclosure is not limited to the embodiments described herein but can vary and modify its features to suit specific needs or application.

[0050] In the foregoing Detailed Description, various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the disclosed embodiments of the present disclosure require more features than are explicitly recited in each claim. Rather, inventive subject matter lies in fewer than all features of a single disclosed embodiment. Thus, the following claims are hereby expressly incorporated into this Detailed Description, with each claim standing on its own as a separate embodiment.

Claims

1. A method for host refresh control, comprising: Use a set of refresh control features to operate the memory device; Read the mode register, which stores the identifier of the version of the refresh control feature set; Transmit the identifier to the host; Receive a command from the host to change at least one of the refresh control feature set; The memory device is operated using the modified set of refresh control features; as well as The refresh control feature set is changed periodically, independent of any commands from the host.

2. The method of claim 1, further comprising writing a value indicating the changed refresh control feature to a different mode register in response to receiving a command to change the at least one refresh control feature.

3. The method of claim 1, further comprising writing the identifier into the mode register prior to deploying the memory device.

4. The method of claim 1, further comprising: In response to receiving a command to change the at least one refresh control feature, a value indicating the changed refresh control feature is written to the mode register.

5. The method of claim 4, wherein writing the value comprises writing the value in response to receiving a valid key input sequence from the host before receiving the command to change the at least one refresh control feature.

6. The method of claim 5, further comprising: Receive a subsequent command to change at least one of the refresh control feature set without immediately receiving the valid key input sequence from the host before receiving the subsequent command; as well as The subsequent commands will not be executed.

7. A device for host refresh control, comprising: Memory array; as well as A control circuit system coupled to the memory array, wherein the control circuit system is configured to: The memory array is refreshed according to a predefined set of refresh control features; In response to a command from the host, change at least one of the predefined refresh control features; and The predefined set of refresh control features is changed periodically, independent of any commands from the host.

8. The device of claim 7, further comprising a serial presence detection hub that stores an identifier of the version of the refresh control feature set.

9. The device of claim 7, further comprising a read-only mode register accessible by the host, which stores an identifier of a version of the refresh control feature set.

10. The device of claim 7, further comprising a writable mode register accessible by the host to store changes to the predefined set of refresh control features; and The control circuit system is configured to refresh the memory array according to the modified set of refresh control features.

11. The device of claim 7, further comprising a writable mode register readable by a host; and The control circuitry is configured to write a value indicating memory access to diagnostic data into the writable mode register.

12. The device of claim 7, wherein one of the refresh control feature set includes a frequency for refreshing the memory array.

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