Decoding of low density parity check codes with highly variable nodes

Abstract

The present disclosure relates to decoding of low-density parity-check codes with highly variable nodes. Apparatuses, systems, and methods for improving decoding operations of a decoder are described. An example method includes receiving a noisy codeword based on a transmitted codeword generated from a low-density parity-check (LDPC) code, the LDPC code having an associated parity-check matrix comprising N columns, wherein each column of at least B columns of the parity-check matrix has a column weight that exceeds a predetermined column weight; processing the N columns based on a message passing algorithm; and determining a candidate version of the transmitted codeword based on the processing, wherein processing each column of the N columns comprises performing a read operation, a variable node update (VNU) operation, and a check node update (CNU) operation on a first set and a second set, the read operation and the CNU operation being performed on each column of the at least B columns spanning two or more time steps.

Description

TECHNICAL FIELD

[0001] The present patent document generally relates to a memory device, and more specifically, to error correction in a non-volatile memory device. BACKGROUND

[0002] Data integrity is an important feature of any data storage device and data transmission. It is recommended to use strong error correction codes (ECC) for various types of data storage devices, including NAND flash memory devices.

[0003] Solid state drives (SSDs) use multi-layered NAND flash memory devices for persistent storage. However, multi-layered NAND flash memory devices are inherently unreliable, and typically require the use of ECC at the expense of additional storage space for ECC parity bits to significantly improve data reliability. There is a need for increasingly efficient ECCs that can provide data protection with lower complexity and lower latency. SUMMARY

[0004] Embodiments of the disclosed technology relate to an efficient decoding method for low-density parity-check (LDPC) codes with highly variable nodes. Processing low-weight columns in a single time step and high-weight columns in multiple time steps using a pipelined architecture facilitates reducing the read latency of the controller and improving the reliability of the SSD.

[0005] In an example aspect, a method for improving decoding operations of a decoder is described. The method includes receiving a noisy codeword based on a transmitted codeword generated from a low-density parity-check (LDPC) code, the LDPC code having an associated parity check matrix including N columns, where N is a positive integer, where each column of at least B columns of the parity check matrix has a column weight that exceeds a predetermined column weight, where B is a positive integer, and where B < N; processing the N columns based on a message passing algorithm between a plurality of variable nodes and a plurality of check nodes, the plurality of check nodes representing the parity check matrix of the LDPC code; and determining a candidate version of the transmitted codeword based on the processing, where processing each column of the N columns includes partitioning the check nodes in each column into at least a first set and a second set; and performing a read operation, a variable node update (VNU) operation, and a check node update (CNU) operation on the first set and the second set, where the first set is performed on the read operation, the VNU operation, and the CNU operation before the second set, and where performing the read operation and the CNU operation on each column of the at least B columns spans two or more time steps.

[0006] In yet another example aspect, the above-described method can be implemented by a video encoder device or a video decoder device including a processor.

[0007] In yet another example aspect, the methods can be embodied in the form of processor-executable instructions and stored on a computer-readable program medium.

[0008] The subject matter described in this patent document can be implemented in specific ways that provide one or more of the following features. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 An example of a memory system is shown.

[0010] Figure 2 is an illustration of an example non-volatile memory device.

[0011] Figure 3 is an example graph showing a cell voltage level distribution (V th ) of a non-volatile memory device.

[0012] Figure 4 is another example graph showing a cell voltage level distribution (V th ) of a non-volatile memory device.

[0013] Figure 5 is an example graph showing a cell voltage level distribution (V th ) of a non-volatile memory device before and after program disturb.

[0014] Figure 6 is an example graph showing a cell voltage level distribution (V th ) of a non-volatile memory device as a function of a reference voltage.

[0015] Figure 7 An example schedule for a 3-stage pipeline decoder for a low-density parity-check (LDPC) code and a quasi-cyclic low-density parity-check (QC-LDPC) code is shown.

[0016] Figure 8 Another example schedule for a 3-stage pipeline decoder for an LDPC code with a B column having a high column weight is shown.

[0017] Figure 9 A flowchart of an example method for improving decoding operations of a decoder in a non-volatile memory is shown. DETAILED DESCRIPTION

[0018] Solid state drives (SSDs) are a new generation of storage devices used in computers. SSDs replace traditional mechanical hard drives by using significantly faster flash-based memory. Because of the short read access times and fast throughput, SSDs can significantly improve the speed of a computer. SSDs can be configured to use LDPC codes or quasi-cyclic LDPC (QC-LDPC) codes to correct any bit errors in pages read from NAND media. LDPC and QC-LDPC codes are used to ensure the integrity of data in storage systems using new generation of NAND flash memory.

[0019] Figures 1 to 6 Non-volatile memory systems (e.g., flash-based memory, NAND flash) in which embodiments of the disclosed technology can be implemented are summarized.

[0020] Figure 1 is a block diagram illustrating an example of a memory system 100 implemented based on some embodiments of the disclosed technology. The memory system 100 includes a memory module 110 that can be used to store information for use by other electronic devices or systems. The memory system 100 can be incorporated (e.g., located on a circuit board) into other electronic devices and systems. Alternatively, the memory system 100 can be implemented as an external storage device such as a USB flash drive and a solid state drive (SSD).

[0021] The memory module 110 included in the memory system 100 can include memory regions (e.g., memory arrays) 102, 104, 106, and 108. Each of the memory regions 102, 104, 106, and 108 can be included in a single memory die or multiple memory dies. The memory dies can be included in an integrated circuit (IC) chip.

[0022] Each of the memory regions 102, 104, 106, and 108 includes a plurality of memory cells. Read operations, program operations, or erase operations can be performed based on the memory cells. Thus, each memory cell can include a predetermined number of memory cells. The memory cells in the memory regions 102, 104, 106, and 108 can be included in a single memory die or multiple memory dies.

[0023] The storage units in each of the memory regions 102, 104, 106, and 108 can be arranged in rows and columns in the memory units. Each of the memory units can be a physical unit. For example, a group of multiple storage units can form one memory unit. Each of the memory units can also be a logical unit. For example, the memory units can be blocks or pages, which can be respectively identified by unique addresses such as block addresses or page addresses. For another example, where the memory regions 102, 104, 106, and 108 can include computer memory including banks of logical units as data storage devices, the memory units can be banks that can be identified by bank addresses. During a read or write operation, the unique address associated with a particular memory unit can be used to access the particular memory unit. Based on the unique address, information can be written to or retrieved from one or more storage units in the particular memory unit.

[0024] The storage units in the memory regions 102, 104, 106, and 108 can include non-volatile storage units. Examples of non-volatile storage units include flash storage units, phase change random access memory (PRAM) units, magnetoresistive random access memory (MRAM) units, or other types of non-volatile storage units. In example implementations where the storage units are configured as NAND flash storage units, read operations or write operations can be performed on a page basis. However, erase operations in NAND flash memory are performed on a block basis.

[0025] Each of the non-volatile storage units can be configured as a single-level cell (SLC) or a multi-level storage unit. A single-level cell can store one bit of information per cell. A multi-level storage unit can store more than one bit of information per cell. For example, each of the storage units in the memory regions 102, 104, 106, and 108 can be configured as a multi-level cell (MLC) that stores two bits of information per cell, a triple-level cell (TLC) that stores three bits of information per cell, or a quad-level cell (QLC) that stores four bits of information per cell. In another example, each of the storage units in the memory regions 102, 104, 106, and 108 can be configured to store at least one bit of information (e.g., one bit of information or more than one bit of information), and each of the storage units in the memory regions 102, 104, 106, and 108 can be configured to store more than one bit of information.

[0026] As Figure 1As shown, the memory system 100 includes a controller module 120. The controller module 120 includes a memory interface 121 to communicate with the memory module 110, a host interface 126 to communicate with a host (not shown), a processor 124 to run firmware layer code, and a buffer / cache 123 and system memory 122 to temporarily or persistently store executable firmware / instructions and associated information, respectively. In some embodiments, the controller module 120 can include an error correction engine 125 to perform error correction operations on information stored in the memory module 110. The error correction engine 125 can be configured to detect / correct single-bit errors or multi-bit errors. In another embodiment, the error correction engine 125 can be located in the memory module 110.

[0027] The host can be a device or system that includes one or more processors that operate to retrieve data from or store or write data to the memory system 100. In some embodiments, examples of the host can include a personal computer (PC), a portable digital device, a digital camera, a digital multimedia player, a television, and a wireless communication device.

[0028] In some embodiments, the controller module 120 can also include a host interface 126 to communicate with the host. The host interface 126 can include components that comply with at least one of the host interface specifications, including but not limited to Serial Advanced Technology Attachment (SATA), Serial Attached Small Computer System Interface (SAS) specification, Peripheral Component Interconnect Express (PCIe).

[0029] Figure 2 An example of a memory cell array implemented based on some embodiments of the disclosed technology is shown.

[0030] In some embodiments, the memory cell array can include a NAND flash memory array partitioned into a number of blocks, and each block contains a number of pages. Each block includes a plurality of strings of memory cells, and each string of memory cells includes a plurality of memory cells.

[0031] In some embodiments where the memory cell array is a NAND flash memory array, read operations and write (program) operations are performed on a page basis, and erase operations are performed on a block basis. Before performing a program operation on any page included in a block, all memory cells within the same block must be simultaneously erased. In an embodiment, the NAND flash memory can use an even / odd bit line structure. In another embodiment, the NAND flash memory can use a full bit line structure. In the even / odd bit line structure, even bit lines and odd bit lines are interleaved along each word line and are accessed alternately, such that each pair of even and odd bit lines can share peripheral circuitry such as a page buffer. In the full bit line structure, all bit lines are accessed simultaneously.

[0032] Figure 3 An example of a threshold voltage distribution curve in a multi-layer cell device is shown, in which the number of cells in each program state / erase state is plotted as a function of threshold voltage. As shown, the threshold voltage distribution curve includes an erase state with the lowest threshold voltage (denoted as "ER" and corresponding to "11"), and three program states (denoted as "Pl", "P2", and "P3" corresponding to "01", "00", and "10", respectively) with a read voltage (denoted by the dashed line) between these states. In some embodiments, each of the threshold voltage distributions of program state / erase state has a finite width due to differences in material properties between memory arrays.

[0033] While Figure 3 A multi-layer cell device is shown by way of example, but each of the storage cells can be configured to store any number of bits per cell. In some implementations, each of the storage cells can be configured as single-layer cells (SLC) storing one bit of information per cell, or three-layer cells (TLC) storing three bits of information per cell, or four-layer cells (QLC) storing four bits of information per cell.

[0034] In writing more than one data bit into a storage cell, the threshold voltage levels of the storage cells need to be finely arranged because of the reduced distance between adjacent distributions. This is achieved by using incremental step pulse programming (ISPP), i.e., using a program and verify method on the storage cells on the same word line with repeated programming with a staircase program voltage applied to the word line. Each program state is associated with a verify voltage used in the verify operation, and sets the target position of each threshold voltage distribution window.

[0035] Read errors can be caused by distorted or overlapping threshold voltage distributions. Due to, for example, program and erase (P / E) cycles, cell-to-cell interference, and data retention errors, which will be discussed below, the ideal storage cell threshold voltage distribution can be significantly distorted or overlapping, and in most cases such read errors can be managed by using error correction codes (ECC).

[0036] Figure 4 An example of an ideal threshold voltage distribution curve 410 and an example of a distorted threshold voltage distribution curve 420 are shown. The vertical axis indicates the number of storage cells having a particular threshold voltage represented on the horizontal axis.

[0037] For an n-bit multi-layer cell NAND flash memory, the threshold voltage of each cell can be programmed to 2 n possible values. In an ideal multi-layer cell NAND flash memory, each value corresponds to a non-overlapping threshold voltage window.

[0038] Flash memory P / E cycles cause damage to the tunnel oxide of the floating gate of the charge trapping layer of the cell transistor, resulting in threshold voltage shift, which gradually reduces the noise margin of the memory device. As the P / E cycles increase, the margin between the adjacent distributions of different programmed states decreases, and eventually, the distributions start to overlap. The data bits stored in the memory cells with threshold voltages programmed in the overlapping range of adjacent distributions can be misjudged as a value different from the original target value.

[0039] Figure 5 An example of cell-to-cell interference in NAND flash memory is shown. Cell-to-cell interference also causes threshold voltage distortion of the flash memory cells. The threshold voltage shift of one memory cell transistor can affect the threshold voltage of its neighboring memory cell transistors through parasitic capacitive coupling effects between the interfering cell and the victim cell. The magnitude of the cell-to-cell interference can be affected by the NAND flash memory bit line structure. In an even / odd bit line structure, the memory cells on one word line are connected to even and odd bit lines alternately, and the even cells are programmed before the odd cells on the same word line. Therefore, the even and odd cells are subjected to different amounts of cell-to-cell interference. The cells in a full bit line structure are subjected to less cell-to-cell interference compared to the even cells in the even / odd bit line structure, and the full bit line structure can effectively support high speed current sensing to improve memory read and verify speed.

[0040] Figure 5 The dashed line in the graph represents the nominal distribution of the P / E state of the considered cell (before programming interference), and the "adjacent state value" represents the value to which the adjacent state has been programmed. As Figure 5 shown, if the adjacent state is programmed as PI, the threshold voltage distribution of the considered cell shifts by a certain amount. However, if the adjacent state is programmed as P2, which has a higher threshold voltage than PI, it results in a larger shift compared to the adjacent state PI. Similarly, when the adjacent state is programmed as P3, the shift of the threshold voltage distribution is the largest.

[0041] Figure 6 An example of retention error in NAND flash memory is shown by comparing the normal threshold voltage distribution with the shifted threshold voltage distribution. The data stored in NAND flash memory tends to deteriorate over time, and this is referred to as data retention error. Retention error is caused by the loss of charge stored in the floating gate or charge trapping layer of the cell transistor. Due to the wear and tear of the floating gate or charge trapping layer, the memory cells with more program erase cycles are more prone to retention error. In the example of Figure 6 the top row voltage distribution (before deterioration) is compared with the bottom row distribution (contaminated with retention error), showing a shift to the left.

[0042] Due to their excellent correction performance and low complexity, LDPC codes are commonly used as forward error correction codes in non-volatile memory devices (e.g., as shown in Figures 1-6 An LDPC decoder can be configured to operate using a lower complexity iterative message passing decoding method (e.g., bit flipping, min-sum algorithm, or sum-product algorithm). The decoding latency of the decoder is mainly affected by the scheduling of the iterative message passing decoding method used by the decoder.

[0043] In an example, a decoding method implementing a flooding schedule performs all variable node update (VNU) operations and then performs all check node update (CNU) operations. This flooding decoder has a relatively low complexity implementation, but requires more decoding iteration counts (and thus higher latency) because the updated messages are not used until the next decoding iteration.

[0044] In another example, a vertical scheduling method can be implemented, where the decoder performs VNU operations and then immediately performs CNU operations for the check nodes associated with the just processed variable nodes. This allows the use of the latest values in each node update, and thus, the decoder requires fewer decoding iterations to correct bit errors in the received codeword.

[0045] When using quasi-cyclic LDPC codes, the decoder can perform node updates in parallel, where the number of updated nodes can equal the size of the circulant sub-matrices in the quasi-cyclic parity check matrix. As shown in Figure 7 To achieve lower latency for each decoding iteration, the implementation of the decoder can perform variable node update and check node update operations in a pipelined manner, as shown in

[0046] As shown in Figure 7 At time t = 1, column 1 of the circulant is processed at stage 1, which reads the check node memory connected to the rows of the respective column and computes the incoming messages for the respective variable nodes. At time t = 2, while the VNU operation for column 1 is performed (stage 2), the check node memory read operation is performed for column 2. And at time t = 3, columns 1-3 are processed simultaneously in stages 1-3, which implement the CN memory read operation, the VNU operation, and the CNU operation, respectively. The CNU in stage 3 performs the CNU operation for the rows connected to the selected column.

[0047] In some embodiments, the correction capability of an LDPC code depends on the degree distribution of the variable nodes (or equivalently, the column weight distribution of its parity check matrix). For large correction capability, it is generally required that there are some columns with large weights. Following Figure 7The decoder for the illustrated scheduling will require additional hardware to be able to perform the VNU operations and CNU operations corresponding to the columns with the largest weights. This results in an increase in the gate-count of the decoder implementation by a factor of two to three.

[0048] Embodiments of the disclosed technology implement a decoder with reasonable gate count and latency that is able to achieve large correction capability using some optimal degree distribution of highly variable nodes. In an example, the rows of the parity check matrix of an LDPC code are partitioned into two or more sets. As illustrated, for columns with large weights, the CNU operations for each set are performed in a fixed order in separate time steps in a pipelined architecture. This decoder implementation only requires hardware to perform the CNU operations for all rows in one set, not column weights. The parity check matrix is designed such that the columns immediately following any large weight column are not connected to rows belonging to the set with outstanding CNU operations. For QC-LDPC codes, the rows are partitioned such that rows belonging to the same row cycle are part of the same set. Figure 8

[0049] In some embodiments, a time step corresponds to a fixed number of clock cycles, where a clock cycle is the amount of time between two pulses of an oscillator in a processor (e.g., a central processing unit (CPU)). For example, a processor running at 2 GHz performs 2,000,000,000 clock cycles per second.

[0050] In some embodiments, a time step is equal to one clock cycle. In other embodiments, a time step is equal to N clock cycles, where N is an integer greater than one. In yet another embodiment, a time step is equal to a unit of time defined by a reference timing signal used by the processor (e.g., a pulse-per-second (PPS) signal).

[0051] An LDPC code is represented by a parity check matrix H = [h ij ] M×N where h is equal to one if and only if the i-th check node is connected to the j-th variable node. The weight of the j-th column (or equivalently, the degree of the j-th variable node) is represented by w j As previously mentioned, an LDPC decoder can be configured to operate using an iterative message passing decoding method (e.g., min-sum, sum-product, or flip bit algorithm).

[0052] ​In the min-sum algorithm, the exchanged messages are based on the log of the probabilities. For example, the message sent from a variable node (v) to a check node (w) corresponds to the reliability of the symbol x in coordinate v determined by the all-check-node equation including the nodes other than w itself. Subsequently, the message sent from a check node to a variable node is a local estimate of the reliability of the symbol x in coordinate v determined by all other coordinates entering the check node w. The min-sum algorithm terminates when it converges (further iterations do not change the local cost) or after a predetermined number of iterations.

[0053] The sum-product algorithm is similar to the min-sum algorithm as described above, except that in the sum-product algorithm the exchanged messages are based on the probabilities themselves (rather than the log of the probabilities).

[0054] In the bit-flipping algorithm, each check node introduces a constraint, and the algorithm attempts to find the bits that, when flipped, will reduce the number of unsatisfied clauses. The algorithm stops when, for each bit, the number of unsatisfied constraints is less than or equal to the number of satisfied constraints. The algorithm has to stop because the number of unsatisfied constraints is reduced in each step.

[0055] The vertical scheduling method of the LDPC decoder can be implemented by the pipelined architecture shown in FIG. 1. As described above, each decoding iteration processes all variable nodes once and processes the check nodes connected to the variable nodes immediately after the VNU operation is completed. Figure 7

[0056] As shown in FIG. 2, the processing of each column is divided into three stages. In the first stage, the memory corresponding to the check nodes connected to the variable nodes of the column is read and the incoming messages of the variable nodes are computed. Figure 7

[0057] In the second stage, the VNU operation is performed. In an example, for a min-sum decoder or a sum-product decoder, performing the VNU operation includes performing a summation of the channel messages and the incoming messages from the previous stage to compute the hard decisions and extrinsic outgoing messages. In another example, for a bit-flipping decoder, performing the VNU operation includes counting the number of unsatisfied neighboring check nodes and deciding whether the hard decision of the variable node should be flipped.

[0058] In the third stage, the CNU operation is performed on the associated check nodes based on the outgoing messages generated in the VNU stage. Due to the pipelined architecture, multiple columns can still be processed at the same time step, although each column is at a different stage. For example, at time t = 4, the first stage of column 4 is being executed to determine the incoming messages of the variable nodes corresponding to column 4. At the same time, the second stage or VNU operation is being performed on column 3 based on the CN memory read at t = 3, and the third stage including the CNU operation is being performed on the check nodes associated with column 2. ​​

[0059] Pipelined architecture implementations typically include sufficient hardware to execute all stages in a single time step. For example, to process a column with weight w, the hardware must be able to read from the CN memory at w in one time step for stage 1, be able to process the VNU operation with w incoming messages in one time step, and perform the CNU operation on w check nodes in one time step. Thus, the gate count of the decoder increases linearly with the maximum column weight max 1≤v≤N w v while the number of iterations increases linearly with the maximum column weight max

[0060] As noted above, LDPC codes with good correction performance typically have some columns with large column weights in their parity check matrix H. Embodiments of the disclosed technology assume that the first B columns of H have large column weights, without loss of generality, denoted as:

[0061]

[0062] This assumption is for illustrative purposes only, and columns with large column weights can occur at other indices.

[0063] When implementing an LDPC code using the pipelined architecture shown in Figure 7 , the gate count can increase by a factor of many to ensure that all stages can be executed in a single time step. For example, when less than 2% of the columns have large column weights (i.e., (B / N) < 0.02) and the columns with large column weights have weights that are 2 to 3 (η) times the column weights of the other columns (i.e., η = 2 to 3), then the gate count is approximately η times that of the non-pipelined architecture. However, when processing the (N-B) columns corresponding to columns with regular weights out of the total N columns, most of the additional hardware is not used.

[0064] In contrast to the implementation using the pipelined architecture shown in Figure 7 , embodiments of the disclosed technology keep the gate count substantially constant at the expense of slightly increasing the latency of the iterative decoder when increasing the column weights for a small number of columns. This is partially achieved by splitting the processing of the first B columns so that some stages take two or more time steps, and partitioning all rows of the parity check matrix of the LDPC code into two or more sets and processing the sets in a particular order.

[0065] Figure 8 An example of a pipelined architecture that splits the processing of the first B columns so that some stages take two or more time steps is shown in Figure 8 ​As shown in FIG. 1, the VNU stage is completed within a single time step, but reading and writing to the CN memory requires two (or more) time steps to ensure that the total gate count does not increase. Thus, stage 1 of column 1 is split over two time steps, e.g., t = 1 and t = 2. Similarly, stage 3 of column 1 is split over time steps t = 4 and t = 5.

[0066] Figure 8 The pipelined architecture shown in FIG. 1 also shows that the entire rows (or equivalently, the entire check nodes) of the parity check matrix H are partitioned into two or more groups, such that the check nodes in the first / second set are processed in the first / second time step of the split process. For example, as shown in FIG. 1, the check nodes belonging to set 1 (in column 1) are processed in time step t = 1, and the check nodes belonging to set 2 (in column 1) are delayed and processed in time step t = 2. Figure 8 Figure 8 Figure 8

[0067] In addition, the processing order is fixed such that the check nodes in set 1 are always processed before the check nodes in set 2. This advantageously ensures that the updated messages are available for processing of the subsequent columns of the parity check matrix. For example, in time step t = 4, set 1 of column 1 is processed in stage 3, and set 2 of column 1 is processed in stage 3 in time step t = 5. These stage 3 processing steps are performed concurrently with the set 1 and set 2 operations for column 2 in stage 1 in time steps t = 4 and t = 5, respectively.

[0068] In some embodiments, the (B + 1)th column of H is constrained such that all the rows connected to it belong to the same set. This ensures that the stage 1 processing of column (B + 1) at t = 3B + 1 reads the CN memory from check nodes that have been updated by the stage 3 processing of column B (if they belong to set 1), or check nodes that have not been updated (if they belong to set 2). Without this constraint, the information read by the stage 3 processing step of column (B + 1) can be partially updated and partially stale, which can lead to error decoding.

[0069] Embodiments of the disclosed technology can increase the scheduling delay of each decoding iteration by approximately 2B time steps, with a relative increase of 2B / N for each decoding iteration (e.g., less than 4% when B « N). This advantageously reduces the gate count compared to the scheduling algorithm shown in FIG. 1, with only a minimal increase in the delay of each decoding iteration. Figure 7 This advantageously reduces the gate count compared to the scheduling algorithm shown in FIG. 1, with only a minimal increase in the delay of each decoding iteration. The constraint imposed on the H matrix is easy to satisfy and does not limit the use of optimal degree distributions that can provide significant correction capabilities.

[0070] In some embodiments, the pipelined architecture described herein (e.g., as shown in FIG. 1) can be used to implement a decoder for a polar code.​​​Figure 7 and Figure 8 The pipeline architecture (e.g., as shown in FIG. 4) can be configured such that the VNU operation for each column requires more than one time step.

[0071] In some embodiments, the pipeline architecture (e.g., as shown in FIG. 4) described herein can be configured such that each of the CN memory read operation, the VNU operation, and the CNU operation for each column requires more than one time step. Figure 7 and Figure 8 The pipeline architecture (e.g., as shown in FIG. 4) can be configured such that each of the CN memory read operation, the VNU operation, and the CNU operation for each column requires more than one time step. This can advantageously reduce the gate count for parity check matrices having columns with much higher weight ratios than typical implementations.

[0072] In some embodiments, a pipeline architecture (e.g., as shown in FIG. 4) can be implemented to decode QC-LDPC in which one or more cyclic columns or a portion of variable nodes belonging to a cyclic column are processed in parallel. Figure 7 and 8 The pipeline architecture (e.g., as shown in FIG. 4) can be configured such that each of the CN memory read operation, the VNU operation, and the CNU operation for each column requires more than one time step. This can advantageously reduce the gate count for parity check matrices having columns with much higher weight ratios than typical implementations.

[0073] Figure 9 A flowchart illustrating a method 900 for improving decoding operations of a decoder in a non-volatile memory is shown. The method 900 includes receiving, at operation 910, a noisy codeword based on a transmitted codeword generated from a low-density parity-check code, the LDPC code having an associated parity check matrix including N columns, where N is a positive integer, where each column of at least B columns of the parity check matrix has a column weight that exceeds a predetermined column weight, where B is a positive integer, and where B < N.

[0074] The method 900 includes processing, at operation 920, the N columns based on a message passing algorithm between a plurality of variable nodes and a plurality of check nodes, the plurality of check nodes representing the LDPC code of the parity check matrix.

[0075] The operation 920 includes partitioning, at operation 922, the check nodes in each column into at least a first set and a second set.

[0076] The operation 920 includes performing, at operation 924, a read operation, a variable node update (VNU) operation, and a check node update (CNU) operation for the first set and the second set, where the first set is performed the read operation, the VNU operation, and the CNU operation before the second set, and where performing the read operation and the CNU operation for each of the at least B columns spans two or more time steps (e.g., as shown in FIG. 4). Figure 8

[0077] The method 900 includes determining, at operation 930, a candidate version of the transmitted codeword based on the processing.

[0078] In some embodiments, the CNU operation for the first set and the second set is performed after the VNU operation.​

[0079] In some embodiments, the decoder comprises a min-sum decoder or a sum-product decoder, and wherein performing the VNU operation comprises computing a sum of the channel messages and the incoming messages.

[0080] In some embodiments, the decoder comprises a bit-flipping decoder, and wherein performing the VNU operation comprises counting a number of unsatisfied neighboring check nodes.

[0081] In some embodiments, performing the VNU operation for each of at least B columns spans two or more time steps.

[0082] In some embodiments, column indices of at least B columns of the parity check matrix are 1, 2,..., B, processing the N columns comprises partitioning check nodes in the (B+1)th column into at least a first set and a second set, wherein all rows of the parity check matrix connected to the (B+1)th column with the partitioned check nodes are in only the first set or in only the second set.

[0083] In some embodiments, the decoder comprises an iterative decoder, and the method 900 further comprises performing a subsequent iteration upon determining that the check sum of the candidate transport codeword is not equal to 0.

[0084] In some embodiments, the decoder comprises an iterative decoder, and the method 900 further comprises refraining from performing a subsequent iteration upon determining that the check sum of the candidate transport codeword is equal to 0 or upon having performed a maximum number of iterations.

[0085] In some embodiments, the LDPC code comprises a QC-LDPC code.

[0086] Implementations of the subject matter and the functional operations described in this patent document can be implemented in various systems, digital electronic circuitry, or in computer software, firmware, or hardware, including the structures disclosed in this specification and their structural equivalents, or in combinations of one or more of them. Implementations of the subject matter described in this specification can be implemented as one or more computer program products, i.e., one or more modules of computer program instructions encoded on a tangible and non-transitory computer readable medium for execution by, or to control the operation of, data processing apparatus. The computer readable medium can be a machine-readable storage device, a machine-readable storage substrate, a memory device, a composition of matter effecting a machine-readable propagated signal, or a combination of one or more of them. The term“data processing apparatus” encompasses all apparatus, devices, and machines for processing data, including by way of example a programmable processor, a computer, or multiple processors or computers. The apparatus can include, in addition to hardware, code that creates an execution environment for the computer program in question, e.g., code that constitutes processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of them.

[0087] A computer program (also known as a program, software, software application, script, or code) can be written in any form of programming language, including compiled or interpreted languages, and it can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. A computer program does not necessarily correspond to a file in a file system. A program can be stored in a portion of a file that holds other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files that store one or more modules, sub programs, or portions of code). A computer program can be deployed to be run on one computer or on multiple computers that are located at one site or distributed across multiple sites and are interconnected by a communication network.

[0088] The processes and logic flows described in this specification can be performed by one or more programmable processors executing one or more computer programs to perform functions by operating on input data and generating output. The processes and logic flows can also be performed by, and apparatus can also be implemented as, special purpose logic circuitry, e.g., an FPGA (field programmable gate array) or an ASIC (application specific integrated circuit).

[0089] Processors suitable for the execution of a computer program include, by way of example, both general and special purpose microprocessors, and any one or more processors of any kind of digital computer. Generally, a processor will receive instructions and data from a read-only memory or a random access memory or both. The essential elements of a computer are a processor for executing instructions and one or more memory devices for storing instructions and data. Generally, a computer will also include, or be operatively coupled to receive data from or transfer data to, or both, one or more mass storage devices for storing data, e.g., magnetic, magneto-optical disks, or optical disks. However, a computer need not have such devices. Computer readable media suitable for storing computer program instructions and data include all forms of non-volatile memory, media and memory devices, including by way of example semiconductor memory devices, e.g., EPROM, EEPROM, and flash memory devices. The processor and the memory can be supplemented by, or incorporated in, special purpose logic circuitry.

[0090] Although the present patent document contains many details, these should not be construed as limiting the scope of any invention or of any of the embodiments described herein but as merely describing features that can be) incorporated into a specific embodiment of the application. Each of the features described herein in the context of separate embodiments can also be implemented in a combination of embodiments. Conversely, various features described in the context of a single embodiment can also be implemented separately or in any suitable subcombination. Moreover, although features can be described above as acting in particular combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination and the claimed combination can be directed to a subcombination or variation of a subcombination.

[0091] Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring such an order, or that all illustrated operations be performed, to achieve desirable results. Additionally, the separation of various system components in the embodiments described herein should not be understood as requiring such separation in all embodiments.

[0092] Only a few implementations and examples are described and other implementations, enhancements and variations can be made based on what is described and illustrated in this patent document.

Claims

1. A method for improving a decoding operation of a decoder in a non-volatile memory, comprising: receiving a noisy codeword, the noisy codeword being based on a transmitted codeword generated from a low-density parity-check (LDPC) code, the LDPC code having an associated parity-check matrix comprising N columns, where N is a positive integer, wherein each column of at least B columns of the parity-check matrix has a column weight that exceeds a predetermined column weight, where B is a positive integer, and wherein B < N; processing the N columns based on a message passing algorithm between a plurality of variable nodes and a plurality of check nodes, the plurality of check nodes representing the parity-check matrix of the LDPC code; and determining a candidate for the transmitted codeword based on the processing, wherein the processing the N columns comprises: partitioning check nodes in each column into at least a first set and a second set, and performing a read operation, a variable node update (VNU) operation, and a check node update (CNU) operation for the first set and the second set, wherein the first set is performed the read operation, the VNU operation, and the CNU operation before the second set, and wherein the read operation and the CNU operation are performed for each of the at least B columns span two or more time steps.

2. The method of claim 1, wherein, the CNU operation for the first set and the second set is performed after the VNU operation.

3. The method of claim 1, wherein, the decoder comprises a min-sum decoder or a sum-product decoder, and wherein performing the VNU operation comprises calculating a sum of a channel message and an incoming message.

4. The method of claim 1, wherein, the decoder comprises a bit-flipping decoder, and wherein performing the VNU operation comprises counting a number of unsatisfied neighboring check nodes.

5. The method of claim 1, wherein, the VNU operation is performed for each of the at least B columns span two or more time steps.

6. The method of claim 1, wherein, the decoder comprises an iterative decoder, and wherein the method further comprises: performing a subsequent iteration when a check sum of a candidate transmitted codeword is determined to not equal zero, or suppressing a subsequent iteration when a check sum of the candidate transmitted codeword is determined to equal zero or a maximum number of iterations has been performed.

7. The method of claim 1, wherein, column indices of the at least B columns of the parity-check matrix are 1, 2, …, B, wherein processing the N columns comprises: partitioning check nodes in a B+1th column into at least a first set and a second set, wherein all rows of the parity-check matrix connected to the B+1th column having partitioned check nodes are only in the first set or the second set.

8. The method of claim 1, wherein, the LDPC code comprises a quasi-cyclic low-density parity-check (QC-LDPC) code.

9. An apparatus for improving a decoding operation of a decoder in a non-volatile memory, comprising: a processor; and a memory, the memory comprising instructions stored thereon, wherein the instructions, when executed by the processor, cause the processor to: ​ receiving a noisy codeword, the noisy codeword being based on a transmitted codeword generated from a low-density parity-check (LDPC) code having an associated parity-check matrix comprising N columns, where N is a positive integer, where each column of at least B columns of the parity-check matrix has a column weight that exceeds a predetermined column weight, where B is a positive integer, and where B < N; processing the N columns based on a message passing algorithm between a plurality of variable nodes and a plurality of check nodes, the plurality of check nodes representing the parity-check matrix of the LDPC code; and determining a candidate for the transmitted codeword based on the processing, wherein, as part of processing each column of the N columns, the processor: partitions check nodes in each column into at least a first set and a second set, and performs a read operation, a variable node update (VNU) operation, and a check node update (CNU) operation for the first set and the second set, where the first set is performed the read operation, the VNU operation, and the CNU operation before the second set, and where performing the read operation and the CNU operation for each of the at least B columns spans two or more time steps.

10. The apparatus of claim 9, wherein, the CNU operation for the first set and the second set is performed after the VNU operation.

11. The apparatus of claim 9, wherein, the decoder comprises a min-sum decoder or a sum-product decoder, and where performing the VNU operation comprises calculating a sum of a channel message and an incoming message.

12. The apparatus of claim 9, wherein, the decoder comprises a bit-flipping decoder, and where performing the VNU operation comprises counting a number of unsatisfied neighboring check nodes.

13. The apparatus of claim 9, wherein, performing the VNU operation for each of the at least B columns spans two or more time steps.

14. The apparatus of claim 9, wherein, the decoder comprises an iterative decoder, and where the processor further: performs a subsequent iteration upon determining that a check sum of a candidate transmitted codeword is not equal to zero.

15. The apparatus of claim 9, wherein, the decoder comprises an iterative decoder, and where the processor further: suppresses performing a subsequent iteration upon determining that a check sum of a candidate transmitted codeword is equal to zero or a maximum number of iterations has been performed.

16. A non-transitory computer-readable storage medium having stored thereon instructions for improving a decoding operation of a decoder in a non-volatile memory, comprising: instructions for receiving a noisy codeword, the noisy codeword being based on a transmitted codeword generated from a low-density parity-check (LDPC) code having an associated parity-check matrix comprising N columns, where N is a positive integer, where each column of at least B columns of the parity-check matrix has a column weight that exceeds a predetermined column weight, where B is a positive integer, and where B < N; instructions for processing the N columns based on a message passing algorithm between a plurality of variable nodes and a plurality of check nodes, the plurality of check nodes representing the parity-check matrix of the LDPC code; and instructions for determining a candidate for the transmitted codeword based on the processing, wherein the instructions for processing each column of the N columns comprise: instructions for partitioning the check nodes in each column into at least a first set and a second set, and instructions for performing read operations, variable node update operations (VNUs), and check node update operations (CNUs) on the first set and the second set, wherein the first set is performed on the read operations, the VNUs, and the CNUs before the second set, and wherein performing the read operations and the CNUs on each of the at least B columns spans two or more time steps.

17. The computer-readable storage medium of claim 16, wherein, performing the CNU operations for the first set and the second set after the VNU operations.

18. The computer-readable storage medium of claim 16, wherein, the decoder comprises a min-sum decoder or a sum-product decoder, and wherein performing the VNU operations comprises calculating a sum of channel messages and incoming messages.

19. The computer-readable storage medium of claim 16, wherein, the decoder comprises a bit-flipping decoder, and wherein performing the VNU operations comprises counting a number of unsatisfied neighboring check nodes.

20. The computer-readable storage medium of claim 16, wherein, the LDPC code comprises a quasi-cyclic low-density parity-check code (QC-LDPC code).

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