Semiconductor device

Abstract

A semiconductor device can be provided that includes a transistor on a substrate; a first interlayer insulating layer on the transistor; a first lower interconnection line and a second lower interconnection line in an upper portion of the first interlayer insulating layer; a dielectric layer selectively on a top surface of the first interlayer insulating layer except for top surfaces of the first lower interconnection line and the second lower interconnection line; an etching stop layer on the first lower interconnection line and the second lower interconnection line and the dielectric layer; a second interlayer insulating layer on the etching stop layer; and an upper interconnection line in the second interlayer insulating layer.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices and / or methods of manufacturing them, and more particularly, to semiconductor devices including field-effect transistors and / or methods of manufacturing them. Background Technology

[0002] Semiconductor devices include integrated circuits composed of metal-oxide-semiconductor field-effect transistors (MOS-FETs). To meet the growing demand for semiconductor devices with smaller pattern sizes and reduced design rules, MOS-FETs are being actively scaled down. However, scaling down MOS-FETs can lead to a deterioration in the operational performance of semiconductor devices. Various studies are underway to overcome the technological limitations associated with the scaling down of semiconductor devices and to achieve high-performance semiconductor devices. Summary of the Invention

[0003] Some exemplary embodiments of the present invention provide semiconductor devices with improved reliability and electrical characteristics and / or methods of manufacturing them.

[0004] According to an exemplary embodiment of the present invention, a semiconductor device may include: a transistor on a substrate; a first interlayer insulating layer on the transistor; a first lower interconnect and a second lower interconnect in the upper portion of the first interlayer insulating layer; a dielectric layer, selectively located on the top surface of the first interlayer insulating layer other than the top surfaces of the first and second lower interconnects; an etch stop layer on the first and second lower interconnects and the dielectric layer; an interlayer insulating layer on the second etch stop layer; and an upper interconnect in the second interlayer insulating layer. The upper interconnect may include a line portion and a strip-shaped passage extending from the line portion to the first and second lower interconnects to penetrate the etch stop layer. The strip-shaped passage may include a first contact portion and a second contact portion respectively connected to the first and second lower interconnects, and a first connection portion between the first contact portion and the second contact portion. Due to the dielectric layer, the bottom surface of the first connection portion may be higher than the top surface of the first interlayer insulating layer and may be lower than the top surface of the etch stop layer.

[0005] According to an exemplary embodiment of the present invention, a semiconductor device may include: a transistor on a substrate; a first interlayer insulating layer on the transistor; a first lower interconnect and a second lower interconnect in the upper portion of the first interlayer insulating layer; a dielectric layer, selectively on the top surface of the first interlayer insulating layer other than the top surfaces of the first and second lower interconnects; an etch stop layer on the first and second lower interconnects and the dielectric layer; a second interlayer insulating layer on the etch stop layer; and a first upper interconnect in the second interlayer insulating layer. The first upper interconnect may include a first line portion and a strip-shaped passage extending from the first line portion to the first and second lower interconnects to penetrate the etch stop layer. The strip-shaped passage may include a first contact portion and a second contact portion respectively connected to the first and second lower interconnects, and a first connection portion between the first and second contact portions. The top surface of the dielectric layer between the first and second contact portions may be covered by the first connection portion. The thickness of the dielectric layer between the first and second contact portions may increase along the direction from the first contact portion to the second contact portion until the thickness reaches a maximum value and then may decrease.

[0006] According to an exemplary embodiment of the present invention, a semiconductor device may include: a substrate including an active region; a device isolation layer defining active patterns on the active region, the device isolation layer covering a lower surface of each active pattern, the upper portion of each active pattern protruding over the device isolation layer; a pair of source / drain patterns at the upper portion of each active pattern; a channel pattern between the pair of source / drain patterns; a gate electrode extending in a first direction to intersect the channel pattern; a gate spacer on the opposite side surface of the gate electrode and extending along the gate electrode in the first direction; and a gate insulating layer on the gate electrode. Between the channel pattern and between the gate electrode and the gate spacer; a gate cap pattern, on the top surface of the gate electrode and extending along the gate electrode in a first direction; a first interlayer insulating layer on the gate cap pattern; an active contact penetrating the first interlayer insulating layer and electrically connected to at least one of the source / drain patterns; a first metal layer in a second interlayer insulating layer, the second interlayer insulating layer being on the first interlayer insulating layer; a second metal layer in a third interlayer insulating layer, the third interlayer insulating layer being on the second interlayer insulating layer; and a dielectric layer and an etch stop layer between the second and third interlayer insulating layers. The etch stop layer may cover the dielectric layer. The first metal layer may include a first lower interconnect and a second lower interconnect. The second metal layer may include a first upper interconnect electrically connected to the first lower interconnect and the second lower interconnect. The first upper interconnect may include a first line portion and a strip passage extending from the first line portion to the first lower interconnect and the second lower interconnect to penetrate the etch stop layer. The strip passage may include a first contact portion and a second contact portion connected to the first lower interconnect and the second lower interconnect, respectively, and a first connection portion between the first contact portion and the second contact portion. Due to the dielectric layer, the bottom surface of the first connection portion can be higher than the top surface of the second interlayer insulating layer and lower than the top surface of the etch stop layer.

[0007] According to an exemplary embodiment of the present invention, a method of manufacturing a semiconductor device may include: forming a transistor on a substrate; forming a first interlayer insulating layer on the transistor; forming a first lower interconnect and a second lower interconnect in an upper portion of the first interlayer insulating layer; selectively forming a dielectric layer on the top surface of the first interlayer insulating layer, excluding the top surfaces of the first and second lower interconnects; forming an etch stop layer on the first and second lower interconnects and the dielectric layer; forming a second interlayer insulating layer on the etch stop layer; patterning the second interlayer insulating layer to form an upper interconnect via; and forming an upper interconnect to fill the upper interconnect via. The upper interconnect via may include a first contact via and a second contact via, which are formed to penetrate the etch stop layer and expose the top surfaces of the first and second lower interconnects, respectively, and the dielectric layer between the first contact via and the second contact via may be exposed through the upper interconnect via. Attached Figure Description

[0008] Figure 1 This is a plan view illustrating a semiconductor device according to an example embodiment of the concept of the present invention.

[0009] Figures 2A to 2D They are along Figure 1 A sectional view taken from lines A-A', B-B', C-C', and D-D'.

[0010] Figure 3 yes Figure 2D An enlarged sectional view of part M.

[0011] Figure 4 It is along Figure 1 A cross-sectional view taken along line D-D' to illustrate the semiconductor device according to the comparative example.

[0012] Figure 5 , Figure 7 , Figure 9 and Figure 11 This is a plan view illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment of the concept of the present invention.

[0013] Figure 6 , Figure 8A , Figure 10A and Figure 12A They are along Figure 5 , Figure 7 , Figure 9 and Figure 11 A sectional view taken by line A-A'.

[0014] Figure 8B , Figure 10B and Figure 12B They are along Figure 7 , Figure 9 and Figure 11 The sectional view taken by line B-B'.

[0015] Figure 10C and Figure 12C They are along Figure 9 and Figure 11 A sectional view taken by line C-C'.

[0016] Figure 10D and 12D They are along Figure 9 and Figure 11 A sectional view taken by line D-D'.

[0017] Figures 13 to 17 It is an enlarged sectional view, which shows Figure 2D Part M is used to illustrate a method for forming an interconnect according to an exemplary embodiment of the concept of the present invention.

[0018] Figures 18 to 20These are sectional views, each sectional view along... Figure 1 The line D-D' is cut off to illustrate a semiconductor device according to another example embodiment of the concept of the present invention.

[0019] Figure 21 It is a sectional view, along Figure 1 The line A-A' is cut off to illustrate a semiconductor device according to another example embodiment of the concept of the present invention.

[0020] Figures 22A to 22D It is a sectional view, which is shown along... Figure 1 Lines A-A', B-B', C-C', and D-D' are cut to illustrate a semiconductor device according to an example embodiment of the concept of the present invention. Detailed Implementation

[0021] Although the terms “same,” “equal,” or “equivalent” are used in the description of the example implementations, it should be understood that some imprecision may exist. Therefore, when an element is said to be the same as another element, it should be understood that one element or value is the same as another element within the expected range of manufacturing or operational tolerances (e.g., ±10%).

[0022] When the terms “about” or “substantially” are used in conjunction with numerical values ​​in this specification, it is intended that the relevant numerical value includes manufacturing or operational tolerances (e.g., ±10%) around the value. Furthermore, when the terms “about” and “substantially” are used in conjunction with geometry, it is intended not to require precision of the geometry, but rather a range of shapes within the scope of this disclosure. Moreover, regardless of whether a numerical value or shape is modified with “about” or “substantially”, it will be understood that these values ​​and shapes should be interpreted as including manufacturing or operational tolerances (e.g., ±10%) around the value or shape.

[0023] Figure 1 This is a plan view illustrating a semiconductor device according to an example embodiment of the concept of the present invention.

[0024] Figures 2A to 2D They are along Figure 1 A sectional view taken from lines A-A', B-B', C-C', and D-D'.

[0025] Figure 3 yes Figure 2D An enlarged sectional view of part M.

[0026] Reference Figure 1 and Figures 2A to 2D The logic unit LC can be provided on the substrate 100. In this specification, the logic unit LC can refer to a logic device (e.g., an inverter, a flip-flop, etc.) configured to perform a specific function. For example, the logic unit LC may include transistors constituting the logic device and interconnections connecting the transistors to each other.

[0027] The substrate 100 may include a first active region PR and a second active region NR. In one example embodiment, the first active region PR may be a PMOSFET region, and the second active region NR may be an NMOSFET region. The substrate 100 may be a semiconductor substrate formed of or including silicon, germanium, silicon-germanium, compound semiconductor materials, etc. In one example embodiment, the substrate 100 may be a silicon wafer.

[0028] The first active region PR and the second active region NR can be defined by a second trench TR2 formed in the upper part of the substrate 100. The second trench TR2 can be positioned between the first active region PR and the second active region NR. The first active region PR and the second active region NR can be spaced apart from each other in a first direction D1, and the second trench TR2 is interposed therebetween. Each of the first active region PR and the second active region NR can extend in a second direction D2, which is different from the first direction D1.

[0029] A first active pattern AP1 and a second active pattern AP2 may be provided on a first active region PR and a second active region NR, respectively. The first active pattern AP1 and the second active pattern AP2 may extend in a second direction D2 and may be parallel to each other. The first active pattern AP1 and the second active pattern AP2 may be portions of the substrate 100 protruding in a vertical direction (e.g., a third direction D3). A first trench TR1 may be defined between adjacent first active patterns AP1 and adjacent second active patterns AP2. The first trench TR1 may be shallower than the second trench TR2.

[0030] The device isolation layer ST may fill the first trench TR1 and the second trench TR2. The device isolation layer ST may be formed of or comprise silicon oxide. The upper portion of the first active pattern AP1 and the second active pattern AP2 may be a protruding pattern extending vertically over the device isolation layer ST (e.g., see...). Figure 2D Each of the upper portions of the first active pattern AP1 and the second active pattern AP2 can be shaped like a fin. The device isolation layer ST may not cover the upper portions of the first active pattern AP1 and the second active pattern AP2. The device isolation layer ST may cover the lower portions of the side surfaces of the first active pattern AP1 and the second active pattern AP2.

[0031] A first source / drain pattern SD1 can be provided in the upper part of a first active pattern AP1. The first source / drain pattern SD1 can be an impurity region of a first conductivity type (e.g., p-type). A first channel pattern CH1 can be inserted between a pair of first source / drain patterns SD1. A second source / drain pattern SD2 can be provided in the upper part of a second active pattern AP2. The second source / drain pattern SD2 can be an impurity region of a second conductivity type (e.g., n-type). A second channel pattern CH2 can be inserted between a pair of second source / drain patterns SD2.

[0032] The first source / drain pattern SD1 and the second source / drain pattern SD2 can be epitaxial patterns formed by a selective epitaxial growth process. As an example, the first source / drain pattern SD1 and the second source / drain pattern SD2 can have top surfaces that are coplanar with the top surfaces of the first channel pattern CH1 and the second channel pattern CH2. As another example, the top surfaces of the first source / drain pattern SD1 and the second source / drain pattern SD2 can be higher than the top surfaces of the first channel pattern CH1 and the second channel pattern CH2.

[0033] The first source / drain pattern SD1 may include a semiconductor element (e.g., SiGe) with a lattice constant greater than that of the semiconductor element in the substrate 100. Therefore, the first source / drain pattern SD1 can apply compressive stress to the first channel pattern CH1. As an example, the second source / drain pattern SD2 may include a semiconductor element (e.g., Si) serving as the substrate 100.

[0034] The gate electrode GE can be provided to intersect with the first active pattern AP1 and the second active pattern AP2 and extend in a first direction D1. The gate electrodes GE can be arranged to be spaced apart from each other in a second direction D2 by a first pitch P1. When viewed in a plan view, the gate electrodes GE can overlap with the first channel pattern CH1 and the second channel pattern CH2. Each gate electrode GE can surround the top surface and the opposite side surface of each of the first channel pattern CH1 and the second channel pattern CH2.

[0035] Return to reference Figure 2D The gate electrode GE can be provided on a first top surface TS1 of the first channel pattern CH1 and on at least one first side surface SW1 of the first channel pattern CH1. The gate electrode GE can be provided on a second top surface TS2 of the second channel pattern CH2 and on at least one second side surface SW2 of the second channel pattern CH2. For example, the transistor according to this exemplary embodiment can be a three-dimensional field-effect transistor (e.g., FinFET), wherein the gate electrode GE is configured to surround the channel patterns CH1 and CH2 in three dimensions.

[0036] Return to reference Figure 1 and Figures 2A to 2D A pair of gate spacers GS can be disposed on opposite side surfaces of each gate electrode GE. The gate spacers GS can extend along the gate electrode GE in a first direction D1. The top surface of the gate spacers GS can be higher than the top surface of the gate electrode GE. The top surface of the gate spacers GS can be coplanar with the top surface of the first interlayer insulating layer 110, which will be described below. The gate spacers GS can be formed of or include at least one of SiCN, SiCON, or SiN. In an example embodiment, the gate spacers GS can be a multilayer structure comprising at least two different materials selected from SiCN, SiCON, and SiN.

[0037] A gate cap pattern GP can be provided on each gate electrode GE. The gate cap pattern GP can extend along the gate electrode GE and in a first direction D1. The gate cap pattern GP can be formed of or include at least one of a material having etch selectivity with respect to the first interlayer insulating layer 110 and the second interlayer insulating layer 120, which will be described below. For example, the gate cap pattern GP can be formed of or include at least one of SiON, SiCN, SiCON, or SiN.

[0038] A gate insulating layer GI can be interposed between the gate electrode GE and the first active pattern AP1, and between the gate electrode GE and the second active pattern AP2. The gate insulating layer GI can extend along the bottom surface of the gate electrode GE thereon. As an example, the gate insulating layer GI can cover the first top surface TS1 and the first side surface SW1 of the first channel pattern CH1. The gate insulating layer GI can cover the second top surface TS2 and the second side surface SW2 of the second channel pattern CH2. The gate insulating layer GI can cover the top surface of the device isolation layer ST below the gate electrode GE (e.g., see...). Figure 2D ).

[0039] In one example embodiment, the gate insulating layer GI may be formed of or comprise a high-k dielectric material having a dielectric constant higher than that of the silicon oxide layer. For example, the high-k dielectric material may include at least one of hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate.

[0040] In another example implementation, the semiconductor device may include a negative capacitance (NC) FET that uses a negative capacitor. For example, the gate insulating layer GI may include a ferroelectric layer exhibiting ferroelectric properties and a paraelectric layer exhibiting paraelectric properties.

[0041] The ferroelectric layer can have negative capacitance, and the paraelectric layer can have positive capacitance. When two or more capacitors are connected in series and each capacitor has positive capacitance, the total capacitance can be reduced to less than the value of each individual capacitor. Conversely, when at least one of the capacitors connected in series has negative capacitance, the total capacitance of the series-connected capacitors can have a positive value and can be greater than the absolute value of each individual capacitor.

[0042] When a ferroelectric layer with negative capacitance and a paraelectric layer with positive capacitance are connected in series, the total capacitance of the series-connected ferroelectric and paraelectric layers can be increased. Due to this increase in total capacitance, a transistor including both ferroelectric and paraelectric layers can have a subthreshold swing (SS) of less than 60 mV / decade at room temperature.

[0043] The ferroelectric layer can possess ferroelectric properties. The ferroelectric layer can be formed or include at least one of, for example, hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and / or lead zirconium titanium oxide. Here, the hafnium zirconium oxide can be a zirconium-doped hafnium oxide. In some example embodiments, the hafnium zirconium oxide can be a compound composed of hafnium (Hf), zirconium (Zr), and / or oxygen (O).

[0044] The ferroelectric layer may further include dopants. For example, dopants may include at least one of aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), and / or tin (Sn). The type of dopant in the ferroelectric layer may vary depending on the ferroelectric material contained in the ferroelectric layer.

[0045] When the ferroelectric layer includes hafnium oxide, the dopant in the ferroelectric layer may include at least one of gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al), and / or yttrium (Y).

[0046] When the dopant is aluminum (Al), the aluminum content in the ferroelectric layer can range from 3 at% to 8 at% (atomic percentage). Here, the aluminum content as a dopant can be the ratio of the number of aluminum atoms to the number of hafnium atoms and aluminum atoms.

[0047] When the dopant is silicon (Si), the silicon content in the ferroelectric layer can range from 2 at% to 10 at%. When the dopant is yttrium (Y), the yttrium content in the ferroelectric layer can range from 2 at% to 10 at%. When the dopant is gadolinium (Gd), the gadolinium content in the ferroelectric layer can range from 1 at% to 7 at%. When the dopant is zirconium (Zr), the zirconium content in the ferroelectric layer can range from 50 at% to 80 at%.

[0048] The paraelectric layer may have paraelectric properties. The paraelectric layer may be formed of, for example, at least one of silicon oxide and / or high-k metal oxides, or include at least one of silicon oxide and / or high-k metal oxides. The metal oxide that can be used as the paraelectric layer may include, for example, at least one of hafnium oxide, zirconium oxide, and / or aluminum oxide, but the inventive concept is not limited to these examples.

[0049] The ferroelectric layer and the paraelectric layer can be formed from or comprise the same material. The ferroelectric layer may have ferroelectric properties, but the paraelectric layer may not. For example, in the case where both the ferroelectric and paraelectric layers contain hafnium oxide, the crystal structure of the hafnium oxide in the ferroelectric layer may differ from the crystal structure of the hafnium oxide in the paraelectric layer.

[0050] Ferroelectric properties can only be exhibited when the thickness of the ferroelectric layer is within a specific range. In one example embodiment, the ferroelectric layer may have a thickness in the range of 0.5 to 10 nm, but the inventive concept is not limited to this example. Since the critical thickness associated with the occurrence of ferroelectric properties varies depending on the type of ferroelectric material, the thickness of the ferroelectric layer may also vary depending on the type of ferroelectric material.

[0051] As an example, the gate insulating layer GI may include a single ferroelectric layer. As another example, the gate insulating layer GI may include multiple ferroelectric layers spaced apart from each other. The gate insulating layer GI may have a multilayer structure in which multiple ferroelectric layers and multiple paraelectric layers are stacked alternately.

[0052] The gate electrode GE may include a first metal and a second metal on the first metal. The first metal may be provided on the gate insulating layer GI and may be adjacent to the first channel pattern CH1 and the second channel pattern CH2. The first metal may include a work function metal that adjusts the threshold voltage of the transistor. By adjusting the thickness and composition of the first metal, a transistor with a desired threshold voltage can be realized.

[0053] The first metal may include a metal nitride layer. For example, the first metal may include at least one metal selected from the group consisting of titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), and molybdenum (Mo), as well as nitrogen (N). In one example embodiment, the first metal may also include carbon (C). The first metal may include multiple stacked work function metal layers.

[0054] The second metal may include a metal having a lower electrical resistance than the first metal. For example, the second metal may include at least one metal selected from the group consisting of tungsten (W), aluminum (Al), titanium (Ti), and tantalum (Ta).

[0055] A first interlayer insulating layer 110 may be provided on the substrate 100. The first interlayer insulating layer 110 may cover the gate spacer GS and the first source / drain pattern SD1 and the second source / drain pattern SD2. The top surface of the first interlayer insulating layer 110 may be substantially coplanar with the top surface of the gate cap pattern GP and the top surface of the gate spacer GS. A second interlayer insulating layer 120 may be provided on the first interlayer insulating layer 110 to cover the gate cap pattern GP. A third interlayer insulating layer 130 may be provided on the second interlayer insulating layer 120. A fourth interlayer insulating layer 140 may be provided on the third interlayer insulating layer 130. In one example embodiment, the first to fourth interlayer insulating layers 110 to 140 may be formed of or comprise silicon oxide.

[0056] A pair of isolation structures DB can be provided on both sides of the logic cell LC, the two sides being opposite to each other in a second direction D2. The isolation structures DB can extend in a first direction D1 and be parallel to the gate electrode GE. In an example embodiment, the pitch between adjacent isolation structures DB and gate electrode GE can be equal to a first pitch P1.

[0057] The isolation structure DB can be provided to penetrate the first interlayer insulation layer 110 and the second interlayer insulation layer 120 and can extend into the first active pattern AP1 and the second active pattern AP2. The isolation structure DB can penetrate the upper portion of each of the first active pattern AP1 and the second active pattern AP2. The isolation structure DB can actively separate the first active region PR and the second active region NR of the logic cell LC from the adjacent logic cells.

[0058] An active contact AC can be provided to penetrate the first interlayer insulation layer 110 and the second interlayer insulation layer 120 and can be electrically connected to the first source / drain pattern SD1 and the second source / drain pattern SD2, respectively. Each active contact AC can be provided between a pair of gate electrodes GE.

[0059] The active contact AC can be a self-aligned contact. For example, the active contact AC can be formed using a gate cap pattern GP and a gate spacer GS via a self-aligned process. For example, the active contact AC can cover at least a portion of the side surface of the gate spacer GS. Although not shown, in some example embodiments, the active contact AC can cover a portion of the top surface of the gate cap pattern GP.

[0060] A silicide pattern SC can be inserted between the active contact AC and the first source / drain pattern SD1, and between the active contact AC and the second source / drain pattern SD2. The active contact AC can be electrically connected to the source / drain pattern SD1 or SD2 via the silicide pattern SC. The silicide pattern SC can be formed of or include at least one of a metal silicide material (e.g., titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, and cobalt silicide).

[0061] A gate contact GC may be provided to penetrate the second interlayer insulating layer 120 and the gate cap pattern GP and connect to the gate electrode GE. When viewed in plan view, the gate contact GC may be provided between the first active region PR and the second active region NR. The bottom surface of the gate contact GC may contact the top surface of the gate electrode GE. The gate contact GC may have a top surface coplanar with the top surface of the second interlayer insulating layer 120.

[0062] Each of the active contact AC and the gate contact GC may include a conductive pattern FM and a barrier pattern BM surrounding the conductive pattern FM. For example, the conductive pattern FM may be formed of or include at least one metal selected from aluminum, copper, tungsten, molybdenum, or cobalt. The barrier pattern BM may cover the side and bottom surfaces of the conductive pattern FM. The barrier pattern BM may include at least one of a metal layer or a metal nitride layer. The metal layer may be formed of or include at least one of titanium, tantalum, tungsten, nickel, cobalt, or platinum. The metal nitride layer may be formed of or include at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), or platinum nitride (PtN).

[0063] A first metal layer M1 may be provided within the third interlayer insulating layer 130. The first metal layer M1 may include a first power line PIL1 and a second power line PIL2, first to fifth lower interconnects LIL1 to LIL5, and a lower pass VI. The lower pass VI may be provided below the first power line PIL1, the second power line PIL2, and the first to fifth lower interconnects LIL1 to LIL5.

[0064] The first power line PIL1 and the second power line PIL2 can be provided to intersect with the logic cell LC and can extend parallel to each other in the second direction D2. The first power line PIL1 and the second power line PIL2 can be respectively applied with a drain voltage VDD and a source voltage VSS.

[0065] Reference Figure 1 A first cell boundary CB1 extending in the second direction D2 can be defined within the region of the logic cell LC. A second cell boundary CB2 extending in the second direction D2 can be defined within the region of the logic cell LC opposite to the first cell boundary CB1. A first power supply line PIL1 with a drain voltage VDD applied can be provided on the first cell boundary CB1. That is, the first power supply line PIL1 with a drain voltage VDD applied can extend along the first cell boundary CB1 and in the second direction D2. A second power supply line PIL2 with an active voltage VSS applied (e.g., ground voltage) can be provided on the second cell boundary CB2. In other words, the second power supply line PIL2 with an active voltage VSS applied can extend along the second cell boundary CB2 and in the second direction D2.

[0066] The first to fifth lower interconnects LIL1 to LIL5 can be positioned between the first power line PIL1 and the second power line PIL2. The first to fifth lower interconnects LIL1 to LIL5 can extend parallel to each other in the second direction D2. When viewed in a plan view, each of the first to fifth lower interconnects LIL1 to LIL5 can be linear or strip-shaped. The first to fifth lower interconnects LIL1 to LIL5 can be arranged to be spaced apart from each other by a second pitch P2 in the first direction D1. The second pitch P2 can be smaller than the first pitch P1.

[0067] The line width of each of the first power line PIL1 and the second power line PIL2 may be a first width W1. The line width of each of the first to fifth lower interconnects LIL1 to LIL5 may be a second width W2.

[0068] The second width W2 can be smaller than the first width W1. For example, the second width W2 can be less than 12nm.

[0069] The first width W1 can be greater than 12nm.

[0070] The lower path VI can be inserted between the first power line PIL1 and the second power line PIL2 and the active contact AC. The lower path VI can be inserted between the first to fifth lower interconnects LIL1 to LIL5 and the active contact AC and the gate contact GC.

[0071] Each of the first power line PIL1, the second power line PIL2, and the first to fifth lower interconnects LIL1 to LIL5 may include a first blocking metal pattern BAP1 and a first metal pattern MEP1 on the first blocking metal pattern BAP1.

[0072] The first barrier metal pattern BAP1 may have a U-shaped cross-section. The top surface of the first barrier metal pattern BAP1 may be at substantially the same level as the top surface of the third interlayer insulation layer 130. As an example, the top surface of the first barrier metal pattern BAP1 may be lower than the top surface of the third interlayer insulation layer 130.

[0073] The first barrier metal pattern BAP1 can improve the adhesion between the first metal pattern MEPl and the third interlayer insulation layer 130. The first barrier metal pattern BAP1 can act as a barrier to prevent metallic elements in the first metal pattern MEPl from diffusing into the third interlayer insulation layer 130. The first barrier metal pattern BAP1 can be formed or include at least one of tantalum nitride (TaN), titanium nitride (TiN), tantalum oxide (TaO), titanium oxide (TiO), manganese nitride (MnN), or manganese oxide (MnO).

[0074] The first metal pattern MEP1 can be provided on the first barrier metal pattern BAP1. The first barrier metal pattern BAP1 can cover the two side surfaces and the bottom surface of the first metal pattern MEP1. The top surface of the first metal pattern MEP1 can be located at a level equal to or lower than the top surface of the third interlayer insulating layer 130. Although not shown, the first metal pattern MEP1 can have a convex top surface.

[0075] The volume of the first metal pattern MEP1 can be larger than the volume of the first blocking metal pattern BAP1. The first metal pattern MEP1 can be formed or include at least one of copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), tungsten (W), molybdenum (Mo), aluminum binary alloys (e.g., Al3Sc, Nb3Al, and AlRu), molybdenum binary alloys (e.g., MoTa and Co3Mo), ruthenium binary alloys, nickel binary alloys, MAX, or combinations thereof. MAX can be formed from or include at least one of copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), tungsten (W), molybdenum (Mo), aluminum binary alloys (e.g., Al3Sc, Nb3Al, and AlRu), molybdenum binary alloys (e.g., MoTa and Co3Mo), ruthenium binary alloys, nickel binary alloys, MAX, or combinations thereof. MAX can be formed from formula M n+1 AX n The term represents a metallic phase compound, where n is 1, 2, or 3, M is a transition metal, A is a group 13 or 14 element, and X is C and / or N. As an example, MAX could be V₂SiN, V₂AlC, or Cr₂AlC.

[0076] In one example embodiment, although not shown, a metal cap pattern may be additionally provided on the top surface of the first metal pattern MEPl. The metal cap pattern may have a thin and uniform thickness. For example, the metal cap pattern may be formed of or include at least one of ruthenium (Ru), cobalt (Co), or graphene.

[0077] The dielectric layer DOD and the etch stop layer ESL can be interposed between the third interlayer insulating layer 130 and the fourth interlayer insulating layer 140. The dielectric layer DOD can be in direct contact with the top surface of the third interlayer insulating layer 130. The dielectric layer DOD can be partially disposed on the top surface of the third interlayer insulating layer 130, but not on the interconnects PIL1, PIL2, and LIL1 to LIL5 of the first metal layer M1. This is because, apart from the interconnects, the dielectric layer DOD is only selectively formed on the top surface of the third interlayer insulating layer 130. Each of the interconnects PIL1, PIL2, and LIL1 to LIL5 of the first metal layer M1 can have a top surface lower than the top surface of the dielectric layer DOD.

[0078] The dielectric layer DOD may contain elements X and Y. Here, element X is selected from the group consisting of Si, Ge, Al, Zr, Y, Hf, and Mo, and element Y may be O or N. The dielectric layer DOD may also contain carbon (C). In an example embodiment, the dielectric layer DOD may be formed of or comprise a material substantially the same as that of the third interlayer insulating layer 130. As an example, the dielectric layer DOD may be formed of or comprise SiOC.

[0079] An etch stop layer (ESL) can be provided on the dielectric layer DOD. The ESL can directly cover the dielectric layer DOD. The ESL can also cover the top surfaces of interconnects PIL1, PIL2, and LIL1 to LIL5 that are not covered by the dielectric layer DOD. In other words, the ESL can directly contact the top surface of the dielectric layer DOD and the top surfaces of interconnects PIL1, PIL2, and LIL1 to LIL5.

[0080] The etch stop layer (ESL) may comprise a metal oxide layer or a metal nitride layer. The metal oxide layer or metal nitride layer may contain at least one metallic element selected from the group consisting of Al, Zr, Y, Hf, and Mo. For example, the etch stop layer (ESL) may be formed of or comprise aluminum oxide, hafnium oxide, hafnium zirconium oxide, aluminum nitride, hafnium nitride, or hafnium zirconium nitride.

[0081] The etch stop layer (ESL) can consist of a single layer or two or more stacked layers. (See reference...) Figure 3 A more detailed description of the Etching Stop Layer (ESL).

[0082] The fourth interlayer insulating layer 140 may cover the top surface of the etch stop layer ESL. A second metal layer M2 may be provided in the fourth interlayer insulating layer 140. The second metal layer M2 may include first to fourth upper interconnects UIL1 to UIL4. The first to fourth upper interconnects UIL1 to UIL4 may extend parallel to each other in a first direction D1. When viewed in a plan view, at least one or each of the first to fourth upper interconnects UIL1 to UIL4 may be linear or strip-shaped. As an example, the first to third upper interconnects UIL1 to UIL3 may be arranged in a second direction D2.

[0083] Each of the first to fourth upper interconnects UIL1 to UIL4 may include a second blocking metal pattern BAP2 and a second metal pattern MEP2 on the second blocking metal pattern BAP2. The second blocking metal pattern BAP2 and the second metal pattern MEP2 may be configured to have substantially the same characteristics as the first blocking metal pattern BAP1 and the first metal pattern MEP1 described above.

[0084] In one example implementation, refer to Figures 2A to 2CThe first upper interconnect UIL1 may include a line portion LIN and an upper pass VVI below it. The line portion LIN may be provided in the upper part of the fourth interlayer insulating layer 140 and may extend in the first direction D1. The upper pass VVI may be provided in the lower part of the fourth interlayer insulating layer 140 and may extend from the line portion LIN toward the first lower interconnect LIL1 and the fifth lower interconnect LIL5, respectively. That is, the upper pass VVI may be inserted between the first metal layer M1 and the line portion LIN to connect them to each other.

[0085] The upper pass VVI may be provided to penetrate the fourth interlayer insulating layer 140 and the etch stop layer ESL and extend toward the first metal layer M1. The upper pass VVI may contact the top surface of a corresponding one of the first lower interconnect LIL1 and the fifth lower interconnect LIL5. Although not shown, the upper pass VVI may contact at least a portion of the dielectric layer DOD adjacent to it.

[0086] The line portion LIN and the upper pass VVI can be connected to each other to form a single conductor (e.g., a first upper interconnect UIL1). The line portion LIN and the upper pass VVI can be formed by a dual damascene process, and in this case, they can form the first upper interconnect UIL1, which is one of the upper interconnects.

[0087] In one example implementation, refer to Figure 2D The second upper interconnect UIL2 may include a line portion LIN and a strip path BVI below it. The strip path BVI may be provided at the lower part of the fourth interlayer insulation layer 140 and may extend from the line portion LIN toward the first lower interconnect LIL1 and the second lower interconnect LIL2. That is, the strip path BVI may be inserted between the first metal layer M1 and the line portion LIN to connect them to each other.

[0088] A pair of adjacent first lower interconnects LIL1 and second lower interconnects LIL2 can be connected to each other through one of the strip path BVI. For example, the width W3 of the strip path BVI in the first direction D1 can be equal to or greater than the second pitch P2 between the first lower interconnects LIL1 and the second lower interconnects LIL2.

[0089] The strip-shaped via (BVI) can be provided to penetrate the fourth interlayer insulating layer 140 and the etch stop layer (ESL) and contact the top surfaces of the first lower interconnect (LIL1) and the second lower interconnect (LIL2). However, the strip-shaped via (BVI) may not penetrate the dielectric layer (DOD) between the first lower interconnect (LIL1) and the second lower interconnect (LIL2). The strip-shaped via (BVI) may directly contact the dielectric layer (DOD) between the first lower interconnect (LIL1) and the second lower interconnect (LIL2).

[0090] The line portion LIN and the stripe path BVI can be connected to each other to form a single conductor (e.g., a second upper interconnect UIL2). The line portion LIN and the stripe path BVI can be formed by a dual damascene process, and in this case, they can form a second upper interconnect UIL2, which is one of the upper interconnects.

[0091] Reference Figure 3 The strip path BVI of the second upper interconnect UIL2 according to this example embodiment is described in more detail. An air gap AG may be inserted between the first lower interconnect LIL1 and the second lower interconnect LIL2. The air gap AG may be provided in a third interlayer insulation layer 130 between the first lower interconnect LIL1 and the second lower interconnect LIL2. In one example embodiment, the air gap AG may be omitted.

[0092] The etch stop layer (ESL) may include a first etch stop layer (ESL1), a second etch stop layer (ESL2), and a third etch stop layer (ESL3). The first etch stop layer (ESL1) may directly cover the first lower interconnect (LIL1), the second lower interconnect (LIL2), and the dielectric layer (DOD). The second etch stop layer (ESL2) may cover the top surface of the first etch stop layer (ESL1). The third etch stop layer (ESL3) may cover the top surface of the second etch stop layer (ESL2).

[0093] The first etch stop layer ESL1 can be a layer with a high dielectric constant and low density. The first etch stop layer ESL1 can be a metal oxide layer or a metal nitride layer, comprising at least one metal selected from the group consisting of Al, Zr, Y, Hf, and Mo. For example, the first etch stop layer ESL1 can be formed or comprise at least one of aluminum oxide, hafnium oxide, hafnium zirconium oxide, aluminum nitride, hafnium nitride, or hafnium zirconium nitride.

[0094] The second etch stop layer ESL2 can be a layer with a low dielectric constant and a high density. The dielectric constant of the second etch stop layer ESL2 can be lower than that of the first etch stop layer ESL1. The density of the second etch stop layer ESL2 can be higher than that of the first etch stop layer ESL1.

[0095] The second etch stop layer ESL2 may contain elements X and Y, as well as carbon (C). Here, element X is selected from the group consisting of Si, Ge, Al, Zr, Y, Hf, and Mo, and element Y may be O or N. For example, the second etch stop layer ESL2 may be formed of or include SiOC, SiNC, GeOC, or GeNC.

[0096] The carbon (C) content in the second etch stop layer ESL2 can range from 10 at% to 25 at%. For example, the carbon (C) content in the second etch stop layer ESL2 can range from 15 at% to 20 at%. The content of element X in the second etch stop layer ESL2 can range from 30 at% to 50 at%.

[0097] The third etch stop layer ESL3 may be a metal oxide layer containing at least one metallic element selected from the group consisting of Al, Zr, Y, Hf, and Mo. For example, the third etch stop layer ESL3 may be formed of or comprise aluminum oxide. In one example embodiment, the third etch stop layer ESL3 may be formed of or comprise the same material as the first etch stop layer ESL1. In another example embodiment, the third etch stop layer ESL3 may be formed of or comprise the same material as the first etch stop layer ESL1. The dielectric constant of the third etch stop layer ESL3 may be higher than that of the second etch stop layer ESL2. The density of the third etch stop layer ESL3 may be lower than that of the second etch stop layer ESL2.

[0098] The thickness of the second etch stop layer ESL2 can be greater than the thickness of each of the first etch stop layer ESL1 and the third etch stop layer ESL3. For example, the thickness of each of the first etch stop layer ESL1 and the third etch stop layer ESL3 can be in the range of 2 nm to 5 nm. The thickness of the second etch stop layer ESL2 can be in the range of 3 nm to 10 nm.

[0099] The strip-shaped path BVI of the second upper interconnect UIL2 may include a first contact portion CTP1, a second contact portion CTP2, and a connection portion CNP between the first contact portion CTP1 and the second contact portion CTP2. The first contact portion CTP1 may be provided to penetrate the first to third etch stop layers ESL1 to ESL3 and contact the top surface of the first lower interconnect LIL1. The second contact portion CTP2 may be provided to penetrate the first to third etch stop layers ESL1 to ESL3 and contact the top surface of the second lower interconnect LIL2. The connection portion CNP may connect the first contact portion CTP1 and the second contact portion CTP2 to each other.

[0100] In one example implementation, the etch stop layer (ESL) can be a triple etch stop layer, consisting of three etch stop layers (e.g., a first etch stop layer ESL1, a second etch stop layer ESL2, and a third etch stop layer ESL3). The triple etch stop layer ESL according to this example implementation can achieve very high etch selectivity. Therefore, the first contact portion CTP1 and the second contact portion CTP2 of the second upper interconnect UIL2 can make stable contact with the first lower interconnect LIL1 and the second lower interconnect LIL2 without any process defects.

[0101] The dielectric layer DOD can be inserted between the first contact portion CTP1 and the second contact portion CTP2. As the dielectric layer DOD moves from the first contact portion CTP1 to the second contact portion CTP2, its thickness TI1 can increase until it reaches a maximum value and then decrease. That is, the dielectric layer DOD can have a dome shape. The bottom surface BOS2 of the connecting portion CNP can be in direct contact with the top surface TOS of the dielectric layer DOD.

[0102] The bottom surface BOS1 of each of the first contact portion CTP1 and the second contact portion CTP2 can be positioned at a first level LV1. The top surface of the third interlayer insulating layer 130 can also be positioned at the first level LV1. The bottom surface BOS2 of the connection portion CNP can be positioned at a second level LV2. The second level LV2 can be higher than the first level LV1. The top surface of the dielectric layer DOD can also be positioned at the second level LV2.

[0103] The top surface of the etch stop layer ESL (e.g., the top surface of the third etch stop layer ESL3) can be located at the third level LV3. The second level LV2 can be the level between the first level LV1 and the third level LV3. The bottom surface BOS3 of the line portion LIN can be located at the fourth level LV4. The fourth level LV4 can be higher than the third level LV3.

[0104] Return to reference Figure 2C The first upper interconnect UIL1 can be connected to the first lower interconnect LIL1 and the fifth lower interconnect LIL5 via multiple upper paths VVI instead of via a strip path BVI. The upper paths VVI can be connected to each other via line portions LIN. As described above, the bottom surface BOS3 of the line portions LIN connecting the upper paths VVI can be located at the fourth level LV4. That is, the bottom surface BOS3 of the line portions LIN connecting the upper paths VVI can be located at a higher level than the bottom surface BOS2 of the connecting portion CNP connecting the first contact portion CTP1 and the second contact portion CTP2.

[0105] In use Figure 2C The upper-pass VVI replaces Figure 3In the case of a strip-shaped path BVI, it may be difficult to form the upper path VVI on the first lower interconnect LIL1 and the second lower interconnect LIL2, which are set with very small pitches (e.g., the second pitch P2). This is due to limitations in design rules and fine patterning processes. However, the strip-shaped path BVI according to this example embodiment can be formed with a strip shape, which allows adjacent interconnects in interconnects spaced apart by very small pitches to be connected simultaneously. As a result, the degree of freedom in constructing the wiring structure using the BEOL process can be increased.

[0106] Figure 4 It is along Figure 1 A cross-sectional view taken along line D-D' to illustrate the semiconductor device according to the comparative example.

[0107] Reference Figure 4 The dielectric layer DOD in the aforementioned example embodiment can be omitted from the semiconductor device according to the comparative example. In this case, the second upper interconnect UIL2 may also include a protrusion PRT extending downward from the strip passage BVI. For example, the protrusion PRT may be formed when the third interlayer insulating layer 130 between the first lower interconnect LIL1 and the second lower interconnect LIL2 is over-etched during the formation of the strip passage BVI.

[0108] In the semiconductor device according to the comparative example, at least one of the upper portions of the first lower interconnect LIL1 and the second lower interconnect LIL2 can be damaged by the protruding portion PRT therebetween. Furthermore, the upper portion of the third interlayer insulating layer 130 can be recessed, and in this case, the electrical characteristics of the semiconductor device can be degraded. Additionally, although not shown, the protruding portion PRT may have an irregular profile that could lead to process failures (e.g., the second barrier metal pattern BAP2 of the protruding portion PRT may not be connected to the second barrier metal pattern BAP2 of the strip passage BVI).

[0109] Conversely, according to an exemplary embodiment of the invention, the dielectric layer DOD on the third interlayer insulating layer 130 can mitigate or prevent [the problem]. Figure 4 The protruding portion PRT is formed. Therefore, the aforementioned process defects caused by the protruding portion PRT can be mitigated or prevented, thereby improving the reliability and electrical characteristics of the semiconductor device.

[0110] Figure 5 , Figure 7 , Figure 9 and Figure 11 This is a plan view illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment of the concept of the present invention. Figure 6 , Figure 8A , Figure 10A and Figure 12A They are along Figure 5 , Figure 7 , Figure 9 and Figure 11 A sectional view taken by line A-A'. Figure 8B , Figure 10B and Figure 12B They are along Figure 7 , Figure 9 and Figure 11 The sectional view taken by line B-B'. Figure 10C and Figure 12C They are along Figure 9 and Figure 11 A sectional view taken by line C-C'. Figure 10D and 12D They are along Figure 9 and Figure 11 A sectional view taken by line D-D'.

[0111] Reference Figure 5 and Figure 6 A substrate 100 may be provided, comprising a first active region PR and a second active region NR. The first active region PR and the second active region NR may define logic cells LC on the substrate 100.

[0112] A first active pattern AP1 and a second active pattern AP2 can be formed by a patterned substrate 100. The first active pattern AP1 can be formed on a first active region PR, and the second active pattern AP2 can be formed on a second active region NR. A first trench TR1 can be formed between the first active pattern AP1 and the second active pattern AP2. The second trench TR2 can be formed in the portion of the patterned substrate 100 between the first active region PR and the second active region NR. The second trench TR2 can be formed to have a depth greater than that of the first trench TR1.

[0113] A device isolation layer ST may be formed on the substrate 100 to fill the first trench TR1 and the second trench TR2. The device isolation layer ST may be formed of or comprise an insulating material (e.g., silicon oxide). The device isolation layer ST may be recessed to expose the upper portions of the first active pattern AP1 and the second active pattern AP2. For example, the upper portions of the first active pattern AP1 and the second active pattern AP2 may protrude vertically over the device isolation layer ST.

[0114] Reference Figure 7 , Figure 8A and Figure 8B The sacrificial pattern PP can be formed to intersect with the first active pattern AP1 and the second active pattern AP2. The sacrificial pattern PP can be formed as a line or strip extending in the first direction D1. For example... Figure 1 As shown, the sacrificial pattern PP can be formed to be spaced apart from each other at a first pitch P1 in the second direction D2.

[0115] For example, the formation of the sacrificial pattern PP may include forming a sacrificial layer on the substrate 100, forming a hard mask pattern MA on the sacrificial layer, and using the hard mask pattern MA as an etch mask to pattern the sacrificial layer. The sacrificial layer may be formed of or comprise polysilicon.

[0116] A pair of gate spacers GS can be formed on both side surfaces of each sacrificial pattern PP. Formation of the gate spacers GS may include conformally forming a gate spacer layer on the substrate 100 and anisotropically etching the gate spacer layer. In one example embodiment, the gate spacer layer may be formed of at least one of SiCN, SiCON, or SiN, or include at least one of SiCN, SiCON, or SiN. In some example embodiments, the gate spacer layer may be a multilayer structure including at least two of SiCN, SiCON, or SiN layers.

[0117] Reference Figure 9 and Figures 10A to 10D The first source / drain pattern SD1 can be formed in the upper part of the first active pattern AP1. A pair of first source / drain patterns SD1 can be formed on both sides of each sacrificial pattern PP.

[0118] For example, the first recess RSR1 can be formed by etching the upper portion of the first active pattern AP1 using a hard mask pattern MA and a gate spacer GS as an etch mask. During the etching of the upper portion of the first active pattern AP1, the device isolation layer ST between the first active patterns AP1 can be recessed (e.g., see...). Figure 10C ).

[0119] The first source / drain pattern SD1 can be formed by performing a selective epitaxial growth process using the inner surface of the first recessed RSR1 of the first active pattern AP1 as a seed layer. As a result of forming the first source / drain pattern SD1, a first channel pattern CH1 can be defined between each pair of first source / drain patterns SD1. In one example embodiment, the selective epitaxial growth process can include a chemical vapor deposition (CVD) process or a molecular beam epitaxy (MBE) process. The first source / drain pattern SD1 can include semiconductor elements (e.g., SiGe) with a lattice constant greater than that of semiconductor elements in the substrate 100. Each first source / drain pattern SD1 can be a multilayer structure comprising multiple semiconductor layers.

[0120] In one example embodiment, the first source / drain pattern SD1 may be doped in situ during a selective epitaxial growth process. In some example embodiments, after the formation of the first source / drain pattern SD1, impurities may be implanted into the first source / drain pattern SD1. The first source / drain pattern SD1 may be doped to have a first conductivity type (e.g., p-type).

[0121] A second source / drain pattern SD2 can be formed on the second active pattern AP2. A pair of second source / drain patterns SD2 can be formed on both sides of each sacrificial pattern PP.

[0122] For example, the second recessed RSR2 can be formed by etching the upper portion of the second active pattern AP2 using a hard mask pattern MA and a gate spacer GS as an etch mask. The second source / drain pattern SD2 can be formed by performing a selective epitaxial growth process using the inner surface of the second recessed RSR2 of the second active pattern AP2 as a seed layer. As a result of forming the second source / drain pattern SD2, a second channel pattern CH2 can be defined between each pair of second source / drain patterns SD2. In one example embodiment, the second source / drain pattern SD2 may include the same semiconductor element (e.g., Si) as the substrate 100. The second source / drain pattern SD2 may be doped to have a second conductivity type (e.g., n-type).

[0123] The first source / drain pattern SD1 and the second source / drain pattern SD2 can be formed in different process sequences. That is, the first source / drain pattern SD1 and the second source / drain pattern SD2 can be formed at different times.

[0124] Reference Figure 11 and Figures 12A to 12D The first interlayer insulating layer 110 may be formed to cover the first source / drain pattern SD1 and the second source / drain pattern SD2, the hard mask pattern MA, and the gate spacer GS. In an example embodiment, the first interlayer insulating layer 110 may be formed of or include silicon oxide.

[0125] The first interlayer insulating layer 110 may be planarized to expose the top surface of the sacrificial pattern PP. Planarization of the first interlayer insulating layer 110 may be performed using an etch-back or chemical mechanical polishing (CMP) process. In one example embodiment, the planarization process may be performed to completely remove the hard mask pattern MA. Therefore, the first interlayer insulating layer 110 may have a top surface that is coplanar with the top surface of the sacrificial pattern PP and the top surface of the gate spacer GS.

[0126] The sacrificial pattern PP can be replaced by the gate electrode GE. For example, the exposed sacrificial pattern PP can be selectively removed. As a result of removing the sacrificial pattern PP, empty spaces can be formed. The gate insulating layer GI, the gate electrode GE, and the gate cap pattern GP can be formed in each empty space. The gate electrode GE can include a first metal pattern and a second metal pattern on the first metal pattern. The first metal pattern can be formed of a work function metal capable of adjusting the threshold voltage of the transistor, and the second metal pattern can be formed of a metallic material with low resistance.

[0127] The second interlayer insulating layer 120 may be formed on the first interlayer insulating layer 110. The second interlayer insulating layer 120 may be formed of or include silicon oxide. The active contact AC may be formed to penetrate the second interlayer insulating layer 120 and the first interlayer insulating layer 110 and be electrically connected to the first source / drain pattern SD1 and the second source / drain pattern SD2. The gate contact GC may be formed to penetrate the second interlayer insulating layer 120 and the gate cap pattern GP and be electrically connected to the gate electrode GE.

[0128] A pair of isolation structures DB can be formed along both sides of a logic cell LC, the two sides being opposite to each other in a second direction D2. The isolation structures DB can overlap with gate electrodes GE formed on both sides of the logic cell LC. For example, the formation of the isolation structures DB may include forming a hole and then filling the hole with an insulating layer that extends through the first interlayer insulating layer 110 and the second interlayer insulating layer 120 and the gate electrode GE into the first active pattern AP1 and the second active pattern AP2.

[0129] Return to reference Figure 1 and Figures 2A to 2D The third interlayer insulating layer 130 may be formed on the second interlayer insulating layer 120. The first metal layer M1 may be formed in the third interlayer insulating layer 130. The formation of the first metal layer M1 may include forming a first power line PIL1 and a second power line PIL2, first to fifth lower interconnects LIL1 to LIL5, and a lower path VI.

[0130] An etch stop layer (ESL) can be formed on the first metal layer M1. A fourth interlayer insulating layer (ILS) 140 can be formed on the ESL. A second metal layer M2 can be formed in the fourth ILS 140. The formation of the second metal layer M2 may include forming first to fourth upper interconnects UIL1 to UIL4. In an example embodiment, the first to fourth upper interconnects UIL1 to UIL4 can be formed using a dual damascene process.

[0131] According to an exemplary embodiment of the present invention, the process for forming interconnects PIL1, PIL2, and LIL1 to LIL5 of the first metal layer M1 or interconnects UIL1 to UIL4 of the second metal layer M2 may include a photolithography process performed using extreme ultraviolet (EUV) light. In this specification, EUV light may have a wavelength in the range of 4 nm to 124 nm, particularly 4 nm to 20 nm, and may be, for example, ultraviolet light with a wavelength of 13.5 nm. EUV light may have an energy of 6.21 eV to 124 eV, particularly 90 eV to 95 eV.

[0132] Photolithography processes using EUV light can include an exposure process that irradiates a photoresist layer with EUV light and a development process. For example, the photoresist layer can be an organic photoresist layer comprising an organic polymer (e.g., polyhydroxystyrene). The organic photoresist layer can also include a photosensitive compound that reacts with EUV light. The organic photoresist layer can also contain materials with high EUV absorption (e.g., organometallic materials, iodine-containing materials, or fluorine-containing materials). As another example, the photoresist layer can be an inorganic photoresist layer comprising an inorganic material (e.g., tin oxide).

[0133] The photoresist layer can be formed to have a relatively small thickness. The photoresist pattern can be formed by developing the photoresist layer exposed to EUV light. When viewed in a planar view, the photoresist pattern can be formed as lines, islands, zigzags, honeycomb shapes, or circles extending in a specific direction, but the inventive concept is not limited to these examples.

[0134] The mask pattern can be formed by patterning at least one mask layer disposed below the photoresist pattern using a photoresist pattern as an etch mask. Subsequently, by using the mask pattern as an etch mask pattern to pattern an interlayer insulating layer 130 or 140 as the target layer, trenches to be filled with the desired pattern (e.g., interconnects) can be formed on the wafer.

[0135] In a comparative example of the inventive concept, multiple patterning (MPT) techniques using two or more photomasks are required to form fine-pitch patterns on the wafer. Conversely, in the case of performing an EUV lithography process according to an exemplary embodiment of the inventive concept, interconnects with fine pitch can be formed using only one photomask.

[0136] For example, return to reference Figure 2D The second pitch P2 between the first lower interconnect LIL1 and the second lower interconnect LIL2, implemented by the EUV lithography process according to this example embodiment, can be less than or equal to 45 nm. That is, the EUV lithography process can be performed to form interconnects precisely and finely without the need for multiple patterning techniques.

[0137] Figures 13 to 17 It is an enlarged sectional view, which shows Figure 2D The section M is used to illustrate a method for forming an upper interconnect according to an exemplary embodiment of the present invention. In the following, the method for forming the second upper interconnect UIL2 will be referred to... Figures 13 to 17 It was described in more detail.

[0138] Reference Figure 13 The first lower interconnect LIL1 and the second lower interconnect LIL2 can be formed in the upper portion of the third interlayer insulating layer 130. The first lower interconnect LIL1 and the second lower interconnect LIL2 can be adjacent to each other. In an example embodiment, the first lower interconnect LIL1 and the second lower interconnect LIL2 can be formed by a single damascene process. Each of the first lower interconnect LIL1 and the second lower interconnect LIL2 can be formed by sequentially forming a first barrier metal pattern BAP1 and a first metal pattern MEP1.

[0139] An air gap AG can be formed in a third interlayer insulating layer 130 between the first lower interconnect LIL1 and the second lower interconnect LIL2. For example, forming the air gap AG may include forming the first lower interconnect LIL1 and the second lower interconnect LIL2 in an initial interlayer insulating layer, removing the initial interlayer insulating layer, forming the third interlayer insulating layer 130 on the exposed first lower interconnect LIL1 and the second lower interconnect LIL2, and planarizing the third interlayer insulating layer 130 to expose the top surfaces of the first lower interconnect LIL1 and the second lower interconnect LIL2. When the third interlayer insulating layer 130 is formed, the air gap AG can be formed between the first lower interconnect LIL1 and the second lower interconnect LIL2.

[0140] Reference Figure 14 The dielectric layer DOD can be selectively formed on the top surface of the third interlayer insulating layer 130. The dielectric layer DOD may not be formed on the top surface of the first lower interconnect LIL1 and the second lower interconnect LIL2.

[0141] For example, the formation of the dielectric layer DOD may include selectively providing inhibitors on the top surfaces of the first lower interconnect LIL1 and the second lower interconnect LIL2 and depositing the dielectric layer DOD on the third interlayer insulating layer 130. The inhibitors may mitigate or prevent the precursors of the dielectric layer DOD from adhering to the top surfaces of the first lower interconnect LIL1 and the second lower interconnect LIL2.

[0142] The dielectric layer DOD can contain elements X and Y. Here, element X is selected from the group consisting of Si, Ge, Al, Zr, Y, Hf, and Mo, and element Y can be O or N. The dielectric layer DOD can also contain carbon (C).

[0143] Reference Figure 15 A first etch stop layer ESL1 can be formed on the dielectric layer DOD and the first lower interconnect LIL1 and the second lower interconnect LIL2. The first etch stop layer ESL1 can cover the top surface of the dielectric layer DOD and the top surfaces of the first lower interconnect LIL1 and the second lower interconnect LIL2. The first etch stop layer ESL1 can be formed with a thickness of 2 nm to 5 nm. The first etch stop layer ESL1 can be formed of a material with a high dielectric constant and low density. The first etch stop layer ESL1 can be a metal oxide layer containing at least one metallic element selected from the group consisting of Al, Zr, Y, Hf, and Mo. The first etch stop layer ESL1 can have etch selectivity relative to the dielectric layer DOD.

[0144] A second etch stop layer (ESL2) can be formed on top of the first etch stop layer (ESL1). The second etch stop layer (ESL2) can be formed with a thickness of 3 nm to 10 nm. The thickness of the second etch stop layer (ESL2) can be greater than the thickness of the first etch stop layer (ESL1). The second etch stop layer (ESL2) can be formed from a material with a low dielectric constant and high density. The second etch stop layer (ESL2) can contain elements X and Y, as well as carbon (C). Here, element X is selected from the group consisting of Si, Ge, Al, Zr, Y, Hf, and Mo, and element Y can be O or N.

[0145] A third etch stop layer ESL3 can be formed on the second etch stop layer ESL2. The second etch stop layer ESL2 can be formed with a thickness of 2 nm to 5 nm. The thickness of the second etch stop layer ESL2 can be greater than the thickness of the first etch stop layer ESL1. The third etch stop layer ESL3 can be a metal oxide layer containing at least one metallic element selected from the group consisting of Al, Zr, Y, Hf, and Mo. For example, the third etch stop layer ESL3 can be formed of the same material as the first etch stop layer ESL1 or can include the same material as the first etch stop layer ESL1.

[0146] Reference Figure 16 The fourth interlayer insulating layer 140 may be formed on the third etch stop layer ESL3. For example, the fourth interlayer insulating layer 140 may comprise a silicon oxide layer containing silicon (Si) and oxygen (O). The fourth interlayer insulating layer 140 may also comprise carbon (C) and hydrogen (H).

[0147] Reference Figure 17 The upper interconnect via UIH can be formed by patterning the upper portion of the fourth interlayer insulating layer 140. The etch stop layer ESL can be patterned to form a first contact via CTH1 and a second contact via CTH2 that expose the top surfaces of the first lower interconnect LIL1 and the second lower interconnect LIL2, respectively.

[0148] Simultaneously, because the dielectric layer DOD has etch selectivity relative to the etch stop layer ESL, it can remain between the first lower interconnect LIL1 and the second lower interconnect LIL2 during the patterning of the etch stop layer ESL. Therefore, the first contact hole CTH1 and the second contact hole CTH2 can be spaced apart from each other, and the dielectric layer DOD is interposed between them. The top surface TOS of the dielectric layer DOD between the first lower interconnect LIL1 and the second lower interconnect LIL2 can be exposed through the upper interconnect UIH.

[0149] According to an exemplary embodiment of the present invention, a triple etch stop layer can achieve high etch selectivity during the etching process for forming the first contact hole CTH1 and the second contact hole CTH2. Therefore, the first contact hole CTH1 and the second contact hole CTH2 can be formed to stably expose the top surfaces of the first lower interconnect LIL1 and the second lower interconnect LIL2. Furthermore, due to the high etch selectivity of the triple etch stop layer, the dielectric layer DOD can be avoided by the etching process, and thus it can be used to protect the third interlayer insulating layer 130 between the first lower interconnect LIL1 and the second lower interconnect LIL2. Therefore, when forming the first contact hole CTH1 and the second contact hole CTH2, over-etching of the third interlayer insulating layer 130 can be mitigated or prevented, thereby preventing process defects (e.g., exposure of the air gap AG).

[0150] Return to reference Figure 3 The second upper interconnect UIL2 can be formed by filling the upper interconnect via UIH with a conductive material. For example, the formation of the second upper interconnect UIL2 may include forming a barrier layer (e.g., a second barrier metal pattern BAP2) in the upper interconnect via UIH and forming a metal layer (e.g., a second metal pattern MEP2) on the barrier layer.

[0151] The second upper interconnect UIL2 may include a strip-shaped path BVI that fills both the first contact hole CTH1 and the second contact hole CTH2. The strip-shaped path BVI may include a connection portion CNP that is provided on the dielectric layer DOD between the first lower interconnect LIL1 and the second lower interconnect LIL2.

[0152] Figures 18 to 20 These are sectional views, each sectional view along... Figure 1 The line D-D' is cut off to illustrate a semiconductor device according to another exemplary embodiment of the concept of the present invention. For the sake of brevity, reference has been previously made to... Figure 1 , Figures 2A to 2D and Figure 3 The described elements may be identified by the same reference numerals without repeating their overlapping descriptions.

[0153] Reference Figure 18 The interconnects PIL1, PIL2, and LIL1 to LIL5 in the first metal layer M1 can be formed by a subtractive process instead of a damascene process. For example, the third lower interconnect LIL3 may include a first barrier metal pattern BAP1 and a first metal pattern MEP1. The first barrier metal pattern BAP1 may be provided only as the bottom of the third lower interconnect LIL3. The first metal pattern MEP1 may be provided on the top surface of the first barrier metal pattern BAP1. The first barrier metal pattern BAP1 may only cover the bottom surface of the first metal pattern MEP1 and may not cover the side surfaces of the first metal pattern MEP1.

[0154] The side surface SW3 of the third lower interconnect LIL3 can have a negative slope. That is, the linewidth of the third lower interconnect LIL3 can gradually decrease as it rises in the third direction D3. An air gap AG can be provided in the third interlayer insulation layer 130 between the first lower interconnect LIL1 and the second lower interconnect LIL2.

[0155] The interconnects PIL1, PIL2, and LIL1 to LIL5 in the first metal layer M1 can be formed by depositing and patterning the metal layer. Therefore, the first metal pattern MEP1 can be formed of or include a metallic material that can be patterned by an etching process. For example, the first metal pattern MEP1 can be formed of or include ruthenium (Ru) and / or molybdenum (Mo).

[0156] Interconnects UIL1 to UIL4 in the second metal layer M2 can be formed using a single damascene process. For example, the second upper interconnect UIL2 may include a line portion LIN and a strip path BVI below it. Each of the line portion LIN and the strip path BVI may include a metal pattern and a blocking metal pattern surrounding the metal pattern. For example, the second blocking metal pattern BAP2 may be provided as an interface layer between the line portion LIN and the strip path BVI.

[0157] The side surface SW4 of the fourth upper interconnect UIL4 can have a positive slope. That is, the slope of the side surface SW4 of the fourth upper interconnect UIL4 can have the opposite sign to the slope of the side surface SW3 of the third lower interconnect LIL3. This is because the interconnects PIL1, PIL2, and LIL1 to LIL5 in the first metal layer M1 are formed by a subtractive process, while the interconnects UIL1 to UIL4 in the second metal layer M2 are formed by a damascene process.

[0158] Reference Figure 19The vias BVI and VVI in the second metal layer M2 can be formed using a single damascene process, and the line portions LIN in the second metal layer M2 can be formed using a subtractive process. That is, the interconnects UIL1 to UIL4 in the second metal layer M2 can be formed using a half-damascene process. The side surface SW4 of the line portion LIN of the fourth upper interconnect UIL4 can have a negative slope. In other words, the slope of the side surface SW4 of the fourth upper interconnect UIL4 can have the same sign as the slope of the side surface SW3 of the third lower interconnect LIL3.

[0159] Reference Figure 20 The strip path BVI of the second upper interconnect UIL2 can be connected to all of the first to third lower interconnects LIL1 to LIL3. For example, the strip path BVI of the second upper interconnect UIL2 may include a first contact portion CTP1, a second contact portion CTP2, and a third contact portion CTP3. The first to third contact portions CTP1 to CTP3 can be connected to the first to third lower interconnects LIL1 to LIL3, respectively.

[0160] The strip-shaped pathway BVI may further include a first connecting portion CNP1 between the first contact portion CTP1 and the second contact portion CTP2, and a second connecting portion CNP2 between the second contact portion CTP2 and the third contact portion CTP3. A first dielectric layer DOD1 may be inserted between the first contact portion CTP1 and the second contact portion CTP2. A second dielectric layer DOD2 may be inserted between the second contact portion CTP2 and the third contact portion CTP3. The bottom surface BOS2 of the first connecting portion CNP1 may be in direct contact with the top surface of the first dielectric layer DOD1, and the bottom surface BOS4 of the second connecting portion CNP2 may be in direct contact with the top surface of the second dielectric layer DOD2.

[0161] The first to third lower interconnects LIL1 to LIL3 can be arranged in the first direction D1 with at least two different pitches. For example, the pitch between the first lower interconnect LIL1 and the second lower interconnect LIL2 can be a second pitch P2, and the pitch between the second lower interconnect LIL2 and the third lower interconnect LIL3 can be a third pitch P3. The third pitch P3 can be greater than the second pitch P2.

[0162] Because the third pitch P3 is greater than the second pitch P2, the width of the second dielectric layer DOD2 can be greater than the width of the first dielectric layer DOD1. Because the third pitch P3 is greater than the second pitch P2, the width of the second connecting portion CNP2 can be greater than the width of the first connecting portion CNP1.

[0163] In one example implementation, the level of the bottom surface BOS2 of the first connection portion CNP1 may differ from the level of the bottom surface BOS4 of the second connection portion CNP2. For example, the level of the bottom surface BOS2 of the first connection portion CNP1 may be higher than the level of the bottom surface BOS4 of the second connection portion CNP2. That is, the highest surface of the first dielectric layer DOD1 may be higher than the highest surface of the second dielectric layer DOD2. This is because the second pitch P2 and the third pitch P3 are different from each other.

[0164] Figure 21 It is a sectional view, along Figure 1 Line A-A' is taken to illustrate a semiconductor device according to another exemplary embodiment of the concept of the present invention. For the sake of brevity, reference has been previously made to... Figure 1 , Figures 2A to 2D and Figure 3 The described elements may be identified by the same reference numerals without repeating their overlapping descriptions.

[0165] Reference Figure 21 The lower dielectric layer LDOD and the lower etch stop layer LESL can be interposed between the second interlayer insulating layer 120 and the third interlayer insulating layer 130. The lower dielectric layer LDOD can directly contact the top surface of the second interlayer insulating layer 120. The lower dielectric layer LDOD can be selectively disposed only on the top surface of the second interlayer insulating layer 120, and not on the active contact AC. The lower etch stop layer LESL can directly cover the dielectric layer DOD.

[0166] The lower stripe path (LBVI) can be provided between the second lower interconnect (LIL2) and the active contact (AC). The lower stripe path (LBVI) may include a first contact portion (CTP1), a second contact portion (CTP2), and a connection portion (CNP) between the first contact portion (CTP1) and the second contact portion (CTP2).

[0167] The first contact portion CTP1 and the second contact portion CTP2 can be provided to penetrate the lower etch stop layer LESL and can be respectively connected to adjacent pairs of active contacts AC. The connection portion CNP can be provided on the lower dielectric layer LDOD between the pairs of active contacts AC.

[0168] That is, the strip-shaped path according to this example embodiment can be provided not only between the first metal layer M1 and the second metal layer M2, but also between the second interlayer insulating layer 120 (in which active contact AC and gate contact GC are provided) and the first metal layer M1.

[0169] Figures 22A to 22D It is a sectional view, which is shown along... Figure 1Lines A-A', B-B', C-C', and D-D' are cut to illustrate a semiconductor device according to an exemplary embodiment of the concept of the present invention. For the sake of brevity, reference has been previously made to... Figure 1 and Figures 2A to 2D The described elements may be identified by the same reference numerals without repeating their overlapping descriptions.

[0170] Reference Figure 1 and Figures 22A to 22D A substrate 100 may be provided, comprising a first active region PR and a second active region NR. A device isolation layer ST may be provided on the substrate 100. The device isolation layer ST may define a first active pattern AP1 and a second active pattern AP2 on the upper part of the substrate 100. The first active pattern AP1 and the second active pattern AP2 may be defined on the first active region PR and the second active region NR, respectively.

[0171] The first active pattern AP1 may include a first channel pattern CH1 vertically stacked on the substrate 100. The stacked first channel patterns CH1 may be spaced apart from each other in the third direction D3. When viewed in a plan view, the stacked first channel patterns CH1 may overlap each other. The second active pattern AP2 may include a second channel pattern CH2 vertically stacked on the substrate 100. The stacked second channel patterns CH2 may be spaced apart from each other in the third direction D3. When viewed in a plan view, the stacked second channel patterns CH2 may overlap each other. The first channel pattern CH1 and the second channel pattern CH2 may be formed or include at least one of silicon (Si), germanium (Ge), or silicon-germanium (SiGe).

[0172] The first active pattern AP1 may also include a first source / drain pattern SD1. A stacked first channel pattern CH1 may be inserted between each pair of adjacent first source / drain patterns SD1. The stacked first channel pattern CH1 can connect each pair of adjacent first source / drain patterns SD1 to each other.

[0173] The second active pattern AP2 may also include a second source / drain pattern SD2. A stacked second channel pattern CH2 may be inserted between each pair of adjacent second source / drain patterns SD2. The stacked second channel pattern CH2 can connect each pair of adjacent second source / drain patterns SD2 to each other.

[0174] The gate electrode GE can be provided to extend in a first direction Dl and intersect with a first channel pattern CH1 and a second channel pattern CH2. When viewed in a plan view, the gate electrode GE can overlap with the first channel pattern CH1 and the second channel pattern CH2. A pair of gate spacers GS can be disposed on two side surfaces of the gate electrode GE. A gate cap pattern GP can be provided on the gate electrode GE.

[0175] The gate electrode GE can be provided around each of the first channel pattern CH1 and the second channel pattern CH2 (e.g., see...). Figure 22D The gate electrode GE can be provided on the first top surface TS1, at least one first side surface SW1, and the first bottom surface BS1 of the first channel pattern CH1. The gate electrode GE can be provided on the second top surface TS2, at least one second side surface SW2, and the second bottom surface BS2 of the second channel pattern CH2. That is, the gate electrode GE can surround the top surface, bottom surface, and two side surfaces of each of the first channel pattern CH1 and the second channel pattern CH2. The transistor according to this exemplary embodiment can be a three-dimensional field-effect transistor (e.g., a multi-bridge channel field-effect transistor (MBCFET)) in which the gate electrode GE is configured to surround the channel patterns CH1 and CH2 in three dimensions.

[0176] A gate insulating layer GI may be provided between the gate electrode GE in each of the first channel pattern CH1 and the second channel pattern CH2. The gate insulating layer GI may surround each of the first channel pattern CH1 and the second channel pattern CH2.

[0177] On the second active region NR, the insulating pattern IP can be interposed between the gate insulating layer GI and the second source / drain pattern SD2. The gate electrode GE can be spaced apart from the second source / drain pattern SD2 by the gate insulating layer GI and the insulating pattern IP. Conversely, on the first active region PR, the insulating pattern IP can be omitted.

[0178] A first interlayer insulating layer 110 and a second interlayer insulating layer 120 may be provided to cover the substrate 100. An active contact AC may be provided to penetrate the first interlayer insulating layer 110 and the second interlayer insulating layer 120 and may be connected to the first source / drain pattern SD1 and the second source / drain pattern SD2, respectively. A gate contact GC may be provided to penetrate the second interlayer insulating layer 120 and the gate cap pattern GP and may be connected to the gate electrode GE.

[0179] A third interlayer insulating layer 130 may be provided on the second interlayer insulating layer 120. A fourth interlayer insulating layer 140 may be provided on the third interlayer insulating layer 130. A first metal layer M1 may be provided in the third interlayer insulating layer 130. A second metal layer M2 may be provided in the fourth interlayer insulating layer 140. The first metal layer M1 and the second metal layer M2 may be referenced. Figure 1 and Figures 2A to 2D The examples described above are essentially the same as those in the previous example implementations.

[0180] In one exemplary embodiment of the invention, a semiconductor device may include lower interconnects and upper interconnects having strip-shaped pathways (hereinafter, strip-shaped pathways), the lower interconnects being adjacent to each other with a very small pitch and connected together to the upper interconnects via the strip-shaped pathways. As a result, the degrees of freedom in constructing wiring structures using the BEOL process can be increased.

[0181] Furthermore, according to an exemplary embodiment of the invention, the protrusion extending downwards from the stripway into the region between the lower interconnects can be mitigated or prevented. Therefore, process failures between the lower interconnects can be mitigated or prevented, and the reliability and electrical characteristics of the semiconductor device can be improved.

[0182] While some exemplary embodiments of the inventive concept have been specifically shown and described, those skilled in the art will understand that changes in form and detail may be made without departing from the spirit and scope of the appended claims.

[0183] This application claims priority to Korean Patent Application No. 10-2020-0177705, filed on December 17, 2020, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor device, comprising: Transistors on a substrate; The first interlayer insulating layer on the transistor; The first lower interconnect and the second lower interconnect in the upper part of the first interlayer insulating layer; The dielectric layer is selectively located on the top surface of the first interlayer insulating layer, excluding the top surfaces of the first lower interconnect and the second lower interconnect; An etch stop layer on the first lower interconnect, the second lower interconnect, and the dielectric layer; A second interlayer insulating layer on the etch stop layer; as well as The upper interconnect in the second interlayer insulating layer The upper interconnect includes, The line part, and A strip-shaped via extending from the line portion to the first lower interconnect and the second lower interconnect to penetrate the etch stop layer, the strip-shaped via comprising, The first contact portion and the second contact portion are respectively connected to the first lower interconnect and the second lower interconnect, and In the first connection portion between the first contact portion and the second contact portion, due to the dielectric layer, the bottom surface of the first connection portion is higher than the top surface of the first interlayer insulating layer and lower than the top surface of the etch stop layer.

2. The semiconductor device of claim 1, wherein the bottom surface of the first connection portion is in contact with the top surface of the dielectric layer between the first contact portion and the second contact portion.

3. The semiconductor device of claim 2, wherein the thickness of the dielectric layer between the first contact portion and the second contact portion increases along the direction from the first contact portion to the second contact portion until the thickness reaches a maximum value and then decreases.

4. The semiconductor device of claim 1, wherein... The first lower interconnect and the second lower interconnect are arranged in a first direction with a first pitch, and The width of the strip passage in the first direction is greater than the first pitch.

5. The semiconductor device of claim 1, wherein the bottom surface of the line portion is higher than the top surface of the etch stop layer.

6. The semiconductor device of claim 1, wherein the etch stop layer comprises a material having etch selectivity relative to the dielectric layer.

7. The semiconductor device of claim 6, wherein... The etch stop layer comprises a first etch stop layer, a second etch stop layer, and a third etch stop layer stacked sequentially. The thickness of the second etch stop layer is greater than the thickness of the first etch stop layer, and The thickness of the second etch stop layer is greater than the thickness of the third etch stop layer.

8. The semiconductor device of claim 1, further comprising: The third lower interconnect in the upper part of the first interlayer insulating layer. The strip passage further includes, The third contact portion connected to the third lower interconnect, and The second connecting portion between the second contact portion and the third contact portion, and The bottom surface of the first connecting portion is at a different level than the bottom surface of the second connecting portion.

9. The semiconductor device of claim 8, wherein The dielectric layer includes a first dielectric layer below the first connection portion and a second dielectric layer below the second connection portion, and The level of the uppermost surface of the first dielectric layer is different from the level of the uppermost surface of the second dielectric layer.

10. The semiconductor device of claim 8, wherein the pitch between the first lower interconnect and the second lower interconnect is different from the pitch between the second lower interconnect and the third lower interconnect.

11. A semiconductor device, comprising: Transistors on a substrate; The first interlayer insulating layer on the transistor; The first lower interconnect and the second lower interconnect in the upper part of the first interlayer insulating layer; The dielectric layer is selectively located on the top surface of the first interlayer insulating layer, excluding the top surfaces of the first lower interconnect and the second lower interconnect; An etch stop layer on the first lower interconnect, the second lower interconnect, and the dielectric layer; A second interlayer insulating layer on the etch stop layer; as well as The first upper interconnect in the second interlayer insulating layer The first upper interconnect includes, First line section; as well as A strip-shaped via extending from the first line portion to the first lower interconnect and the second lower interconnect to penetrate the etch stop layer, the strip-shaped via comprising, The first contact portion and the second contact portion are respectively connected to the first lower interconnect and the second lower interconnect, and The first connection portion between the first contact portion and the second contact portion The top surface of the dielectric layer between the first contact portion and the second contact portion is covered by the first connection portion, and The thickness of the dielectric layer between the first contact portion and the second contact portion increases along the direction from the first contact portion to the second contact portion until the thickness reaches a maximum value and then decreases.

12. The semiconductor device of claim 11, wherein the top surface of the dielectric layer below the first line portion is covered by the etch stop layer.

13. The semiconductor device of claim 11, further comprising: The third and fourth lower interconnects in the upper part of the first interlayer insulating layer; as well as The second upper interconnect in the second interlayer insulating layer The second upper interconnect includes, The first upper path and the second upper path are respectively connected to the third lower interconnect and the fourth lower interconnect, and The second line portion between the first upper passage and the second upper passage, and the bottom surface of the second line portion are higher than the bottom surface of the first connecting portion.

14. The semiconductor device of claim 11, further comprising: The third lower interconnect in the upper part of the first interlayer insulating layer. The strip-shaped pathway includes, The third contact portion connected to the third lower interconnect, and The second connecting portion between the second contact portion and the third contact portion, and The bottom surface of the first connecting portion is at a different level than the bottom surface of the second connecting portion.

15. The semiconductor device of claim 14, wherein the pitch between the first lower interconnect and the second lower interconnect is different from the pitch between the second lower interconnect and the third lower interconnect.

16. A semiconductor device, comprising: The substrate includes the active region; A device isolation layer defines an active pattern on the active region, the device isolation layer covering the lower surface of each active pattern, and the upper part of each active pattern protruding above the device isolation layer. A pair of source / drain patterns at the upper part of each active pattern; The channel pattern between the pair of source / drain patterns; A gate electrode extending in a first direction to intersect the channel pattern; Gate spacers are located on the opposite side surface of the gate electrode and extend along the gate electrode in the first direction; A gate insulating layer is provided between the gate electrode and the channel pattern, and between the gate electrode and the gate spacer. A gate cap pattern extends on the top surface of the gate electrode and along the gate electrode in the first direction; The first interlayer insulating layer on the gate cover pattern; An active contact that penetrates the first interlayer insulation layer and is electrically connected to at least one of the source / drain patterns; A first metal layer in a second interlayer insulating layer, wherein the second interlayer insulating layer is on the first interlayer insulating layer; A second metal layer in a third interlayer insulating layer, wherein the third interlayer insulating layer is on the second interlayer insulating layer; as well as A dielectric layer and an etch stop layer between the second interlayer insulating layer and the third interlayer insulating layer. The etch stop layer covers the dielectric layer. The first metal layer includes a first lower interconnect and a second lower interconnect. The second metal layer includes a first upper interconnect electrically connected to the first lower interconnect and the second lower interconnect, and The first upper interconnect includes, The first line section, and A strip-shaped via extending from the first line portion to the first lower interconnect and the second lower interconnect to penetrate the etch stop layer, the strip-shaped via comprising, The first contact portion and the second contact portion are respectively connected to the first lower interconnect and the second lower interconnect, and In the first connection portion between the first contact portion and the second contact portion, due to the dielectric layer, the bottom surface of the first connection portion is higher than the top surface of the second interlayer insulating layer and lower than the top surface of the etch stop layer.

17. The semiconductor device of claim 16, wherein the bottom surface of the first connection portion is in contact with the top surface of the dielectric layer between the first contact portion and the second contact portion.

18. The semiconductor device of claim 17, wherein the thickness of the dielectric layer between the first contact portion and the second contact portion increases along a direction from the first contact portion to the second contact portion until the thickness reaches a maximum value and then decreases.

19. The semiconductor device of claim 16, wherein The first metal layer also includes a third lower interconnect and a fourth lower interconnect. The second metal layer includes a second upper interconnect electrically connected to the third lower interconnect and the fourth lower interconnect. The second upper interconnect includes, The first upper path and the second upper path are respectively connected to the third lower interconnect and the fourth lower interconnect, and The second line portion between the first upper passage and the second upper passage, and the bottom surface of the second line portion are higher than the bottom surface of the first connecting portion.

20. The semiconductor device of claim 16, wherein The etch stop layer comprises a first etch stop layer, a second etch stop layer, and a third etch stop layer stacked sequentially. Each of the first and third etch stop layers comprises a metal oxide layer or a metal nitride layer, wherein the metal oxide layer or the metal nitride layer contains at least one metallic element selected from the group consisting of Al, Zr, Y, Hf, and Mo, and The second etch stop layer contains elements X and Y and carbon (C), wherein element X is selected from the group consisting of Si, Ge, Al, Zr, Y, Hf and Mo, and element Y is O or N.

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