Contact structure in semiconductor devices

Abstract

Contact structures in semiconductor devices are disclosed. A semiconductor device having a linerless contact structure and a method of manufacturing the same are disclosed. The method includes forming a first dielectric layer between first source / drain (S / D) regions and second S / D regions formed on first and second fin structures; forming a second dielectric layer on the first and second dielectric layers and first gate all around (GAA) structures and second GAA structures formed on the first and second fin structures; forming a tapered trench opening in the second dielectric layer and on the first and second GAA structures and the first dielectric layer; selectively forming a seed layer on exposed top surfaces of the first and second GAA structures and the first dielectric layer; and selectively depositing a conductive layer on the seed layer.

Description

Technical Field

[0001] This disclosure relates to contact structures in semiconductor devices. Background Technology

[0002] With advancements in semiconductor technology, the demand for higher storage capacity, faster processing systems, higher performance, and lower costs continues to grow. To meet these demands, the semiconductor industry is constantly shrinking the size of semiconductor devices, such as metal-oxide-semiconductor field-effect transistors (MOSFETs), including planar MOSFETs, fin field-effect transistors (finFETs), and gate-all-around FETs (GAA FETs). This scaling down increases the complexity of semiconductor manufacturing processes. Summary of the Invention

[0003] According to a first aspect of this disclosure, a method for forming a semiconductor device is provided, comprising: forming a first source / drain (S / D) region and a second S / D region on a first fin structure and a second fin structure, respectively; forming a first dielectric layer between the first S / D region and the second S / D region; forming a first gate all-around (GAA) structure and a second GAA structure on the first fin structure and the second fin structure, respectively, wherein the first GAA structure and the second GAA structure are electrically isolated by the first dielectric layer; forming a second dielectric layer on the first GAA structure, the second GAA structure, and the first dielectric layer; forming a tapered trench opening in the second dielectric layer and on the first GAA structure, the second GAA structure, and the first dielectric layer; selectively forming a seed layer on the top surface of the first GAA structure, the second GAA structure, and the first dielectric layer exposed in the tapered trench opening; and selectively depositing a conductive layer on the seed layer to fill the tapered trench opening.

[0004] According to a second aspect of this disclosure, a method for forming a semiconductor device is provided, comprising: forming a first source / drain (S / D) region and a second S / D region on a first fin structure and a second fin structure, respectively; forming a first dielectric layer between the first S / D region and the second S / D region; forming a first gate structure and a second gate structure on the first fin structure and the second fin structure, respectively, wherein the first gate structure and the second gate structure are electrically isolated by the first dielectric layer; forming a second dielectric layer on the first gate structure, the second gate structure, and the first dielectric layer; forming a linerless contact structure having a seed layer and a conductive layer in the second dielectric layer and on the first gate structure, the second gate structure, and the first dielectric layer; and forming an isolation structure in the linerless contact structure.

[0005] According to a third aspect of this disclosure, a semiconductor device is provided, comprising: a substrate; a first source / drain (S / D) region and a second S / D region, respectively disposed on a first fin structure and a second fin structure; a first dielectric layer disposed between the first S / D region and the second S / D region; a first gate structure and a second gate structure, respectively disposed on the first fin structure and the second fin structure, wherein the first gate structure and the second gate structure are electrically isolated by the first dielectric layer; a second dielectric layer disposed on the first gate structure, the second gate structure, and the first dielectric layer; a linerless contact structure having a seed layer and a conductive layer, the linerless contact structure being in the second dielectric layer and on the first gate structure, the second gate structure, and the first dielectric layer; and an isolation structure disposed in the linerless contact structure. Attached Figure Description

[0006] Various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings.

[0007] Figure 1A An isometric view of a semiconductor device according to some embodiments is shown.

[0008] Figure 1B An isometric view of a semiconductor device having a contact structure according to some embodiments is shown.

[0009] Figures 1C-1E A cross-sectional view of a semiconductor device having a contact structure according to some embodiments is shown.

[0010] Figure 2 This is a flowchart of a method for manufacturing a semiconductor device having a contact structure according to some embodiments.

[0011] Figure 3 and Figures 4A-18B Isometric views and cross-sectional views of a semiconductor device with a contact structure according to some embodiments are shown at various stages of its manufacturing process.

[0012] Illustrative embodiments will now be described with reference to the accompanying drawings. In the drawings, similar reference numerals generally denote the same, functionally similar, and / or structurally similar elements. Detailed Implementation

[0013] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first feature over a second feature can include embodiments in which the first and second features are formed in direct contact, and can also include embodiments in which an additional feature can be formed between the first and second features such that the first and second features do not need to be in direct contact. As used herein, forming a first feature over a second feature means that the first feature is formed in direct contact with the second feature. Furthermore, reference numerals and / or letters may be repeated in various examples of this disclosure. Such repetition, in itself, does not prescribe a relationship between the various embodiments and / or configurations discussed.

[0014] Spatially related terms (e.g., “below,” “under,” “down,” “above,” “up,” etc.) may be used herein to readily describe the relationship of one element or feature shown in the figure relative to another element(s) or feature(s). These spatially related terms are intended to cover different orientations of the device in use or operation other than those shown in the figure. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein may be interpreted accordingly.

[0015] It should be noted that references to "an embodiment," "embodiment," "example embodiment," "exemplary," etc., in the specification indicate that the described embodiment may include specific features, structures, or characteristics, but each embodiment may not necessarily include that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Additionally, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, implementing such a feature, structure, or characteristic in conjunction with other embodiments will be within the knowledge of those skilled in the art.

[0016] It should be understood that the wording or terminology used herein is for descriptive purposes and not restrictive, and that the terminology or terminology used herein should be interpreted by one or more persons skilled in the art based on the teachings herein.

[0017] In some embodiments, the terms “about” and “basic” can mean that the value of a given quantity varies within 5% of that value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of that value). These values ​​are merely examples and not limiting. The terms “about” and “basic” can refer to percentages of values ​​as interpreted by one or more persons skilled in the art based on the teachings herein.

[0018] The fin structures disclosed herein can be patterned using any suitable method. For example, the fin structures can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Dual-patterning or multi-patterning processes can combine photolithography and self-alignment processes, allowing patterns to be created with, for example, smaller spacing than that achievable using a single direct photolithography process. For example, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fin structure.

[0019] This disclosure provides an example method for addressing the challenge of forming continuous unlined contact structures and / or metal lines on conductive structures separated by insulating structures. These challenges may arise from the lower deposition selectivity of the conductive material for insulating surfaces compared to conductive surfaces, which can prevent substantially uniform deposition of the conductive material on both the conductive and insulating structures. The term "deposition selectivity" refers to the ratio of deposition rates on two different materials or surfaces under the same deposition conditions. Due to non-uniform deposition of the conductive material, discontinuous unlined contact structures and / or metal lines may form on the conductive structure, potentially degrading the electrical connection between the conductive structures.

[0020] In some embodiments, the example method includes forming unlined contact structures extending along the top surface of the gate structures of different FETs (e.g., finFET, GAA FET, or MOSFET) and the top surface of an insulating structure disposed between the gate structures. In some embodiments, the example method may further include a process of “cutting” the unlined contact structure into shorter portions to form individual contact structures on each gate structure. In other words, the process may remove portions of the unlined contact structure between the gate structures (e.g., portions of the unlined contact structure on the insulating structure) to form one or more isolation trenches (also referred to as “metal cuts”) that electrically isolate the remaining portions of the unlined contact structure from each other. This method of forming individual contact structures by cutting longer contact structures can reduce the manufacturing process complexity of forming smaller contact structures. Furthermore, this method can reduce structural and / or compositional inhomogeneities between the contact structures of different FETs in a semiconductor device, and thus improve device performance.

[0021] In some embodiments, an example method may include: forming a contact opening along the top surface of the gate structure of different FETs and the top surface of an insulating structure disposed between the gate structures; forming a seed layer on the top surfaces of the gate structure and the insulating structure within the contact opening; and selectively depositing a conductive material on the seed layer. A similar method may be used to form linerless metal lines along the top surface of vias and / or metal lines beneath an interconnect structure and the top surface of an insulating structure disposed between the vias and / or metal lines.

[0022] Figure 1A An isometric view of a semiconductor device 100 having FETs 102A-102B according to some embodiments is shown. Although the semiconductor device 100 is shown as having two FETs 102A-102B, the semiconductor device 100 may have any number of FETs. In some embodiments, FETs 102A-102B may represent n-type FETs 102A-102B (NFET 102A-102B) or p-type FETs 102A-102B (PFET 102A-102B). Unless otherwise stated, the discussion of FETs 102A-102B applies to both NFETs 102A-102B and PFETs 102A-102B. Figure 1B An isometric view of a semiconductor device 100 having contact structures 120 and 126A-126B according to some embodiments is shown. Figures 1C-1E The semiconductor device 100 is shown along Figure 1A-Figure 1B Cross-sectional views of lines AA, CC, and BB. Figures 1C-1E It shows that, for simplicity, Figure 1A-Figure 1B A cross-sectional view of the semiconductor device 100 with additional structures not shown is included. Unless otherwise stated, the discussion of the elements with the same icons for FETs 102A-102B applies to each other.

[0023] refer to Figures 1A-1EThe semiconductor device 100 may include: (i) a substrate 104; (ii) fin structures 106A-106B; (iii) gate structures 112A-113A disposed on the fin structure 106A; (iv) gate structures 112B-113B disposed on the fin structure 106B; (v) source / drain (S / D) regions 110A-110B disposed on portions of the fin structures 106A-106B not covered by the gate structures 112A-113A and 112B-113B; (vi) an S / D contact structure 120 disposed on the S / D regions 110A-110B; (vii) a gate contact structure 126A disposed on the gate structures 112A-112B; and (viii) a gate contact structure 126B disposed on the gate structures 113A-113B. Unless otherwise stated, the discussion of gate structures 112A-113A applies to gate structures 112B-113B respectively. Semiconductor device 100 may also include (i) gate spacer 114, (ii) shallow trench isolation (STI) region 116, (iii) etch stop layers (ESL) 117A-117B, and (iv) interlayer dielectric (ILD) layers 118A-118B. For simplicity, in Figure 1A-Figure 1B The portion of ILD layer 118A, STI region 116, and substrate 104 between FETs 102A and 102B is not shown. In some embodiments, gate spacer 114, STI region 116, ESL 117A-117B, and ILD layers 118A-118B may include insulating materials such as silicon oxide, silicon nitride (SiN), silicon carbonitride (SiCN), silicon carbonitride oxynitride (SiOCN), silicon germanium oxide, and other suitable insulating materials.

[0024] Semiconductor device 100 may be formed on substrate 104. Other FETs and / or structures (e.g., isolation structures) may be formed on substrate 104. Substrate 104 may be a semiconductor material, such as silicon, germanium (Ge), silicon-germanium (SiGe), silicon-on-insulator (SOI) structure, other suitable semiconductor materials, and combinations thereof. Furthermore, substrate 104 may be doped with p-type dopant (e.g., boron, indium, aluminum, or gallium) or n-type dopant (e.g., phosphorus or arsenic). In some embodiments, fin structures 106A-106B may comprise a material similar to substrate 104 and extend along the Z-axis.

[0025] refer to Figure 1C and Figure 1EFET 102A may include: (i) a stack of nanostructured channel regions 138A, surrounded by a gate structure 112A and disposed on a fin structure 106A; (ii) a stack of nanostructured channel regions 140A, surrounded by a gate structure 113A and disposed on a fin structure 106A; and (iii) an epitaxial S / D region 110A disposed between the stacks of nanostructured channel regions 138A and 140A. The term "nanostructured" refers to a structure, layer, and / or region having a horizontal dimension (e.g., along the X-axis and / or Y-axis) and / or a vertical dimension (e.g., along the Z-axis) of less than about 100 nm (e.g., about 90 nm, about 50 nm, about 10 nm, or other values ​​less than about 100 nm are within the scope of this disclosure). Similarly, references... Figures 1D-1E FET 102B may include: (i) a stack of nanostructured channel regions 138B, surrounded by gate structure 112B and disposed on fin structure 106B; (ii) a stack of nanostructured channel regions 140B, surrounded by gate structure 113B and disposed on fin structure 106B; and (iii) an epitaxial S / D region 110B disposed between the stacks of nanostructured channel regions 138B and 140B. Unless otherwise stated, the discussion of nanostructured channel regions 138A-140A applies to nanostructured channel regions 138B-140B respectively. In some embodiments, FETs 102A-102B may be finFETs and may have fin regions (not shown) instead of nanostructured channel regions 138A-140A and 138B-140B. These finFETs 102A-102B can have gate structures 112A-113A and 112B-113B disposed on the fin region.

[0026] refer to Figure 1C and Figure 1EThe nanostructured channel regions 138A-140A may include semiconductor materials similar to or different from the substrate 104, and may include semiconductor materials similar to or different from each other. In some embodiments, the nanostructured channel regions 138A-140A may include Si, silicon arsenide (SiAs), silicon phosphide (SiP), silicon carbide (SiC), silicon phosphide carbon (SiCP), SiGe, silicon germanium boron (SiGeB), germanium boron (GeB), silicon germanium tin boron (SiGeSnB), group III-V semiconductor compounds, or other suitable semiconductor materials. Although two nanostructured channel regions are shown in each stack, FETs 102A-102B may include any number of nanostructured channel regions in each stack. Although a rectangular cross-section of the nanostructured channel regions 138A-140A is shown, the nanostructured channel regions 138A-140A may have cross-sections of other geometries (e.g., circular, elliptical, triangular, or polygonal). In some embodiments, due to the different configurations of the gate structures 112A and 113A, the length L1 of the nanostructured channel region 138A may be shorter than the length L2 of the nanostructured channel region 140A, as will be described in detail below. In some embodiments, the ratio of lengths L1 to L2 (L1:L2) may be in the range of about 1:2 to about 1:5 to achieve different gate performance characteristics for the gate structures 112A and 113A.

[0027] For NFETs 102A-102B, the S / D regions 110A-110B may include epitaxially grown semiconductor materials (e.g., Si) and n-type dopants (e.g., phosphorus and other suitable n-type dopants). For PFETs 102A-102B, the S / D regions 110A-110B may include epitaxially grown semiconductor materials (e.g., Si and SiGe) and p-type dopants (e.g., boron and other suitable p-type dopants).

[0028] Gate structures 112A and 113A can be multilayer structures and can surround the nanostructured channel regions 138A and 140A. Therefore, gate structures 112A-112B can be called "gate full surround (GAA) structures" or "horizontal gate full surround (HGAA) structures". FET 102A can be called "GAA FET 102A". Figure 1C As shown, the gate portions of gate structures 112A and 113A surrounding the nanostructured channel regions 138A and 140A can be electrically isolated from the adjacent S / D region 110A via internal spacers 115. Figure 1CAs shown, the gate portions of gate structures 112A and 113A disposed on the stack of nanostructured channel regions 138A and 140A can be electrically isolated from the adjacent S / D region 110A by gate spacer 114. The internal spacer 115 and the gate spacer 114 may comprise insulating materials such as SiO2, SiN, SiCN, SiOCN, and other suitable insulating materials.

[0029] In some embodiments, the gate structure 112A may have a length GL1 shorter than the gate length GL2 of the gate structure 113A, and the ratio of lengths GL1 to GL2 (GL1:GL2) may be in the range of about 1:2 to about 1:5 to achieve different gate performance characteristics for the gate structures 112A and 113A. In some embodiments, the gate length GL1 may be less than about 30 nm (e.g., about 25 nm, about 20 nm, about 10 nm, and about 5 nm), and the gate length GL2 may be greater than about 30 nm (e.g., about 35 nm, about 50 nm, about 60 nm, and about 70 nm). Each of the gate structures 112A and 113A may include an interface oxide (IO) layer 132, a high-k (HK) gate dielectric layer 134 disposed on the IO layer 132, and a conductive layer 136 disposed on the HK gate dielectric layer 134. As used herein, the term "high-k (HK)" refers to a high dielectric constant. In the field of semiconductor device structure and manufacturing process, HK refers to a dielectric constant greater than that of SiO2 (e.g., greater than 3.9).

[0030] IO layer 132 may include silicon oxide (SiO2) and silicon germanium oxide (SiGeO) x or germanium oxide (GeO) xThe HK gate dielectric layer 134 may include a high-k dielectric material, such as hafnium oxide (HfO2), titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O3), hafnium silicate (HfSiO4), zirconium oxide (ZrO2), and zirconium silicate (ZrSiO2). The conductive layer 136 may be a multilayer structure. For simplicity, the different layers in the conductive layer 136 are not shown. Each conductive layer 136 may include a WFM layer disposed on the HK dielectric layer 134 and a gate metal filling layer on the WFM layer. In some embodiments, the WFM layer may include titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), tantalum aluminum (TaAl), tantalum aluminum carbide (TaAlC), Al-doped Ti, Al-doped TiN, Al-doped Ta, Al-doped TaN, other suitable aluminum-based materials, or combinations thereof. In some embodiments, the WFM layer may comprise a Ti-based or Ta-based nitride or alloy that is substantially Al-free (e.g., without Al), such as titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium-gold (Ti-Au) alloy, titanium-copper (Ti-Cu) alloy, tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum-gold (Ta-Au) alloy, tantalum copper (Ta-Cu), and combinations thereof. The gate metal filler layer may comprise a suitable conductive material, such as tungsten (W), Ti, silver (Ag), ruthenium (Ru), molybdenum (Mo), copper (Cu), cobalt (Co), Al, iridium (Ir), nickel (Ni), metal alloys, and combinations thereof.

[0031] In some embodiments, each S / D contact structure 120 may include: (i) a silicide layer 122 disposed within each S / D region 110A-110B; and (ii) a contact plug 124 disposed on the silicide layer 122. In some embodiments, for NFETs 102A-102B, the silicide layer 122 may include a metal or a metal silicide whose work function value is closer to the conduction band edge energy relative to the valence band edge energy of the material in the S / D regions 110A-110B. For example, the work function value of the metal or metal silicide may be less than 4.5 eV (e.g., about 3.5 eV to about 4.4 eV), which may be closer to the conduction band energy (e.g., 4.1 eV for Si) relative to the valence band energy (e.g., 5.2 eV for Si) of the Si-based material in the S / D regions 110A-110B. In some embodiments, for NFETs 102A-102B, the metal silicide of silicide layer 122 may include titanium silicide (Ti). x Si y ), tantalum silicide (Ta x Si y ), molybdenum silicide (Mo x Si y Zirconium silicide (Zr)x Si y ), Hafnium silicide (Hf) x Si y Scandium silicide (Sc) x Si y ), yttrium silicide (Y x Si y ), terbium silicide (Tb) x Si y ), Lutetium silicide (Lu) x Si y ), Erbium silicide (Er x Si y ), Ytterbium silicide (Yb x Si y Europium silicide (Eu) x Si y ), Thorium silicide (Th) x Si y Other suitable metal silicide materials, or combinations thereof.

[0032] In some embodiments, for PFETs 102A-102B, the silicide layer 122 may comprise a metal or a metal silicide whose work function value is closer to the valence band edge energy relative to the conduction band edge energy of the material in the S / D regions 110A-110B. For example, the work function value of the metal or metal silicide may be greater than about 4.5 eV (e.g., about 4.5 eV to about 5.5 eV), which may be closer to the valence band energy (e.g., about 5.2 eV for Si) relative to the conduction band energy (e.g., about 4.1 eV for Si) of the Si-based material in the S / D regions 110A-110B. In some embodiments, for PFETs 102A-102B, the metal silicide of the silicide layer 122 may comprise nickel silicide (Ni x Si y ), cobalt silicide (Co) x Si y ), manganese silicide (Mn) x Si y ), Tungsten silicide (W) x Si y ), iron silicide (Fe) x Si y Rhodium silicide (Rh) x Si y ), Palladium silicide (Pd) x Si y ), Ruthenium silicide (Ru) x Si y Platinum silicide (Pt) x Si y ), Iridium silicide (Ir) x Siy ), Osmium silicide (Os) x Si y Other suitable metal silicide materials, or combinations thereof.

[0033] The contact plug 124 may include a conductive material having a low resistivity (e.g., a resistivity of about 50 μΩ-cm, about 40 μΩ-cm, about 30 μΩ-cm, about 20 μΩ-cm, or about 10 μΩ-cm), such as cobalt (Co), tungsten (W), ruthenium (Ru), iridium (Ir), nickel (Ni), osmium (Os), rhodium (Rh), aluminum (Al), molybdenum (Mo), other suitable conductive materials having low resistivity, and combinations thereof.

[0034] refer to Figures 1B-1E Gate contact structure 126A can extend along the Y-axis and can be disposed on the portion of gate structures 112A-112B and ILD layer 118A disposed between gate structures 112A-112B. Gate contact structure 126B can extend along the Y-axis and can be disposed on the portion of gate structures 113A-113B and ILD layer 118A disposed between gate structures 113A-113B. In order to optimize the contact area between gate contact structures 126A-126B and gate structures 112A-112B and 113A-113B to obtain the desired device performance, the width (e.g., width W1, W2) formed by gate contact structure 126A on gate structures 112A-112B with a shorter gate length GL1 is larger than the width (e.g., width W3, W4) formed by gate contact structure 126B on gate structures 112A-112B with a longer gate length GL2. In some embodiments, for optimizing the contact area between gate contact structure 126A and gate structures 112A-112B, the ratio of the width W2 of gate contact structure 126A to the gate length GL1 (W2:GL1) can be in the range of about 1:3 to about 1:6. Similarly, for optimizing the contact area between gate contact structure 126B and gate structures 113A-113B, the ratio of the width W4 of gate contact structure 126B to the gate length GL2 (W4:GL2) can be in the range of about 1:3 to about 1:6.

[0035] The gate contact structures 126A-126B may include seed layers 128A-128B and conductive layers 130A-130B disposed on the seed layers 128A-128B. The gate contact structures 126A-126B are not lined along the sidewalls of the seed layers 128A-128B and / or along the sidewalls of the conductive layers 130A-130B, and therefore, the gate contact structures 126A-126B may be referred to as liner-free contact structures 126A-126B. The seed layers 128A-128B provide surfaces that facilitate the selective deposition of the conductive layers 130A-130B, which will be described in detail below. Without the seed layer 128A, the conductive layer 130A may be formed as a discontinuous layer on the gate structures 112A-112B, unlike... Figure 1E The discontinuity is shown as a continuous layer. This discontinuity may arise because the deposition selectivity of the conductive material of conductive layer 130A for the insulating surface of ILD layer 118A is lower than its deposition selectivity for the conductive surfaces of gate structures 112A-112B. This difference in deposition selectivity may prevent the conductive material from being deposited substantially uniformly on gate structures 112A-112B and on the portion of ILD layer 118A disposed between gate structures 112A-112B. Similarly, without the seed layer 128B, conductive layer 130B may be formed as a discontinuous layer on gate structures 113A-113B.

[0036] In some embodiments, each of seed layers 128A-128B may include a conductive material, such as a metal and a metal nitride. In some embodiments, the metal may include Ti, Ta, W, Ru, Co, other suitable metals, or combinations thereof. In some embodiments, the metal nitride may include titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), other suitable metal nitrides, or combinations thereof. In some embodiments, seed layers 128A-128B may include conductive materials that are similar to or different from each other. In some embodiments, each of conductive layers 130A-130B may include a conductive material, such as W, Co, Ru, Cu, Al, other suitable conductive materials, or combinations thereof. In some embodiments, conductive layers 130A-130B may include conductive materials that are similar to or different from each other.

[0037] The gate contact structure 126A may have a tapered shape, comprising a wider top portion 126Aa, a narrower bottom portion 126Ac, and a transition portion 126Ab (also referred to as the "shoulder portion 126Ab") located between the top portion 126Aa and the bottom portion 126Ac. The wider top portion 126Aa compared to the bottom portion 126Ac prevents the formation of voids within the conductive layer 130A during selective deposition, as will be described in detail below. The sidewalls of the top portion 126Aa and the bottom portion 126Ac may be substantially vertical, and the sidewalls of the transition portion 126Ab may be curved or inclined. The top portion 126Aa may have a height H1 ranging from about 30 nm to about 40 nm, the bottom portion 126Ac may have a height H3 ranging from about 10 nm to about 30 nm, and the transition portion 126Ab may have a height H2 ranging from about 5 nm to about 10 nm. The height ratio of H3 to H1 (H3:H1) can be in the range of about 1:1 to about 1:2. The total height H123 of the gate contact structure 126A can be in the range of about 50 nm to about 80 nm.

[0038] The top portion 126Aa may have a width W1 of less than about 20 nm (e.g., in the range of about 10 nm to about 15 nm), and the bottom portion 126Ac may have a width W2 of less than about 15 nm (e.g., in the range of about 2 nm to about 10 nm). The ratio of width W2 to W1 (W2:W1) may be in the range of about 1:1.5 to about 1:3. The ratio of width W1 to gate length GL1 (W1:GL1) may be in the range of about 1:1.5 to about 1:3, and the ratio of width W2 to gate length GL1 (W2:GL1) may be in the range of about 1:3 to about 1:6. The aspect ratio (H123:W1) between the height H123 and width W1 of the gate contact structure 126A may be in the range of about 5:1 to about 10:1. In addition to providing an optimized contact area between the gate contact structure 126A and the gate structures 112A-112B, the aforementioned size range and proportions of the gate contact structure 126A can prevent the formation of voids within the conductive layer 130A during the selective deposition of the conductive layer 130A.

[0039] In some embodiments, the sidewalls of the transition portion 126Ab may form an angle A with the X-axis, and the angle A ranges between approximately 45 degrees and 90 degrees, to minimize material deposition along the sidewalls and facilitate etching of the deposited material along the sidewalls during the formation of the seed layer 128A, as will be described in detail below. In some embodiments, to adequately deposit the conductive layer 130A on the seed layer 128A, the thickness T1 of the seed layer 128A may range from approximately 2 nm to approximately 4 nm, depending on the width W2. The ratio of thickness T1 to width W2 (T1:W2) may range from approximately 1:1 to approximately 1:5. In some embodiments, the thickness of the seed layer 128A may vary along the Y-axis, such as... Figure 1E As shown. For example, as Figure 1E As shown, the seed layer 128A can have different thicknesses T1, T3, and T4 along the Y-axis on the gate structure 112A, gate spacer 114, and gate structure 112B, respectively. Similarly, due to the non-coplanarity between the top surfaces of the gate structures 112A-112B, gate spacer 114, ESL 117A, and ILD layer 118A, the thickness of the conductive layer 130A can vary along the Y-axis, such as... Figure 1E As shown. The non-coplanarity of these top surfaces is likely a result of the etching process performed during the formation of the gate contact structure 126A, which will be described in detail below.

[0040] Similar to gate contact structure 126A, gate contact structure 126B may have a tapered shape having a wider top portion 126Ba, a narrower bottom portion 126Bc, and a transition portion 126Bb (also referred to as "shoulder portion 126Bb") located between the top portion 126Ba and the bottom portion 126Bc. The sidewalls of the top portion 126Ba and the bottom portion 126Bc may be substantially vertical, and the sidewalls of the transition portion 126Bb may be curved or inclined. Unless otherwise stated, the discussion of heights H1, H2, H3, and H123 applies to heights H4, H5, H6, and H456 of gate contact structure 126B, respectively. The top portion 126Ba may have a width W3 greater than about 20 nm (e.g., in the range of about 30 nm to about 50 nm), and the bottom portion 126Bc may have a width W4 greater than about 20 nm (e.g., in the range of about 25 nm to about 40 nm). The ratio of width W4 to W3 (W4:W3) may be in the range of about 1:1.5 to about 1:3. The ratio of width W3 to gate length GL2 (W3:GL2) may be in the range of about 1:1.5 to about 1:3, and the ratio of width W4 to gate length GL2 (W4:GL2) may be in the range of about 1:3 to about 1:6. The aspect ratio (H456:W3) between the height H456 and width W3 of the gate contact structure 126B may be in the range of about 5:1 to about 10:1. In addition to providing an optimized contact area between the gate contact structure 126B and the gate structures 113A-113B, the aforementioned size range and proportions of the gate contact structure 126B can prevent the formation of voids within the conductive layer 130B during the selective deposition of the conductive layer 130B.

[0041] In some embodiments, the sidewalls of the transition portion 126Bb may form an angle B with the X-axis, and the angle B ranges between approximately 45 degrees and 90 degrees, to minimize material deposition along the sidewalls and facilitate etching of the deposited material along the sidewalls during the formation of the seed layer 128B, as will be described in detail below. In some embodiments, to adequately deposit the conductive layer 130B on the seed layer 128B, the thickness T2 of the seed layer 128B may range from approximately 4 nm to approximately 6 nm, which may depend on the width W4. The ratio of thickness T2 to width W4 (T2:W4) may range from approximately 1:5 to approximately 1:10. In some embodiments, the ratio of thickness T1 to T2 (T1:T2) may range from approximately 1:2 to approximately 1:3.

[0042] refer to Figure 1B and Figure 1EIn some embodiments, the semiconductor device 100 may include an isolation structure 131 (also referred to as "metal cutout 131") located on the ILD layer 118A to cut the gate contact structures 126A-126B into shorter portions that are electrically isolated from each other. The isolation structure 131 may include a dielectric material, such as an oxide material, a nitride material, or a combination thereof. In some embodiments, the isolation structure 131 may have a height H7 that is substantially equal to or greater than the heights H123 and H456 of the gate contact structures 126A and 126B. The height H123 to H7 ratio (H123:H7) may be in the range of about 1:1 to about 1:2 for electrical isolation between the shorter portions of the gate contact structure 126A.

[0043] In some embodiments, reference Figure 1E The semiconductor device 100 may include a dielectric region 119 on the ILD layer 118A. The material of the dielectric region 119 may be different from the material of the ILD layer 118A, and may have a higher density than the material of the ILD layer 118A. In some embodiments, reference... Figure 1E The ILD layers 118A and ESL 117A can extend below the gate structures 112A-112B, as shown by the dashed lines.

[0044] Figure 2 This is a flowchart of an example method 200 for manufacturing a semiconductor device 100 according to some embodiments. For illustrative purposes, reference will be made to... Figure 3 and Figures 4A-18B The example manufacturing process for manufacturing semiconductor device 100 is described below. Figure 2 The operation shown. Figure 3 These are isometric views of the semiconductor device 100 at various manufacturing stages according to various embodiments. Figures 4A-18A It is along the various manufacturing stages of the semiconductor device 100 according to various embodiments. Figure 1B The cross-sectional view of line AA, and Figures 4B-18B It is along the various manufacturing stages of the semiconductor device 100 according to various embodiments. Figure 1B A cross-sectional view of line BB. The operations of method 200 may be performed in different orders or not at all, depending on the specific application. It should be noted that method 200 may not produce a complete semiconductor device 100. Therefore, it should be understood that additional processes may be provided before, during, and after method 200, and some other processes may only be briefly described herein. The above describes a process with... Figures 1A-1E The same icon for the components in Figure 3 and Figures 4A-18B The components in.

[0045] In operation 205, a superlattice structure is formed on the fin structure of the FET, and a polycrystalline silicon structure is formed on the superlattice structure. For example, as... Figure 3 As shown, superlattice structures 341A and 341B are formed on fin structures 106A and 106B, respectively. Polycrystalline silicon structures 312A-313A are formed on superlattice structure 341A, and polycrystalline silicon structures 312B-313B are formed on superlattice structure 341B. Superlattice structure 341A may include nanostructured layers 342A and 344A arranged in an alternating configuration. Similarly, superlattice structure 341B may include nanostructured layers 342B and 344B arranged in an alternating configuration. In some embodiments, nanostructured layers 342A-342B comprise materials similar to each other, and nanostructured layers 344A-344B comprise materials similar to each other. Nanostructured layers 344A and 344B are also referred to as sacrificial layers 344A and 344B.

[0046] refer to Figure 2 In operation 210, an S / D region is formed on the fin structure, and an isolation structure is formed between the polysilicon structures. For example, as referenced... Figures 4A-5B As described, an S / D region 110A is formed on the fin structure 106A, and an ILD layer 118A is formed between the polysilicon structures 312A-313A. The ILD layer 118A can serve as an isolation structure between the polysilicon structures 312A-313A. The formation of the S / D region 110A may include the following sequential operations: (i) forming an S / D opening 410 through the superlattice structure 341A on the portion of the fin structure 106A not below the polysilicon structures 312A-313A, as shown. Figure 4A As shown; and (ii) epitaxial growth of semiconductor material inside and outside the S / D opening 410, such as Figure 5A As shown. In some embodiments, an internal spacer 115 may be formed between operations (i) and (ii) of the formation process of the epitaxial S / D region 110A, as... Figure 5A As shown. After forming the S / D region 110A, an ESL 117A and an ILD layer 118A can be formed on the S / D region 110A to form... Figures 5A-5B The structure. In some embodiments, the isolation structure 119 may be formed after the formation of the ILD layer 118A (in Figure 5B (as shown in the image).

[0047] refer to Figure 2 In operation 215, the polysilicon structure and sacrificial layer of the superlattice structure are replaced with a gate structure. For example, as referenced... Figures 6A-7B As described, gate structures 112A, 112B, 113A, and 113B (in) Figures 6A-7B(Not shown in the image) Replace polysilicon structures 312A, 312B, 313A, and 313B (in...) Figures 6A-7B (not shown in the image) and sacrificial layers 344A and 344B. The gate replacement process may include the following sequential operations: (i) from Figures 5A-5B The polysilicon structures 312A, 312B, and 313A, as well as the sacrificial layers 344A and 344B, are removed to form gate openings 612A, 612B, and 613A, as shown below. Figures 6A-6B As shown; (ii) an IO oxide layer 132 is formed within gate openings 612A, 612B, and 613A, as follows Figures 7A-7B As shown; (iii) An HK dielectric layer 134 is formed on the IO oxide layer 132 within the gate openings 612A, 612B, and 613A, as follows: Figures 7A-7B As shown; and (iv) a conductive layer 136 is formed on the HK dielectric layer 134 within the gate openings 612A, 612B, and 613A, as... Figures 7A-7B As shown. In some embodiments, together with polysilicon structures 312A, 312B, and 313A, the portion of STI region 116 below polysilicon structures 312A, 312B, and 313A is etched, as shown. Figure 6B As shown. A portion of STI region 116 was etched to ensure that no residual material from polysilicon structures 312A, 312B, and 313A remained in gate openings 612A-612B (in...). Figure 6B At the bottom corners and / or edges of 613A-613B (not shown). In some embodiments, gate opening 612A may extend a distance D1-D2 below the top surface 106At of fin structure 106A, and gate opening 612B may extend a distance D3-D4 below the top surface 106Bt of fin structure 106B, as shown in the figure. Figure 6B As shown. In some embodiments, distances D1-D4 may be substantially equal to or different from each other. In some embodiments, distances D1-D4 may be in the range of about 1 nm to about 10 nm. After forming the gate structure, ESL 117B, ILD layer 118B, and S / D contact structure 120 may be formed, as shown. Figures 7A-7B As shown.

[0048] refer to Figure 2 In operation 220, trench openings extending on the gate structure and the isolation structure are formed. For example, as referenced... Figures 8A-10BAs described, trench openings 1026A are formed on gate structures 112A-112B and ILD layer 118A (or on isolation structure 119, if present), and trench openings 1026B are formed on gate structures 113A-113B and ILD layer 118A (or on isolation structure 119, if present). The formation of trench openings 1026A-1026B may include the following sequential operations: (i) forming trench openings 1026A-1026B by etching ILD layer 118B, ESL 117B, and conductive layer 136, as... Figures 8A-8B As shown; (ii) a masking layer 946A-946B is formed within the trench openings 826A-826B, as shown. Figures 9A-9B As shown; (iii) Laterally etching the exposed ILD layer 118B in the top portions 126Aa-126Ba of the trench openings 826A-826B to form Figures 10A-10B The structure; and (iv) removal of masking layers 946A-946B.

[0049] In some embodiments, trench openings 826A-826B can be formed using a dry etching process, and the width W2-W4 of the trench openings 826A-826B defines the width W2-W4 of the bottom portions 126Ac-126Bc of the gate contact structures 126A-126B formed in subsequent processing. Due to the different etching rates of the different materials of the gate structures 112A-112B, gate spacer 114, ESL 117A, and ILD layer 118A, the bottom surface 826Ab of the trench opening 826A can be non-uniform, such as... Figure 8B As shown. In some embodiments, the vertical distance D5 between the highest point (“peak”) and the lowest point (“valley”) on the bottom surface 826Ab can be in the range of about 0.5 nm to about 2 nm. Figure 8B The bottom surface 826Ab of the groove opening 826A is shown, but for simplicity, the sidewalls of the groove opening 826A are not shown. The groove opening 826B may have a bottom surface similar to the bottom surface 826Ab.

[0050] In some embodiments, while the top portions of the trench openings 826A-826B are laterally etched to form the wider top portions 126Aa-126Ba of the trench openings 1026A-1026B, the masking layers 946A-946B protect the shape and size of the bottom portions of the trench openings 826A-826B, such as... Figure 10AAs shown. In some embodiments, lateral etching can be performed by wet etching, plasma etching, or other suitable etching methods for lateral etching. The widths W1-W3 of the trench openings 1026A-1026B define the widths W1-W3 of the top portions 126Aa-126Ba of the gate contact structures 126A-126B formed in subsequent processing.

[0051] refer to Figure 2 In operation 225, a seed layer is formed in the trench opening. For example, as referenced... Figures 11A-13B As described, seed layers 128A-128B are formed in trench openings 1026A-1026B. The formation of seed layers 128A-128B may include the following sequential operations: (i) after removing masking layers 946A-946B, in... Figures 10A-10B The seed layer material 1128 is deposited on the structure to form Figures 11A-11B (ii) Etching portions of the seed layer material 1128 from the sidewalls of trench openings 1026A-1026B, such as Figure 12A As shown; (iii) fill the trench openings 1026A-1026B with masking layers 1248A-1248B to form Figures 12A-12B The structure; (iv) the structure of Figures 12A-12B The structure undergoes an etching process to remove portions of the seed layer material 1128 on the ILD layer 118B and the S / D contact structure 120, such as... Figure 13A As shown; and (v) removing masking layers 1248A-1248B to form Figures 13A-13B The structure.

[0052] The parameters of the deposition process used to deposit the seed layer material 1128 are controlled so that the portion of the seed layer material 1128 formed at the bottom of the trench openings 1026A-1026B is thicker than the portion of the seed layer material 1128 formed along the sidewalls of the trench openings 1026A-1026B. Figure 11AAs shown. The thinner portion of the sidewalls along the trench openings 1026A-1026B facilitates selective etching of the sidewall portion of the seed layer material 1128 without significantly etching the thicker portion of the seed layer material 1128 at the bottom of the trench openings 1026A-1026B. The portion of the seed layer material 1128 at the bottom of the trench openings 1026A-1026B may have a thickness T1*-T2*, which is greater than the thickness T5-T10 of the portion of the seed layer material 1128 along the sidewalls of the trench openings 1026A-1026B. In some embodiments, the thicknesses T5-T10 may be less than about 1.5 nm (e.g., about 0.1 nm, about 0.5 nm, about 0.7 nm, and about 1 nm). In some embodiments, thicknesses T6 and T9 may be thicker than thicknesses T5, T7, T8, and T10 due to the curved or inclined sidewalls of the transition portions. In some embodiments, during the etching of a portion of the seed layer material 1128 from the sidewalls of the trench openings 1026A-1026B, a small portion of the seed layer material 1128 at the bottom of the trench openings 1026A-1026B may be etched, and the thickness T1*-T3* may be reduced to a thickness T1-T3, such as Figures 12A-12B As shown.

[0053] In some embodiments, a physical vapor deposition (PVD) process utilizing plasma can be used to deposit the seed layer material 1128. To achieve a thicker bottom portion of the seed layer material 1128 (compared to the sidewall portion of the seed layer material 1128), a high voltage greater than about 60 mTorr (e.g., in the range of about 61 mTorr to about 150 mTorr) can be maintained in the deposition chamber. RF plasma with a frequency between about 14 MHz and 60 MHz can be used to ionize the atoms of the seed layer material 1128 from the target, and a bias voltage can be applied to the substrate 104 to attract and guide the ionized atoms toward the bottom of the trench openings 1026A-1026B.

[0054] refer to Figure 2 In operation 230, a conductive layer is formed on the seed layer using a bottom-up deposition process to fill the trench openings. For example, as referenced... Figures 14A-18B As described, conductive layers 130A-130B can be formed on seed layers 128A-128B in trench openings 1026A-1026B. The formation of conductive layers 130A-130B may include the following sequential operations: (i) depositing conductive layers 1430A-1430B on seed layers 128A-128B to partially fill trench openings 1026A-1026B to a height H9 of approximately 10 nm to approximately 15 nm, as... Figures 14A-14B As shown; (ii) removing portions of conductive layers 1430A-1430B along the sidewalls of trench openings 1026A-1026B to form Figures 15A-15B (iii) Depositing conductive layers 1630A-1630B on conductive layers 1530A-1530B to fill trench openings 1026A-1026B, such as Figures 16A-16B As shown; (iv) in Figures 16A-16B A conductive layer 1750 is deposited on the structure to form Figures 17A-17B The structure; (v) for Figures 17A-17B The structure is subjected to a chemical mechanical polishing (CMP) process to form Figures 18A-18B The structure.

[0055] In some embodiments, the deposition of conductive layers 1430A-1430B and 1630A-1630B can be performed using an atomic layer deposition (ALD) process utilizing a metal precursor (e.g., a metal halide). This ALD process exhibits higher selectivity for depositing the conductive material of the seed layers 128A-128B than for depositing the insulating material of the ILD layer 118B along the sidewalls of the trench openings 1026A-1026B. In some embodiments, conductive layers 1430A-1430B and 1630A-1630B may have similar or different materials from each other.

[0056] In some embodiments, after the formation of conductive layers 130A-130B, region 1852 (in Figure 18B (As shown in the diagram) can be etched and replaced with isolation structure 131, such as Figure 1E As shown.

[0057] This disclosure provides an example method for addressing the challenges of forming continuous unlined contact structures (e.g., contact structures 126A-126B) on conductive structures (e.g., gate structures 112A-112B) separated by insulating structures (e.g., ILD layers 118A). These challenges may arise from the lower deposition selectivity of the conductive material for insulating surfaces compared to conductive surfaces, which can prevent substantially uniform deposition of the conductive material on both the conductive and insulating structures. Due to the non-uniform deposition of the conductive material, discontinuous unlined contact structures and / or metal lines may form on the conductive structures, potentially degrading the electrical connections between the conductive structures.

[0058] In some embodiments, the example method (e.g., method 200) includes forming linerless contact structures extending along the top surface of the gate structures of different FETs (e.g., FETs 102A-102B) and the top surface of an insulating structure (e.g., ILD layer 118A) disposed between the gate structures. In some embodiments, the example method may further include a process of “cutting” the linerless contact structures into shorter portions to form individual contact structures on each gate structure. In other words, the process may remove portions of the linerless contact structures between the gate structures (e.g., region 1852) to form one or more isolation trenches (e.g., isolation structure 131) that electrically isolate the remaining portions of the linerless contact structures from each other. This method of forming individual contact structures by cutting longer contact structures can reduce the manufacturing process complexity of forming smaller contact structures. Furthermore, this method can reduce structural and / or compositional inhomogeneities between the contact structures of different FETs in a semiconductor device, and thus improve device performance.

[0059] In some embodiments, a method includes: forming a first source / drain (S / D) region and a second S / D region on a first fin structure and a second fin structure, respectively; forming a first dielectric layer between the first S / D region and the second S / D region; forming a first gate all-around (GAA) structure and a second GAA structure on the first fin structure and the second fin structure, respectively; forming a second dielectric layer on the first GAA structure, the second GAA structure, and the first dielectric layer; forming a tapered trench opening in the second dielectric layer and on the first GAA structure, the second GAA structure, and the first dielectric layer; selectively forming a seed layer on the top surface of the first GAA structure, the second GAA structure, and the first dielectric layer exposed in the tapered trench opening; and selectively depositing a conductive layer on the seed layer to fill the tapered trench opening. The first GAA structure and the second GAA structure are electrically isolated through the first dielectric layer.

[0060] In some embodiments, a method includes: forming a first source / drain (S / D) region and a second S / D region on a first fin structure and a second fin structure, respectively; forming a first dielectric layer between the first S / D region and the second S / D region; forming a first gate structure and a second gate structure on the first fin structure and the second fin structure, respectively; forming a second dielectric layer on the first gate structure, the second gate structure, and the first dielectric layer; forming a linerless contact structure having a seed layer and a conductive layer in the second dielectric layer and on the first gate structure, the second gate structure, and the first dielectric layer; and forming an isolation structure in the linerless contact structure. The first gate structure and the second gate structure are electrically isolated through the first dielectric layer.

[0061] In some embodiments, a semiconductor device includes: a substrate; a first source / drain (S / D) region and a second S / D region, respectively disposed on a first fin structure and a second fin structure; a first dielectric layer disposed between the first S / D region and the second S / D region; a first gate structure and a second gate structure, respectively disposed on the first fin structure and the second fin structure; a second dielectric layer disposed on the first gate structure, the second gate structure, and the first dielectric layer; a linerless contact structure having a seed layer and a conductive layer, the linerless contact structure being in the second dielectric layer and on the first gate structure, the second gate structure, and the first dielectric layer; and an isolation structure disposed in the linerless contact structure. The first gate structure and the second gate structure are electrically isolated through the first dielectric layer.

[0062] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0063] Example

[0064] Example 1. A method for forming a semiconductor device, comprising: forming a first source / drain (S / D) region and a second S / D region on a first fin structure and a second fin structure, respectively; forming a first dielectric layer between the first S / D region and the second S / D region; forming a first gate all-around (GAA) structure and a second GAA structure on the first fin structure and the second fin structure, respectively, wherein the first GAA structure and the second GAA structure are electrically isolated by the first dielectric layer; forming a second dielectric layer on the first GAA structure, the second GAA structure, and the first dielectric layer; forming a tapered trench opening in the second dielectric layer and on the first GAA structure, the second GAA structure, and the first dielectric layer; selectively forming a seed layer on the top surface of the first GAA structure, the second GAA structure, and the first dielectric layer exposed in the tapered trench opening; and selectively depositing a conductive layer on the seed layer to fill the tapered trench opening.

[0065] Example 2. According to the method of Example 1, wherein forming the tapered groove opening comprises: forming a groove opening including a top portion and a bottom portion having substantially vertical sidewalls and a transition portion having inclined sidewalls, wherein the top portion is wider than the bottom portion.

[0066] Example 3. The method according to Example 1, wherein forming the tapered trench opening comprises: forming a trench opening having a first width in the second dielectric layer; depositing a masking layer on the bottom portion of the trench opening having the first width to partially fill the trench opening; and performing lateral etching on a portion of the second dielectric layer exposed in the top portion of the trench opening above the masking layer to form a second width of the top portion greater than the first width of the bottom portion.

[0067] Example 4. The method according to Example 1, wherein selectively forming the seed layer comprises: depositing a seed layer material in the tapered trench opening, wherein a first portion of the seed layer material is deposited along the sidewall of the tapered trench opening, and a second portion of the seed layer material is deposited on the first GAA structure and the second GAA structure and the first dielectric layer; and selectively etching the first portion of the seed layer material.

[0068] Example 5. The method according to Example 1, wherein selectively forming the seed layer comprises: depositing a seed layer material in the tapered trench opening and on the second dielectric layer; selectively etching a first portion of the seed layer material along the sidewall of the tapered trench opening; filling the tapered trench opening with a masking layer; and etching a second portion of the seed layer material on the second dielectric layer.

[0069] Example 6. The method according to Example 1, wherein selectively depositing the conductive layer comprises: depositing a first conductive layer on the seed layer using a first deposition process with a precursor having a metal halide; etching a portion of the first conductive layer along the sidewall of the tapered trench opening; and depositing a second conductive layer on the first conductive layer using the first deposition process.

[0070] Example 7. The method according to Example 1, wherein forming the tapered groove opening comprises: forming a groove opening comprising a bottom portion having a first width and a top portion having a second width, wherein the ratio of the first width to the second width is in the range of about 1:1.5 to about 1:3.

[0071] Example 8. The method according to Example 1, wherein forming the tapered groove opening comprises: forming a groove opening comprising a bottom portion having a first height and a top portion having a second height, wherein the ratio of the first height to the second height is in the range of about 1:1 to about 1:2.

[0072] Example 9. The method according to Example 1, wherein forming the tapered groove opening comprises: forming a groove opening with an aspect ratio in the range of about 5:1 to about 10:1.

[0073] Example 10. The method according to Example 1, wherein forming the tapered trench opening comprises: forming a trench opening including a bottom portion having a first width and a top portion having a second width, wherein the ratio of the first width to the gate length of the first GAA structure is in the range of 1:3 to about 1:6, and wherein the ratio of the second width to the gate length of the first GAA structure is in the range of 1:1.5 to about 1:3.

[0074] Example 11. A method for forming a semiconductor device, comprising: forming a first source / drain (S / D) region and a second S / D region on a first fin structure and a second fin structure, respectively; forming a first dielectric layer between the first S / D region and the second S / D region; forming a first gate structure and a second gate structure on the first fin structure and the second fin structure, respectively, wherein the first gate structure and the second gate structure are electrically isolated by the first dielectric layer; forming a second dielectric layer on the first gate structure, the second gate structure, and the first dielectric layer; forming a linerless contact structure having a seed layer and a conductive layer in the second dielectric layer and on the first gate structure, the second gate structure, and the first dielectric layer; and forming an isolation structure in the linerless contact structure.

[0075] Example 12. The method according to Example 11, wherein forming the linerless contact structure includes: forming a tapered trench opening in the second dielectric layer and on the first gate structure, the second gate structure, and the first dielectric layer; selectively forming the seed layer on the top surface of the first gate structure, the second gate structure, and the first dielectric layer exposed in the tapered trench opening; and selectively depositing the conductive layer on the seed layer to fill the tapered trench opening.

[0076] Example 13. The method according to Example 11, wherein forming the isolation structure includes: replacing a portion of the unlined contact structure on the first dielectric layer with an insulating layer.

[0077] Example 14. The method according to Example 11, wherein forming the linerless contact structure comprises: forming a tapered trench opening in the second dielectric layer and on the first gate structure, the second gate structure, and the first dielectric layer; depositing a seed layer material in the tapered trench opening, the seed layer material having a first portion along the sidewall of the tapered trench opening and a second portion located on the first gate structure, the second gate structure, and the first dielectric layer; and selectively etching the first portion of the seed layer material.

[0078] Example 15. The method according to Example 11, wherein forming the linerless contact structure comprises: forming a tapered trench opening in the second dielectric layer and on the first gate structure, the second gate structure, and the first dielectric layer; selectively forming a seed layer on the top surface of the first gate structure, the second gate structure, and the first dielectric layer exposed in the tapered trench opening; depositing a first conductive layer on the seed layer using a first deposition process with a precursor having a metal halide; etching a portion of the first conductive layer along the sidewall of the tapered trench opening; and depositing a second conductive layer on the first conductive layer using the first deposition process.

[0079] Example 16. The method according to Example 11, wherein forming the unlined contact structure includes: forming a groove opening including a top portion and a bottom portion having substantially vertical sidewalls and a transition portion having inclined sidewalls, wherein the top portion is wider than the bottom portion.

[0080] Example 17. A semiconductor device, comprising: a substrate; a first source / drain (S / D) region and a second S / D region, respectively disposed on a first fin structure and a second fin structure; a first dielectric layer disposed between the first S / D region and the second S / D region; a first gate structure and a second gate structure, respectively disposed on the first fin structure and the second fin structure, wherein the first gate structure and the second gate structure are electrically isolated by the first dielectric layer; a second dielectric layer disposed on the first gate structure, the second gate structure, and the first dielectric layer; a linerless contact structure having a seed layer and a conductive layer, the linerless contact structure being in the second dielectric layer and on the first gate structure, the second gate structure, and the first dielectric layer; and an isolation structure disposed in the linerless contact structure.

[0081] Example 18. The semiconductor device according to Example 17, wherein the linerless contact structure includes a top portion and a bottom portion having substantially vertical sidewalls and a transition portion having sloping sidewalls, wherein the top portion is wider than the bottom portion.

[0082] Example 19. The semiconductor device according to Example 17, wherein the linerless contact structure includes a bottom portion having a first width and a top portion having a second width, wherein the ratio of the first width to the second width is in the range of about 1:1.5 to about 1:3.

[0083] Example 20. The semiconductor device according to Example 17, wherein the linerless contact structure includes a bottom portion having a first height and a top portion having a second height, wherein the ratio of the first height to the second height is in the range of about 1:1 to about 1:2.

Claims

1. A method for forming a semiconductor device, comprising: A first source / drain S / D region and a second source / drain S / D region are formed on the first fin structure and the second fin structure, respectively; A first dielectric layer is formed between the first source / drain S / D region and the second source / drain S / D region; A first gate-around-all-GAA structure and a second gate-around-all-GAA structure are formed on the first fin structure and the second fin structure, respectively, wherein the first gate-around-all-GAA structure and the second gate-around-all-GAA structure are electrically isolated by the first dielectric layer. A second dielectric layer is formed on the first gate-around-all-GAA structure, the second gate-around-all-GAA structure, and the first dielectric layer. A tapered trench opening is formed in the second dielectric layer and on the first gate all-around GAA structure, the second gate all-around GAA structure and the first dielectric layer. Seed layers are selectively formed on the top surfaces of the first gate-around-all-GAA structure, the second gate-around-all-GAA structure, and the first dielectric layer exposed in the tapered trench opening. as well as A conductive layer is selectively deposited on the seed layer to fill the tapered trench opening.

2. The method according to claim 1, wherein, Forming the tapered groove opening includes: forming a groove opening comprising a top portion and a bottom portion having substantially vertical sidewalls and a transition portion having inclined sidewalls, wherein the top portion is wider than the bottom portion.

3. The method according to claim 1, wherein, Forming the tapered groove opening includes: A trench opening with a first width is formed in the second dielectric layer; A masking layer is deposited at the bottom portion of the trench opening having the first width to partially fill the trench opening; and Lateral etching is performed on a portion of the second dielectric layer exposed in the top portion above the masking layer in the trench opening to form a second width of the top portion that is greater than the first width of the bottom portion.

4. The method according to claim 1, wherein, Selectively forming the seed layer includes: Seed layer material is deposited in the tapered trench opening, wherein a first portion of the seed layer material is deposited along the sidewall of the tapered trench opening, and a second portion of the seed layer material is deposited on the first gate all-around GAA structure, the second gate all-around GAA structure, and the first dielectric layer; and The first portion of the seed layer material is selectively etched.

5. The method according to claim 1, wherein, Selectively forming the seed layer includes: Seed layer material is deposited in the tapered trench opening and on the second dielectric layer; Selectively etch a first portion of the seed layer material along the sidewall of the tapered trench opening; Fill the tapered trench opening with a masking layer; and Etch a second portion of the seed layer material on the second dielectric layer.

6. The method according to claim 1, wherein, Selectively depositing the conductive layer includes: A first conductive layer is deposited on the seed layer using a first deposition process with a precursor containing a metal halide. Etching a portion of the first conductive layer along the sidewall of the tapered trench opening; and A second conductive layer is deposited on the first conductive layer using the first deposition process.

7. The method according to claim 1, wherein, Forming the tapered groove opening includes: forming a groove opening comprising a bottom portion having a first width and a top portion having a second width, wherein the ratio of the first width to the second width is in the range of 1:1.5 to 1:

3.

8. The method according to claim 1, wherein, Forming the tapered groove opening includes: forming a groove opening comprising a bottom portion having a first height and a top portion having a second height, wherein the ratio of the first height to the second height is in the range of 1:1 to 1:

2.

9. The method according to claim 1, wherein, Forming the tapered groove opening includes forming a groove opening with an aspect ratio in the range of 5:1 to 10:

1.

10. The method according to claim 1, wherein, Forming the tapered trench opening includes: forming a trench opening comprising a bottom portion having a first width and a top portion having a second width, wherein the ratio of the first width to the gate length of the first gate-around-the-GAA structure is in the range of 1:3 to 1:6, and wherein the ratio of the second width to the gate length of the first gate-around-the-GAA structure is in the range of 1:1.5 to 1:

3.

11. A method for forming a semiconductor device, comprising: A first source / drain S / D region and a second source / drain S / D region are formed on the first fin structure and the second fin structure, respectively; A first dielectric layer is formed between the first source / drain S / D region and the second source / drain S / D region; A first gate structure and a second gate structure are formed on the first fin structure and the second fin structure, respectively, wherein the first gate structure and the second gate structure are electrically isolated by the first dielectric layer; A second dielectric layer is formed on the first gate structure, the second gate structure, and the first dielectric layer; A linerless contact structure having a seed layer and a conductive layer is formed in the second dielectric layer and on the first gate structure, the second gate structure, and the first dielectric layer; and An isolation structure is formed in the unlined contact structure.

12. The method according to claim 11, wherein, Forming the unlined contact structure includes: A tapered trench opening is formed in the second dielectric layer and on the first gate structure, the second gate structure, and the first dielectric layer. The seed layer is selectively formed on the top surfaces exposed in the tapered trench opening of the first gate structure, the second gate structure, and the first dielectric layer; and The conductive layer is selectively deposited on the seed layer to fill the tapered trench opening.

13. The method according to claim 11, wherein, Forming the isolation structure includes replacing a portion of the unlined contact structure on the first dielectric layer with an insulating layer.

14. The method according to claim 11, wherein, Forming the unlined contact structure includes: A tapered trench opening is formed in the second dielectric layer and on the first gate structure, the second gate structure, and the first dielectric layer. Seed layer material is deposited in the tapered trench opening, the seed layer material having a first portion along the sidewall of the tapered trench opening and a second portion located on the first gate structure, the second gate structure, and the first dielectric layer; and The first portion of the seed layer material is selectively etched.

15. The method according to claim 11, wherein, Forming the unlined contact structure includes: A tapered trench opening is formed in the second dielectric layer and on the first gate structure, the second gate structure, and the first dielectric layer. Seed layers are selectively formed on the top surfaces exposed in the tapered trench openings of the first gate structure, the second gate structure, and the first dielectric layer. A first conductive layer is deposited on the seed layer using a first deposition process with a precursor containing a metal halide. Etching a portion of the first conductive layer along the sidewall of the tapered trench opening; and A second conductive layer is deposited on the first conductive layer using the first deposition process.

16. The method according to claim 11, wherein, Forming the unlined contact structure includes forming a groove opening comprising a top portion and a bottom portion having substantially vertical sidewalls and a transition portion having sloping sidewalls, wherein the top portion is wider than the bottom portion.

17. A semiconductor device, comprising: Substrate; The first source / drain S / D region and the second source / drain S / D region are respectively disposed on the first fin structure and the second fin structure; A first dielectric layer is disposed between the first source / drain S / D region and the second source / drain S / D region; A first gate structure and a second gate structure are respectively disposed on the first fin structure and the second fin structure, wherein the first gate structure and the second gate structure are electrically isolated by the first dielectric layer; A second dielectric layer is disposed on the first gate structure, the second gate structure, and the first dielectric layer; A linerless contact structure having a seed layer and a conductive layer, the linerless contact structure being in the second dielectric layer and on the first gate structure, the second gate structure, and the first dielectric layer; and An isolation structure is provided in the unlined contact structure.

18. The semiconductor device according to claim 17, wherein, The unlined contact structure includes a top portion and a bottom portion with substantially vertical sidewalls, and a transition portion with sloping sidewalls, wherein the top portion is wider than the bottom portion.

19. The semiconductor device according to claim 17, wherein, The unlined contact structure includes a bottom portion having a first width and a top portion having a second width, wherein the ratio of the first width to the second width is in the range of 1:1.5 to 1:

3.

20. The semiconductor device according to claim 17, wherein, The unlined contact structure includes a bottom portion having a first height and a top portion having a second height, wherein the ratio of the first height to the second height is in the range of 1:1 to 1:2.

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