Semiconductor devices and methods

Abstract

This disclosure relates to semiconductor devices and methods. In one embodiment, a device includes: a first nanostructure on a substrate, the first nanostructure including a channel region and a first lightly doped source / drain (LDD) region adjacent to the channel region; a first epitaxial source / drain region surrounding four sides of the first LDD region; an interlayer dielectric (ILD) layer on the first epitaxial source / drain region; source / drain contacts extending through the ILD layer surrounding four sides of the first epitaxial source / drain region; and a gate stack adjacent to the source / drain contacts and the first epitaxial source / drain region, the gate stack surrounding four sides of the channel region.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor devices and methods. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material on a semiconductor substrate, and then using photolithography to pattern the various material layers to form circuit components and elements thereon.

[0003] The semiconductor industry continuously improves the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by constantly reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, other problems arise that need to be addressed. Summary of the Invention

[0004] According to one embodiment of this disclosure, a method for forming a semiconductor device is provided, comprising: patterning a plurality of semiconductor layers to form a first nanostructure, a second nanostructure, and a third nanostructure, wherein the second nanostructure is disposed between the first nanostructure and the third nanostructure; doping a first region of the second nanostructure with impurities while covering a second region of the second nanostructure; removing portions of the first nanostructure and the third nanostructure to expose the top and bottom of the first region of the second nanostructure; growing epitaxial source / drain regions around the top and bottom of the first region of the second nanostructure; and forming a gate stack around the top and bottom of the second region of the second nanostructure.

[0005] According to another embodiment of this disclosure, a semiconductor device is provided, comprising: a first nanostructure on a substrate, the first nanostructure including a channel region and a first lightly doped source / drain (LDD) region, the first LDD region being adjacent to the channel region; a first epitaxial source / drain region surrounding four sides of the first LDD region; an interlayer dielectric (ILD) layer on the first epitaxial source / drain region; source / drain contacts extending through the ILD layer, the source / drain contacts surrounding four sides of the first epitaxial source / drain region; and a gate stack adjacent to the source / drain contacts and the first epitaxial source / drain region, the gate stack surrounding four sides of the channel region.

[0006] According to another embodiment of this disclosure, a semiconductor device is provided, comprising: a nanostructure on a substrate, the nanostructure including a channel region and a lightly doped source / drain (LDD) region, the LDD region being adjacent to the channel region, the channel region having a first width and a first thickness in a first cross-section, the LDD region having a second width and a second thickness in a second cross-section, the second width being less than the first width, the second thickness being less than the first thickness, the first cross-section and the second cross-section being perpendicular to the longitudinal axis of the nanostructure; a gate stack completely surrounding the channel region in the first cross-section; and an epitaxial source / drain region completely surrounding the LDD region in the second cross-section. Attached Figure Description

[0007] Various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily enlarged or reduced.

[0008] Figure 1 An example of a simplified nanostructured field-effect transistor (nano-FET) according to some embodiments is shown.

[0009] Figures 2 to 6 This is a three-dimensional view of an intermediate stage in the fabrication of a nanostructured FET according to some embodiments.

[0010] Figures 7A to 20C This is a cross-sectional view of an intermediate stage in the fabrication of a nanostructured FET according to some embodiments.

[0011] Figures 21 to 23 This is a cross-sectional view of an intermediate stage in the fabrication of a nanostructured FET according to some embodiments.

[0012] Figure 24 This is a cross-sectional view of a nanostructured FET according to some other embodiments.

[0013] Figure 25A , Figure 25B and Figure 25C This is a cross-sectional view of a nanostructured FET according to some other embodiments. Detailed Implementation

[0014] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples throughout this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0015] In addition, spatially related terms (e.g., "below," "below," "lower than," "above," "upper") may be used herein to facilitate the description of the relationship of one element or feature shown in the figure relative to another element(s) or feature(s). These spatially related terms are intended to cover different orientations of the device in use or operation other than those shown in the figure. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein shall be interpreted accordingly.

[0016] According to some embodiments, source / drain regions for a nanostructured FET are grown around a nanostructure. The source / drain regions surround all (e.g., four) sides of the nanostructure. Therefore, subsequently formed contacts can surround all (e.g., four) sides of the source / drain regions. This increases the contact area and reduces the contact resistance (Rt) of the source / drain contacts. C ), and improve the performance of nanostructured FETs.

[0017] Figure 1 An example of a simplified nanostructured FET according to some embodiments is shown. Figure 1 This is a cross-sectional 3D view; for clarity, some features of the nanostructure FET have been omitted. Nanostructure FETs can be nanosheet field-effect transistors (NSFETs), nanowire field-effect transistors (NWFETs), gate all-around field-effect transistors (GAAFETs), etc.

[0018] The nanostructure FET includes a nanostructure 56 on a substrate 50, for example, on a fin 54 extending from the substrate 50. The nanostructure 56 is a semiconductor layer that serves as the channel region of the nanostructure FET. Isolation regions 60, such as shallow trench isolation (STI) regions, are disposed on the substrate 50 and between adjacent fins 54, which may protrude above and between adjacent isolation regions 60. Although the isolation regions 60 are shown / described as separate from the substrate 50, as used herein, the term "substrate" may refer to a single semiconductor substrate or a combination of a semiconductor substrate and an isolation region. Furthermore, although the fins 54 are shown as a single continuous material with respect to the substrate 50, the fins 54 and / or the substrate 50 may comprise a single material or multiple materials. In this context, a fin 54 refers to a portion extending above and between adjacent isolation regions 60.

[0019] Gate structure 100 surrounds nanostructure 56. Gate structure 100 includes gate dielectric 102 and gate electrode 104. Gate dielectric 102 extends along the top surface, sidewalls, and bottom surface of nanostructure 56, and may extend along the sidewalls of fin 54 and over the top surface of fin 54. Gate electrode 104 is over gate dielectric 102. Epitaxial source / drain regions 88 surround nanostructure 56 and are arranged on opposite sides of gate structure 100. In embodiments in which multiple transistors are formed, epitaxial source / drain regions 88 may be shared among various transistors. For example, adjacent epitaxial source / drain regions 88 may be electrically coupled, for example, by coupling epitaxial source / drain regions 88 to the same source / drain contact. One or more interlayer dielectric (ILD) layers (discussed in more detail below) are formed over the epitaxial source / drain region 88 and / or gate structure 100, through which contacts to the epitaxial source / drain region 88 and gate electrode 104 are formed (discussed in more detail below).

[0020] Some embodiments discussed herein are discussed in the context of nanostructured FETs formed using a post-gate process. In other embodiments, a pre-gate process may be used. Furthermore, some embodiments contemplate aspects of use in planar devices (e.g., planar FETs) or in FinFETs.

[0021] Figure 1Reference cross sections used in subsequent figures are further illustrated. Cross section AA is along the longitudinal axis of nanostructure 56 and, for example, in the direction of current flow between the epitaxial source / drain regions 88 of the nanostructure FET. Cross section BB is perpendicular to cross section AA and along the longitudinal axis of the gate electrode 104. Cross section CC is perpendicular to cross section AA and parallel to cross section BB, and extends through the epitaxial source / drain regions 88 of the nanostructure FET. For clarity, subsequent figures refer to these reference cross sections.

[0022] Figures 2 to 6 This is a three-dimensional view of an intermediate stage in the fabrication of a nanostructured FET according to some embodiments. Figures 2 to 6 It shows the relationship with Figure 1 A similar 3D view.

[0023] exist Figure 2 In this embodiment, a substrate 50 is provided for forming a nanostructure FET. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which may be doped (e.g., with p-type or n-type dopants) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on a substrate, which is typically a silicon substrate or a glass substrate. Other substrates may also be used, such as multilayer substrates or gradient substrates. In some embodiments, the semiconductor material of the substrate 50 may include: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium arsenide phosphide; or combinations thereof.

[0024] The substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form an n-type device, such as an NMOS transistor, like an n-type nanoFET, and the p-type region 50P can be used to form a p-type device, such as a PMOS transistor, like a p-type nanoFET. The n-type region 50N can be physically separated from the p-type region 50P (not shown separately), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be formed between the n-type region 50N and the p-type region 50P.

[0025] The substrate 50 may be lightly doped with p-type or n-type impurities. A punch-through (APT) implantation may be performed on the upper portion of the substrate 50 to form an APT region. During APT implantation, dopants may be implanted into the n-type region 50N and the p-type region 50P. The dopants may have a conductivity type opposite to that of the source / drain regions subsequently formed in each of the n-type region 50N and the p-type region 50P. The APT region may extend below the source / drain regions subsequently formed in the nanostructured FET, which will be formed in subsequent processes. The APT region can be used to reduce leakage from the source / drain regions to the substrate 50. In some embodiments, the doping concentration in the APT region may be approximately 10. 18 cm -3 To about 10 19 cm -3 Within the range.

[0026] A multilayer stack 52 is formed on a substrate 50. The multilayer stack 52 includes alternating first semiconductor layers 52A and second semiconductor layers 52B. The first semiconductor layer 52A is formed of a first semiconductor material, and the second semiconductor layer 52B is formed of a second semiconductor material. The semiconductor materials may each be selected from candidate semiconductor materials of the substrate 50. In the illustrated embodiment, the multilayer stack 52 includes three layers of each of the first semiconductor layer 52A and the second semiconductor layer 52B. It should be understood that the multilayer stack 52 may include any number of first semiconductor layers 52A and second semiconductor layers 52B.

[0027] In the illustrated embodiment, the second semiconductor layer 52B is used to form the channel regions for the nanostructured FET in both the n-type region 50N and the p-type region 50P. The first semiconductor layer 52A is a sacrificial layer (or dummy layer) that will be removed in a subsequent process to expose the top and bottom surfaces of the second semiconductor layer 52B in both regions. The second semiconductor material of the second semiconductor layer 52B is a material suitable for both n-type and p-type nanostructured FETs, such as silicon, and the first semiconductor material of the first semiconductor layer 52A is a material with high etch selectivity relative to the etching of the second semiconductor material, such as silicon-germanium.

[0028] In another embodiment, a first semiconductor layer 52A is used to form a channel region for a nanostructured FET in one region (e.g., p-type region 50P), and a second semiconductor layer 52B is used to form a channel region for a nanostructured FET in another region (e.g., n-type region 50N). The first semiconductor material of the first semiconductor layer 52A may be suitable for a p-type nanostructured FET, for example, silicon germanium (e.g., Si...). x Ge 1-xThe first semiconductor material 52B can be in the range of 0 to 1, and can be pure or substantially pure germanium, III-V compound semiconductor, II-VI compound semiconductor, etc. The second semiconductor material can be suitable for n-type nanostructure FETs, such as silicon, silicon carbide, III-V compound semiconductor, II-VI compound semiconductor, etc. The etching of the first and second semiconductor materials relative to each other can have high etch selectivity, so that the first semiconductor layer 52A can be removed in the n-type region 50N without removing the second semiconductor layer 52B, and the second semiconductor layer 52B can be removed in the p-type region 50P without removing the first semiconductor layer 52A.

[0029] Each layer of the multilayer stack 52 can be formed using processes such as vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), chemical vapor deposition (CVD), atomic layer deposition (ALD), etc. Each layer can be formed with a relatively small thickness, for example, in the range of about 5 nm to about 30 nm. In some embodiments, one set of layers (e.g., a second semiconductor layer 52B) is formed to be thinner than another set of layers (e.g., a first semiconductor layer 52A). For example, in an embodiment where the second semiconductor layer 52B is used to form the channel region and the first semiconductor layer 52A is a sacrificial layer (or dummy layer), the first semiconductor layer 52A can be formed to a first thickness T1 and the second semiconductor layer 52B can be formed to a second thickness T2, and the second thickness T2 is about 30% to about 60% smaller than the first thickness T1. Forming the second semiconductor layer 52B to a smaller thickness allows the channel region to be formed at a higher density.

[0030] exist Figure 3 In this process, trenches are etched in a substrate 50 and a multilayer stack 52 to form fins 54 and nanostructures 56. Fins 54 are patterned semiconductor strips in the substrate 50. Nanostructures 56 comprise the remainder of the multilayer stack 52 on the fins 54. Specifically, nanostructures 56 comprise alternating first nanostructures 56A and second nanostructures 56B. The first nanostructures 56A and second nanostructures 56B are formed from the remainder of the first semiconductor layer 52A and the second semiconductor layer 52B, respectively. After formation, second nanostructures 56B at intermediate levels of the structure are each disposed between two first nanostructures 56A. Etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), etc., or combinations thereof. Etching can be anisotropic.

[0031] The fins 54 and nanostructures 56 can be patterned using any suitable method. For example, one or more photolithography processes can be used to pattern the fins 54 and nanostructures 56, including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing the creation of patterns with, for example, smaller pitches than that achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fins 54 and nanostructures 56.

[0032] The fins 54 and nanostructures 56 may have widths ranging from about 8 nm to about 40 nm. For illustrative purposes, the fins 54 and nanostructures 56 in the n-type region 50N and the p-type region 50P are shown to have substantially equal widths. In some embodiments, the fins 54 and nanostructures 56 in one region (e.g., the n-type region 50N) may be wider or narrower than the fins 54 and nanostructures 56 in another region (e.g., the p-type region 50P).

[0033] exist Figure 4 An STI region 60 is formed adjacent to fin 54. The STI region 608 can be formed by depositing an insulating material on the substrate 50 and nanostructure 56 and between adjacent fins 54. The insulating material can be an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), or a combination thereof, and can be formed by high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), or a combination thereof. Other insulating materials formed by any acceptable process can be used. In the illustrated embodiment, the insulating material is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process can be performed. In the embodiment, the insulating material is formed such that excess insulating material covers the nanostructure 56. Although the insulating material is shown as a single layer, some embodiments may employ multiple layers. For example, in some embodiments, a liner can be formed first along the surfaces of the substrate 50, fins 54, and nanostructure 56. A filler material, such as described above, can then be formed on the liner.

[0034] Then, a removal process is applied to the insulating material to remove excess insulating material above the nanostructure 56. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), etch-back process, or a combination thereof may be used. This planarization process exposes the nanostructure 56 such that the top surface of the nanostructure 56 and the insulating material are coplanar after the planarization process is completed (within process variations).

[0035] The insulating material is then recessed to form the STI region 60. The insulating material is recessed such that the upper portion of the fin 54 protrudes between adjacent STI regions 60. In the illustrated embodiment, the top surface 60 of the STI region is below the top surface of the fin 54. In some embodiments, the top surface of the STI region 60 is above or coplanar with the top surface of the fin 54 (within process variations). Furthermore, the top surface of the STI region 60 may have a flat surface (as shown), a convex surface, a concave surface (e.g., dish-shaped), or a combination thereof. The top surface of the STI region 60 can be formed as flat, convex, and / or concave by appropriate etching. The STI region 60 can be recessed using an acceptable etching process, such as an etching process selective for the material of the insulating material (e.g., etching the material of the insulating material at a faster rate than the materials of the fin 54 and the nanostructure 56). For example, removal can be achieved using an oxide, such as a diluted hydrofluoric acid (dHF) acid.

[0036] The above-described process is merely one example of how the fins 54 and nanostructures 56 can be formed. In some embodiments, the fins 54 and nanostructures 56 can be formed by an epitaxial growth process. For example, a dielectric layer can be formed over the top surface of the substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. Epitaxial structures can be epitaxially grown in the trenches, and the dielectric layer can be recessed such that the epitaxial structures protrude from the dielectric layer to form the fins 54 and nanostructures 56. The epitaxial structures may include alternating semiconductor materials discussed above, such as a first semiconductor material and a second semiconductor material. In embodiments where the epitaxial structures are epitaxially grown, the epitaxially grown material can be in-situ doped during growth, which avoids prior and / or subsequent implantation, but in-situ doping and implantation doping can be used together.

[0037] Furthermore, suitable wells can be formed in the substrate 50, fin 54, and / or nanostructure 56. In some embodiments, a p-type well can be formed in an n-type region 50N, and an n-type well can be formed in a p-type region 50P. In another embodiment, either a p-type well or an n-type well can be formed in both the n-type region 50N and the p-type region 50P.

[0038] In embodiments with different well types, photoresist or other masks can be used to implement different implantation steps for the n-type region 50N and the p-type region 50P. For example, photoresist can be formed over the fins 54, nanostructures 56, and STI region 60 in the n-type region 50N. The photoresist is patterned to expose the p-type region 50P. The photoresist can be formed using spin coating and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, n-type impurity implantation is performed in the p-type region 50P, and the photoresist can be used as a mask to substantially prevent n-type impurities from being implanted into the n-type region 50N. The n-type impurities can be phosphorus, arsenic, antimony, etc., implanted into the region at a concentration of about 10. 13 cm -3 To about 10 14 cm -3 Within the specified range. After implantation, the photoresist is removed, for example, through an acceptable ashing process.

[0039] Following implantation into the p-type region 50P, a photoresist is formed over the fins 54, nanostructures 56, and STI region 60 within the p-type region 50P. The photoresist is patterned to expose the n-type region 50N. The photoresist can be formed using spin coating and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, p-type impurity implantation can be performed in the n-type region 50N, and the photoresist can be used as a mask to substantially prevent p-type impurities from being implanted into the p-type region 50P. The p-type impurities can be boron, boron fluoride, indium, etc., implanted into the region at a concentration of approximately 10. 13 cm -3 To about 10 14 cm -3 Within the specified range. After injection, the photoresist can be removed, for example, by an acceptable ashing process.

[0040] Following implantation into the n-type region 50N and the p-type region 50P, annealing can be performed to repair implantation damage and activate the implanted p-type and / or n-type impurities. In some embodiments, the growth material of the epitaxial fins can be in-situ doped during growth, which eliminates implantation, but in-situ doping and implantation doping can be used together.

[0041] exist Figure 5In this process, a dummy dielectric layer 62 is formed on the fin 54 and the nanostructure 56. The dummy dielectric layer 62 can be, for example, silicon oxide, silicon nitride, a combination thereof, etc., and can be deposited or thermally grown according to acceptable techniques. A dummy gate layer 64 is formed on the dummy dielectric layer 62, and a mask layer 66 is formed on the dummy gate layer 64. The dummy gate layer 64 can be deposited on the dummy dielectric layer 62 and then planarized, for example, by CMP. The mask layer 66 can be deposited on the dummy gate layer 64. The dummy gate layer 64 can be a conductive or non-conductive material, and can be selected from the group consisting of amorphous silicon, polysilicon, poly-SiGe, metal nitrides, metal silicides, metal oxides, and metals. The dummy gate layer 64 can be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques for depositing the selected material. The dummy gate layer 64 may be made of one or more materials that have high etch selectivity relative to the etching of the isolation material (e.g., one or more materials of the STI region 60 and / or the dummy dielectric layer 62). The mask layer 66 may comprise one or more layers, such as silicon nitride, silicon oxynitride, etc. In this example, a single dummy gate layer 64 and a single mask layer 66 are formed across the n-type region 50N and the p-type region 50P. Although the dummy dielectric layer 62 is shown as covering the STI region 60, it should be understood that the dummy dielectric layer 62 may be formed in other ways. In some embodiments, for example when the dummy dielectric layer 62 is thermally grown, the dummy dielectric layer 62 is formed to cover only the fin 54 and the nanostructure 56.

[0042] exist Figure 6 In this process, mask layer 66 is patterned using acceptable photolithography and etching techniques to form mask 76. The pattern of mask 76 is then transferred to dummy gate layer 64 using acceptable etching techniques to form dummy gate 74. Optionally, the pattern of mask 76 can be further transferred to dummy dielectric layer 62 using acceptable etching techniques to form dummy dielectric 72. Dummy gate 74 covers a portion of nanostructure 56 that will be exposed in subsequent processing to form channel region. Specifically, dummy gate 74 extends along a portion of second nanostructure 56B that will be used to form channel region 58 (see [link to documentation]). Figure 7A The pattern of mask 76 can be used to physically separate adjacent dummy gates 74. The dummy gates 74 may also have a length direction substantially perpendicular to the length direction of fin 54 (within process variations). Mask 76 may optionally be removed after patterning, for example, by an acceptable etching technique.

[0043] Figures 7A to 20C This is a cross-sectional view of other intermediate stages in the fabrication of nanostructured FETs according to some embodiments. Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A , Figure 19A and Figure 20A Along Figure 1 The reference section AA is shown in the figure. Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11B , Figure 12B , Figure 13B , Figure 14B , Figure 15B , Figure 16B , Figure 17B , Figure 18B , Figure 19B and Figure 20B Along Figure 1 The reference section BB is shown, but with the difference that two fins are shown. Figure 7C , Figure 8C , Figure 9C , Figure 10C , Figure 11C , Figure 12C , Figure 13C , Figure 14C , Figure 15C , Figure 16C , Figure 17C , Figure 18C , Figure 19C and Figure 20C Along Figure 1 The reference section CC is shown, but with the difference that two fins are shown. Figures 7A to 20C This applies to both n-type region 50N and p-type region 50P. The structural differences between n-type region 50N and p-type region 50P (if any) are described in the text accompanying each figure.

[0044] exist Figure 7A , Figure 7B and Figure 7CIn this embodiment, a gate spacer 80 is formed on the nanostructure 56 and fin 54, on the exposed sidewalls of the mask 76, dummy gate 74, and dummy dielectric 72. The gate spacer 80 can be formed by conformally forming an insulating material and subsequently etching that insulating material. The insulating material of the gate spacer 80 can be silicon nitride, silicon carbonitride, silicon carbonitride, combinations thereof, etc., and can be formed by thermal oxidation, deposition, combinations thereof, etc. The gate spacer 80 can be formed from a single layer or multiple layers of insulating material. In some embodiments, the gate spacer 80 comprises multiple layers of silicon carbonitride, wherein each layer may have a different silicon carbonitride composition. In some embodiments, the gate spacer 80 comprises a layer of silicon oxide disposed between two layers of silicon nitride. Other spacer structures can be formed. The etching of the insulating material can be anisotropic. For example, the etching process can be dry etching, such as RIE, NBE, etc. After etching, the gate spacer 80 can have straight or curved sidewalls. A dry etching process is performed to remove insulating material from the sidewalls of the nanostructure 56 (and optionally the fin 54). For example, the dry etching process may be performed for a duration ranging from about 1 second to about 15 seconds to remove insulating material from the sidewalls of the nanostructure 56. In the illustrated embodiment, insulating material is also removed from the sidewalls of the fin 54, leaving material without the gate spacer 80 above the STI region 60. In another embodiment, some insulating material may remain on the sidewalls of the fin 54 but not on the sidewalls of the nanostructure 56.

[0045] Prior to forming the gate spacer 80, implantation for the lightly doped source / drain (LDD) region 82 can be performed. In embodiments with different device types, similar to the implantation discussed above, a mask (e.g., photoresist) can be formed over the n-type region 50N while exposing the p-type region 50P, and an impurity of an appropriate type (e.g., p-type) can be implanted into the nanostructures 56 and fins 54 exposed in the p-type region 50P. The mask can then be removed. Subsequently, a mask (e.g., photoresist) can be formed over the p-type region 50P while exposing the n-type region 50N, and an impurity of an appropriate type (e.g., n-type) can be implanted into the nanostructures 56 and fins 54 exposed in the n-type region 50N. The mask can then be removed. The n-type impurity can be any of the previously discussed n-type impurities, and the p-type impurity can be any of the previously discussed p-type impurities. The lightly doped source / drain region can have approximately 10 15 cm -3 To about 10 19 cm -3 The impurity concentration is within a certain range. Annealing can be used to repair implantation damage and reactivate the implanted impurities. During implantation, the channel region 58 remains covered by the dummy gate 74, so that the channel region 58 remains substantially free of impurities implanted into the LDD region 82.

[0046] Note that the above disclosure generally describes the process for forming the spacers and LDD regions. Other processes and sequences can be used. For example, fewer or additional spacers can be used, and different step sequences can be employed (e.g., additional spacers can be formed and removed, etc.). Furthermore, different structures and steps can be used to form n-type and p-type devices.

[0047] exist Figure 8A , Figure 8B and Figure 8C In this process, a portion of the first nanostructure 56A is removed to form a source / drain opening 84. Specifically, the portion of the first nanostructure 56A not laterally covered by the gate spacer 80 and the dummy gate 74 is removed to expose the top and bottom surfaces of the second nanostructure 56B, such as the top and bottom surfaces of the LDD region 82. The source / drain opening 84 thus extends laterally between the sidewalls of the fin 54, as... Figure 8C As shown. These portions of the first nanostructure 56A can be removed by an acceptable etching process that selectively etches the material of the first nanostructure 56A at a faster rate than the material of the second nanostructure 56B and fin 54(one or more). The etching can be isotropic. For example, when the fin 54 and the second nanostructure 56B are formed of silicon and the first nanostructure 56A is formed of silicon germanium, the etching process can be a wet etching using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc. Since the gate spacer 80 does not extend along the sidewalls of the nanostructure 56, the first nanostructure 56A can be... Figure 8C It was completely removed from the cross section.

[0048] exist Figure 9A , Figure 9B and Figure 9C In this configuration, internal spacers 86 are optionally formed on the sidewalls of the remaining portion of the first nanostructure 56A, for example, those sidewalls exposed by the source / drain openings 84. As will be described in detail below, source / drain regions will subsequently be formed in the source / drain openings 84, and the first nanostructure 56A will subsequently be replaced by a corresponding gate structure. The internal spacers 86 serve as an isolation feature between the subsequently formed source / drain regions and the subsequently formed gate structure. Furthermore, the internal spacers 86 can be used to prevent damage to the subsequently formed source / drain regions by subsequent etching processes (e.g., etching processes for subsequently forming the gate structure).

[0049] As an example of forming the internal spacer 86, the source / drain opening 84 may be enlarged. Specifically, the portion of the sidewall of the first nanostructure 56A exposed by the source / drain opening 84 may be recessed. Although the sidewall of the first nanostructure 56A is shown as straight, it may be concave or convex. The sidewall can be recessed by an acceptable etching process that selectively etches the material of the first nanostructure 56A at a faster rate than the material(s) of the second nanostructure 56B and the fin 54. The etching may be isotropic. For example, when the fin 54 and the second nanostructure 56B are formed of silicon and the first nanostructure 56A is formed of silicon-germanium, the etching process may be a wet etching using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc. In another embodiment, the etching process may be a dry etching using a fluorine-based gas such as hydrogen fluoride. In some embodiments, the same etching process may be continuously performed to both form the source / drain opening 84 and recess the sidewall of the first nanostructure 56A. The internal spacer 86 can then be formed by conformally forming an insulating material and subsequently etching that insulating material. The insulating material can be a material such as silicon nitride or silicon oxynitride, but any suitable material can be used, for example, a low dielectric constant (low-k) material with a k-value less than about 3.5. The insulating material can be deposited using a conformal deposition process (e.g., ALD, CVD, etc.). The etching of the insulating material can be anisotropic. For example, the etching process can be dry etching, such as RIE, NBE, etc. Although the outer wall of the internal spacer 86 is shown as flush with the sidewall of the gate spacer 80, the outer wall of the internal spacer 86 may extend beyond or be recessed from the sidewall of the gate spacer 80. In other words, the internal spacer 86 may partially fill, fully fill, or overfill the sidewall recess. Furthermore, although the sidewall of the internal spacer 86 is shown as straight, the sidewall of the internal spacer 86 may be concave or convex.

[0050] exist Figure 10A , Figure 10B and Figure 10C Optionally, the portions of the second nanostructure 56B and fin 54 exposed by the source / drain opening 84 can be trimmed. This trimming reduces the dimensions (e.g., thickness and width) of the exposed portion of the second nanostructure 56B (e.g., LDD region 82), while the unexposed portions of the second nanostructure 56B (e.g., channel region 58) retain their original dimensions. The unexposed portions of the second nanostructure 56B are those covered by the gate spacer 80 and the dummy gate 74. The unexposed portions of the fin 54 are those extending above the STI region 60. For example, this trimming can reduce the thickness of the exposed portion of the second nanostructure 56B from a second thickness T2 (as described above). Figure 2(Discussion) The thickness is reduced to a third thickness T3, wherein the third thickness T3 is in the range of about 3 nm to about 15 nm, and the third thickness T3 is about 25% to about 40% smaller than the second thickness T2. Similarly, this trimming can reduce the width of the exposed portion of the fin 54 and the second nanostructure 56B from a first width W1 to a second width W2, wherein the first width W1 is in the range of about 5 nm to about 20 nm, the second width W2 is in the range of about 3 nm to about 15 nm, and the second width W2 is about 25% to about 50% smaller than the first width W1. After this trimming, the second nanostructure 56B in Figure 10B The cross-section has a first perimeter (e.g., twice the sum of the second thickness T2 and the first width W1), and Figure 10C The cross-section has a second perimeter (e.g., twice the sum of the third thickness T3 and the second width W2), where the second perimeter is smaller than the first perimeter. This trimming enlarges the source / drain openings 84 so that they can accommodate larger source / drain regions of the nanostructure FET. The exposed portions of the second nanostructure 56B and fin 54 can be trimmed by an acceptable etching process that selectively etches one or more materials of the second nanostructure 56B and fin 54 at a faster rate than the materials of the first nanostructure 56A, the internal spacer 86, and the gate spacer 80. The etching can be isotropic. For example, when the fin 54 and the second nanostructure 56B are formed of silicon and the first nanostructure 56A is formed of silicon-germanium, the etching process can be a wet etching using a dilute ammonium hydroxide-hydrogen peroxide mixture (APM), a sulfuric acid-hydrogen peroxide mixture (SPM), etc. When this trimming process is omitted, the channel region 58 and the LDD region 82 can each have the same thickness.

[0051] exist Figure 11A , Figure 11B and Figure 11C In the process, an epitaxial source / drain region 88 is formed within the source / drain opening 84 and around the exposed / trimmed portion (e.g., LDD region 82) of the second nanostructure 56B. After formation, the epitaxial source / drain region 88 surrounds the four sides (e.g., top surface, sidewalls, and bottom surface) of the second nanostructure 56B. Therefore, in Figure 11CIn the cross-section, the epitaxial source / drain region 88 completely surrounds the second nanostructure 56B. The epitaxial source / drain region 88 may also optionally be formed on the exposed / trimmed portion of the fin 54, such that a first subset 88A of the epitaxial source / drain region surrounds the second nanostructure 56B, and a second subset 88B of the epitaxial source / drain region extends along the fin 54. The epitaxial source / drain region 88 is formed in the source / drain opening 84 such that the respective groups of the epitaxial source / drain regions 88 are disposed between adjacent pairs of the dummy gate 74. In some embodiments, the gate spacer 80 and the internal spacer 86 are used to separate the epitaxial source / drain region 88 from the dummy gate 74 and the first nanostructure 56A by an appropriate lateral distance, such that the epitaxial source / drain region 88 does not short-circuit the subsequently formed gate of the nanostructure FET. The epitaxial source / drain region 88 may be formed to contact the internal spacer 86 (if present). When the nanostructure 56B is modified, the epitaxial source / drain region 88 can apply stress to the channel region 58, thereby improving performance.

[0052] The epitaxial source / drain region 88 in the n-type region 50N can be formed by masking the p-type region 50P. The epitaxial source / drain region 88 is then epitaxially grown in the source / drain opening 84 in the n-type region 50N. The epitaxial source / drain region 88 can comprise any acceptable material suitable for an n-type nanoFET. For example, the epitaxial source / drain region 88 in the n-type region 50N can comprise a material on which tensile strain is applied to the channel region 58, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon-phosphorus, etc. The epitaxial source / drain region 88 in the n-type region 50N can have surfaces protruding from the corresponding surfaces of the second nanostructure 56B and the fin 54, and can have facets.

[0053] The epitaxial source / drain region 88 in the p-type region 50P can be formed by masking the n-type region 50N. The epitaxial source / drain region 88 is then epitaxially grown in the source / drain opening 84 in the p-type region 50P. The epitaxial source / drain region 88 can comprise any acceptable material suitable for a p-type nanoFET. For example, the epitaxial source / drain region 88 in the p-type region 50P can comprise a material on which compressive strain is applied to the channel region 58, such as silicon-germanium, boron-doped silicon-germanium, germanium, germanium-tin, etc. The epitaxial source / drain region 88 in the p-type region 50P can also have surfaces protruding from the corresponding surfaces of the second nanostructure 56B and the fin 54, and can have small facets.

[0054] Epitaxial source / drain regions 88, second nanostructures 56B, and / or fins 54 can be implanted with dopants to form source / drain regions, similar to the previously discussed process for forming lightly doped source / drain regions, followed by annealing. The impurity concentration of the source / drain regions can be around 10. 19cm -3 To about 10 21 cm -3 Within the range. The n-type and / or p-type impurities used for the source / drain regions can be any of the previously discussed impurities. In some embodiments, the epitaxial source / drain regions 88 can be doped in situ during growth.

[0055] As a result of the epitaxial process used to form the epitaxial source / drain region 88, the upper surface of the epitaxial source / drain region 88 has facets that extend laterally outward beyond the surfaces of the second nanostructure 56B and the fin 54. In embodiments where no material of the gate spacer 80 remains above the STI region 60, the epitaxial source / drain region 88B may extend along and contact the STI region 60. The epitaxial source / drain region 88 is formed to a thickness T4, which is chosen such that the epitaxial source / drain region 88 does not coalesce during the epitaxial process. In some embodiments, the thickness T4 of the epitaxial source / drain region 88 is up to the original thickness T1 of the first nanostructure 56A (relative to the original thickness T1 of the first nanostructure 56A). Figure 2 (Discussed above) approximately one-quarter of the thickness. For example, the thickness T4 can be in the range of approximately 5 nm to approximately 15 nm. Forming the epitaxial source / drain region 88 to a thickness T4 within this range avoids the merging of the epitaxial source / drain region 88. Forming the epitaxial source / drain region 88 to a thickness T4 outside this range does not avoid the merging of the epitaxial source / drain region 88. Avoiding the merging of the epitaxial source / drain region 88 allows the subsequently formed source / drain contacts to surround all (e.g., four) sides of the epitaxial source / drain region 88A, thereby increasing the contact area of ​​the epitaxial source / drain contacts and reducing their contact resistance (R). C ).

[0056] The epitaxial source / drain region 88 may include one or more semiconductor material layers. For example, the epitaxial source / drain region 88 may include a first semiconductor material layer, a second semiconductor material layer, and a third semiconductor material layer. Any number of semiconductor material layers may be used for the epitaxial source / drain region 88. Each of the first, second, and third semiconductor material layers may be formed of a different semiconductor material and / or may be doped with different dopant concentrations. In some embodiments, the first semiconductor material layer may have a dopant concentration smaller than that of the second semiconductor material layer and greater than that of the third semiconductor material layer. When the epitaxial source / drain region 88 includes three semiconductor material layers, the first semiconductor material layer may be grown from the second nanostructure 56B and the fin 54, the second semiconductor material layer may be grown from the first semiconductor material layer, and the third semiconductor material layer may be grown from the second semiconductor material layer.

[0057] exist Figure 12A , Figure 12B and Figure 12C In this process, a dummy layer 92 is formed on and around the epitaxial source / drain regions 88. The dummy layer 92 surrounds the four sides (e.g., top surface, sidewalls, and bottom surface) of the epitaxial source / drain regions 88A and the three sides (e.g., top surface and sidewalls) of the epitaxial source / drain regions 88B. Specifically, a dummy layer 92 is formed around each set of epitaxial source / drain regions 88 disposed between adjacent dummy gates 74. The dummy layer 92 fills the remaining portion of the source / drain opening 84 that is not filled by the epitaxial source / drain regions 88. The dummy layer 92 can be formed of a dielectric material such as silicon carbonitride, silicon oxynitride, or silicon carbonitride, but other suitable dielectric materials can be used. Note that the dummy layer 92 is formed of a dielectric material with high etch selectivity relative to the etching of the subsequently formed ILD. The dummy layers 92 are so named because they will be removed in a subsequent process used to form source / drain contacts via the subsequently formed ILD. The dummy layer 92 can be deposited using conformal deposition processes such as ALD and CVD.

[0058] As an example of forming the dummy layer 92, the dielectric material of the dummy layer 92 can be conformally deposited, for example, by ALD, around the epitaxial source / drain region 88 and over the gate spacer 80 and mask 76. A removal process is then applied to remove excess dielectric material over the gate spacer 80 and mask 76. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), etch-back, or a combination thereof can be used. This planarization process exposes the gate spacer 80 and mask 76 such that the top surfaces of the dielectric material, gate spacer 80, and mask 76 are coplanar after the planarization process is completed (within process variations). The dielectric material is then recessed to form the dummy layer 92. The top surface of the dummy layer 92 is recessed below the top surface of the mask 76 and may be recessed below the top surface of the dummy gate 74.

[0059] exist Figure 13A , Figure 13B and Figure 13CIn this configuration, a first ILD 94 is deposited over a dummy layer 92, a gate spacer 80, and a mask 76. The first ILD 94 can be formed of a dielectric material and can be deposited by any suitable method such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process may be used. In some embodiments, an etch stop layer is formed between the dummy layer 92 and the first ILD 94. The etch stop layer may include a dielectric material having an etch rate different from that of the first ILD 94, such as silicon nitride, silicon oxide, silicon oxynitride, etc.

[0060] exist Figure 14A , Figure 14B and Figure 14C In this process, a planarization process such as CMP can be performed to make the top surface of the first ILD 94 flush with the top surface of the dummy gate 74 or mask 76. This planarization process can also remove the mask 76 on the dummy gate 74, as well as portions of the gate spacer 80 along the sidewalls of the mask 76. After this planarization process, the top surfaces of the first ILD 94, the gate spacer 80, and the mask 76 (if present) or the dummy gate 74 are coplanar (within a process variation). Therefore, the top surface of the mask 76 (if present) or the dummy gate 74 is exposed through the first ILD 94. In the illustrated embodiment, the mask 76 is retained, and the planarization process makes the top surface of the first ILD 94 flush with the top surface of the mask 76.

[0061] exist Figure 15A , Figure 15B and Figure 15C In the etching process, the mask 76 (if present) and the dummy gate 74 are removed to form the recess 96. A portion of the dummy dielectric 72 in the recess 96 may also be removed. In some embodiments, the dummy gate 74 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using one or more reactive gases that selectively etch the dummy gate 74 at a rate faster than the first ILD 94 or the gate spacer 80. During removal, the dummy dielectric 72 may serve as an etch stop layer while etching the dummy gate 74. The dummy dielectric 72 may then be removed after the dummy gate 74 has been removed. Each recess 96 exposes and / or overlies a portion of the channel region 58 in the second nanostructure 56B. The portion of the second nanostructure 56B that serves as the channel region 58 is disposed between adjacent pairs of epitaxial source / drain regions 88.

[0062] Then, the remaining portion of the first nanostructure 56A is removed to enlarge the recess 96. The remaining portion of the first nanostructure 56A can be removed by an acceptable etching process that selectively etches the first nanostructure 56A at a faster rate than the materials of the second nanostructure 56B, fin 54, and STI region 60. This etching can be isotropic. For example, when the fin 54 and the second nanostructure 56B are formed of silicon and the first nanostructure 56A is formed of silicon-germanium, the etching process can be a wet etching using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc.

[0063] exist Figure 16A , Figure 16B and Figure 16C In this process, a gate dielectric 102 and a gate electrode 104 are formed to replace the gate. The gate dielectric 102 is conformally deposited in the recess 96, for example, on the top surface and sidewalls of the fin 54, and on the top surface, sidewalls, and bottom surface of the second nanostructure 56B. The gate dielectric 102 may also be deposited on the top surfaces of the first ILD 94, the gate spacer 80, and the STI region 60. According to some embodiments, the gate dielectric 102 comprises silicon oxide, silicon nitride, or a multilayer thereof. In some embodiments, the gate dielectric 102 comprises a high-k dielectric material, and in these embodiments, the gate dielectric 102 may have a k value greater than about 7.0, and may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. Methods for forming the gate dielectric 102 may include molecular beam deposition (MBD), ALD, PECVD, etc.

[0064] Gate electrode 104 is deposited on gate dielectric 102 and fills the remainder of recess 96. Gate electrode 104 may comprise a metallic material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiples thereof. For example, although a single-layer gate electrode 104 is shown, gate electrode 104 may comprise any number of liner layers, any number of work function adjustment layers, and filler material. Any combination of layers constituting gate electrode 104 may be deposited in the region between each second nanostructure 56B, and in the region between fin 54 and second nanostructure 56B. After filling recess 96, a planarization process such as CMP may be performed to remove excess material from gate dielectric 102 and gate electrode 104 above the top surface of first ILD 94 and gate spacer 80. The remaining material from gate dielectric 102 and gate electrode 104 thus forms the replacement gate of the resulting nanostructure FET. The gate dielectric 102 and the gate electrode 104 can be collectively referred to as the gate structure 100 or the "gate stack".

[0065] The formation of the gate dielectric 102 in regions 50N and 50P can occur simultaneously, such that the gate dielectric 102 in each region is formed of the same material, and the formation of the gate electrode 104 can occur simultaneously, such that the gate electrode 104 in each region is formed of the same material. In some embodiments, the gate dielectric 102 in each region can be formed by different processes, such that the gate dielectric 102 can be made of different materials, and / or the gate electrode 104 in each region can be formed by different processes, such that the gate electrode 104 can be made of different materials. When using different processes, various masking steps can be used to mask and expose appropriate regions.

[0066] exist Figure 17A , Figure 17B and Figure 17C In the first ILD 94, a source / drain contact opening 106 is formed. The source / drain contact opening 106 can be formed using acceptable photolithography and etching techniques, such as using an etching process that is selective to the first ILD 94 (e.g., etching the material of the first ILD 94 at a faster rate than the material of the dummy layer 92). During etching, the dummy layer 92 can be used as an etch stop layer, such that the source / drain contact opening 106 exposes the dummy layer 92.

[0067] exist Figure 18A , Figure 18B and Figure 18C In this process, the dummy layer 92 is removed to enlarge the source / drain contact opening 106 and expose the epitaxial source / drain region 88. Removing the dummy layer 92 exposes all outer surfaces of the epitaxial source / drain region 88 (e.g., top surface, sidewalls, and bottom surface). The dummy layer 92 can be removed using an acceptable etching process, such as a selective etching process for the dummy layer 92 (e.g., etching the material of the dummy layer 92 at a faster rate than the material of the first ILD 94).

[0068] exist Figure 19A , Figure 19B and Figure 19CIn this process, silicide 108 is formed in the source / drain contact opening 106 and on the epitaxial source / drain region 88. The silicide 108 surrounds the epitaxial source / drain region 88. The silicide 108 may be formed by depositing a metal layer in the source / drain contact opening 106 and performing an annealing process. The metal layer may be conformally formed on the top surface of the first ILD 94, the sidewalls of the first ILD 94, and all surfaces (e.g., top surface, sidewalls, and bottom surface) of the epitaxial source / drain region 88. The metal layer may be formed of titanium, cobalt, tungsten, etc., and may be deposited by any suitable method, such as ALD, PVD, CVD, and PECVD. In some embodiments, a liner is also formed in the source / drain contact opening 106. This liner may be a diffusion barrier layer, an adhesion layer, etc., and may help prevent the metal layer from diffusing into the first ILD 94 during annealing. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The metal layer and optional liner are then annealed to form silicide 108. Silicide 108 is physically coupled and electrically coupled to the epitaxial source / drain region 88. Excess portions of the metal layer and / or liner can then be removed by an acceptable etching process.

[0069] Then, a lower source / drain contact 112A is formed in the source / drain contact opening 106. A liner, such as a diffusion barrier layer or an adhesion layer, and a conductive material are formed in the source / drain contact opening 106. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The liner can be deposited using a conformal deposition process, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc. In some embodiments, the liner may include an adhesion layer, and at least a portion of the adhesion layer may be treated to form a diffusion barrier layer. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. The conductive material can be deposited using ALD, CVD, PVD, etc. A planarization process, such as CMP, can be performed to remove excess material from the surface of the first ILD 94. The remaining liner and conductive material in the source / drain contact opening 106 form the lower source / drain contact 112A. The lower source / drain contact 112A is physically coupled and electrically coupled to the silicide 108.

[0070] exist Figure 20A , Figure 20B and Figure 20CIn this process, a second ILD 114 is deposited on top of a first ILD 94. The second ILD 114 can be formed of a dielectric material and can be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The dielectric material can include: oxides, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc.; nitrides, such as silicon nitride; etc. After formation, the second ILD 114 can be planarized, for example, by CMP. In some embodiments, an etch stop layer is formed between the first ILD 94 and the second ILD 114. This etch stop layer can include a dielectric material having an etch rate different from that of the second ILD 114, such as silicon nitride, silicon oxide, silicon oxynitride, etc.

[0071] Then, upper source / drain contacts 112B and gate contacts 116 extending through the second ILD 114 are formed. Openings for the upper source / drain contacts 112B and gate contacts 116 are formed through the second ILD 114. These openings can be formed using acceptable photolithography and etching techniques. A liner, such as a diffusion barrier layer, an adhesion layer, etc., and a conductive material are formed in the openings. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The liner can be deposited using conformal deposition processes, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc. In some embodiments, the liner may include an adhesion layer, and at least a portion of the adhesion layer may be treated to form a diffusion barrier layer. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. The conductive material can be deposited using ALD, CVD, PVD, etc. A planarization process, such as CMP, can be performed to remove excess material from the surface of the second ILD 114. The remaining liner and conductive material in the source / drain contact opening 106 form the upper source / drain contact 112B and the gate contact 116. The upper source / drain contact 112B is physically coupled and electrically coupled to the lower source / drain contact 112A, and the gate contact 116 is physically coupled and electrically coupled to the gate electrode 104. The upper source / drain contact 112B and the lower source / drain contact 112A can be collectively referred to as the source / drain contact 112. After formation, the lower source / drain contact 112A physically contacts the gate spacer 80 and the internal spacer 86, and has a portion disposed between the epitaxial source / drain regions 88 in the same column. In this embodiment, the source / drain contact 112 includes a first conductive feature (e.g., lower source / drain contact 112A) extending through the first ILD 94, and a second conductive feature (e.g., upper source / drain contact 112B) extending through the second ILD 114.

[0072] The source / drain contact 112 and the gate contact 116 can be formed using different processes or the same process. Although the source / drain contact 112 and the gate contact 116 are shown in the same cross-section, these contacts can be formed in different cross-sections, which can prevent short circuits in the contacts.

[0073] Figures 21 to 23 This is a cross-sectional view of an intermediate stage in the fabrication of a nanostructured FET according to some embodiments. As will be discussed in more detail below, Figures 21 to 23 The contact cutting process is shown, wherein adjacent lower source / drain contacts 112A are separated from each other by forming dielectric features between them. Figures 21 to 23 along Figure 1 The reference section CC is shown, but with the difference that four fins are shown. Figures 7A to 20C This applies to both n-type region 50N and p-type region 50P. The structural differences between n-type region 50N and p-type region 50P (if any) are described in the text accompanying each figure.

[0074] exist Figure 21 In the middle, obtain the position regarding Figure 12C The structure of the processing state is similar to that of the processing state. Figure 21 A first set of fins 54 (e.g., on the left side of the page) and a second set of fins 54 (e.g., on the right side of the page) are shown on substrate 50. Each set of fins 54 can be used to form a nanostructured FET. A diced opening 98 is formed in the dummy layer 92. The diced opening 98 can be formed using acceptable photolithography and etching techniques. After formation, the diced opening 98 exposes the underlying insulating material, such as the STI region 60. The diced opening 98 is formed between the first set of fins 54 and the second set of fins 54 and defines the location of dielectric features that will subsequently be formed between the source / drain contacts of the nanostructured FET.

[0075] exist Figure 22 In China, use and about Figures 13A to 14C A similar process is used to form and planarize the first ILD 94. The first ILD 94 is formed in the cut opening 98 and on the dummy layer 92. Therefore, the first ILD 94 includes a lower region 94A (e.g., in the cut opening 98) and an upper region 94B (e.g., on the dummy layer 92).

[0076] exist Figure 23 In China, use and about Figures 17A to 20CThe process described above is similar to that used to form the lower source / drain contact 112A, the second ILD 114, and the upper source / drain contact 112B. After formation, the lower region 94A of the first ILD 94 thus becomes a dielectric feature that separates the adjacent lower source / drain contacts 112A.

[0077] It should be understood that Figures 21 to 23 An example contact cutting process is shown. Other dielectric features that separate adjacent lower source / drain contacts 112A can be formed. For example, dielectric features made of a different material than the first ILD 94 and the dummy layer 92 can be formed between adjacent lower source / drain contacts 112A.

[0078] In the above embodiments, adjacent epitaxial source / drain regions 88 (e.g., epitaxial source / drain regions 88 disposed on different fins 54) are electrically coupled to the same source / drain contact 112. In other words, each lower source / drain contact 112A is coupled to multiple rows of epitaxial source / drain regions 88. In another embodiment (discussed in more detail below), adjacent epitaxial source / drain regions 88 may each be coupled to different corresponding source / drain contacts 112.

[0079] Figure 24 This is a cross-sectional view of a nanostructured FET according to some other embodiments. This embodiment is similar to that regarding... Figure 23 The described embodiment differs in that adjacent epitaxial source / drain regions 88 are each coupled to different lower source / drain contacts 112A. In other words, each lower source / drain contact 112A is coupled to a row of epitaxial source / drain regions 88.

[0080] Figure 25A , Figure 25B and Figure 25C This is a cross-sectional view of a nanostructured FET according to some other embodiments. This embodiment is similar to that regarding... Figure 20A , Figure 20B and Figure 20C The described embodiment differs in that the source / drain contact 112 is a continuous conductive feature extending through both the first ILD layer 94 and the second ILD layer 114. The nanostructured FET according to this embodiment can be formed as follows: obtaining a state related to... Figure 16A , Figure 16B and Figure 16C The processing state is similar to that described above, and then a second ILD layer 114 is formed on top of the first ILD layer 94 before forming the source / drain contact opening 106. After forming the second ILD layer 114, it can be used with respect to... Figures 17A to 18CA process similar to the described one is used to form the source / drain contact opening 106 through both the second ILD layer 114 and the first ILD layer 94, and the dummy layer 92 can be removed. Then, it can be used with respect to... Figure 19A , Figure 19B and Figure 19C A process similar to that described above is used to form source / drain contacts 112 in the source / drain contact opening 106.

[0081] It should be understood that, regarding Figure 25A , Figure 25B and Figure 25C The described embodiments can be related to those from... Figures 21 to 24 The features of the described embodiments are combined. For example, Figure 25A , Figure 25B and Figure 25C The source / drain contacts 112 can be coupled to one or more rows of epitaxial source / drain regions 88. Similarly, they can be coupled to... Figure 25A , Figure 25B and Figure 25C The source / drain contact 112 undergoes a contact cutting process.

[0082] The embodiment offers advantages. Forming the source / drain contact 112 by forming and removing the dummy layer 92 allows the source / drain contact 112 to extend around all (e.g., four) sides of the epitaxial source / drain region 88. The contact area of ​​the source / drain contact 112 can therefore be increased, reducing the contact resistance (Rt) of the source / drain contact 112. C This improves the performance of the nanostructured FET. Specifically, the source / drain contacts 112 can have similar contact resistances for the epitaxial source / drain regions 88 located near the substrate 50 and for the epitaxial source / drain regions 88 located far from the substrate 50.

[0083] In one embodiment, a method includes: patterning a plurality of semiconductor layers to form a first nanostructure, a second nanostructure, and a third nanostructure, the second nanostructure being disposed between the first nanostructure and the third nanostructure; doping a first region of the second nanostructure with impurities while covering a second region of the second nanostructure; removing portions of the first and third nanostructures to expose the top and bottom of the first region of the second nanostructure; growing epitaxial source / drain regions around the top and bottom of the first region of the second nanostructure; and forming a gate stack around the top and bottom of the second region of the second nanostructure.

[0084] In some embodiments, the method further includes: trimming a first region of the second nanostructure to reduce the thickness of the first region of the second nanostructure before growing the epitaxial source / drain region. In some embodiments of the method, after trimming the first region of the second nanostructure, the thickness of the first region of the second nanostructure is less than the thickness of the second region of the second nanostructure. In some embodiments, the method further includes: depositing a dummy layer around the top and bottom of the epitaxial source / drain region after growing the epitaxial source / drain region; depositing an interlayer dielectric (ILD) layer on the dummy layer; etching the ILD layer to form a first opening exposing the dummy layer; and etching the dummy layer to enlarge the first opening and expose the epitaxial source / drain region. In some embodiments, the method further includes: depositing a metal layer in the first opening and around the epitaxial source / drain region; annealing the metal layer to form a silicide around the epitaxial source / drain region; and depositing a conductive material in the first opening to form a source / drain contact around the silicide. In some embodiments of the method, the dummy layer includes a first dielectric material, the ILD layer includes a second dielectric material, etching the ILD layer includes etching the second dielectric material at a faster rate than etching the first dielectric material, and etching the dummy layer includes etching the first dielectric material at a faster rate than etching the second dielectric material. In some embodiments of the method, the first dielectric material is silicon carbonitride, and the second dielectric material is silicon oxide. In some embodiments, the method further includes etching a second opening in the dummy layer before depositing the ILD layer, wherein depositing the ILD layer includes depositing a portion of the ILD layer in the second opening. In some embodiments, the method further includes forming a semiconductor layer on a substrate; patterning the substrate to form a fin, on which a second nanostructure is disposed; and trimming the upper portion of the fin before growing epitaxial source / drain regions. In some embodiments of the method, forming a gate stack includes removing the remainder of the first and third nanostructures to expose the top and bottom of a second region of the second nanostructure; depositing a gate dielectric around the top and bottom of the second region of the second nanostructure; and forming a gate electrode on the gate dielectric.

[0085] In one embodiment, a device includes: a first nanostructure on a substrate, the first nanostructure including a channel region and a first lightly doped source / drain (LDD) region adjacent to the channel region; a first epitaxial source / drain region surrounding four sides of the first LDD region; an interlayer dielectric (ILD) layer on the first epitaxial source / drain region; source / drain contacts extending through the ILD layer surrounding four sides of the first epitaxial source / drain region; and a gate stack adjacent to the source / drain contacts and the first epitaxial source / drain region, the gate stack surrounding four sides of the channel region.

[0086] In some embodiments of the device, the first LDD region has a first thickness, the channel region has a second thickness, and the second thickness is greater than the first thickness. In some embodiments of the device, the first LDD region and the channel region have the same thickness. In some embodiments, the device further includes: a second nanostructure on a substrate, the second nanostructure including the second LDD region; and a second epitaxial source / drain region surrounding four sides of the second LDD region, with source / drain contacts surrounding the four sides of the second epitaxial source / drain region. In some embodiments, the device further includes: a first spacer disposed between the gate stack and the first epitaxial source / drain region, with the source / drain contacts physically contacting the first spacer; and a second spacer disposed between the gate stack and the second epitaxial source / drain region, with the source / drain contacts physically contacting the second spacer. In some embodiments of the device, the source / drain contacts have a first portion and a second portion, the first portion extending through the ILD layer, and the second portion disposed between the first epitaxial source / drain region and the second epitaxial source / drain region, the width of the second portion being greater than the width of the first portion.

[0087] In one embodiment, a device includes: a nanostructure on a substrate, the nanostructure including a channel region and a lightly doped source / drain (LDD) region adjacent to the channel region, the channel region having a first width and a first thickness in a first cross-section, the LDD region having a second width and a second thickness in a second cross-section, the second width being less than the first width and the second thickness being less than the first thickness, the first cross-section and the second cross-section being perpendicular to the longitudinal axis of the nanostructure; a gate stack completely surrounding the channel region in the first cross-section; and an epitaxial source / drain region completely surrounding the LDD region in the second cross-section.

[0088] In some embodiments, the device further includes: an interlayer dielectric (ILD) layer over the epitaxial source / drain region; and a source / drain contact extending through the ILD layer, the source / drain contact completely surrounding the epitaxial source / drain region in a second cross-section. In some embodiments, the device further includes: a silicide between the source / drain contact and the epitaxial source / drain region, the silicide completely surrounding the epitaxial source / drain region in a second cross-section. In some embodiments, the device further includes: an isolation region over a substrate; and a fin having a first portion and a second portion, the first portion extending through the isolation region and the second portion extending above the isolation region, a nanostructure disposed on the fin, the first portion of the fin having a third width and the second portion of the fin having a fourth width, the second width and the fourth width being smaller than the third width.

[0089] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0090] Example 1 is a method for forming a semiconductor device, comprising: patterning a plurality of semiconductor layers to form a first nanostructure, a second nanostructure, and a third nanostructure, the second nanostructure being disposed between the first nanostructure and the third nanostructure; doping a first region of the second nanostructure with an impurity while covering a second region of the second nanostructure; removing portions of the first nanostructure and the third nanostructure to expose the top and bottom of the first region of the second nanostructure; growing epitaxial source / drain regions around the top and bottom of the first region of the second nanostructure; and forming a gate stack around the top and bottom of the second region of the second nanostructure.

[0091] Example 2 is the method of Example 1, further comprising: trimming the first region of the second nanostructure to reduce the thickness of the first region of the second nanostructure before growing the epitaxial source / drain region.

[0092] Example 3 is the method described in Example 2, wherein, after trimming the first region of the second nanostructure, the thickness of the first region of the second nanostructure is less than the thickness of the second region of the second nanostructure.

[0093] Example 4 is the method of Example 1, further comprising: after growing the epitaxial source / drain regions, depositing a dummy layer around the top and bottom of the epitaxial source / drain regions; depositing an interlayer dielectric (ILD) layer on the dummy layer; etching the ILD layer to form a first opening exposing the dummy layer; and etching the dummy layer to enlarge the first opening and expose the epitaxial source / drain regions.

[0094] Example 5 is the method of Example 4, further comprising: depositing a metal layer in the first opening and around the epitaxial source / drain region; annealing the metal layer to form a silicide around the epitaxial source / drain region; and depositing a conductive material in the first opening to form a source / drain contact around the silicide.

[0095] Example 6 is the method described in Example 4, wherein the dummy layer includes a first dielectric material, the ILD layer includes a second dielectric material, etching the ILD layer includes etching the second dielectric material at a faster rate than etching the first dielectric material, and etching the dummy layer includes etching the first dielectric material at a faster rate than etching the second dielectric material.

[0096] Example 7 is the method described in Example 6, wherein the first dielectric material is silicon carbonitride and the second dielectric material is silicon oxide.

[0097] Example 8 is the method of Example 4, further comprising: etching a second opening in the dummy layer prior to depositing the ILD layer, wherein depositing the ILD layer includes depositing a portion of the ILD layer in the second opening.

[0098] Example 9 is the method of Example 1, further comprising: forming the semiconductor layer on a substrate; patterning the substrate to form a fin, wherein the second nanostructure is disposed on the fin; and trimming the upper portion of the fin prior to growing the epitaxial source / drain region.

[0099] Example 10 is the method of Example 1, wherein forming the gate stack includes: removing the remaining portions of the first nanostructure and the third nanostructure to expose the top and bottom of a second region of the second nanostructure; depositing a gate dielectric around the top and bottom of the second region of the second nanostructure; and forming a gate electrode on the gate dielectric.

[0100] Example 11 is a semiconductor device comprising: a first nanostructure on a substrate, the first nanostructure including a channel region and a first lightly doped source / drain (LDD) region adjacent to the channel region; a first epitaxial source / drain region surrounding four sides of the first LDD region; an interlayer dielectric (ILD) layer on the first epitaxial source / drain region; source / drain contacts extending through the ILD layer surrounding four sides of the first epitaxial source / drain region; and a gate stack adjacent to the source / drain contacts and the first epitaxial source / drain region, the gate stack surrounding four sides of the channel region.

[0101] Example 12 is the device described in Example 11, wherein the first LDD region has a first thickness, the channel region has a second thickness, and the second thickness is greater than the first thickness.

[0102] Example 13 is the device described in Example 11, wherein the first LDD region and the channel region have the same thickness.

[0103] Example 14 is the device described in Example 11, further comprising: a second nanostructure on the substrate, the second nanostructure including a second LDD region; and a second epitaxial source / drain region surrounding four sides of the second LDD region, the source / drain contacts surrounding the four sides of the second epitaxial source / drain region.

[0104] Example 15 is the device described in Example 14, further comprising: a first spacer disposed between the gate stack and the first epitaxial source / drain region, wherein the source / drain contact physically contacts the first spacer; and a second spacer disposed between the gate stack and the second epitaxial source / drain region, wherein the source / drain contact physically contacts the second spacer.

[0105] Example 16 is the device described in Example 14, wherein the source / drain contact has a first portion and a second portion, the first portion extending through the ILD layer, the second portion being disposed between the first epitaxial source / drain region and the second epitaxial source / drain region, and the width of the second portion being greater than the width of the first portion.

[0106] Example 17 is a semiconductor device comprising: a nanostructure on a substrate, the nanostructure including a channel region and a lightly doped source / drain (LDD) region adjacent to the channel region, the channel region having a first width and a first thickness in a first cross-section, the LDD region having a second width and a second thickness in a second cross-section, the second width being less than the first width and the second thickness being less than the first thickness, the first cross-section and the second cross-section being perpendicular to the longitudinal axis of the nanostructure; a gate stack completely surrounding the channel region in the first cross-section; and an epitaxial source / drain region completely surrounding the LDD region in the second cross-section.

[0107] Example 18 is the device described in Example 17, further comprising: an interlayer dielectric (ILD) layer over the epitaxial source / drain region; and source / drain contacts extending through the ILD layer, the source / drain contacts completely surrounding the epitaxial source / drain region in the second cross-section.

[0108] Example 19 is the device described in Example 18, further comprising: a silicide between the source / drain contact and the epitaxial source / drain region, the silicide completely surrounding the epitaxial source / drain region in the second cross section.

[0109] Example 20 is the device described in Example 17, further comprising: an isolation region on the substrate; and a fin having a first portion and a second portion, the first portion extending through the isolation region and the second portion extending above the isolation region, the nanostructure disposed on the fin, the first portion of the fin having a third width and the second portion of the fin having a fourth width, the second width and the fourth width being smaller than the third width.

Claims

1. A method of forming a semiconductor device, comprising: patterning a plurality of semiconductor layers to form a first nanostmcture, a second nanostmcture, and a third nanostmcture, the second nanostmcture disposed between the first nanostmcture and the third nanostmcture; doping a first region of the second nanostmcture with an impurity while covering a second region of the second nanostmcture; removing portions of the first nanostmcture and the third nanostmcture to expose a top and a bottom of the first region of the second nanostmcture; growing epitaxial source / drain regions around the top and the bottom of the first region of the second nanostmcture; depositing a dummy layer around the top and the bottom of the epitaxial source / drain regions, the dummy layer comprising a first dielectric material; depositing an interlayer dielectric (ILD) layer on the dummy layer, the ILD layer comprising a second dielectric material, the second dielectric material different from the first dielectric material; and forming a gate stack around a top and a bottom of the second region of the second nanostmcture.

2. The method of claim 1, further comprising: prior to growing the epitaxial source / drain regions, trimming the first region of the second nanostmcture to reduce a thickness of the first region of the second nanostmcture.

3. The method of claim 2, wherein, after trimming the first region of the second nanostmcture, the thickness of the first region of the second nanostmcture is less than a thickness of the second region of the second nanostmcture.

4. The method of claim 1, further comprising: etching the ILD layer to form a first opening exposing the dummy layer; and etching the dummy layer to enlarge the first opening and expose the epitaxial source / drain regions.

5. The method of claim 4, further comprising: depositing a metal layer in the first opening and around the epitaxial source / drain regions; annealing the metal layer to form silicides around the epitaxial source / drain regions; and depositing a conductive material in the first opening to form source / drain contacts around the silicides. etching the ILD layer comprises etching the second dielectric material at a faster rate than etching the first dielectric material, and etching the dummy layer comprises etching the first dielectric material at a faster rate than etching the second dielectric material. the first dielectric material is silicon carbonitride, and the second dielectric material is silicon oxide.

6. The method of claim 4, wherein, 8. The method of claim 4, further comprising:

7. The method of claim 6, wherein, prior to depositing the ILD layer, etching a second opening in the dummy layer, wherein depositing the ILD layer comprises depositing a portion of the ILD layer in the second opening.

9. The method of claim 1, further comprising: forming the semiconductor layers over a substrate; patterning the substrate to form a fin, the second nanostmcture disposed over the fin; and prior to growing the epitaxial source / drain regions, trimming an upper portion of the fin. forming the gate stack comprises: removing remaining portions of the first nanostmcture and the third nanostmcture to expose a top and a bottom of the second region of the second nanostmcture; ​ 10. The method of claim 1, wherein, ​ ​ depositing a gate dielectric around a top and a bottom of a second region of the second nanostructure; and forming a gate electrode on the gate dielectric.

11. A semiconductor device, comprising: a first nanostructure over a substrate, the first nanostructure comprising a channel region and a first lightly doped source / drain (LDD) region, the first LDD region adjacent to the channel region, the first LDD region having a first thickness, the channel region having a second thickness, and the second thickness greater than the first thickness; a first epitaxial source / drain region surrounding four sides of the first LDD region; an interlayer dielectric (ILD) layer over the first epitaxial source / drain region; a source / drain contact extending through the ILD layer, the source / drain contact surrounding four sides of the first epitaxial source / drain region; and a gate stack adjacent to the source / drain contact and the first epitaxial source / drain region, the gate stack surrounding four sides of the channel region.

12. The device of claim 11, further comprising: a second nanostructure over the substrate, the second nanostructure comprising a second LDD region; a second epitaxial source / drain region surrounding four sides of the second LDD region, the source / drain contact surrounding four sides of the second epitaxial source / drain region.

13. The device of claim 12, further comprising: a first spacer disposed between the gate stack and the first epitaxial source / drain region, the source / drain contact in physical contact with the first spacer; a second spacer disposed between the gate stack and the second epitaxial source / drain region, the source / drain contact in physical contact with the second spacer. the source / drain contact having a first portion extending through the ILD layer and a second portion disposed between the first epitaxial source / drain region and the second epitaxial source / drain region, the second portion having a width greater than a width of the first portion.

15. A semiconductor device, comprising: a nanostructure over a substrate, the nanostructure comprising a channel region and a lightly doped source / drain (LDD) region, the LDD region adjacent to the channel region, the channel region having a first width and a first thickness in a first cross-section, the LDD region having a second width and a second thickness in a second cross-section, the second width less than the first width, the second thickness less than the first thickness, the first cross-section and the second cross-section each perpendicular to a longitudinal axis of the nanostructure; 14. The device of claim 12, wherein, a gate stack completely surrounding the channel region in the first cross-section; and an epitaxial source / drain region completely surrounding the LDD region in the second cross-section.

16. The device of claim 15, further comprising: an interlayer dielectric (ILD) layer over the epitaxial source / drain region; and a source / drain contact extending through the ILD layer, the source / drain contact surrounding four sides of the epitaxial source / drain region. ​ ​ ​ ​ a source / drain contact extending through the ILD layer, the source / drain contact completely surrounding the epitaxial source / drain region in the second cross-section.

17. The device of claim 16, further comprising: a silicide between the source / drain contact and the epitaxial source / drain region, the silicide completely surrounding the epitaxial source / drain region in the second cross-section.

18. The device of claim 15, further comprising: an isolation region above the substrate; and a fin having a first portion and a second portion, the first portion extending through the isolation region, the second portion extending above the isolation region, the nanostructure disposed above the fin, the first portion of the fin having a third width, the second portion of the fin having a fourth width, the second width and the fourth width being less than the third width.

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