Chip-on-lead semiconductor device and chip-on-lead semiconductor device manufacturing method

Abstract

Embodiments of the present disclosure relate to a chip-on-lead semiconductor device and a chip-on-lead semiconductor device manufacturing method. The semiconductor device includes a support substrate having leads arranged therearound, a semiconductor die on the support substrate, and a layer of laser-activatable material molded to the die and the leads. The leads include a proximal portion facing the support substrate and a distal portion facing away from the support substrate. The semiconductor die includes a bond pad at a front surface thereof opposite the support substrate and is arranged onto the proximal portion of the leads. The semiconductor device has a conductive structure laser-structured at selected locations of the laser-activatable material. The conductive structure includes first vias extending between the bond pad and a front surface of the laser-activatable material, second vias extending between the distal portion of the leads and the front surface of the laser-activatable material, and lines extending at the front surface of the laser-activatable material and connecting selected first vias to selected second vias.

Description

[0001] Priority requirements

[0002] This application claims priority to Italian Patent Application No. 102020000031229, filed on December 17, 2020, the contents of which are incorporated herein by reference in their entirety to the fullest extent permitted by law. Technical Field

[0003] This article describes semiconductor devices including chip arrangements on leads, which can be suitable for use in a variety of sectors such as automotive, industrial and / or consumer electronics. Background Technology

[0004] A conventionally packaged semiconductor device may include a metal leadframe comprising a die pad and a set of conductive leads disposed around the die pad (e.g., extending radially around the die pad), and at least one semiconductor die or chip disposed on the die pad (e.g., attached to the die pad). The semiconductor die disposed on the die pad may include a set of bonding pads (e.g., surfaces that may typically be designated as a top surface or upper surface) on its front surface opposite the die pad. The bonding pads may be electrically coupled to the leads of the leadframe via bonding wires (e.g., gold wires). The semiconductor device may also include an encapsulation housing of a plastic material (e.g., resin) that encapsulates the semiconductor die disposed on at least a portion of the die pad, bonding wires, and conductive leads facing the die pad to prevent damage or corrosion.

[0005] In conventional on-chip semiconductor devices, the semiconductor die can be larger than the die pads of the leadframe. Therefore, the semiconductor die can protrude "laterally" from the area of ​​the die pad on which it is disposed, and it can be disposed (at least partially) on (at least some of the ends of the leads) facing the die pad (e.g., the portion of the leads "proximal" to the die pad). This particular arrangement is advantageous for accommodating a relatively large semiconductor die in a relatively small package.

[0006] In on-chip semiconductor devices, the (lateral) sidewalls of the semiconductor die can be located at a short distance from the (lateral) sidewalls of the encapsulation housing, and the area of ​​the leads available for wire bonding inside the housing can be reduced. Therefore, electrically coupling the bonding pads of the semiconductor die to the leads can be cumbersome, and the reliability of wire bonding operations in on-chip semiconductor devices may be negatively impacted.

[0007] Therefore, there is a need in the art to provide improved bonding techniques for on-chip semiconductor devices.

[0008] There is a need in the art for improved bonding techniques that can be used for leaded chip semiconductor devices. Summary of the Invention

[0009] One or more embodiments may relate to semiconductor devices.

[0010] One or more embodiments may relate to corresponding methods of manufacturing semiconductor devices.

[0011] In one or more embodiments, the semiconductor device may include a support substrate, conductive leads disposed around the support substrate, a semiconductor die disposed on the support substrate, and a laser-activated material layer molded onto the semiconductor die and leads. The leads may have a corresponding proximal portion facing the support substrate and a corresponding distal portion facing away from the support substrate. The semiconductor die may have a set of bonding pads on its front surface opposite the support substrate, and the semiconductor die may also be disposed on the proximal portions of one or more leads. The semiconductor device may include laser-structured conductive structures at selected spatial locations of the laser-activated material. The conductive structures may include a first via extending between the bonding pads of the semiconductor die and the front surface of the laser-activated material layer, a second via extending between the distal portion of the lead and the front surface of the laser-activated material layer, and a line extending at the front surface of the laser-activated material layer and connecting the selected first via to the selected second via.

[0012] Therefore, one or more embodiments can facilitate the assembly of relatively large semiconductor dies into relatively small packages, while providing reliable electrical connections between the semiconductor die and leads even in a small space. Attached Figure Description

[0013] One or more embodiments will now be described by way of example only with reference to the accompanying drawings, in which:

[0014] Figure 1 and 2 This is an exemplary cross-sectional side view of certain components of a conventional on-chip semiconductor device;

[0015] Figures 3A to 3H This is an exemplary cross-sectional side view of certain steps of a method for manufacturing an on-chip semiconductor device according to one or more embodiments of this specification;

[0016] Figure 4A Is it as it is? Figure 3E A plan view of the front (e.g., top or upper) surface of a lead-on-chip semiconductor device according to one or more embodiments of this specification after the metal deposition step illustrated in the diagram; and

[0017] Figure 4B Is it as it is? Figure 3E A plan view of the back (e.g., bottom or lower) surface of an on-chip semiconductor device according to one or more embodiments of this specification after the metal deposition step illustrated in the figure. Detailed Implementation

[0018] In the following description, one or more specific details are shown to provide a thorough understanding of examples of embodiments of this specification. Embodiments may be obtained without one or more of these specific details or by other methods, components, materials, etc. In other instances, known structures, materials, or operations have not been shown or described in detail so that certain aspects of the embodiments will not be obscured.

[0019] References to "embodiment" or "an embodiment" within the framework of this specification are intended to indicate that a particular configuration, structure, or feature described with respect to that embodiment is included in at least one embodiment. Therefore, phrases such as "in an embodiment" or "in one embodiment" that may appear at one or more points in this specification do not necessarily refer to one and the same embodiment. Furthermore, in one or more embodiments, particular configurations, structures, or features may be combined in any suitable manner.

[0020] The headings / references used herein are provided for convenience only and therefore do not limit the scope of protection or the scope of the embodiments.

[0021] Throughout the accompanying drawings, unless the context otherwise indicates, the same parts or elements are indicated by the same reference numerals / numbers, and for the sake of brevity, the corresponding descriptions will not be repeated.

[0022] The following detailed description of exemplary embodiments can be first referred to... Figure 1 and 2 , Figure 1 and 2 These are exemplary cross-sectional side views of conventional on-chip semiconductor devices 10 and 10', respectively. In particular, the semiconductor devices 10 and 10' illustrated herein include flat, leadless packages (e.g., QFN packages).

[0023] As in Figure 1 and 2As illustrated, a conventional on-chip semiconductor device includes a lead frame (e.g., a metal lead frame) comprising a die pad 100 and a plurality of conductive leads 102 arranged around the die pad 100. A semiconductor die 12 is disposed on the die pad 100, for example, by means of a non-conductive die attachment material 14. In cases where the semiconductor die 12 is larger than the die pad 100 (e.g., wider and / or longer), it protrudes laterally from the die pad 100 and is disposed on a proximal portion 103 of the lead 102 facing the die pad 100. For example, a peripheral portion of the semiconductor die 12 can be attached to the proximal portion 103 of the lead 102 using the same non-conductive die attachment material 14 for attaching the semiconductor die 12 to the die pad 100.

[0024] As in Figure 1 and Figure 2 As illustrated, a conventional on-chip semiconductor device may include a bonding wire 16 (see example). Figure 1 ) or 16' (see Figure 2 The semiconductor device is arranged to electrically couple bonding pads disposed on the front surface (e.g., top or upper) surface 12a of the semiconductor die 12 to the lead 102. The semiconductor device also includes an encapsulation housing 18 (e.g., a molded housing) comprising a plastic material encapsulating at least a portion of the semiconductor die 12, the die pad 100, the bonding wire 16, and the conductive lead 102 facing the die pad 100. Purely as an example, conventional QFN chip-on-a-chip leaded semiconductor devices 10, 10' can have a diameter of 5 mm × 5 mm (1 mm = 10). -3 The maximum lateral dimension (m).

[0025] Since the semiconductor die 12 is disposed on the proximal portion 103 of the lead 102, the distance (or gap) D1 between the (lateral) sidewall 12b of the semiconductor die 12 and the (lateral) sidewall 18b of the encapsulation housing 18 can be short (e.g., about 0.3 mm). Therefore, the area on the lead 102 available for performing the wire bonding process may be limited, potentially leading to poor reliability of the wire bonding process.

[0026] For example, as in Figure 1 As illustrated, the bonding line 16 can be arranged to have a high "landing angle" on the lead 102, which can result in the bonding seam being mechanically stressed during the lead bonding process. Additionally, the bonding line 16 can be arranged close to the upper edge of the semiconductor die 12, posing a risk of contact with the semiconductor die 12 before or after the molding of the encapsulation housing 18.

[0027] As in Figure 2As illustrated, the bonding line 16' can be arranged to maintain a safe distance from the upper edge of the semiconductor die 12, but this can result in an excessively high wire loop height, posing a risk of sagging and / or damage to the line 16' during or after the molding of the encapsulation housing 18.

[0028] Therefore, one or more embodiments of this specification relate to on-chip semiconductor devices including die-to-wire interconnects implemented by laser direct structuring (LDS) technology, which helps to increase the reliability of the bonding process and provide reliable electrical connections to the wires even in small spaces.

[0029] The following description Figures 3A to 3H This is an exemplary cross-sectional side view of certain steps of a method for manufacturing an on-chip semiconductor device 30 according to one or more embodiments of this specification. It should be noted that, for ease of understanding, various details of the semiconductor device itself will be disclosed with reference to possible manufacturing methods. It should also be noted that... Figures 3A to 3H A pair of semiconductor devices 30 are shown being manufactured, which are cut off at the end of the manufacturing process to separate one of the individual devices from the others, provided that conventional manufacturing processes in the semiconductor industry are performed on multiple batches of devices sharing a common substrate or lead frame (e.g., during a so-called “cut-off” step).

[0030] like Figure 3A As illustrated, the method according to one or more embodiments may include the step of providing other conventional leadframes. For each semiconductor device 30, the leadframe may include a die pad 300 and a corresponding lead 302 arranged around the die pad 300. The lead 302 may include a corresponding proximal (end) portion 303 facing the die pad 300.

[0031] It should be noted that while this specification primarily relates to providing a “lead frame” (e.g., a metal lead frame), one or more embodiments may include a non-conductive support substrate instead of the die pad 300, the support substrate having a conductive structure integrated therein and acting as a “lead,” as in the case of a ball grid array (BGA) package.

[0032] As in Figure 3BAs illustrated, a method according to one or more embodiments may include the step of arranging a semiconductor die 32 on each die pad 300 of a leadframe, depending on the chip configuration on the lead. For example, the semiconductor die 32 may be attached to the die pad 300 via a die attachment material 34 (e.g., a die attachment film). Since the semiconductor die 32 may be larger (e.g., wider and / or longer) than the die pad 300, it may protrude laterally from the die pad 300 and may be arranged on the ends 303 of (at least some) of the leads 302 facing the die pad 300. For example, a peripheral portion of the semiconductor die 32 may be attached to a proximal portion 303 of the lead 302 via a non-conductive die attachment material 34 (e.g., a non-conductive die attachment film). Alternatively, this non-conductive die attachment material may be the same die attachment material used to attach the semiconductor die 32 to the die pad 300 (e.g., a continuous adhesive film 34 may be disposed on the die pad 300 and the end 303 of the lead 302).

[0033] It should be noted that while this specification primarily relates to providing a semiconductor die 32 larger than the die pad 300, one or more embodiments may be applied to any situation where the semiconductor die is at least partially arranged on the lead 302, regardless of its size. For example, a multi-die semiconductor device may include a plurality of semiconductor dies arranged on the die pad 300, none of which are larger than the die pad 300, but at least one of them is at least partially arranged on the lead 302 (e.g., to accommodate a plurality of dies appropriately spaced apart from each other and / or to accommodate die-to-die interconnects).

[0034] As in Figure 3C As illustrated, a method according to one or more embodiments may include the step of providing (e.g., molding) a laser-activated material layer 38 (e.g., a resin material suitable for performing a laser direct structuring (LDS) process) onto a semiconductor die 32 and a lead frame to encapsulate the semiconductor die 32 and the lead frame, thereby leaving the die pads 300 and the lead frame exposed on the rear (e.g., bottom or lower) side.

[0035] By way of example only, the laser-activated material layer 38 may have a thickness T, measured from the front (e.g., top or upper) surface of the substrate (e.g., the front surface 302A of the lead 302 or the front surface of the die pad 300), which is at least 100 μm. Alternatively, the thickness T may be from 100 μm to 140 μm, optionally from 110 μm to 130 μm, optionally about 120 μm (1 μm = 10⁻⁶). -6 Within the range of m).

[0036] According to LDS technology, a laser-activated inorganic metal compound can be provided in a plastic material (or at least a portion 38 of the encapsulation housing in contact with the semiconductor die 32) used for molding a semiconductor device 30. The laser radiation can then be directed onto the laser-activated plastic material 38 to pattern pathways of circuit traces on and within the laser-activated plastic material. Upon impact of the laser radiation onto the plastic material, the metal additive forms laser-activated (e.g., micro-roughened) tracks or lines. The metal particles of these laser-activated tracks or lines form a nucleus for a subsequent metallization step, which grows conductive tracks on the laser-activated plastic material.

[0037] like Figure 3D As shown, a method according to one or more embodiments may include the steps of: directing laser radiation onto a laser-activated material 38 to pattern (or construct) a set of laser-activated lines 36L at a front (e.g., top or upper) surface 38A of the laser-activated material 38, and a laser-activated via 36V extending through the laser-activated material 38 (through-mold via, TMW). The laser-activated via 36V may include via 36V' and via 36V'. Via 36V is configured to couple a laser-activated line 36L extending at the front surface 38A to a bonding pad disposed on the front surface 32A of the semiconductor die 32, and via 36V is configured to couple the laser-activated line 36L to a bonding region on the lead 302. Such laser-activated lines and vias 36L and 36V will therefore serve as "seed" lines and vias for one or more subsequent electroplating steps to provide electrical connection between the bonding pad disposed on the front surface 32A of the semiconductor die 32 and the lead 302. The following will refer to the appendix... Figure 4A and 4B Discuss the various advantages of laser-activated lines and vias 36L and 36V.

[0038] like Figure 3E As shown, the method according to one or more embodiments may include the step of depositing (e.g., growing) a metal layer (e.g., a copper layer) onto laser-activated lines and vias 36L, 36V to provide corresponding conductive lines and vias 37L, 37V. The conductive via 37V (through-mold via, TMW) may therefore include via 37V' and via 37V''. Via 37V is configured to couple a conductive line 37L extending at the front surface 38A to a bonding pad disposed on the front surface 32A of the semiconductor die 32, and via 37V is configured to couple the conductive line 37L to a bonding region on the lead 302.

[0039] The metal layer can be deposited onto the laser-activated lines and vias 36L and 36V by electroless deposition and / or by electroplating (electroplating). Optionally, a first chemical plating step can be performed to provide a first thin layer of metal material (e.g., having a thickness of a few micrometers, such as between 2 μm and 5 μm), and a second electroplating step can be performed to provide a second thick layer of metal material (e.g., having a thickness of tens of micrometers, such as between 10 μm and 100 μm) onto the first metal layer. The following will refer to the appendix. Figure 4A and 4B Discuss the various advantageous details of conductive lines and vias 37L and 37V.

[0040] like Figure 3F As shown, the method according to one or more embodiments may include the step of providing an encapsulation layer 39 (e.g., comprising a plastic material) to encapsulate the conductive wire 37L. The material of the encapsulation layer 39 may be, for example, the same plastic material used to perform the LDS process, with or without a laser-activated metal additive compound. Alternatively, the material of the encapsulation layer 39 may be a different material (e.g., a photoresist material) and may be deposited by means of any suitable deposition technique.

[0041] like Figure 3G As shown, the method according to one or more embodiments may include in Figure 3F The step of providing (e.g., electroplating) a metal layer 304 on the exposed (back) surfaces of the die pads 300 and / or leads 302 after the encapsulation of the illustrated semiconductor device 30. The metal layer 304 may include tin (Sn). Such a step is purely optional and can be avoided, for example, in the case where the lead frame is of the pre-plated type (e.g., it is provided by the beginning having a tin-plated layer on its back surface).

[0042] like Figure 3H As illustrated, a method according to one or more embodiments may include the step of separating semiconductor devices 30 from each other, for example by cutting or sawing along a cutting line X30 (“cutting” step).

[0043] Therefore, relying on the LDS technology used to manufacture die-to-lead interconnects 37L, 37V can facilitate the provision of reliable electrical connections, even when the distance (or gap) D3 between the (lateral) sidewall 32B of the semiconductor die 32 and the (lateral) sidewall 38B of the encapsulation housing 38 is short, as in the on-chip QFN semiconductor device illustrated herein.

[0044] In this regard, we can refer to Figure 4A and Figure 4B , Figure 4A and Figure 4BThese are plan views of the front (e.g., top or upper) and rear (e.g., bottom or lower) surfaces of the on-chip semiconductor device 30 after a metal deposition step, according to one or more embodiments of this specification, as shown in... Figure 3E exemplified in .

[0045] In one or more embodiments, the vias 37V' and / or 37V” may have a cross-section (e.g., a circular cross-section) having a smaller dimension (e.g., diameter) of at least 30 μm. Optionally, the smaller dimension may be in the range of 30 μm to 70 μm. Optionally, the smaller dimension may be in the range of 40 μm to 60 μm. Optionally, the smaller dimension may be equal to about 50 μm.

[0046] It should be noted that the process of fabricating through-hole vias by direct laser structuring can result in vias 37V' and 37V' having a generally conical shape (i.e., a cross-section with its area decreasing from the surface 38A of the LDS material toward the surface 32A of the semiconductor die 32 and / or the surface of the lead 302). This may be due, for example, to losses in laser focusing at different depths through the LDS material 38. Therefore, when referring to the “size” or “diameter” of the via 37V or the line 37L in the context of this specification, such size or diameter is intended to be measured at the front surface 38A of the LDS material 38, where the laser beam is positioned at... Figure 3D The steps illustrated in the example are focused on.

[0047] In such a state Figure 4A and 4B In one or more embodiments illustrated, the lead via 37V” may have an elliptical or elongated cross-section of a certain type, having a first diameter d (or secondary axis) measured in a direction perpendicular to the respective (lateral) sidewalls 32B and 38B of the semiconductor die 32 and the encapsulation housing 38, and a second diameter D (or primary axis) measured in a direction parallel to the respective (lateral) sidewalls 32B and 38B and parallel to the plane of the front surface 32A of the semiconductor die 32.

[0048] In one or more embodiments, the length of the first diameter d can be at least 30 μm. Optionally, the length of the first diameter d can be in the range of 30 μm to 70 μm. Optionally, the length of the first diameter d can be in the range of 40 μm to 60 μm. Optionally, the length of the first diameter d can be approximately 50 μm.

[0049] In one or more embodiments, the length of the second diameter D can be determined as a function of the thickness T of the LDS material 38 measured relative to the front surface 302A of the lead 302 (i.e., the length of the second diameter D can be determined as a function of the depth of the via 37V”). For example, the length of the second diameter D can be equal to at least 0.8*T. Optionally, the length of the second diameter D can be in the range of 0.8*T to 1.2*T. Optionally, the length of the second diameter D can be in the range of 0.9*T to 1.1*T. Optionally, the length of the second diameter D can be equal to approximately T.

[0050] In one or more embodiments, providing an elliptical via 37V” can help overcome the conventional electroplating process design rules (applicable to circular vias) that rely on a 1:1 aspect ratio (diameter to depth) of the via. With an elliptical via, the shorter diameter d can be as short as 30 μm, while the longer diameter D can be approximately equal to the thickness T of the LDS material 38.

[0051] Alternatively or additionally, the length of the second diameter D can be determined as a function of the width W of the conductive lead 302. For example, the length of the second diameter D can be equal to the width W minus the precision of the laser beam used during the LDS method. This precision can be, for example, in the range of 10 μm to 20 μm, and may be equal to 15 μm.

[0052] It should be noted that although this specification primarily relates to providing an elliptical or elongated via 37V", one or more embodiments may include vias 37V" having other shapes (e.g., square or rectangular), which may also be defined with reference to the first axis and the second axis.

[0053] In one or more embodiments, the distance (or gap) d3 between the (lateral) sidewall of via 37V” and the corresponding (lateral) sidewall 32B of the semiconductor die 32 can be selected based on the precision of the laser beam used during the LDS process. Additionally or alternatively, the distance (or gap) d3 between the (lateral) sidewall of via 37V” and the corresponding (lateral) sidewall 38B of the package housing 38 can be selected based on the precision of the laser beam used during the LDS process. For example, such distances d3 and / or d3' can be at least 10 μm. Optionally, distances d3 and / or d3' can be in the range of 10 μm to 50 μm. Optionally, distances d3 and / or d3' can be in the range of 15 μm to 30 μm. Optionally, distances d3 and / or d3' can be equal to 20 μm.

[0054] Therefore, in one or more embodiments, providing a via 37 with a small first diameter d (e.g., as small as 30 μm) is beneficial for manufacturing on-chip semiconductor devices, wherein the distance D3 between the (lateral) sidewall 32B of the semiconductor die 32 and the (lateral) sidewall 38B of the package housing 38 is short.

[0055] For example, in the purely exemplary case where via 37” has a secondary axis d of 30 μm and is spaced 15 μm from each of walls 32B and 38B, the distance D3 can be as short as 60 μm. In another purely exemplary case where via 37” has a secondary axis d of 50 μm and is spaced 30 μm from each of walls 32b and 38b, the distance D3 can be as short as 110 μm.

[0056] Therefore, in one or more embodiments, the semiconductor die 32 may even be arranged over most of the area of ​​the lead 302.

[0057] Therefore, one or more embodiments may provide one or more of the following advantages: the area of ​​the semiconductor die 32 can be the same as the area of ​​the encapsulation housing, minus a certain margin or gap D3 on each side, wherein the margin can be as small as, for example, 60 μm or 110 μm; short leads 302 can be used on conventional QFN chip-based leaded semiconductor devices; the semiconductor die bonding process can be made less critical and more reliable compared to conventional wire bonding processes; and the contact area of ​​the elliptical / elongated via 37V” can be increased compared to conventional circular vias.

[0058] As illustrated herein, a semiconductor device (e.g., 30) may include: a support substrate (e.g., 300); conductive leads (e.g., 302) disposed around the support substrate, the conductive leads including a respective proximal portion (e.g., 303) facing the support substrate and a respective distal portion facing away from the support substrate; a semiconductor die (e.g., 32) disposed (e.g., 34) on the support substrate and disposed on the proximal portions of one or more conductive leads, the semiconductor die including a set of bonding pads (e.g., 32A) on its front surface opposite the support substrate; a laser-activated material layer (e.g., 38) molded onto the semiconductor die and the conductive leads; and a laser-structured conductive structure (e.g., 37L, 37V) at selected spatial locations of the laser-activated material.

[0059] As illustrated herein, the conductive structure may include: i) a first conductive via (e.g., 37V') extending between a bonding pad at the front surface of a semiconductor die and the front surface of a laser-activated material layer (e.g., 38A); ii) a second conductive via (e.g., 37V”) extending between a distal portion of a conductive lead and the front surface of the laser-activated material layer; and iii) a conductive line (e.g., 37L) extending at the front surface of the laser-activated material layer and connecting the selected first conductive via to the selected second conductive via.

[0060] As illustrated herein, the first and second conductive vias may have a cross-section of at least 30 μm with a smaller dimension (e.g., d), optionally in the range of 30 μm to 70 μm, optionally in the range of 40 μm to 60 μm, and optionally about 50 μm.

[0061] As illustrated herein, the second conductive via may have an elongated cross-section (e.g., approximately elliptical or rectangular) having a secondary axis (e.g., d) extending in a direction perpendicular to the respective sidewall (e.g., 32B) of the semiconductor die and a primary axis (e.g., D) extending in a direction parallel to the respective sidewall and the front surface of the semiconductor die.

[0062] As illustrated herein, the length of the secondary axis of the second conductive via can be at least 30 μm, optionally in the range of 30 μm to 70 μm, optionally in the range of 40 μm to 60 μm, or optionally about 50 μm.

[0063] As illustrated herein, the laser-activated material layer may have a thickness T, and the length of the main axis of the second conductive via may be equal to at least 0.8*T, optionally in the range of 0.8*T to 1.2*T, optionally in the range of 0.9*T to 1.1*T, optionally approximately the same as T.

[0064] As illustrated herein, the thickness T may be at least 100 μm, optionally in the range of 100 μm to 140 μm, optionally in the range of 110 to 130 μm, and optionally about 120 μm.

[0065] As illustrated herein, the conductive lead may have a width W, and the length of the main axis of the second conductive via may be equal to the width W minus a value in the range of 10 μm to 20 μm, optionally minus a value of 15 μm.

[0066] As illustrated herein, the distance (e.g., d3) between the second conductive via and the corresponding sidewall of the semiconductor die may be at least 10 μm, optionally in the range of 10 μm to 50 μm, optionally in the range of 15 μm to 30 μm, and optionally about 20 μm.

[0067] As illustrated herein, the distance (e.g., d3') between the second conductive via and the corresponding sidewall of the laser-activated material layer can be at least 10 μm, optionally in the range of 10 μm to 50 μm, optionally in the range of 15 μm to 30 μm, and optionally about 20 μm.

[0068] As illustrated herein, a semiconductor device may also include an encapsulating material layer (e.g., 39) deposited on the front surface of a laser-activated material layer to encapsulate conductive lines.

[0069] As illustrated herein, the semiconductor device may also include a non-conductive die attachment material layer (e.g., 34) that attaches the semiconductor die to a support substrate and to the proximal portion of one or more conductive leads in a conductive lead network. The non-conductive die attachment material may optionally include a die attachment film.

[0070] As illustrated in this article, the semiconductor die disposed on the support substrate can be longer and / or wider than the support substrate.

[0071] As illustrated in this article, the support substrate may include the die pads of a metal lead frame.

[0072] As illustrated herein, conductive structures may include metallic materials deposited by means of electroless deposition and / or electroplating deposition.

[0073] As illustrated herein, a method of manufacturing a semiconductor device may include: providing a support substrate and conductive leads disposed around the support substrate, wherein the conductive leads include a corresponding proximal portion facing the support substrate and a corresponding distal portion facing away from the support substrate; disposing a semiconductor die on the support substrate and on the proximal portions of one or more conductive leads, wherein the semiconductor die includes a set of bonding pads on its front surface opposite the support substrate; forming a laser-activated material layer on the semiconductor die and the conductive leads; and directing laser radiation onto the laser-activated material layer to pattern a set of laser-activated structures.

[0074] The group of laser-activated structures includes: i) a first laser-activated via extending between a bonding pad on the front surface of a semiconductor die and the front surface of a laser-activated material layer; ii) a second laser-activated via extending between the distal portion of a conductive lead and the front surface of a laser-activated material layer; and iii) a laser-activated line extending on the front surface of a laser-activated material layer and connecting the selected first laser-activated via to the selected second laser-activated via.

[0075] The manufacturing method may further include depositing a metal layer onto a first laser-activated via, a second laser-activated via, and a laser-activated line to provide corresponding first conductive via, second conductive via, and conductive line (37L).

[0076] Without prejudice to the fundamental principles, details and embodiments may vary, even significantly, from the content and embodiments described as examples only, without departing from the scope of protection.

Claims

1. A semiconductor device, comprising: Supporting base; A conductive lead is arranged around the supporting substrate, the conductive lead including a corresponding proximal portion facing the supporting substrate and a corresponding distal portion facing away from the supporting substrate; A semiconductor die is disposed on the support substrate and on the proximal portion of one or more conductive leads in the conductive leads, the semiconductor die including a set of bonding pads on the front surface of the semiconductor die opposite to the support substrate; Lasers molded onto the semiconductor die and the conductive leads can activate material layers; as well as A conductive structure, wherein the conductive structure comprises: i) A first conductive via extends between the set of bonding pads on the front surface of the semiconductor die and the front surface of the laser-activated material layer; ii) A second conductive via extending between the distal portion of the conductive lead and the front surface of the laser-activated material layer, wherein the second conductive via has an elliptical cross-section having a secondary axis and a primary axis, the secondary axis extending in a direction perpendicular to the corresponding sidewall of the semiconductor die, and the primary axis extending in a direction parallel to the corresponding sidewall of the semiconductor die and the front surface of the semiconductor die; and iii) Conductive lines extending at the front surface of the laser-activated material layer and connecting the selected first conductive via to the selected second conductive via.

2. The semiconductor device according to claim 1, wherein the first conductive via and the second conductive via have a cross-section with a smaller size of at least 30 μm.

3. The semiconductor device according to claim 2, wherein the length of the secondary axis is equal to at least 30 μm.

4. The semiconductor device of claim 3, wherein the laser-activated material layer has a thickness T, and wherein the length of the main axis is equal to at least 0.8*T.

5. The semiconductor device of claim 4, wherein the thickness T is equal to at least 100 μm.

6. The semiconductor device of claim 3, wherein the conductive lead has a width W, and wherein the length of the main axis is equal to the width W minus a value in the range of 10 μm to 20 μm.

7. The semiconductor device of claim 1, wherein the distance between the second conductive via and the corresponding sidewall of the semiconductor die is at least 10 μm.

8. The semiconductor device of claim 1, wherein the distance between the second conductive via and the corresponding sidewall of the laser-activated material layer is equal to at least 10 μm.

9. The semiconductor device of claim 1, further comprising an encapsulation material layer on the front surface of the laser-activated material layer for encapsulating the conductive wire.

10. The semiconductor device of claim 1, further comprising a non-conductive die attachment material layer that attaches the semiconductor die to the support substrate and to the proximal portion of one or more of the conductive leads.

11. The semiconductor device of claim 10, wherein the non-conductive die attachment material layer comprises a die attachment film.

12. The semiconductor device of claim 1, wherein the semiconductor die disposed on the supporting substrate is larger than the corresponding size of the supporting substrate.

13. The semiconductor device of claim 1, wherein the supporting substrate comprises die pads of a metal lead frame.

14. The semiconductor device of claim 1, wherein the conductive structure comprises a metallic material.

15. A method for manufacturing a semiconductor device, the method comprising: A semiconductor die is disposed on a support substrate and on a proximal portion of one or more conductive leads disposed around the support substrate, such that the conductive leads have a corresponding proximal portion facing the support substrate and a corresponding distal portion facing away from the support substrate, wherein the semiconductor die includes a set of bonding pads on the front surface of the semiconductor die opposite to the support substrate. A laser-activated material layer is formed on the semiconductor die and the conductive leads; Guiding laser radiation onto the laser-activated material layer to pattern a set of laser-activated structures, wherein patterning the set of laser-activated structures includes: i) Patterning a first laser-activated via, the first laser-activated via extending between the set of bonding pads on the front surface of the semiconductor die and the front surface of the laser-activated material layer. ii) Patterning the second laser-activated via such that the second laser-activated via has an elliptical cross-section and extends between the distal portion of the conductive lead and the front surface of the layer of laser-activated material, and iii) Patterning laser-activated lines, the laser-activated lines extending at the front surface of the laser-activated material layer and connecting a selected first laser-activated via to a selected second laser-activated via. as well as A metal layer is deposited onto the first laser-activated via, the second laser-activated via, and the laser-activated line to provide a corresponding first conductive via, second conductive via, and conductive line.

16. The method of claim 15, further comprising depositing an encapsulating material layer onto the front surface of the laser-activated material layer to encapsulate the conductive wire.

17. The method of claim 15, further comprising using a non-conductive die attachment material layer to attach the semiconductor die to the support substrate and to the proximal portion of one or more of the conductive leads.

18. The method of claim 17, wherein the non-conductive die attachment material layer comprises a die attachment film.

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