Semiconductor structure and method of forming a semiconductor structure

Abstract

A semiconductor structure and a method for forming the same, the structure comprising: a substrate including a scribe line region, the scribe line region including a cutout region, the cutout region including a plurality of probe regions arranged along the scribe line region and a plurality of spacer regions between adjacent probe regions, at least one of the spacer regions being a device region and at least one of the spacer regions being an antenna region, the device region and the antenna region being separate from each other; a structure to be tested located on the device region; and an antenna structure located on the antenna region, the antenna structure being electrically connected to the structure to be tested, the antenna structure projected onto the substrate surface being an annular shape. The performance of the semiconductor structure is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the semiconductor structure. Background Technology

[0002] During wafer fabrication, the electrical performance of the wafer needs to be tested. Typically, this testing involves using probes to contact test structures on the wafer. As chips become increasingly miniaturized, their area shrinks, while the test structures, which need to interact with the probes, cannot be reduced in size. Therefore, to increase the utilization rate of the chip's effective area, the test structures are formed on the wafer's dicing area, allowing them to be removed during subsequent wafer dicing.

[0003] However, existing test structures located on the cutting area still pose a risk of affecting the structure on the chip area. Summary of the Invention

[0004] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the semiconductor structure, so as to improve the situation where the test structure on the dicing region affects the structure on the chip region.

[0005] To address the aforementioned technical problems, the present invention provides a semiconductor structure comprising: a substrate, the substrate including a dicing region, the dicing region including a cut-off region, the cut-off region including a plurality of probe regions arranged along the extension direction of the dicing region and a plurality of spacer regions located between adjacent probe regions, at least one of the spacer regions being a device region, at least one of the spacer regions being an antenna region, and the device region and the antenna region being discrete from each other; a structure to be tested located on the device region; and an antenna structure located on the antenna region, the antenna structure being electrically connected to the structure to be tested, the projection pattern of the antenna structure on the substrate surface being annular.

[0006] Optionally, the projection pattern of the antenna structure onto the substrate surface is a concentric ring.

[0007] Optionally, the antenna structure includes: a multi-layer metal structure, wherein a single-layer metal structure includes several annular first metal layers, the several annular first metal layers being concentrically ringed and mutually independent; and adjacent first metal layers are electrically connected by several first plugs.

[0008] Optionally, the ring may be circular or elliptical.

[0009] Optionally, the projection of the antenna structure onto the substrate surface is within the area of ​​the cut-off region.

[0010] Optionally, the structure under test includes a transistor; the transistor includes a gate structure and source doped regions and drain doped regions located in the device regions on both sides of the gate structure, the source doped regions and drain doped regions being located on both sides of the gate structure along the extension direction of the diced channel region; the antenna structure is electrically connected to the gate structure.

[0011] Optionally, it also includes: a conductive structure located on several of the probe regions; the conductive structure includes: multiple layers of second metal layers; adjacent two layers of second metal layers are electrically connected by several second plugs.

[0012] Optionally, the conductive structure on the probe region is electrically connected to one or more of the gate structure, source doped region, drain doped region, and substrate.

[0013] Optionally, the width of the excised area in the direction perpendicular to the extension of the cutting channel ranges from 0 micrometers to 40 micrometers.

[0014] Optionally, the substrate further includes a plurality of chip regions arranged in an array; the dicing area is located between adjacent chip regions.

[0015] Optionally, the cutting channel area further includes a buffer zone located between the cut-off area and the chip area, with a gap between the cut-off area and the buffer zone, and the buffer zone extending in the same direction as the cutting channel area.

[0016] Optionally, it may also include: a plurality of buffer structures located on the buffer zone, wherein the plurality of buffer structures are arranged along the extension direction of the cutting channel zone.

[0017] Optionally, the buffer structure includes: several third metal layers; adjacent third metal layers are electrically connected by several third plugs.

[0018] Optionally, several of the third metal layers are arranged in parallel along the extension direction of the dicing zone.

[0019] Optionally, the spacing between the buffer structure and the conductive structure on the probe region is in the range of 10 mm to 15 mm.

[0020] Accordingly, the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a dicing region, the dicing region including a cut-off region, the cut-off region including a plurality of probe regions arranged along the extension direction of the dicing region and a plurality of spacer regions located between adjacent probe regions, at least one of the spacer regions being a device region, at least one of the spacer regions being an antenna region, and the device region and the antenna region being discrete from each other; forming a structure to be tested on the device region; forming an antenna structure on the antenna region, the antenna structure being electrically connected to the structure to be tested, and the projection pattern of the antenna structure on the substrate surface being annular.

[0021] Optionally, the projection pattern of the antenna structure onto the substrate surface is a concentric ring.

[0022] Optionally, the antenna structure includes: a multi-layer metal structure, wherein a single-layer metal structure includes several annular first metal layers, the several annular first metal layers being concentrically ringed and mutually independent; and adjacent first metal layers are electrically connected by several first plugs.

[0023] Optionally, the ring may be circular or elliptical.

[0024] Optionally, the projection of the antenna structure onto the substrate surface is within the area of ​​the cut-off region.

[0025] Optionally, the structure under test includes a transistor; the transistor includes a gate structure and source doped regions and drain doped regions located in the device regions on both sides of the gate structure, the source doped regions and drain doped regions being located on both sides of the gate structure along the extension direction of the diced channel region; the antenna structure is electrically connected to the gate structure.

[0026] Optionally, while forming the antenna structure on the antenna region, the method also includes: forming a conductive structure on a plurality of probe regions; the conductive structure includes: multiple layers of second metal layers; adjacent two layers of second metal layers are electrically connected through a plurality of second plugs.

[0027] Optionally, the conductive structure on the probe region is electrically connected to one or more of the gate structure, source doped region, drain doped region, and substrate.

[0028] Optionally, the width of the excised area in the direction perpendicular to the extension of the cutting channel ranges from 0 micrometers to 40 micrometers.

[0029] Optionally, the substrate further includes a plurality of chip regions arranged in an array; the dicing area is located between adjacent chip regions.

[0030] Optionally, the cutting channel area further includes a buffer zone located between the cut-off area and the chip area, with a gap between the cut-off area and the buffer zone, and the buffer zone extending in the same direction as the cutting channel area.

[0031] Optionally, while forming the antenna structure on the probe region, the method also includes forming a plurality of buffer structures on the buffer zone, wherein the plurality of buffer structures are arranged along the extension direction of the cutting channel region.

[0032] Optionally, the buffer structure includes: several third metal layers; adjacent third metal layers are electrically connected by several third plugs.

[0033] Optionally, several of the third metal layers are arranged in parallel along the extension direction of the dicing zone.

[0034] Optionally, the spacing between the buffer structure and the conductive structure on the probe region is in the range of 10 mm to 15 mm.

[0035] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0036] The semiconductor structure in this invention includes an antenna structure located on the antenna region, which is electrically connected to the structure under test. The projection pattern of the antenna structure onto the substrate surface is ring-shaped. Therefore, while ensuring the maximum length of a single antenna structure, the antenna structure can be located within the cut-off region. This allows the structure under test and the antenna structure to be removed simultaneously when the cut-off region is subsequently removed using a laser or a cutting wheel. This reduces the risk of breakage of the structure under test and the antenna structure when they are not completely within the cut-off region, which could lead to delamination and crack propagation affecting other areas of the substrate, thus improving the performance of the semiconductor structure.

[0037] Furthermore, since the structure under test and the antenna structure are located within the cut-off region, the size of the structure under test and the antenna structure becomes smaller. Consequently, the number of antenna structures needs to be increased to meet design requirements. As a result, the number of probe regions is much greater than the number of conductive structures. Therefore, it is not possible to form conductive structures with the same number of probe regions, thereby reducing the number of conductive structures, reducing the device density on the cut-off region, and reducing the resistance to removing the cut-off region.

[0038] Furthermore, the cut-out area also includes a buffer zone. While forming the antenna structure on the antenna region, several buffer structures are also formed on the buffer zone, and these buffer structures are arranged along the extension direction of the cut-out area. The buffer structures can buffer the stress generated during the removal of the cut-out area, preventing damage to the chip region from the stress generated during the removal of the cut-out area. Attached Figure Description

[0039] Figure 1 and Figure 2 These are a top view and a partial cross-sectional view of a semiconductor structure in one embodiment;

[0040] Figures 3 to 9 These are top views and partial cross-sectional views of the semiconductor structure formation process in embodiments of the present invention. Detailed Implementation

[0041] As described in the background section, existing test structures located on the cutting area still pose a risk of affecting the structure on the chip area. This will now be analyzed and explained with reference to specific embodiments.

[0042] Figure 1 and Figure 2These are a top view and a partial cross-sectional view of a semiconductor structure in one embodiment.

[0043] Please refer to Figure 1 and Figure 2 , Figure 1 This is a top view of a semiconductor structure, omitting the dielectric structure. Figure 2 yes Figure 1 A cross-sectional structural diagram along section line AA1 includes: a substrate (not shown), the substrate including a test region 100 and a chip region (not shown), the test region 100 being located between adjacent chip regions, the test region 100 including a first region I, a second region II, and a third region III arranged along the extension direction X of the test region 100, the number of third regions III being multiple, the multiple third regions III being arranged alternately along the extension direction X of the test region 100, the number of second regions II being multiple, the multiple second regions II being arranged alternately along the extension direction X of the test region 100, the first region I being located between adjacent third regions, and the second region II being located between adjacent third regions III; a gate structure 1 located on the first region I. 01; Source region 102 and drain region 103 located in the first region I on both sides of the gate structure 101 extending along the X direction of the test region 100; Antenna structure 104 located on the second region II, the antenna structure 104 being electrically connected to the gate structure 101, the antenna structure including a plurality of metal layers 107 and plugs 106 electrically connecting adjacent metal layers 107; Conductive structure 105 located on the third region III, the substrate, gate structure 101, source region 102 and drain region 103 being respectively connected to one of the conductive structures 105 (not shown); Dielectric structure (not shown) located on the substrate, the dielectric structure including multiple dielectric layers, the gate structure 101, antenna structure 104 and conductive structure 105 being located within the dielectric structure.

[0044] The formation of the semiconductor structure requires multiple depositions and etchings of dielectric and metal materials to form multiple dielectric and metal layers. These deposition and etching processes typically involve a large amount of plasma, which conducts along the metal layers. If the metal layers are electrically connected to the gate structure 101, the plasma will be conducted to the gate structure 101, causing damage. The greater the number and density of metal layers electrically connected to the gate structure 101, the greater the amount and energy of plasma conducted to it, and thus the greater the degree of damage to the gate structure 101. Therefore, the semiconductor structure is a test structure for testing the degree of damage to the gate structure 101 caused by plasma. Within the range of metal density allowed by the design rules, the density and number of metal layers electrically connected to the gate structure 101 are maximized to conduct a limit test on the plasma damage to the gate structure 101. If the performance of the semiconductor structure can be tested OK when the metal layers electrically connected to the gate structure 101 are at their maximum density and number, then semiconductor structures with metal density within the design rules can be considered to have plasma damage to the gate structure 101 within an acceptable range.

[0045] Since the substrate, gate structure 101, source region 102, and drain region 103 are each connected to one of the conductive structures 105, and the conductive structure 105 is used to apply voltage to the substrate, gate structure 101, source region 102, and drain region 103, a high metal density in the conductive structure 105 will increase the resistance of the circuit, affecting the performance of the semiconductor structure. Therefore, multiple antenna structures 104 electrically connected to the gate structure 101 are required, and the length of the metal layer 107 of the antenna structure 104 within the test region 100 should be maximized to increase the metal density of the semiconductor structure.

[0046] However, the test area 100 is the cutting channel of the substrate. After the semiconductor structure is tested, the substrate needs to be cut along the cutting channel using laser cutting or a cutting wheel. The semiconductor structure will be cut during the cutting process. Due to the high metal density of the semiconductor structure, i.e., the long length and large number of metal layers 107, the stress generated by the antenna structure 104 is large. When the laser or cutting wheel cuts the semiconductor structure, it will cut from the middle of the antenna structure 104. Therefore, during the cutting, delamination and cracks will extend from the fracture point of the semiconductor structure to both sides of the test area 100. The delamination and cracks may even extend into the chip area, thereby damaging the chip.

[0047] To address the aforementioned problems, the present invention provides a semiconductor structure and a method for forming the semiconductor structure, by making the projection pattern of the antenna structure on the substrate surface into a ring shape. Therefore, while ensuring the maximum length of a single antenna structure, the antenna structure can be located within the cut-off region. This allows the test structure and the antenna structure to be removed simultaneously when the cut-off region is subsequently removed using a laser or a cutting wheel. This reduces the risk of breakage of the test structure and antenna structure during the removal of the cut-off region when they are not completely within it, which could lead to delamination and crack propagation affecting other areas of the substrate, thereby improving the performance of the semiconductor structure.

[0048] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0049] Figures 3 to 9 These are top views and partial cross-sectional views of the semiconductor structure formation process in embodiments of the present invention.

[0050] Please refer to Figure 3 A substrate is provided, the substrate including a dicing region 200, the dicing region 200 including a cut-out region 201, the cut-out region 201 including a plurality of probe regions I arranged along the extension direction X of the dicing region 200 and a plurality of spacer regions II located between adjacent probe regions I, at least one of the spacer regions II being a device region, at least one of the spacer regions II being an antenna region, and the device region and the antenna region being separate from each other.

[0051] In this embodiment, the substrate further includes a plurality of chip regions (not shown) arranged in an array; the dicing channel region 200 is located between adjacent chip regions.

[0052] In this embodiment, the cutting channel area 200 further includes a buffer zone 202, which is located between the cut area 201 and the chip area. There is a gap between the cut area 201 and the buffer zone 202, and the extension direction of the buffer zone 202 is the same as the extension direction X of the cutting channel area 200.

[0053] The probe region I is used to form a conductive structure on the probe region I for electrical connection with an external probe; the spacer region II is used to form a device and antenna structure on the spacer region II; the buffer 202 is used to form a buffer structure on the buffer 202.

[0054] The width of the excised area 201 in the direction X perpendicular to the extension of the cutting channel area 200 ranges from 0 micrometers to 40 micrometers. Subsequently, the excised area 201 is removed using a laser or a scalpel wheel.

[0055] In this embodiment, the width of the cut area 201 in the direction X perpendicular to the extension of the dicing area 200 ranges from 0 micrometers to 20 micrometers. This width of 0 to 20 micrometers ensures that when the cut area 201 is removed using a laser or a scalpel, its width is within the range that can be removed in one cut by the laser or scalpel. This allows the device structure subsequently formed on the cut area 201 to be completely removed, avoiding situations where the device structure cannot be completely removed and breaks, easily leading to delamination and crack propagation affecting other areas of the substrate, thereby improving the performance of the semiconductor structure.

[0056] In this embodiment, the substrate is made of silicon.

[0057] In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0058] Please refer to Figure 4 The structure to be tested is formed on the device region.

[0059] In this embodiment, the structure to be tested includes a transistor; the transistor includes a gate structure 203 and a source doped region 204 and a drain doped region 205 located in the device regions on both sides of the gate structure 203, the source doped region 204 and the drain doped region 205 being located on both sides of the gate structure 203 along the extension direction X of the dicing region.

[0060] The gate structure 203 includes: a gate dielectric layer (not shown) and a gate layer (not shown) located on the gate dielectric layer.

[0061] The material of the gate dielectric layer includes silicon oxide or a low-K (K less than 3.9) material; the material of the gate layer includes polysilicon.

[0062] The source doped region 204 and the drain doped region 205 contain doped ions, which are of the N-type or P-type. The N-type ions include phosphorus ions, arsenic ions, or antimony ions; the P-type ions include boron ions, boron-fluorine ions, or indium ions.

[0063] In other embodiments, the gate structure further includes a work function layer located between the gate dielectric layer and the gate layer.

[0064] In other embodiments, the material of the gate dielectric layer includes a high dielectric constant material with a dielectric constant greater than 3.9, and the high dielectric constant material includes aluminum oxide or hafnium oxide; the material of the gate layer includes a metal, and the metal includes tungsten; the material of the work function layer includes an N-type work function material or a P-type work function material, the N-type work function material includes titanium aluminum, and the P-type work function material includes titanium nitride or tantalum nitride.

[0065] The processes and methods for forming the transistors are common techniques in the field and will not be described in detail here.

[0066] In this embodiment, the method further includes forming a first dielectric layer (not shown) on a substrate, wherein the transistor is located within the first dielectric layer.

[0067] The material of the first dielectric layer includes a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon carbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon carbide nitride.

[0068] In other embodiments, the structure to be tested may also include other semiconductor structures that need to be tested.

[0069] Please refer to Figure 5 and Figure 6 , Figure 6 for Figure 5 A partially enlarged schematic diagram of the antenna structure shows that the antenna structure is formed on the antenna region and is electrically connected to the structure under test. The projection pattern of the antenna structure on the substrate surface is ring-shaped.

[0070] In this embodiment, the projection pattern of the antenna structure onto the substrate surface is a concentric ring. In other embodiments, the projection pattern of the antenna structure onto the substrate surface is a single ring.

[0071] In this embodiment, the projection of the antenna structure onto the substrate surface is within the area of ​​the cut-off region 201. Therefore, when the cut-off region 201 is subsequently removed using a laser or a squeegee, the width of the cut-off region 201 is within the range that the laser or squeegee can remove in one stroke. This ensures that the test structure and antenna structure formed on the cut-off region 201 can be completely removed, avoiding the situation where the test structure and antenna structure cannot be completely removed during the removal of the cut-off region 201, leading to breakage, delamination, and crack propagation that could affect other areas of the substrate, thereby improving the performance of the semiconductor structure.

[0072] In this embodiment, the antenna structures are interconnected via connection structure 220 and electrically connected to the gate structure 203 via connection structure 220. The antenna structures are used to conduct plasma generated during the semiconductor structure formation process to the gate structure 203 to verify the limits of plasma damage to the gate structure 203. The antenna structure includes: a multilayer metal structure, wherein each single-layer metal structure includes a plurality of annular first metal layers 206, which are concentrically arranged and separated from each other; adjacent first metal layers 206 are electrically connected via a plurality of first plugs 207.

[0073] In this embodiment, the connection structure 220 is electrically connected to the bottom metal structure of the antenna structure, that is, electrically connected to the bottom concentric ring of several first metal layers 206.

[0074] In other embodiments, the connection structure is electrically connected to other layers of the metal structure of the antenna structure.

[0075] The material of the first metal layer 206 includes metal, which includes one or more combinations of copper, aluminum, tungsten, cobalt, nickel and tantalum; the material of the first plug 207 includes metal, which includes one or more combinations of copper, aluminum, tungsten, cobalt, nickel and tantalum.

[0076] The ring can be circular or elliptical.

[0077] In this embodiment, the ring shape includes an ellipse. Within the width of the cut area 201 and the length of the spacer area II along the X-direction of the cut area 200, the elliptical annular first metal layer 206 can have a large perimeter, and the single-layer metal structure includes several annular first metal layers 206, thereby enabling the antenna structure to maximize metal density to meet design requirements.

[0078] In this embodiment, the number of antenna structures is at least one. The specific number is determined by meeting the metal density requirements in the design rules.

[0079] In this embodiment, the projections of two adjacent metal structures on the substrate surface coincide to ensure the effect of electrical connection between the two adjacent metal structures through the first plug 207.

[0080] In other embodiments, the projections of adjacent metal structures onto the substrate surface may only partially overlap. This allows for a larger process window for forming the multilayered metal structures.

[0081] In this embodiment, the method further includes forming a second dielectric layer (not shown) on the first dielectric layer, wherein the antenna structure is located within the second dielectric layer.

[0082] Please refer to Figure 7 In addition to forming an antenna structure on the antenna region, the method also includes forming a conductive structure 208 on several of the probe regions I.

[0083] The conductive structure 208 is located within the second dielectric layer.

[0084] The conductive structure 208 includes: multiple layers of second metal layers (not shown); adjacent second metal layers are electrically connected by a plurality of second plugs (not shown).

[0085] The material of the second metal layer includes a metal, which includes one or more combinations of copper, aluminum, tungsten, cobalt, nickel, and tantalum; the material of the second plug includes a metal, which includes one or more combinations of copper, aluminum, tungsten, cobalt, nickel, and tantalum.

[0086] The conductive structure 208 on the probe region I is electrically connected to one or more of the gate structure 203, the source doped region 204, the drain doped region 205, and the substrate.

[0087] In this embodiment, the conductive structure 208 on the probe region I is electrically connected to the gate structure 203, the source doped region 204, the drain doped region 205 and the substrate, respectively, that is, there are 4 probe regions I with conductive structure 208.

[0088] The structure under test and the antenna structure are located within the cut-off region 201, thus reducing their size. This necessitates increasing the number of antenna structures to meet design requirements. The antenna structure is located on the antenna region, and the number of probe regions I with conductive structures 208 is four. Since the number of probe regions I is much greater than the number of conductive structures 208, it is possible to avoid forming the same number of conductive structures 208 as the number of probe regions I. This reduces the number of conductive structures 208, thereby decreasing the device density on the cut-off region 201 and reducing the resistance to removing the cut-off region 201.

[0089] The number of probe regions I is greater than the number of conductive structures 208. Therefore, when a probe region I adjacent to the antenna structure has a conductive structure 208, there is a first gap (not shown) between the antenna structure and the conductive structure 208; when a probe region I adjacent to the antenna structure does not have a conductive structure 208, there is a second gap (not shown) between the antenna structure and the probe region I; the first gap is greater than the second gap.

[0090] The first spacing is greater than the second spacing. On the one hand, when there is a conductive structure 208 on the probe area I adjacent to the antenna structure, the antenna structure and the conductive structure 208 need to have a sufficient isolation distance to avoid electrical crosstalk. On the other hand, when there is no conductive structure 208 on the probe area I adjacent to the antenna structure, the spacing between the antenna structure and the probe area I is smaller, thereby maximizing the perimeter of a single antenna structure to increase the metal density.

[0091] Please refer to Figure 8 and Figure 9 , Figure 9 for Figure 8 A schematic diagram of the cross-sectional structure of several antenna structures along the section line AA1 is shown. While forming the antenna structure on the probe area I, it also includes: forming several buffer structures on the buffer zone 202. The several buffer structures are arranged along the extension direction X of the cutting channel area 200.

[0092] The buffer structure can buffer the stress generated when removing the cut area 201, thus preventing the stress from damaging the chip area. The buffer structure is located within the second dielectric layer.

[0093] The buffer structure includes: several third metal layers 209; adjacent third metal layers 209 are electrically connected by several third plugs 210.

[0094] The plurality of third metal layers 209 are arranged parallel to each other along the extension direction X of the dicing area 200. Thus, the plurality of third metal layers 209 are mutually independent along the extension direction X of the dicing area 200. Consequently, when stress propagates to the buffer zone 202 during the removal of the cut area 201, the mutually independent third metal layers 209 are less likely to fracture. Furthermore, if fracture occurs, the third metal layers 209 are less likely to generate significant secondary stress, thereby reducing the likelihood of stress propagation from fractured third metal layers 209 to the chip area and preventing damage to the chip area.

[0095] The material of the third metal layer 209 includes metals, and the metals include one or more combinations of copper, aluminum, tungsten, cobalt, nickel and tantalum; the material of the third plug 210 includes metals, and the metals include one or more combinations of copper, aluminum, tungsten, cobalt, nickel and tantalum.

[0096] In this embodiment, the spacing between the buffer structure and the conductive structure 208 on the probe region I ranges from 10 mm to 15 mm.

[0097] If the spacing between the buffer structure and the conductive structure 208 on the probe region I is too small, the buffer structure is at risk of short-circuiting with the conductive structure 208 on the probe region I and the antenna structure on the antenna region.

[0098] Thus, the formed semiconductor structure includes an antenna structure located on the antenna region, which is electrically connected to the structure under test. The projection pattern of the antenna structure onto the substrate surface is ring-shaped. Therefore, while ensuring the maximum length of a single antenna structure, the antenna structure can be located within the cut-off region 201. This allows the structure under test and the antenna structure to be removed simultaneously when the cut-off region 201 is subsequently removed using a laser or a scalpel wheel. This reduces the risk of breakage of the structure under test and the antenna structure when the cut-off region 201 is not completely within it, which could lead to delamination and crack propagation affecting other areas of the substrate. This improves the performance of the semiconductor structure.

[0099] Accordingly, embodiments of the present invention also provide a semiconductor structure, please refer to [the relevant documentation]. Figure 8 ,include:

[0100] The substrate includes a dicing region 200, the dicing region 200 includes a cut-out region 201, the cut-out region 201 includes a plurality of probe regions I arranged along the extension direction X of the dicing region 200 and a plurality of spacer regions II located between adjacent probe regions I, at least one of the spacer regions II is a device region, at least one of the spacer regions II is an antenna region, and the device region and the antenna region are mutually independent.

[0101] The structure to be tested located on the device region;

[0102] An antenna structure located on the antenna region, the antenna structure being electrically connected to the structure under test, and the projection pattern of the antenna structure on the substrate surface being ring-shaped.

[0103] In this embodiment, the antenna structure includes: a multi-layer metal structure, wherein a single-layer metal structure includes several annular first metal layers, the several annular first metal layers being concentrically ringed and mutually independent; and several first plugs electrically connecting adjacent first metal layers.

[0104] In this embodiment, the ring may be circular or elliptical.

[0105] In this embodiment, the projection of the antenna structure onto the substrate surface is within the area of ​​the cut-off region.

[0106] In this embodiment, the structure to be tested includes a transistor; the transistor includes a gate structure 203 and a source doped region 204 and a drain doped region 205 located in the device regions on both sides of the gate structure 203, the source doped region 204 and the drain doped region 205 being located on both sides of the gate structure 203 along the extension direction X of the diced channel region 200; the antenna structure is electrically connected to the gate structure 203.

[0107] In this embodiment, it further includes: a conductive structure 208 located on a plurality of the probe regions I; the conductive structure 208 includes: multiple layers of second metal layers (not shown); adjacent two layers of second metal layers are electrically connected through a plurality of second plugs (not shown).

[0108] In this embodiment, the conductive structure 208 on the probe region I is electrically connected to one or more of the gate structure 203, the source doped region 204, the drain doped region 205, and the substrate.

[0109] In this embodiment, the width of the excision area 201 in the direction X perpendicular to the extension of the cutting channel area 200 ranges from 0 micrometers to 40 micrometers.

[0110] In this embodiment, the substrate further includes a plurality of chip regions (not shown) arranged in an array; the dicing channel region 200 is located between adjacent chip regions.

[0111] In this embodiment, the cutting channel area 200 further includes a buffer zone 202, which is located between the cut area 201 and the chip area. There is a gap between the cut area 201 and the buffer zone 202, and the buffer zone 202 extends in the same direction X as the cutting channel area 200.

[0112] In this embodiment, it also includes: a plurality of buffer structures located on the buffer zone 202, wherein the plurality of buffer structures are arranged along the extension direction X of the cutting channel zone 200.

[0113] In this embodiment, the buffer structure includes: several third metal layers; adjacent third metal layers are electrically connected by several third plugs.

[0114] In this embodiment, several of the third metal layers are arranged parallel to each other along the extension direction X of the cut channel region 200.

[0115] In this embodiment, the spacing between the buffer structure and the conductive structure 208 on the probe region I ranges from 10 mm to 15 mm.

[0116] The semiconductor structure in this invention includes an antenna structure located on the antenna region, which is electrically connected to the structure under test. The projection pattern of the antenna structure onto the substrate surface is ring-shaped. Therefore, while ensuring the maximum length of a single antenna structure, the antenna structure can be located within the cut-off region 201. This allows the structure under test and the antenna structure to be removed simultaneously when the cut-off region 201 is subsequently removed using a laser or a scalpel wheel. This reduces the risk of breakage of the structure under test and the antenna structure during the removal of the cut-off region 201 if they are not completely within it, which could lead to delamination and crack propagation affecting other areas of the substrate. This ultimately improves the performance of the semiconductor structure.

[0117] Furthermore, the structure under test and the antenna structure are located within the cut-off region 201, thereby reducing the size of the structure under test and the antenna structure. Consequently, the number of antenna structures needs to be increased to meet design requirements, and the number of probe regions I is much greater than the number of conductive structures 208. Therefore, it is not possible to form the same number of conductive structures 208 as the number of probe regions I, thereby reducing the number of conductive structures 208, reducing the device density on the cut-off region 201, and reducing the resistance to removing the cut-off region 201.

[0118] Furthermore, the cut channel region 200 also includes a buffer zone 202. While forming the antenna structure on the antenna region, a plurality of buffer structures are also formed on the buffer zone 202, and the plurality of buffer structures are arranged along the extension direction X of the cut channel region 200. The buffer structures can buffer the stress generated when removing the cut area 201, and avoid the stress generated when removing the cut area 201 from damaging the chip region.

[0119] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: The substrate includes a dicing region, the dicing region includes a cut-out region, the cut-out region includes a plurality of probe regions arranged along the extension direction of the dicing region and a plurality of spacer regions located between adjacent probe regions, at least one of the spacer regions is a device region, at least one of the spacer regions is an antenna region, and the device region and the antenna region are mutually independent. The structure under test is located on the device region, and the projection of the structure under test onto the substrate surface is within the area of ​​the cut-off region; An antenna structure located on the antenna region, the antenna structure being electrically connected to the structure under test, the projection pattern of the antenna structure on the substrate surface being annular, and the projection of the antenna structure on the substrate surface being within the area of ​​the cut-off region; A conductive structure located on several probe regions, the projection of the conductive structure on the substrate surface within the cut area, the structure to be tested, the antenna structure and the conductive structure are arranged along the extension direction of the cut area.

2. The semiconductor structure as described in claim 1, characterized in that, The projection pattern of the antenna structure onto the substrate surface is a concentric ring.

3. The semiconductor structure as described in claim 2, characterized in that, The antenna structure includes: a multi-layer metal structure, wherein a single-layer metal structure includes several annular first metal layers, the several annular first metal layers being concentrically ringed and mutually independent; and adjacent first metal layers are electrically connected by several first plugs.

4. The semiconductor structure as described in claim 3, characterized in that, The ring can be circular or elliptical.

5. The semiconductor structure as described in claim 1, characterized in that, The structure under test includes a transistor; the transistor includes a gate structure and source doped regions and drain doped regions located in the device regions on both sides of the gate structure, the source doped regions and drain doped regions being located on both sides of the gate structure along the extension direction of the diced channel region; the antenna structure is electrically connected to the gate structure.

6. The semiconductor structure as described in claim 5, characterized in that, The conductive structure includes: multiple layers of second metal layers; adjacent layers of second metal layers are electrically connected by a plurality of second plugs.

7. The semiconductor structure as described in claim 6, characterized in that, The conductive structures on the probe region are electrically connected to one or more of the gate structure, source doped region, drain doped region, and substrate.

8. The semiconductor structure as described in claim 1, characterized in that, The width of the excised area in the direction perpendicular to the extension of the cutting channel ranges from 0 micrometers to 40 micrometers.

9. The semiconductor structure as described in claim 1, characterized in that, The substrate also includes several chip regions arranged in an array; the dicing area is located between adjacent chip regions.

10. The semiconductor structure as described in claim 9, characterized in that, The cutting channel area also includes a buffer zone, which is located between the cut-off area and the chip area. There is a gap between the cut-off area and the buffer zone, and the extension direction of the buffer zone is the same as the extension direction of the cutting channel area.

11. The semiconductor structure as claimed in claim 10, characterized in that, Also includes: A plurality of buffer structures are located on the buffer zone, and the plurality of buffer structures are arranged along the extension direction of the cutting channel area.

12. The semiconductor structure as claimed in claim 11, characterized in that, The buffer structure includes: several third metal layers; adjacent third metal layers are electrically connected by several third plugs.

13. The semiconductor structure as described in claim 12, characterized in that, Several of the third metal layers are arranged in parallel along the extension direction of the cutting zone.

14. The semiconductor structure as claimed in claim 11, characterized in that, The spacing between the buffer structure and the conductive structure on the probe area is 10 mm to 15 mm.

15. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a dicing region, the dicing region including a cut-out region, the cut-out region including a plurality of probe regions arranged along the extension direction of the dicing region and a plurality of spacer regions located between adjacent probe regions, at least one of the spacer regions being a device region, at least one of the spacer regions being an antenna region, and the device region and the antenna region being separate from each other; A test structure is formed on the device region, and the projection of the test structure onto the substrate surface is within the area of ​​the cut-off region; An antenna structure is formed on the antenna region, the antenna structure is electrically connected to the structure under test, the projection pattern of the antenna structure on the substrate surface is annular, and the projection of the antenna structure on the substrate surface is within the area of ​​the cut-off region; Conductive structures are formed on several probe regions, the projection of the conductive structures onto the substrate surface within the cut-out region, and the structure under test, the antenna structure, and the conductive structures are arranged along the extension direction of the cut-out region.

16. The method for forming a semiconductor structure as described in claim 15, characterized in that, The projection pattern of the antenna structure onto the substrate surface is a concentric ring.

17. The method for forming a semiconductor structure as described in claim 15, characterized in that, The antenna structure includes: a multi-layer metal structure, wherein a single-layer metal structure includes several annular first metal layers, the several annular first metal layers being concentrically ringed and mutually independent; and adjacent first metal layers are electrically connected by several first plugs.

18. The method for forming a semiconductor structure as described in claim 17, characterized in that, The ring can be circular or elliptical.

19. The method for forming a semiconductor structure as described in claim 15, characterized in that, The structure under test includes a transistor; the transistor includes a gate structure and source doped regions and drain doped regions located in the device regions on both sides of the gate structure, the source doped regions and drain doped regions being located on both sides of the gate structure along the extension direction of the diced channel region; the antenna structure is electrically connected to the gate structure.

20. The method for forming a semiconductor structure as described in claim 19, characterized in that, The antenna structure and the conductive structure are formed simultaneously; the conductive structure includes: multiple layers of second metal layers; adjacent second metal layers are electrically connected by a plurality of second plugs.

21. The method for forming a semiconductor structure as described in claim 20, characterized in that, The conductive structures on the probe region are electrically connected to one or more of the gate structure, source doped region, drain doped region, and substrate.

22. The method for forming a semiconductor structure as described in claim 15, characterized in that, The width of the excised area in the direction perpendicular to the extension of the cutting channel ranges from 0 micrometers to 40 micrometers.

23. The method for forming a semiconductor structure as described in claim 15, characterized in that, The substrate also includes several chip regions arranged in an array; the dicing area is located between adjacent chip regions.

24. The method for forming a semiconductor structure as described in claim 23, characterized in that, The cutting channel area also includes a buffer zone, which is located between the cut-off area and the chip area. There is a gap between the cut-off area and the buffer zone, and the extension direction of the buffer zone is the same as the extension direction of the cutting channel area.

25. The method for forming a semiconductor structure as described in claim 24, characterized in that, While forming the antenna structure on the probe region, the method also includes forming several buffer structures on the buffer zone, wherein the several buffer structures are arranged along the extension direction of the cutting channel region.

26. The method for forming a semiconductor structure as described in claim 25, characterized in that, The buffer structure includes: several third metal layers; adjacent third metal layers are electrically connected by several third plugs.

27. The method for forming a semiconductor structure as described in claim 26, characterized in that, Several of the third metal layers are arranged in parallel along the extension direction of the cutting zone.

28. The method for forming a semiconductor structure as described in claim 25, characterized in that, The spacing between the buffer structure and the conductive structure on the probe area is 10 mm to 15 mm.

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