Semiconductor Structure and Method for Forming the Same

Abstract

The present application provides a semiconductor structure and a method for forming the same. The semiconductor structure includes: a bottom wafer, the bottom wafer includes a bottom substrate, a first bottom auxiliary layer and a second bottom auxiliary layer sequentially located on the bottom substrate, and bottom bonding marks are formed in the first bottom auxiliary layer; a stacked wafer, the stacked wafer includes a stacked substrate and a third stacked auxiliary layer located on the stacked substrate, and second groove bonding marks are formed on the surface of the third stacked auxiliary layer; the bottom wafer and the stacked wafer are aligned and bonded through the bottom bonding marks and the second groove bonding marks. Forming an auxiliary layer capable of changing the curvature of the wafer on the wafer surface can reduce the bubble defects after wafer bonding; using metal bonding marks and groove bonding marks for alignment bonding can save process costs; before bonding, trimming the wafer can reduce the broken edge defects and improve the device reliability.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and particularly to a semiconductor structure and a method for forming the same. Background Art

[0002] With the continuous development of micro-nano technology, the feature size of semiconductor structures has been continuously reduced, thereby greatly improving the integration of transistors in a chip. However, as the feature size gets closer and closer to the limit, the continuation of Moore's Law has encountered great challenges. Some technologies beyond Moore's Law, such as three-dimensional electronic packaging technology (3DIC), have come into people's view. Through 3DIC, chips of different technology types can be bonded together. Compared with traditional planar two-dimensional electrical connections, 3DIC has advantages such as small volume, light weight, high integration, small signal delay, and low power consumption. At the same time, wafer-to-wafer bonding, compared with wafer-to-chip and chip-to-chip bonding, performs packaging and testing at the wafer level and then dicing, which can reduce the volume of packaging; at the same time, the area of the chips finally cut out by wafer-level bonding is close to the area of the bare die, significantly reducing the production cost. Three-dimensional electronic packaging technology can integrate modules such as micro-electromechanical systems, radio frequency modules, memory, and processors into one system. It greatly improves the integration of the system, reduces power consumption, and improves performance.

[0003] There are many existing ways of wafer bonding, including: adhesive bonding, anodic bonding, metal bonding, direct wafer bonding, etc. Compared with other wafer bonding methods, direct wafer bonding has advantages such as simple process flow and low production cost. However, it has high requirements for the bending degree of the wafer, the film layer structure of the wafer, and the alignment accuracy of the wafer. The current process results of direct wafer bonding are not very ideal, and often lead to situations such as insufficient alignment accuracy, bubble defects, and chipping defects after bonding. At the same time, currently, mostly two wafers are bonded, and multi-wafer bonding (wafer-to-wafer level) has not been realized due to technical reasons. Therefore, it is necessary to provide a more effective and reliable technical solution. Summary of the Invention

[0004] This application provides a semiconductor structure and a method for forming the same, which can reduce bubble defects and chipping defects after wafer bonding and improve device reliability.

[0005] One aspect of the present application provides a method for forming a semiconductor structure, including: providing a bottom wafer, the bottom wafer including a bottom substrate and a first bottom auxiliary layer and a second bottom auxiliary layer sequentially located on the bottom substrate, a bottom bonding mark being formed in the first bottom auxiliary layer; providing a stacked wafer, the stacked wafer including a stacked substrate and a first stacked auxiliary layer and a second stacked auxiliary layer sequentially located on the stacked substrate, a first stacked bonding mark being formed in the first stacked auxiliary layer; providing a carrier wafer, the carrier wafer including a carrier substrate and a carrier auxiliary layer located on the carrier substrate, a groove bonding mark being formed on the surface of the carrier auxiliary layer; aligning the groove bonding mark and the first stacked bonding mark, and bonding the carrier wafer and the stacked wafer; thinning the other side of the stacked wafer to a set thickness; forming a third stacked auxiliary layer on the other side of the stacked wafer, and forming a second groove bonding mark on the surface of the third stacked auxiliary layer; aligning the bottom bonding mark and the second groove bonding mark, and bonding the bottom wafer and the stacked wafer; removing the carrier wafer.

[0006] In some embodiments of the present application, the method for forming the semiconductor structure further includes: performing a first trimming process on the stacked wafer.

[0007] In some embodiments of the present application, the method for forming the semiconductor structure further includes: after thinning the other side of the stacked wafer to a set thickness, performing a second trimming process on the carrier wafer and the stacked wafer.

[0008] In some embodiments of the present application, the groove bonding mark is located in the bonding area of the carrier wafer, the second groove bonding mark is located in the bonding area of the stacked wafer, and the bonding areas are respectively located in the diameter direction of the wafer.

[0009] In some embodiments of the present application, the bonding areas are symmetric about the center of the wafer near the edge of the wafer.

[0010] In some embodiments of the present application, both the bottom bonding mark and the first stacked bonding mark are metal bonding marks.

[0011] In some embodiments of the present application, the method for forming the bottom wafer includes: providing a bottom substrate; depositing a first bottom auxiliary layer material on the bottom substrate; forming a bottom bonding mark on the first bottom auxiliary layer material; continuously depositing the first bottom auxiliary layer material on the first bottom auxiliary layer material and the bottom bonding mark to form a first bottom auxiliary layer that completely covers the bottom bonding mark; forming a second bottom auxiliary layer on the first bottom auxiliary layer.

[0012] In some embodiments of the present application, the method of forming the first bottom auxiliary layer further includes performing an annealing process and a chemical mechanical polishing process on the first bottom auxiliary material layer.

[0013] In some embodiments of the present application, the material of the first bottom auxiliary layer includes silicon oxide, and the material of the second bottom auxiliary layer includes silicon nitride.

[0014] In some embodiments of the present application, the thickness of the first bottom auxiliary layer is 500 angstroms to 4000 angstroms, and the thickness of the second bottom auxiliary layer is 100 angstroms to 1000 angstroms.

[0015] In some embodiments of the present application, the carrier auxiliary layer includes a first carrier auxiliary layer, a second carrier auxiliary layer, and a third carrier auxiliary layer stacked in sequence.

[0016] In some embodiments of the present application, the material of the third carrier auxiliary layer includes silicon oxide.

[0017] In some embodiments of the present application, the method of forming the semiconductor structure further includes: providing a second stacked wafer and a second carrier wafer, where the second stacked wafer and the second carrier wafer have the same structure as the stacked wafer and the carrier wafer; using the stacked wafer and the bottom wafer after stacking as a new bottom wafer, and bonding the second stacked wafer to the new bottom wafer using the method of forming the semiconductor structure as described above.

[0018] In some embodiments of the present application, the method of forming the semiconductor structure further includes repeating the above steps, and sequentially stacking a third stacked wafer, a fourth stacked wafer to an Nth stacked wafer on the second stacked wafer, where N is a natural number greater than or equal to 2.

[0019] Another aspect of the present application provides a semiconductor structure, including: a bottom wafer, the bottom wafer includes a bottom substrate and a first bottom auxiliary layer and a second bottom auxiliary layer sequentially located on the bottom substrate, and bottom bonding marks are formed in the first bottom auxiliary layer; a stacked wafer, the stacked wafer includes a stacked substrate and a third stacked auxiliary layer located on the stacked substrate, and second groove bonding marks are formed on the surface of the third stacked auxiliary layer; the bottom wafer and the stacked wafer are aligned and bonded through the bottom bonding marks and the second groove bonding marks.

[0020] In some embodiments of the present application, the semiconductor structure further includes a second stacked wafer, the second stacked wafer includes a second stacked substrate and a sixth stacked auxiliary layer located on the second stacked substrate, and a fourth groove bonding mark is formed on the surface of the sixth stacked auxiliary layer; a first stacked auxiliary layer and a second stacked auxiliary layer are further included on a surface of the stacked wafer away from the bottom wafer, and a first stacked bonding mark is formed in the first stacked auxiliary layer; the stacked wafer and the second stacked wafer are aligned and bonded through the first stacked bonding mark and the fourth groove bonding mark.

[0021] In some embodiments of the present application, by analogy with the above-described structure, the semiconductor structure further includes a third stacked wafer, a fourth stacked wafer to an Nth stacked wafer stacked in sequence, where N is a natural number greater than or equal to 2.

[0022] For the semiconductor structure and its forming method described in the present application, an auxiliary layer capable of changing the curvature of the wafer is formed on the wafer surface, which can reduce the bubble defects after wafer bonding; using metal bonding marks and groove bonding marks for alignment bonding can save process costs; there is always a silicon surface on one surface of the wafer, and the robotic arm for gripping the wafer does not need to be designed separately, which can also reduce the risk of wafer dropping; before bonding, trimming the wafer can reduce the edge breakage defects and improve the device reliability. Description of the Drawings

[0023] The following drawings detail the exemplary embodiments disclosed in the present application. Wherein the same reference numerals represent similar structures in several views of the drawings. Those of ordinary skill in the art will understand that these embodiments are non-limiting, exemplary embodiments, and the drawings are only for the purpose of illustration and description, and are not intended to limit the scope of the present application. Embodiments in other ways may also achieve the inventive concept in the present application. It should be understood that the drawings are not drawn to scale. Wherein:

[0024] Figures 1 to 18 It is a schematic structural diagram of each step in the forming method of the semiconductor structure according to the embodiment of the present application. Detailed Description of the Embodiments

[0025] The following description provides specific application scenarios and requirements of the present application, aiming to enable those skilled in the art to manufacture and use the content in the present application. For those skilled in the art, various partial modifications to the disclosed embodiments are obvious, and without departing from the spirit and scope of the present application, the general principles defined here can be applied to other embodiments and applications. Therefore, the present application is not limited to the illustrated embodiments, but is the broadest scope consistent with the claims.

[0026] The technical solution of the present invention will be described in detail below in conjunction with the embodiments and the drawings.

[0027] The curvature of the bonded wafers is controlled by depositing a film layer on the back of the wafer to make the curvatures of the two wafers meet the requirements. The deposited film layer is mostly a non-conductive film layer. Since wafer bonding is performed on the back-end machine, the electrostatic chuck (E-chunk) of the back-end machine cannot hold the wafer, posing a risk of scribe.

[0028] During the bonding of some wafers, alignment is performed through grooves. Although this alignment method is simple, its accuracy is insufficient. During the bonding of some wafers, bonding marks are used for alignment. This alignment method requires depositing metal layers on the two wafers, which increases the process flow and the cost of depositing metal is also relatively high. At the same time, when performing multi-layer bonding, a carrier wafer needs to be used. In this way, every time two wafers are aligned, deposition of metal layers is used for alignment. For the carrier wafer to be removed, both the growth of metal bonding marks and the carrier wafer during the bonding stage will make the process flow more complex and increase the production cost. During the bonding of some wafers, a bonding mark is etched on the bonded film layer, for example, etching the corresponding bonding mark on a silicon wafer or depositing other film layers. Direct etching on a silicon wafer requires first growing a layer of thermal oxide by thermal oxidation as an etching barrier layer. The reaction temperature is generally above 800 degrees Celsius. Too high a temperature will affect the performance of the device. When etching in other film layers, considering the clarity of the bonding mark, a special film layer structure needs to be introduced. Since the newly introduced film layer structure only serves to increase the clarity of the bonding mark, corresponding process adjustments are also required to eliminate the changes in the curvature, roughness, and surface topography of the wafer caused by the introduction of the new film layer structure. This increases the process flow and production cost.

[0029] The wafers are not trimmed before bonding, which may cause the risk of broken edges during bonding and subsequent wafer thinning (especially during multi-wafer bonding).

[0030] To address the above problems, the present application provides a semiconductor structure and a method for forming the same. An auxiliary layer capable of changing the curvature of the wafer is formed on the wafer surface, which can reduce the bubble defects after wafer bonding; using metal bonding marks and groove bonding marks for alignment bonding can save process costs; one surface of the wafer is always a silicon surface, and the robotic arm for gripping the wafer does not need to be designed separately, which can also reduce the risk of wafer dropping; before bonding, the wafers are trimmed, which can reduce the broken edge defects and improve the device reliability.

[0031] Embodiments of the present application provide a method for forming a semiconductor structure, including: providing a bottom wafer, the bottom wafer including a bottom substrate and a first bottom auxiliary layer and a second bottom auxiliary layer sequentially located on the bottom substrate, and a bottom bonding mark is formed in the first bottom auxiliary layer; providing a stacked wafer, the stacked wafer including a stacked substrate and a first stacked auxiliary layer and a second stacked auxiliary layer sequentially located on the stacked substrate, and a first stacked bonding mark is formed in the first stacked auxiliary layer; providing a carrier wafer, the carrier wafer including a carrier substrate and a carrier auxiliary layer located on the carrier substrate, and a groove bonding mark is formed on the surface of the carrier auxiliary layer; aligning the groove bonding mark and the first stacked bonding mark, and bonding the carrier wafer and the stacked wafer; thinning the other side of the stacked wafer to a set thickness; forming a third stacked auxiliary layer on the other side of the stacked wafer, and forming a second groove bonding mark on the surface of the third stacked auxiliary layer; aligning the bottom bonding mark and the second groove bonding mark, and bonding the bottom wafer and the stacked wafer; removing the carrier wafer.

[0032] Figures 1 to 18 FIGS. are schematic structural diagrams of the steps in the method for forming a semiconductor structure according to the embodiments of the present application. The method for forming a semiconductor structure according to the embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0033] Refer to Figures 1 to 5 As shown, a bottom wafer 100 is provided. The bottom wafer 100 includes a bottom substrate 110 and a first bottom auxiliary layer 120 and a second bottom auxiliary layer 130 sequentially located on the bottom substrate 110, and a bottom bonding mark 140 is formed in the first bottom auxiliary layer 120.

[0034] Refer to Figure 1 As shown, a bottom substrate 110 is provided. The bottom substrate 110 may be a wafer to be bonded, including but not limited to a semiconductor substrate, and active devices may be formed in the semiconductor substrate.

[0035] Refer to Figure 2 As shown, a first bottom auxiliary layer material 120a is deposited on the bottom substrate 110.

[0036] Refer to Figure 3 As shown, a bottom bonding mark 140 is formed on the first bottom auxiliary layer material 120a. The material of the bottom bonding mark 140 includes aluminum, etc. The method for forming the bottom bonding mark 140 includes physical vapor deposition process and etching process.

[0037] Refer to Figure 4As shown, the first bottom auxiliary layer material 120a is continuously deposited on the first bottom auxiliary layer material 120a and the bottom bonding mark 140 to form the first bottom auxiliary layer 120 that completely covers the bottom bonding mark 140. In some embodiments of the present application, the method of forming the first bottom auxiliary layer 120 further includes an annealing process and a chemical mechanical polishing process for the first bottom auxiliary material layer 120a. The annealing process can improve the film formation quality, and the chemical mechanical polishing process can improve the film layer morphology to ensure the quality of the subsequent deposition of the second bottom auxiliary layer. In some embodiments of the present application, the temperature for depositing the first bottom auxiliary layer material 120a is 350 degrees Celsius to 450 degrees Celsius, such as 375 degrees Celsius, 390 degrees Celsius, 400 degrees Celsius, 425 degrees Celsius, etc.

[0038] Reference Figure 5 As shown, a second bottom auxiliary layer 130 is formed on the first bottom auxiliary layer 120. In some embodiments of the present application, the method of forming the second bottom auxiliary layer material 130 includes a chemical vapor deposition process, and the deposition temperature is 350 degrees Celsius to 450 degrees Celsius, such as 375 degrees Celsius, 390 degrees Celsius, 400 degrees Celsius, 425 degrees Celsius, etc.

[0039] In some embodiments of the present application, the material of the first bottom auxiliary layer 120 includes silicon oxide, and the material of the second bottom auxiliary layer 130 includes silicon nitride. In some embodiments of the present application, the thickness of the first bottom auxiliary layer 120 is 500 angstroms to 4000 angstroms, such as 1900 angstroms, 2000 angstroms, 2100 angstroms, 2200 angstroms or 2300 angstroms, etc., and the thickness of the second bottom auxiliary layer is 100 angstroms to 1000 angstroms, such as 350 angstroms, 400 angstroms, 450 angstroms, 500 angstroms or 550 angstroms, etc. Specifically, the thicknesses of the first bottom auxiliary layer 120 and the second bottom auxiliary layer 130 can be set according to the required curvature.

[0040] For the direct bonding of wafers, especially for the direct bonding of multiple wafers, the curvature of the wafers is a very critical parameter, so it is necessary to continuously and finely control the curvature of the wafers. The applicant has found that it is best for the curvature of the upper wafer to be negative (about -50 microns); the closer the curvature of the bottom wafer is to 0, the better. According to the applicant's experiments: for every additional 1 micron of silicon nitride deposited, the curvature increases by 140 - 160 microns; for every additional 1 micron of silicon oxide deposited, the curvature decreases by 40 - 70 microns. The thickness of the sequentially deposited film layers is very small relative to the overall thickness of the wafer and will not affect the overall size of the wafer, but it has a very obvious effect on changing the curvature of the wafer. At the same time, silicon oxide and silicon nitride can also serve as the bonding interface. In some embodiments of the present application, it is necessary to ensure that the materials of the outermost layers of the two wafers to be bonded are silicon oxide and silicon nitride respectively.

[0041] Therefore, in the method for forming the semiconductor structure described in the present application, a silicon oxide material and a silicon nitride material capable of adjusting the curvature are deposited on the surface of the wafer, so that the curvature of the wafer reaches the optimal value, the bonding quality is improved, and the bubble defects are reduced, thereby improving the reliability of the device during that period.

[0042] Reference Figure 6 As shown, a stacked wafer 200 is provided. The stacked wafer 200 includes a stacked substrate 210, a first stacked auxiliary layer 220 and a second stacked auxiliary layer 230 sequentially located on the stacked substrate 210. A first stacked bonding mark 240 is formed in the first stacked auxiliary layer 220.

[0043] The method for forming the stacked wafer 200 is the same as the method for forming the bottom wafer 100, so it will not be described in detail herein. The difference is that the position of the first stacked bonding mark 240 on the stacked wafer 200 and the position of the bottom bonding mark 140 on the bottom wafer 100 are symmetric with respect to the center of the wafer.

[0044] In some embodiments of the present application, the curvature of the bottom wafer 100 is from -10 microns to 10 microns; the curvature of the stacked wafer 200 is from -40 microns to -60 microns.

[0045] Reference Figure 7 As shown, in some embodiments of the present application, the method for forming the semiconductor structure further includes: performing a first trimming process on the stacked wafer 200. The first trimming process refers to trimming the edge of the wafer 200 through an etching process. Among them, the height h of the part of the wafer removed by etching is from 120 microns to 180 microns, such as 140 microns, 150 microns or 160 microns, etc., and the width d is from 0.5 mm to 2 mm, such as 1 mm or 1.5 mm, etc.

[0046] In the method for forming the semiconductor structure described in the present application, trimming the wafer to be bonded before bonding can reduce the broken edge defects, thereby improving the device reliability.

[0047] Reference Figure 8 As shown, a carrier wafer 300 is provided. The carrier wafer 300 includes a carrier substrate 310 and a carrier auxiliary layer 320 located on the carrier substrate 310. A groove bonding mark 330 is formed on the surface of the carrier auxiliary layer 320.

[0048] In some embodiments of the present application, the carrier auxiliary layer 320 includes a first carrier auxiliary layer 321, a second carrier auxiliary layer 322, and a third carrier auxiliary layer 323 stacked in sequence. The bottom of the groove bonding mark 330 is lower than the top surface of the second carrier auxiliary layer 322.

[0049] In some embodiments of the present application, the material of the third carrier auxiliary layer 323 includes silicon oxide, such as TEOS, and the thickness of the third carrier auxiliary layer 323 is 1800 Å to 2000 Å.

[0050] In some embodiments of the present application, the height of the groove bonding mark 330 is 2500 Å to 3000 Å, such as 2600 Å or 2800 Å, etc.

[0051] In some embodiments of the present application, the method for forming the carrier wafer includes: providing a carrier substrate 310; sequentially depositing a first carrier auxiliary layer 321, a second carrier auxiliary layer 322, and a third carrier auxiliary layer 323 on the carrier substrate 310; etching the third carrier auxiliary layer 323 into the second carrier auxiliary layer 322 to form the groove bonding mark 330. Wherein, an annealing process and a chemical mechanical polishing process can also be performed after each deposition to improve the film formation quality and the film morphology. When etching the third carrier auxiliary layer 323, over-etching can be performed into the second carrier auxiliary layer 322 to form the groove bonding mark 330, making the mark clearer.

[0052] Reference Figure 9 As shown, align the groove bonding mark 330 and the first stacked bonding mark 240, and bond the carrier wafer 300 and the stacked wafer 200. The method for bonding the carrier wafer and the stacked wafer includes alloying the carrier wafer 300 and the stacked wafer 200.

[0053] In some embodiments of the present application, before bonding, the surfaces of the carrier wafer 300 and the stacked wafer 200 also need to be cleaned, and plasma is used for surface activation.

[0054] In the method for forming the semiconductor structure described in the present application, since the curvature of the wafer is improved and the wafer is trimmed before bonding, bubble defects and broken edge defects can be reduced, and the device reliability can be improved. In addition, one side of the carrier substrate and the stacked substrate in the carrier wafer 300 and the stacked wafer 200 is silicon material, so a conventional robotic arm can be used to grasp the wafer without the risk of wafer dropping.

[0055] Reference Figure 10 As shown, thin the other side of the stacked wafer 200 to a set thickness. The set thickness is 50 to 60 microns, such as 52 microns, 54 microns, 56 microns, or 58 microns, etc.

[0056] Reference Figure 11As shown, in some embodiments of the present application, the method for forming the semiconductor structure further includes: after thinning the other side of the stacked wafers to a set thickness, performing a second trimming process on the carrier wafer 300 and the stacked wafers 200. Wherein, after the second trimming process, the height h of the part of the wafer etched away is 270 microns to 390 microns, such as 300 microns, 350 microns or 380 microns, etc., and the width d is 0.7 mm to 2.2 mm, such as 1.2 mm or 1.7 mm, etc.

[0057] In some embodiments of the present application, the width of the part of the wafer removed after the second trimming process is 0.2 mm to 0.5 mm larger than the width of the wafer removed after the first trimming process.

[0058] Reference Figure 12 As shown, a third stacked auxiliary layer 250 is formed on the other side of the stacked wafers 200, and a second groove bonding mark 260 is formed on the surface of the third stacked auxiliary layer 250.

[0059] In some embodiments of the present application, the third stacked auxiliary layer 250 includes a first stacked layer 251, a second stacked layer 252, and a third stacked layer 253 stacked in sequence. The second groove bonding mark 260 exposes the second stacked layer 252. The bottom of the second groove bonding mark 260 is lower than the top surface of the second stacked layer 252.

[0060] In some embodiments of the present application, the material of the third stacked layer 253 includes silicon oxide, such as TEOS, and the thickness of the third stacked layer 253 is 1800 Å to 2000 Å.

[0061] In some embodiments of the present application, the height of the second groove bonding mark 260 is 2500 Å to 3000 Å, such as 2600 Å or 2800 Å, etc.

[0062] Reference Figure 13 As shown, align the bottom bonding mark 140 and the second groove bonding mark 260, and bond the bottom wafer 100 and the stacked wafers 200.

[0063] Reference Figure 14 As shown, remove the carrier wafer 300. If other wafers need to be stacked continuously, only remove the carrier wafer 300, and retain the first stacked auxiliary layer 220, the second stacked auxiliary layer 230 and the first stacked bonding mark 240 for subsequent stacking; if other wafers do not need to be stacked continuously, then it is necessary to remove the carrier wafer 300, the first stacked auxiliary layer 220, the second stacked auxiliary layer 230 and the first stacked bonding mark 240. Embodiments of the present application take bonding multiple wafers as an example, so only the carrier wafer 300 is removed here.

[0064] In some embodiments of the present application, both the bottom bonding mark 140 and the first stacked bonding mark 240 are metal bonding marks.

[0065] In some embodiments of the present application, the groove bonding mark 330 is located in the bonding area 390 of the carrier wafer 300, and the second groove bonding mark 260 is located in the bonding area 290 of the stacked wafer 200. The bonding areas are respectively located in the diameter direction of the wafer. Refer to Figure 15 and Figure 16 , the Figure 15 and Figure 16 respectively show the plan views of the carrier wafer 300 and the stacked wafer 200.

[0066] The surface of a wafer includes several dies. It is not necessary to make groove bonding marks on each die. Groove bonding marks only need to be made on a part of the dies (bonding areas) to achieve alignment, which can save costs.

[0067] In some embodiments of the present application, the bonding areas are symmetric about the center of the wafer and close to the edge of the wafer.

[0068] The method for forming the semiconductor structure described in the present application can be used for bonding two wafers or multiple wafers. When only multiple wafers need to be bonded, the method for forming the semiconductor structure further includes: Refer to Figure 17 , providing a second stacked wafer 400 and a second carrier wafer 500, where the second stacked wafer 400 and the second carrier wafer 500 have the same structure as the stacked wafer 200 and the carrier wafer 300; using the method as shown in Figures 6 to 12 to bond the second stacked wafer 400 and the second carrier wafer 500 together. The details of bonding the second stacked wafer 400 and the second carrier wafer 500 will not be elaborated here, but it should be understood that generally it includes: providing a second stacked wafer 400 (similar to Figure 6 ) and a second carrier wafer 500 (similar to Figure 8 ); trimming the second stacked wafer 400 (similar to Figure 7 ); bonding the second stacked wafer 400 and the second carrier wafer 500 (similar to Figure 9 ); thinning the second stacked wafer 400 (similar to Figure 10 ).

[0069] Refer to Figure 18 , using the stacked wafer 200 and the bottom wafer 100 after stacking (refer to Figure 14 ) as the new bottom wafer, and using the method as shown in Figures 11 to 14The method for forming the semiconductor structure bonds the second stacked wafer 400 to a new bottom wafer. Details are not elaborated here, but it should be understood that it generally includes: trimming the second stacked wafer 400 and the second carrier wafer 500 (similar to Figure 11 ); forming a sixth stacked auxiliary layer 450 and a fourth groove bonding mark 460 on the other side of the second stacked wafer 400 (similar to Figure 12 ); bonding the second stacked wafer 400 to the stacked wafer 200 (similar to Figure 13 ); removing the second carrier wafer 500 (similar to Figure 14 ).

[0070] In some embodiments of the present application, the method for forming the semiconductor structure further includes repeating Figure 17 and Figure 18 the above steps to stack a third stacked wafer, a fourth stacked wafer up to an Nth stacked wafer on the second stacked wafer in sequence, where N is a natural number greater than or equal to 2.

[0071] In the method for forming the semiconductor structure described in the present application, forming an auxiliary layer capable of changing the wafer curvature on the wafer surface can reduce bubble defects after wafer bonding; using metal bonding marks and groove bonding marks for alignment bonding can save process costs; the wafer always has a silicon surface, and the robotic arm for gripping the wafer does not need to be designed separately, which can also reduce the risk of wafer dropping; before bonding, trimming the wafer can reduce edge breakage defects and improve device reliability.

[0072] Embodiments of the present application further provide a semiconductor structure. Referring to Figure 18 , the semiconductor structure includes: a bottom wafer 100, the bottom wafer 100 includes a bottom substrate and a first bottom auxiliary layer and a second bottom auxiliary layer sequentially located on the bottom substrate, and a bottom bonding mark is formed in the first bottom auxiliary layer; a stacked wafer 200, the stacked wafer includes a stacked substrate and a third stacked auxiliary layer located on the stacked substrate, and a second groove bonding mark is formed on the surface of the third stacked auxiliary layer; the bottom wafer 100 and the stacked wafer 200 are aligned and bonded through the bottom bonding mark and the second groove bonding mark.

[0073] The semiconductor structure described in the embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0074] Referring to Figure 5 and Figure 18 shown, the bottom wafer 100 includes a bottom substrate 110 and a first bottom auxiliary layer 120 and a second bottom auxiliary layer 130 sequentially located on the bottom substrate 110, and a bottom bonding mark 140 is formed in the first bottom auxiliary layer 120.

[0075] The bottom substrate 110 may be a wafer to be bonded, including but not limited to a semiconductor substrate, in which active devices may be formed. The material of the bottom bonding mark 140 includes aluminum and the like.

[0076] In some embodiments of the present application, the material of the first bottom auxiliary layer 120 includes silicon oxide, and the material of the second bottom auxiliary layer 130 includes silicon nitride. In some embodiments of the present application, the thickness of the first bottom auxiliary layer 120 is 500 Å to 4000 Å, such as 1900 Å, 2000 Å, 2100 Å, 2200 Å or 2300 Å, etc., and the thickness of the second bottom auxiliary layer is 100 Å to 1000 Å, such as 350 Å, 400 Å, 450 Å, 500 Å or 550 Å, etc. Specifically, the thicknesses of the first bottom auxiliary layer 120 and the second bottom auxiliary layer 130 can be set according to the required curvature.

[0077] For the direct bonding of wafers, especially the direct bonding of multiple wafers, the curvature of the wafers is a very critical parameter, so it is necessary to continuously and finely control the curvature of the wafers. The applicant has found that it is best for the curvature of the upper wafer to be negative (about -50 microns); the closer the curvature of the bottom wafer is to 0, the better. According to the applicant's experiments: for every additional 1 micron of silicon nitride deposited, the curvature increases by 140 - 160 microns; for every additional 1 micron of silicon oxide deposited, the curvature decreases by 40 - 70 microns. The thicknesses of the sequentially deposited film layers are very small relative to the overall thickness of the wafer and will not affect the overall size of the wafer, but the change in the curvature of the wafer is very obvious. At the same time, silicon oxide and silicon nitride can also serve as bonding interfaces. In some embodiments of the present application, it is necessary to ensure that the materials of the outermost layers of the two wafers to be bonded are silicon oxide and silicon nitride respectively.

[0078] Therefore, in the semiconductor structure described in the present application, silicon oxide materials and silicon nitride materials capable of adjusting the curvature are deposited on the wafer surface, so that the curvature of the wafer reaches the optimal value, the bonding quality is improved, the bubble defects are reduced, and thus the reliability during the period is improved.

[0079] Reference Figure 12 and Figure 18 As shown, the stacked wafer 200 includes a third stacked auxiliary layer 250, and a second groove bonding mark 260 is formed on the surface of the third stacked auxiliary layer 250. The bottom wafer 100 and the stacked wafer 200 are aligned and bonded through the bottom bonding mark and the second groove bonding mark.

[0080] In some embodiments of the present application, the third stacked auxiliary layer 250 includes a first stacked layer 251, a second stacked layer 252, and a third stacked layer 253 stacked in sequence. The second groove bonding mark 260 exposes the second stacked layer 252. The bottom of the second groove bonding mark 260 is lower than the top surface of the second stacked layer 252.

[0081] In some embodiments of the present application, the material of the third stacked layer 253 includes silicon oxide, such as TEOS, and the thickness of the third stacked layer 253 is 1800 angstroms to 2000 angstroms.

[0082] In some embodiments of the present application, the height of the second groove bonding mark 260 is 2500 angstroms to 3000 angstroms, such as 2600 angstroms or 2800 angstroms, etc.

[0083] Reference Figure 18 As shown, in some embodiments of the present application, the semiconductor structure further includes a second stacked wafer 400, the second stacked wafer 400 includes a second stacked substrate and a sixth stacked auxiliary layer 450 located on the second stacked substrate, and a fourth groove bonding mark 460 is formed on the surface of the sixth stacked auxiliary layer 450; reference Figure 6 And Figure 18 As shown, the side of the stacked wafer 200 away from the bottom wafer 100 further includes a first stacked auxiliary layer 220 and a second stacked auxiliary layer 230, and a first stacked bonding mark 240 is formed in the first stacked auxiliary layer 220; the stacked wafer 200 and the second stacked wafer 400 are aligned and bonded through the first stacked bonding mark 240 and the fourth groove bonding mark 460.

[0084] In some embodiments of the present application, by analogy with Figure 18 the structures of the stacked wafer 200 and the second stacked wafer 400 described above, the semiconductor structure may further include a third stacked wafer, a fourth stacked wafer to an Nth stacked wafer stacked in sequence, where N is a natural number greater than or equal to 2.

[0085] In some embodiments of the present application, both the bottom bonding mark 140 and the first stacked bonding mark 240 are metal bonding marks.

[0086] In some embodiments of the present application, the second groove bonding mark 260 is located in the bonding area 290 of the stacked wafer 200, and the bonding area is located in the diameter direction of the stacked wafer. Reference Figure 16 , the Figure 16 shows a plan view of the stacked wafer 200.

[0087] The surface of the wafer includes several dies. It is not necessary to make recessed bonding marks on each die. Only by making recessed bonding marks on a part of the dies (bonding areas) can alignment be achieved, which can save costs.

[0088] In some embodiments of the present application, the bonding areas are symmetric about the center of the wafer and close to the edge of the wafer.

[0089] For the semiconductor structure and its forming method described in the present application, an auxiliary layer capable of changing the curvature of the wafer is formed on the wafer surface, which can reduce the bubble defects after wafer bonding; using metal bonding marks and recessed bonding marks for alignment during bonding can save process costs; there is always a silicon surface on one side of the wafer, so the robotic arm for gripping the wafer does not need to be designed separately, and the risk of wafer dropping can also be reduced; before bonding, trimming the wafer can reduce the edge breakage defects and improve the device reliability.

[0090] In summary, after reading the content of the present application, those skilled in the art can understand that the foregoing application content can be presented only by way of example and may not be restrictive. Although not explicitly stated here, those skilled in the art can understand that the present application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are within the spirit and scope of the exemplary embodiments of the present application.

[0091] It should be understood that the term "and / or" used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there may also be intermediate elements.

[0092] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it can be directly on the other element, or there may also be intermediate elements. In contrast, the term "directly" means without intermediate elements. It should also be understood that the terms "comprise", "comprising", "include", or "including", when used in this application document, specify the presence of the recited features, wholes, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or groups thereof.

[0093] It should also be understood that although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element in some embodiments may be referred to as a second element in other embodiments without departing from the teachings of the present application. The same reference numerals or the same reference identifiers represent the same elements throughout the specification.

[0094] In addition, the present application specification describes exemplary embodiments by referring to idealized exemplary cross-sectional views and / or plan views and / or three-dimensional views. Accordingly, differences from the shapes shown due to, for example, manufacturing techniques and / or tolerances are foreseeable. Therefore, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but should include deviations in the shapes caused by, for example, manufacturing. For example, an etched region shown as rectangular will typically have rounded or curved features. Thus, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shape of the regions of the device nor to limit the scope of the exemplary embodiments.

Claims

1. A method for forming a semiconductor structure, characterized in that, Comprising: Providing a bottom wafer, the bottom wafer including a bottom substrate, a first bottom auxiliary layer, and a second bottom auxiliary layer sequentially located on the bottom substrate. A bottom bonding mark is formed in the first bottom auxiliary layer. The material of the first bottom auxiliary layer includes silicon oxide, and the material of the second bottom auxiliary layer includes silicon nitride; Providing a stacked wafer, the stacked wafer including a stacked substrate, a first stacked auxiliary layer, and a second stacked auxiliary layer sequentially located on the stacked substrate. A first stacked bonding mark is formed in the first stacked auxiliary layer; Providing a carrier wafer, the carrier wafer including a carrier substrate and a carrier auxiliary layer located on the carrier substrate. A groove bonding mark is formed on the surface of the carrier auxiliary layer. The carrier auxiliary layer includes a first carrier auxiliary layer, a second carrier auxiliary layer, and a third carrier auxiliary layer stacked in sequence. The material of the third carrier auxiliary layer includes silicon oxide; Aligning the groove bonding mark and the first stacked bonding mark, and bonding the carrier wafer and the stacked wafer; Thinning the other side of the stacked wafer to a set thickness; Forming a third stacked auxiliary layer on the other side of the stacked wafer, and forming a second groove bonding mark on the surface of the third stacked auxiliary layer. The third stacked auxiliary layer includes a first stacked layer, a second stacked layer, and a third stacked layer stacked in sequence. The material of the third stacked layer includes silicon oxide; Aligning the bottom bonding mark and the second groove bonding mark, and bonding the bottom wafer and the stacked wafer; Removing the carrier wafer.

2. The method for forming a semiconductor structure as described in claim 1, wherein, Further comprising: Performing a first trimming process on the stacked wafer.

3. The method for forming a semiconductor structure according to claim 1, wherein, Further comprising: After thinning the other side of the stacked wafer to a set thickness, performing a second trimming process on the carrier wafer and the stacked wafer.

4. The method for forming a semiconductor structure according to claim 1, wherein, The groove bonding mark is located in the bonding area of the carrier wafer, and the second groove bonding mark is located in the bonding area of the stacked wafer. The bonding areas are respectively located in the diameter direction of the wafer.

5. The method for forming a semiconductor structure according to claim 4, wherein, The bonding areas are symmetric about the center of the wafer near the edge of the wafer.

6. The method for forming a semiconductor structure according to claim 1, wherein The bottom bonding mark and the first stacked bonding mark are both metal bonding marks.

7. The method for forming a semiconductor structure as claimed in claim 1, wherein The method for forming the bottom wafer includes: Providing a bottom substrate; Depositing a first bottom auxiliary layer material on the bottom substrate; Forming a bottom bonding mark on the first bottom auxiliary layer material; Continuing to deposit the first bottom auxiliary layer material on the first bottom auxiliary layer material and the bottom bonding mark to form a first bottom auxiliary layer that completely covers the bottom bonding mark; Forming a second bottom auxiliary layer on the first bottom auxiliary layer.

8. The method for forming a semiconductor structure according to claim 7, wherein The method for forming the first bottom auxiliary layer further includes performing an annealing process and a chemical mechanical polishing process on the first bottom auxiliary material layer.

9. The method for forming a semiconductor structure as described in claim 1, wherein, The thickness of the first bottom auxiliary layer is 500 Å to 4000 Å, and the thickness of the second bottom auxiliary layer is 100 Å to 1000 Å.

10. The method for forming a semiconductor structure as described in claim 1, wherein, Further comprising: Providing a second stacked wafer and a second carrier wafer, the second stacked wafer and the second carrier wafer having the same structure as the stacked wafer and the carrier wafer; Using the stacked wafer and the bottom wafer after stacking as the new bottom wafer, bond the second stacked wafer to the new bottom wafer using the method for forming a semiconductor structure according to any one of claims 1 to 9.

11. The method for forming a semiconductor structure according to claim 10, wherein, Repeat the steps described in claim 10 to stack a third stacked wafer, a fourth stacked wafer up to an Nth stacked wafer on the second stacked wafer in sequence, where N is a natural number greater than or equal to 5.

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