Semiconductor structure and its formation method

Abstract

A semiconductor structure and a method for forming the same are disclosed. The method includes: providing a substrate, including a base and a fin protruding from the substrate; forming a gate structure across the fin on the substrate; the gate structure covering a portion of the top and a portion of the sidewalls of the fin; the fin extending along a first direction; and the gate structure extending along a second direction, the first and second directions being perpendicular; etching the gate structure at a location to be cut in the gate structure to form a partition opening; the partition opening dividing the gate structure in the second direction; and the end of the gate structure exposed at the partition opening protruding inward along the second direction. By making the end of the gate structure exposed at the partition opening protrude along the second direction, the distance between the end of the gate structure exposed at the partition opening and the adjacent fin covered by the gate structure is increased, thereby improving the controllability of the channel and thus improving the operating performance of the semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] With the gradual development of semiconductor process technology, semiconductor process nodes are continuously shrinking in accordance with Moore's Law. To adapt to the shrinking process nodes and the development of highly integrated semiconductor devices, the critical dimensions of metal-oxide-semiconductor (MOS) devices are also constantly shrinking, with gate length and gate pitch also shrinking to even smaller dimensions. Correspondingly, the manufacturing process of semiconductor devices is also constantly being improved to meet people's requirements for device performance.

[0003] Currently, the gate structure forming process typically employs gate cutting technology to cut the strip gate. The cut gate corresponds to different transistors, which can improve the transistor integration density. In addition, when multiple gates are arranged in a row along the extension direction, gate cutting technology can precisely reduce the spacing in the mating direction between the disconnected gates after gate cutting (Gate Cut CD). Summary of the Invention

[0004] The problem addressed by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, thereby improving the performance of the semiconductor structure.

[0005] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure, comprising: a substrate, including a base and a fin protruding from the substrate, the fin extending in a first direction; a gate structure, located on the substrate and spanning the fin, the gate structure covering a portion of the top and a portion of the sidewalls of the fin, the gate structure extending in a second direction, the first direction and the second direction being perpendicular; a partition opening located in the gate structure at a gate cut-off position, the partition opening dividing the gate structure in the second direction, wherein the end of the gate structure exposed by the partition opening protrudes into the partition opening along the second direction; and a gate isolation structure located in the partition opening.

[0006] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate, including a substrate and a fin protruding from the substrate, wherein a gate structure is formed on the substrate spanning the fin, the gate structure covering a portion of the top and a portion of the sidewalls of the fin, the fin extending along a first direction, the gate structure extending along a second direction, the first direction and the second direction being perpendicular; etching the gate structure at a location to be cut in the gate structure to form a partition opening in the gate structure, the partition opening dividing the gate structure in the second direction, and the end of the gate structure exposed by the partition opening protruding into the partition opening along the second direction.

[0007] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0008] In the semiconductor structure provided by this embodiment of the invention, in the gate structure located at the gate cut-off position, the partition opening divides the gate structure in the second direction. The end of the gate structure exposed by the partition opening protrudes into the partition opening along the second direction, thereby increasing the distance between the end (head) of the gate structure exposed by the partition opening and the adjacent fin covered by the gate structure. This is beneficial to improving the controllability of the channel and thus improving the working performance of the semiconductor structure.

[0009] In the formation method provided by the embodiments of the present invention, the gate structure is etched at the location to be cut in the gate structure to form a partition opening. The partition opening divides the gate structure in the second direction, and the end of the gate structure exposed by the partition opening protrudes into the partition opening along the second direction. By making the end of the gate structure exposed by the partition opening protrude along the second direction, the distance between the end of the gate structure exposed by the partition opening and the adjacent fin covered by the gate structure is increased, which is beneficial to improving the controllability of the channel and thus improving the working performance of the semiconductor structure. Attached Figure Description

[0010] Figures 1 to 4 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0011] Figures 5 to 7 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;

[0012] Figures 8 to 26 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0013] The performance of current semiconductor structures still needs improvement. This paper analyzes the reasons why the performance of a semiconductor structure still needs improvement, using an example of its formation method.

[0014] refer to Figures 1 to 4 The diagram shows a schematic representation of each step in a method for forming a semiconductor structure.

[0015] Reference Figure 1 and Figure 2 , Figure 1 This is a top view of the fin and gate structure. Figure 2 Based on Figure 1 A cross-sectional view along the AA direction is provided, showing a substrate including a substrate 10 and a fin 11 protruding from the substrate 10. A gate structure 20 is formed on the substrate 10 across the fin 11, the gate structure 20 covering a portion of the top and a portion of the sidewalls of the fin 11. The fin 11 extends along a first direction (not shown), and the gate structure 20 extends along a second direction (not shown), the first direction and the second direction being perpendicular to each other.

[0016] Reference Figure 3 and Figure 4 , Figure 3 This is a top view of the fin and gate structure. Figure 4 Based on Figure 3 A cross-sectional view along the AA direction, at the location to be cut in the gate structure 20 (e.g. Figure 3 (At the dashed box in the middle), the gate structure 20 is etched in a direction perpendicular to the surface of the substrate 10, forming a partition opening 42 in the gate structure 20, and the partition opening 42 divides the gate structure 20 in a second direction.

[0017] In order to form the isolation opening 42, the minimum linewidth dimension of the isolation opening 42 along the second direction is easily limited. As the feature size of the device continues to shrink, the spacing between adjacent fins 11 gradually decreases. Correspondingly, after forming the isolation opening 42, in the second direction, the distance between the end of the gate structure 20 exposed by the isolation opening 42 and the adjacent fin 11 covered by the gate structure 20 is easily reduced, thereby weakening the channel's controllability and affecting the working performance of the semiconductor structure.

[0018] To address the aforementioned technical problem, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, including a substrate and a fin protruding from the substrate, wherein a gate structure is formed on the substrate spanning the fin, the gate structure covering a portion of the top and a portion of the sidewalls of the fin, the fin extending along a first direction, and the gate structure extending along a second direction, the first direction and the second direction being perpendicular; etching the gate structure at a location to be cut in the gate structure to form a partition opening in the gate structure, the partition opening dividing the gate structure in the second direction, and the end of the gate structure exposed by the partition opening protruding into the partition opening along the second direction.

[0019] In the forming method provided by the embodiments of the present invention, by making the end of the gate structure exposed by the partition opening protrude along the second direction, the distance between the end of the gate structure exposed by the partition opening and the adjacent fin covered by the gate structure is increased, which is beneficial to improving the controllability of the channel and thus beneficial to improving the working performance of the semiconductor structure.

[0020] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0021] Reference Figures 5 to 7 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention. Figure 5 This is a top view of the fin and gate structure. Figure 6 Based on Figure 5 Sectional view along the AA direction. Figure 7 Based on Figure 5 A cross-sectional view along the CC direction.

[0022] The semiconductor structure includes: a substrate, comprising a substrate 101 and fins 111 protruding from the substrate 101, wherein the fins 111 extend in a first direction (e.g., ...). Figure 5 (As shown in the X direction); Gate structure 201, located on the substrate 101 and spanning the fin 111, the gate structure 201 covers part of the top and part of the sidewalls of the fin 111, and the extending direction of the gate structure 201 is a second direction (e.g., as shown in the X direction); Figure 5 (As shown in the Y direction), the first direction and the second direction are perpendicular; a partition opening (not shown) is located in the gate structure 201 at the gate cut-off position, the partition opening divides the gate structure 201 in the second direction, wherein the end 431 of the gate structure 201 exposed by the partition opening protrudes into the partition opening along the second direction; a gate partition structure 501 is located in the partition opening.

[0023] In the semiconductor structure provided by this embodiment of the invention, in the gate structure 201 located at the gate cut-off position, the partition opening divides the gate structure 201 in the second direction. The end 431 of the gate structure 201 exposed by the partition opening protrudes into the partition opening along the second direction, thereby increasing the distance between the end of the gate structure 201 exposed by the partition opening and the adjacent fin 111 covered by the gate structure 201. This is beneficial to improving the channel controllability and thus improving the working performance of the semiconductor structure.

[0024] The substrate provides the basis for the process operation of forming the semiconductor structure. In this embodiment, the substrate includes a substrate 101, and the material of the substrate 101 is silicon. In other embodiments, the material of the substrate 101 may also be one or more of germanium, silicon germanide, silicon carbide, gallium arsenide, and indium gallium dihydrogen phosphate. The substrate 101 may also be other types of substrates such as silicon-on-insulator substrates or germanium-on-insulator substrates. The material of the substrate 101 may be a material suitable for process requirements or easy to integrate.

[0025] The fin 111 is used to provide a channel for the fin field-effect transistor. In this embodiment, the fin 111 and the substrate 101 are integrally formed. In other embodiments, the fin 111 may also be a semiconductor layer epitaxially grown on the substrate 101, thereby achieving precise control over the height of the fin 101.

[0026] In this embodiment, the material of the fin 111 is the same as the material of the substrate 101, and the material of the fin 111 is silicon. In other embodiments, the material of the fin 111 may also be one or more of germanium, silicon germanide, silicon carbide, gallium arsenide, and indium gallium ide, and the material of the fin 111 may also be different from the material of the substrate 101.

[0027] The gate structure 201 includes a device gate structure or a pseudo-gate structure, wherein the device gate structure includes a metal gate structure. The device gate structure is used to control the switching on or off of the channel of the fin field-effect transistor. In this embodiment, the gate structure 201 is a metal gate structure, which includes a high-k gate dielectric layer (not shown), a work function layer (not shown) located on the high-k gate dielectric layer, and a gate electrode layer (not shown) located on the work function layer.

[0028] The high-k gate dielectric layer is made of a high-k dielectric material, which refers to a dielectric material with a relative permittivity greater than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer can be selected from HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc. As an example, the material of the high-k gate dielectric layer is HfO2.

[0029] The work function layer is used to adjust the threshold voltage of the transistor. When forming a PMOS transistor, the work function layer is a P-type work function layer, and the material of the P-type work function layer includes one or more of TiN, TaN, TaSiN, TaAlN, and TiAlN; when forming an NMOS transistor, the work function layer is an N-type work function layer, and the material of the N-type work function layer includes one or more of TiAl, Mo, MoN, AlN, and TiAlC.

[0030] The gate electrode layer is used to bring out the electrical properties of the gate structure 201. In this embodiment, the material of the gate electrode layer is Al, Cu, Ag, Au, Pt, Ni, Ti, or W.

[0031] In other embodiments, depending on process requirements, the gate structure may also be a polysilicon gate structure, which is used to control the switching on or off of the channel of the fin field-effect transistor. In other embodiments, the gate structure may also be a dummy gate structure, which occupies space for the subsequent formation of a metal gate structure. The dummy gate structure may be a single-layer structure or a multilayer structure, and the material of the dummy gate structure includes one or both of amorphous silicon and polysilicon. Alternatively, the material of the dummy gate structure may also include silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbonitride, or amorphous carbon.

[0032] The isolation opening provides space for the formation of the gate isolation structure 501. In this embodiment, the isolation opening is located in the gate structure 201 at the gate cut position. The gate cut position is the location where the gate structures 201 need to be separated and isolated from each other in the second direction.

[0033] The gate isolation structure 501 is used to insulate the gate structures 201 from each other.

[0034] It should be noted that if the gate structure 201 is a pseudo-gate structure, the gate isolation structure 501 is also used to provide a process platform for the subsequent formation of the device gate structure.

[0035] The gate isolation structure 501 is made of a material with high hardness and density, thereby reducing the probability of damage to the gate isolation structure 501 during the formation of the semiconductor structure, and thus ensuring the isolation performance of the gate isolation structure 501. For example, during the formation of the semiconductor structure, after the device gate structure is formed, a portion of the device gate structure may be removed according to process requirements. By making the material of the gate isolation structure 501 have high hardness and density, the probability of damage to the gate isolation structure 501 during the removal of the portion of the device gate structure can be effectively reduced, thus improving the integrity of the gate isolation structure 501.

[0036] In this embodiment, the gate isolation structure 501 is made of silicon nitride. In other embodiments, the gate isolation structure may also be made of other nitrogen-containing dielectric materials.

[0037] In this embodiment, the semiconductor structure further includes an interlayer dielectric layer 231 located on the substrate 101 on the side of the gate structure 201, and the interlayer dielectric layer 231 covers the sidewall of the gate structure 201.

[0038] The interlayer dielectric layer 231 serves as an isolation layer between adjacent devices. The material of the interlayer dielectric layer 231 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride. In this embodiment, the material of the interlayer dielectric layer 231 is silicon oxide.

[0039] In this embodiment, the semiconductor structure further includes a gate opening (not shown) that penetrates the interlayer dielectric layer 231 on both sides of the isolation opening, and the gate opening is connected to the isolation opening. The gate opening provides the basis for the process operation of forming the isolation opening, and also provides spatial location for the formation of the gate isolation structure 501.

[0040] Therefore, the gate isolation structure 501 is also located in the gate opening. That is, in the first direction, the gate isolation structure 501 penetrates the gate structure 201 and extends into a portion of the interlayer dielectric layer 231.

[0041] It should be noted that, in the first direction, the distance between the sidewalls of the gate opening linewidth d on either side of the gate structure 201 cannot be too large or too small. In the process of forming the isolation opening, the gate opening is formed first, and then the exposed sidewalls of the gate structure 201 are etched through the gate opening to form the isolation opening. If the linewidth d of the gate opening on either side of the gate structure 201 is too small, the process windows for forming both the gate opening and the isolation opening will be too small, increasing the difficulty of the process operations. If the linewidth d of the gate opening on either side of the gate structure 201 is too large, it will easily damage adjacent gate structures 201 during the process of forming the gate opening. Therefore, in the first direction, the linewidth d of the gate opening on either side of the gate structure 201 is 5 nanometers to 20 nanometers. For example, in the first direction, the linewidth d of the gate opening on either side of the gate structure 201 is 10 nanometers or 15 nanometers.

[0042] It should also be noted that, as an example, in the first direction, at the gate cut-off position, only one gate structure 201 is cut off. In other embodiments, along the first direction, at the gate cut-off position, multiple gate structures are cut off, that is, multiple isolation openings are connected in the first direction. Accordingly, the linewidth of the gate opening on any side of the gate structure refers to the linewidth of the gate opening located at the outermost edge in the first direction.

[0043] In this embodiment, the semiconductor structure further includes a gate cap layer 211, located on top of the gate structure 201 and extending to the top of the partition opening. The gate cap layer 211 is used to reduce damage to the gate structure 201 at the location corresponding to the partition opening during the gate opening formation process, thereby reducing the probability of a decrease in the height of the gate structure 201 at the location corresponding to the partition opening. This, in turn, helps ensure that the morphology of the end 431 of the gate structure 201 exposed by the partition opening meets process requirements.

[0044] In this embodiment, the gate cap layer 211 is a dielectric material. Specifically, the material of the gate cap layer 211 includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, boron nitride, and boron carbonitride. As an example, the material of the gate cap layer 211 is silicon nitride. In other embodiments, if the gate structure is a dummy gate structure, the gate cap layer is a hard mask layer and also serves as an etching mask in the process of forming the dummy gate structure.

[0045] In this embodiment, the interlayer dielectric layer 231 also covers the sidewalls of the capping layer 211 located on top of the gate structure 201. The gate capping layer 211 is formed by etching back the gate structure 201, so the interlayer dielectric layer 231 covering the sidewalls of the gate structure 201 also covers the sidewalls of the capping layer 211 located on top of the gate structure 201.

[0046] In this embodiment, the gate isolation structure 501 in the gate opening also covers the sidewall of the gate cap layer 211 located at the top of the isolation opening. That is, the gate isolation structure 501 fills the gate opening and the isolation opening, which is beneficial to improving the flatness of the top of the gate isolation structure 501, the top of the interlayer dielectric layer 231 and the top of the gate cap layer 211.

[0047] The thickness of the gate cap layer 211 cannot be too large or too small. If the thickness of the gate cap layer 211 is too large, it will occupy too much space in the gate structure 201, affecting the working performance of the gate structure 201; if the thickness of the gate cap layer 211 is too small, it will easily lead to poor protection of the top of the gate structure 201. Therefore, in this embodiment, the thickness of the gate cap layer 211 is 5 nanometers to 20 nanometers. For example, the thickness of the gate cap layer 211 is 10 nanometers or 15 nanometers.

[0048] In this embodiment, the semiconductor structure further includes a sidewall 221 located on the sidewall of the gate structure 201. The sidewall 221 is used to protect the sidewall of the gate structure 201 during the fabrication process of forming the semiconductor structure.

[0049] In this embodiment, the partition opening further extends into the sidewall 221 along the first direction and divides the sidewall 221 in the second direction. The gate opening is connected to the partition opening, thus the partition opening extends into the sidewall 221 along the first direction.

[0050] In this embodiment, the semiconductor structure further includes an isolation layer 121 located on the substrate 101 and covering a portion of the sidewalls of the fin 111. The isolation layer 121 is used to achieve insulation between different devices; for example, in CMOS manufacturing processes, an isolation layer is typically formed between NMOS transistors and PMOS transistors. The isolation layer 121 is made of an insulating material. As an example, the material of the isolation layer 121 is silicon oxide.

[0051] It should be noted that this embodiment uses gate structure 201 as an example for illustration. In other embodiments, when the gate structure is a dummy gate structure, in subsequent processes, it is necessary to remove the dummy gate structure, form a gate opening at the original position of the dummy gate structure, and then form the device gate structure (e.g., a metal gate structure) in the gate opening. Since the end of the gate structure protrudes into the partition opening along the second direction, the distance between the end of the gate structure and the adjacent fin along the second direction becomes larger. This correspondingly increases the distance from the sidewall of the gate opening in the second direction to the adjacent fin. When forming the device gate structure, it is easier for the device gate structure to fill the gap between the sidewall of the gate opening in the second direction and the adjacent fin, improving the filling performance when forming the device gate structure, thereby forming a higher quality device gate structure and improving the working performance of the semiconductor structure. In particular, metal gate structures are usually multilayer structures, which have higher requirements for filling performance.

[0052] Figures 8 to 26 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0053] Reference Figures 8 to 10 ,in, Figure 8 This is a top view of the fin and gate structure. Figure 9 Based on Figure 8 Sectional view along the AA direction. Figure 10 Based on Figure 8 A cross-sectional view along the CC direction, showing a substrate (not shown), including a substrate 100 and a fin 110 protruding from the substrate 100, wherein a gate structure 200 is formed on the substrate 100 across the fin 110, the gate structure 200 covering a portion of the top and a portion of the sidewalls of the fin 110, the fin 110 along a first direction (e.g., Figure 8 The gate structure 200 extends along the second direction (as shown in the X direction), and extends along the second direction (as shown in the X direction). Figure 8 Extending in the Y direction (as shown), the first and second directions are perpendicular.

[0054] The substrate provides the basis for the process operation of forming the semiconductor structure. In this embodiment, the substrate includes a substrate 100, which is made of silicon. In other embodiments, the substrate 100 may also be made of one or more of germanium, silicon germanide, silicon carbide, gallium arsenide, and indium gallium dihydrogen phosphate. The substrate 100 may also be other types of substrates such as silicon-on-insulator substrates or germanium-on-insulator substrates. The material of the substrate 100 may be a material suitable for process requirements or easy to integrate.

[0055] The fin 110 is used to provide a channel for the fin field-effect transistor. In this embodiment, the fin 110 and the substrate 100 are integrally formed. In other embodiments, the fin 110 may also be a semiconductor layer epitaxially grown on the substrate 100, thereby achieving precise control over the height of the fin 100.

[0056] In this embodiment, the material of the fin 110 is the same as the material of the substrate 100, and the material of the fin 110 is silicon. In other embodiments, the material of the fin may also be one or more of germanium, silicon germanide, silicon carbide, gallium arsenide, and indium gallium ide, and the material of the fin may also be different from the material of the substrate.

[0057] The gate structure 200 includes a device gate structure or a pseudo-gate structure, wherein the device gate structure includes a metal gate structure. The device gate structure is used to control the switching on or off of the channel of the fin field-effect transistor. In this embodiment, the gate structure 200 is a metal gate structure, which includes a high-k gate dielectric layer (not shown), a work function layer (not shown) located on the high-k gate dielectric layer, and a gate electrode layer (not shown) located on the work function layer.

[0058] The high-k gate dielectric layer is made of a high-k dielectric material, which refers to a dielectric material with a relative permittivity greater than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer can be selected from HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc. As an example, the material of the high-k gate dielectric layer is HfO2.

[0059] The work function layer is used to adjust the threshold voltage of the transistor. When forming a PMOS transistor, the work function layer is a P-type work function layer, and the material of the P-type work function layer includes one or more of TiN, TaN, TaSiN, TaAlN, and TiAlN; when forming an NMOS transistor, the work function layer is an N-type work function layer, and the material of the N-type work function layer includes one or more of TiAl, Mo, MoN, AlN, and TiAlC.

[0060] The gate electrode layer is used to bring out the electrical properties of the gate structure 200. In this embodiment, the material of the gate electrode layer is Al, Cu, Ag, Au, Pt, Ni, Ti, or W.

[0061] In other embodiments, depending on process requirements, the gate structure may also be a polysilicon gate structure, used to control the switching on or off of the channel of the fin field-effect transistor. In other embodiments, the gate structure may also be a dummy gate structure, occupying space for the subsequent formation of a metal gate structure. The dummy gate structure may be a single-layer structure or a multilayer structure, and the material of the dummy gate structure may include one or both of amorphous silicon and polysilicon. Alternatively, the material of the dummy gate structure may also include silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbonitride, or amorphous carbon.

[0062] In this embodiment, an interlayer dielectric layer 230 is formed on the substrate 100 on the side of the gate structure 200, and the interlayer dielectric layer 230 covers the sidewall of the gate structure 200. The interlayer dielectric layer 230 serves to isolate adjacent devices. The material of the interlayer dielectric layer 230 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride. As an example, the material of the interlayer dielectric layer 230 is silicon oxide.

[0063] In this embodiment, a sidewall 220 is formed on the sidewall of the gate structure 200. The sidewall 220 is used to protect the sidewall of the gate structure 200 during the manufacturing process. As an example, the material of the sidewall 220 is silicon nitride.

[0064] In this embodiment, during the step of providing the substrate, a gate cap layer 210 is formed on the top of the gate structure 200 (e.g., Figure 10 (As shown). Subsequent processes also include: at the location to be cut in the gate structure 200 (e.g.) Figure 8 (As shown in the dashed box), gate openings penetrating the interlayer dielectric layer 230 are formed on both sides of the gate structure 200. These gate openings expose the sidewalls of the gate structure 200 at the location to be cut. Through these gate openings, isotropic lateral etching is performed on the sidewalls of the gate structure 200 along a first direction to form an isolation opening in the gate structure. This isolation opening is connected to the gate opening. The gate cap layer 210 is used to reduce damage to the gate structure 200 at the location corresponding to the isolation opening during the gate opening formation process, thereby reducing the probability of a decrease in the height of the gate structure 200. This, in turn, helps ensure that the end morphology of the gate structure 200 exposed by the subsequent isolation opening meets process requirements.

[0065] In this embodiment, the gate cap layer 210 is a dielectric material. In this embodiment, the material of the gate cap layer 210 includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, boron nitride, and boron carbonitride.

[0066] In other embodiments, if the gate structure is a pseudo-gate structure, then the gate cap layer is a hard mask layer, which serves as an etching mask in the process of forming the pseudo-gate structure.

[0067] In this embodiment, the interlayer dielectric layer 230 also covers the sidewalls of the gate cap layer 210. Specifically, the step of forming the gate cap layer 210 includes: etching back a portion of the thickness of the gate structure 200 to form a groove (not shown) surrounded by the gate structure 200 and the interlayer dielectric layer 230; forming the gate cap layer 210 in the groove, the gate cap layer 210 covering the top of the gate structure 200.

[0068] The groove provides space for forming the gate cap layer 210, thereby improving the top surface flatness of the gate cap layer 210 and the interlayer dielectric layer 230.

[0069] In this embodiment, an anisotropic dry etching process is used to etch back the thickness of the gate structure 200. Using anisotropic dry etching is beneficial for controlling the thickness of the etch back. Furthermore, the anisotropic dry etching process has greater etching directionality, which is beneficial for improving the formation quality and dimensional accuracy of the groove sidewalls.

[0070] The depth of the groove cannot be too large or too small. If the groove depth is too large, the thickness of the gate cap layer 210 formed will be too large, and the gate cap layer 210 will occupy too much space of the gate structure 200, affecting the working performance of the gate structure 200. If the groove depth is too small, the thickness of the gate cap layer 210 formed will be too small, which may lead to poor protection of the top of the gate structure 200 by the gate cap layer 210. Therefore, in this embodiment, in the step of etching back a portion of the thickness of the gate structure 200, the depth of the groove is 5 nanometers to 20 nanometers. For example, the depth of the groove is 10 nanometers or 15 nanometers.

[0071] Reference Figures 9 to 20 At the location to be cut in the gate structure 200, the gate structure 200 is etched to form a partition opening 420 in the gate structure 200. The partition opening 420 divides the gate structure 200 in the second direction, and the end 430 of the gate structure 200 exposed by the partition opening 420 protrudes into the partition opening 420 along the second direction.

[0072] In this embodiment, by making the end 430 of the gate structure 200 exposed at the partition opening 420 protrude along the second direction, the distance between the end 430 of the gate structure 200 exposed at the partition opening 420 and the adjacent fin 110 covered by the gate structure 200 is increased, thereby improving the channel's controllability and consequently improving the operating performance of the semiconductor structure. Figure 8 As shown in the dashed box, the gate cut-off position is the position where the gate structure 200 needs to be divided and isolated from each other in the second direction.

[0073] The isolation opening 420 is used to provide space for the subsequent formation of the gate isolation structure.

[0074] In this embodiment, the step of etching the gate structure 200 includes: performing isotropic lateral etching on the sidewalls of the gate structure 200 along a first direction. During the isotropic lateral etching of the sidewalls of the gate structure 200, the sidewalls of the gate structure 200 gradually concave inward until the gate structure 200 is clamped off. This causes the end 430 of the gate structure 200 exposed by the partition opening 420 to protrude along the second direction after the partition opening 420 is formed.

[0075] In this embodiment, the lateral etching process includes one or more of isotropic dry etching, remote plasma etching, and wet etching. Isotropic dry etching, remote plasma etching, and wet etching processes have good isotropic characteristics, which is beneficial for achieving the effect of the exposed end 430 of the gate structure 200 protruding along the second direction at the isolation opening 420. Remote plasma etching also has good etching selectivity, thereby reducing the loss of other film layers during etching. The principle of remote plasma etching is to form plasma outside the etching chamber (e.g., by generating plasma through a remote plasma generator), then introduce it into the etching chamber and use the chemical reaction between the plasma and the layer to be etched for etching, thus achieving an isotropic etching effect. Furthermore, because there is no ion bombardment, the loss of other film layers can be reduced. In dry etching processes, isotropic etching effects are easily achieved by reducing the bias power.

[0076] Reference Figures 9 to 14 Before performing the lateral etching, the method further includes: forming a gate opening 410 through the interlayer dielectric layer 230 on both sides of the gate structure 200 at the location to be cut in the gate structure 200, with the gate opening 410 exposing the sidewall at the location to be cut in the gate structure 200.

[0077] The gate opening 410 provides a process operation basis for subsequent isotropic lateral etching of the sidewalls of the gate structure 200 along the first direction, and also provides a spatial location for the subsequent formation of the gate isolation structure.

[0078] Specifically, in conjunction with reference Figure 9 and Figure 10 ,in, Figure 9 Based on Figure 8 Sectional view along the AA direction. Figure 10 Based on Figure 8 The CC-direction cross-sectional view of the gate structure 200, before forming the gate openings 410 through the interlayer dielectric layer 230 on both sides of the gate structure 200, also includes: forming a mask layer 300 covering the interlayer dielectric layer 230.

[0079] After the subsequent patterning of the mask layer 300, the mask layer 300 is used as a mask for the subsequent formation of the gate opening 410.

[0080] In this embodiment, the mask layer 300 has a stacked structure, including a planarization layer 310 and a photoresist layer 320 located on the planarization layer 310. In this embodiment, the material of the planarization layer 310 is spin-on carbon (SOC). The mask layer 300 may also include an anti-reflective coating (not shown) located between the planarization layer 310 and the photoresist layer 320, and the material of the anti-reflective coating may be Si-ARC (silicon-containing anti-reflective coating).

[0081] Reference Figure 11 and Figure 12 ,in, Figure 11 Based on Figure 9 sectional view, Figure 12 Based on Figure 10 A cross-sectional view of the mask layer 300 is provided, which graphically represents the mask layer 300. A mask opening 330 is formed in the mask layer 300 at the location to be cut in the gate structure 200. The mask opening 330 extends along a first direction to both sides of the gate structure 200 and exposes the top of a portion of the interlayer dielectric layer 230 on both sides of the gate structure 200.

[0082] A mask opening 330 is formed, exposing the tops of portions of the interlayer dielectric layer 230 on both sides of the gate structure 200, in preparation for the subsequent formation of the gate opening 410. The mask opening 330 extends along a first direction towards both sides of the gate structure 200, exposing the tops of portions of the interlayer dielectric layer 230 on both sides of the gate structure 200. Compared to a scheme where the mask opening is only located at the top of the gate structure 200, this embodiment provides a larger process window for the photolithography process forming the mask opening 330. In this embodiment, after patterning the photoresist layer 320, the planarization layer 310 is etched using the photoresist layer 320 as a mask to form the opening 330 located in the mask layer.

[0083] Reference Figure 13 and Figure 14 ,in, Figure 13 Based on Figure 11 sectional view, Figure 14 Based on Figure 12 The cross-sectional view shows that the step of forming a gate opening 410 through the interlayer dielectric layer 230 on both sides of the gate structure 200 includes: using a mask layer 300 as a mask, removing the interlayer dielectric layer 230 exposed by the mask opening 330.

[0084] Using the mask layer 300 as a mask, removing the interlayer dielectric layer 230 exposed by the mask opening 330 facilitates the accurate transfer of the pattern of the mask opening 330. In this embodiment, the step of forming the gate opening 410 includes: using an anisotropic dry etching process to etch the interlayer dielectric layer 230 at the location to be cut in the gate structure 200. Using anisotropic dry etching helps reduce damage to the bottom isolation layer 120 of the gate opening 410 during the etching process. At the same time, the anisotropic dry etching process is more directional, which helps improve the morphological quality and dimensional accuracy of the sidewalls of the gate opening 410, thereby reducing damage to the sidewalls of other adjacent gate structures 200 that do not want to be laterally etched.

[0085] The linewidth d of the gate opening 410 on either side of the gate structure 200 cannot be too large or too small. In the process of forming the isolation opening 420, the gate opening 410 is formed first, and then the isolation opening 420 is formed by etching through the sidewall of the gate structure 200 exposed by the gate opening 410. If the linewidth d of the gate opening 410 on either side of the gate structure 200 is too small, the process window for forming the gate opening 410 will be too small, increasing the difficulty of the process operations for forming the gate opening 410 and the isolation opening. If the linewidth d of the gate opening 410 on either side of the gate structure 200 is too large, it will easily damage adjacent gate structures 200 during the process of forming the gate opening 410. Therefore, in the first direction, the linewidth d of the gate opening 410 on either side of the gate structure 200 is 5 nanometers to 20 nanometers. For example, in the first direction, the linewidth d of the gate opening 410 on either side of the gate structure 200 is 10 nanometers or 15 nanometers.

[0086] It should also be noted that, as an example, in the first direction, at the gate cut-off position, only one gate structure 200 is cut off. In other embodiments, along the first direction, at the gate cut-off position, multiple gate structures are cut off, that is, multiple isolation openings are connected in the first direction. Accordingly, the linewidth of the gate opening on any side of the gate structure refers to the linewidth of the gate opening located at the outermost edge in the first direction.

[0087] In this embodiment, after forming gate openings 410 penetrating the interlayer dielectric layer 230 on both sides of the gate structure 200, the method further includes removing the mask layer 300. Removing the mask layer 300 provides a platform foundation for subsequent process steps. As an example, after forming the isolation opening in the gate structure 200, the mask layer 300 is removed, ensuring that the mask layer 300 can still protect areas other than the cut-off location in the gate structure 200, thereby improving process reliability.

[0088] Reference Figures 15 to 17 ,in, Figure 15 This is a top view of the fin and gate structure. Figure 16 Based on Figure 15 Sectional view along the AA direction. Figure 17 Based on Figure 15 The CC-direction cross-sectional view, the step of forming the isolation opening 420 further includes: before isotropic lateral etching of the gate structure 200 along the first direction through the gate opening 410, isotropic lateral etching of the sidewall 220 along the first direction at the position to be cut in the gate structure 200 until the sidewall of the gate structure 200 is exposed.

[0089] Isotropic lateral etching is performed on the sidewall 220 along the first direction to expose the sidewall of the gate structure 200, preparing for subsequent lateral etching of the sidewall of the gate structure 200 along the first direction. In this embodiment, by performing isotropic lateral etching on the sidewall 220 along the first direction, the sidewall 220 and the gate structure 200 can be laterally etched sequentially.

[0090] Reference Figures 18 to 20 ,in, Figure 18 This is a top view of the fin and gate structure. Figure 19 Based on Figure 18 Sectional view along the AA direction. Figure 20 Based on Figure 18 A cross-sectional view along the CC direction shows that, through the gate opening 410, isotropic lateral etching is performed on the sidewall of the gate structure 200 along the first direction, and the isolation opening 420 is connected to the gate opening 410.

[0091] The isolation opening 420 is connected to the gate opening 410, which helps to effectively ensure that the gate structure 200 is completely disconnected at the position to be cut off.

[0092] In this embodiment, after isotropic lateral etching of the sidewall 220 along the first direction, the process parameters are adjusted, and isotropic lateral etching of the sidewall of the gate structure 200 is continued along the first direction, etching each film layer in the gate structure 200 layer by layer.

[0093] In this embodiment, after forming the isolation opening 420, the gate capping layer 210 at the location to be cut in the gate structure 200 is retained, thereby eliminating the need to remove the gate capping layer 210 at that location. In other embodiments, depending on the actual situation, the gate capping layer at the location to be cut in the gate structure is removed during the lateral etching process. In other embodiments, after forming the isolation opening, the gate capping layer at the location to be cut in the gate structure may also be removed according to process requirements.

[0094] Reference Figures 21 to 23 ,in, Figure 21 This is a top view of the fin and gate structure. Figure 22 Based on Figure 21 Sectional view along the AA direction. Figure 23 Based on Figure 21 A cross-sectional view along the CC direction, showing the removal of the mask layer 300 after the isolation opening 420 is formed in the gate structure 200.

[0095] After the isolation opening 420 is formed in the gate structure 200, the mask layer 300 is removed. The mask layer 300 can protect the interlayer dielectric layer 230 when the isolation opening 420 is formed, and at the same time, it helps to maintain the morphological accuracy of the gate opening 410. Removing the mask layer 300 is used to prepare for subsequent process operations.

[0096] Reference Figures 24 to 26 ,in, Figure 24 This is a top view of the fin and gate structure. Figure 25 Based on Figure 24 Sectional view along the AA direction. Figure 26 Based on Figure 24 The CC-direction cross-sectional view, after forming the isolation opening 420, further includes: forming a gate isolation structure 500 in the isolation opening 420.

[0097] The gate isolation structure 501 is used to insulate the gate structures 201 from each other.

[0098] The gate isolation structure 500 is made of a material with high hardness and density, thereby reducing the probability of damage to the gate isolation structure 500 during the formation of the semiconductor structure, and thus ensuring the isolation performance of the gate isolation structure 500. For example, during the formation of the semiconductor structure, after the device gate structure is formed, a portion of the device gate structure may be removed according to process requirements. By making the material of the gate isolation structure 500 have high hardness and density, the probability of damage to the gate isolation structure 500 during the removal of part of the device gate structure can be effectively reduced, thus improving the integrity of the gate isolation structure 500.

[0099] In this embodiment, the gate isolation structure 500 is made of silicon nitride. In other embodiments, the gate isolation structure may also be made of other nitrogen-containing dielectric materials.

[0100] It should be noted that this embodiment uses gate structure 200 as an example for illustration. In other embodiments, when the gate structure is a pseudo-gate structure, the gate isolation structure also provides a process platform for the subsequent formation of a metal gate structure. Moreover, when the gate structure is a pseudo-gate structure, in subsequent processes, it is necessary to remove the pseudo-gate structure, form a gate opening at the original position of the pseudo-gate structure, and then form the device gate structure in the gate opening. Wherein, the end of the gate structure protrudes into the isolation opening along the second direction, and the linewidth dimension between the end of the gate structure and the adjacent fin along the second direction becomes larger. This correspondingly increases the distance from the sidewall of the gate opening in the second direction to the adjacent fin. When forming the device gate structure, it is easier for the device gate structure to fill the gap between the sidewall of the gate opening in the second direction and the adjacent fin, improving the filling performance when forming the device gate structure, thereby forming a higher quality device gate structure and improving the working performance of the semiconductor structure.

[0101] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized by, The semiconductor structure comprises: a substrate comprising a base substrate and a fin standing on the base substrate, the fin extending in a first direction; a gate structure on the base substrate and across the fin, the gate structure covering part of a top and part of a sidewall of the fin, the gate structure extending in a second direction, the first direction being perpendicular to the second direction; a gate cut-off opening in the gate structure at a gate cut-off position, the gate cut-off opening dividing the gate structure in the second direction, wherein a terminal of the gate structure exposed by the gate cut-off opening protrudes into the gate cut-off opening in the second direction; a gate cut-off structure in the gate cut-off opening.

2. The semiconductor structure of claim 1, wherein, The semiconductor structure further comprises: an interlayer dielectric layer on the base substrate at a side of the gate structure, the interlayer dielectric layer covering the sidewall of the gate structure; a gate opening through the interlayer dielectric layer on both sides of the gate cut-off opening, the gate opening being in communication with the gate cut-off opening; 3. The semiconductor structure of claim 2, wherein, the gate cut-off structure is further in the gate opening. The semiconductor structure further comprises: a gate cap layer on the top of the gate structure and extending to the top of the gate cut-off opening; 4. The semiconductor structure of claim 1, wherein, the interlayer dielectric layer further covers a sidewall of the gate cap layer on the top of the gate structure; the gate cut-off structure in the gate opening further covers a sidewall of the gate cap layer on the top of the gate cut-off opening.

5. The semiconductor structure of claim 2, wherein, The semiconductor structure further comprises:

6. The semiconductor structure of claim 3, wherein, a sidewall on the sidewall of the gate structure; 7. The semiconductor structure of claim 3, wherein, the gate cut-off opening further extends into the sidewall in the first direction and divides the sidewall in the second direction.

8. The semiconductor structure of claim 1, wherein, In the first direction, a line width dimension of the gate opening on either side of the gate structure is 5-20 nm.

9. A method of forming a semiconductor structure, comprising: The gate cap layer has a thickness of 5-20 nm. The gate cap layer comprises one or more of silicon nitride, silicon carbide, silicon carbon nitride, silicon carbon nitrogen oxide, silicon nitrogen oxide, boron nitride and boron carbon nitride. The gate structure comprises a device gate structure or a dummy gate structure, the device gate structure comprising a metal gate structure.

10. The method of forming a semiconductor structure of claim 9, wherein, The semiconductor structure comprises:

11. The method of forming a semiconductor structure of claim 10, wherein, a substrate comprising a base substrate and a fin standing on the base substrate, the base substrate having a gate structure formed thereon and crossing the fin, the gate structure covering part of a top and part of a sidewall of the fin, the fin extending in a first direction, the gate structure extending in a second direction, the first direction being perpendicular to the second direction; at a position to be cut off in the gate structure, etching the gate structure to form a gate cut-off opening in the gate structure, the gate cut-off opening dividing the gate structure in the second direction, and a terminal of the gate structure exposed by the gate cut-off opening protruding into the gate cut-off opening in the second direction. The step of etching the gate structure comprises isotropic lateral etching of the sidewall of the gate structure in the first direction. In the step of providing the substrate, an interlayer dielectric layer is formed on the base substrate at a side of the gate structure, the interlayer dielectric layer covering the sidewall of the gate structure; Before the lateral etching, further comprising: forming a gate opening through the interlayer dielectric layer at the position to be cut off of the gate structure, the gate opening exposing the sidewall of the gate structure at the position to be cut off; The lateral etching of the sidewall of the gate structure is performed through the gate opening along the first direction, and the isolation opening is in communication with the gate opening.

12. The method of forming a semiconductor structure of claim 11, wherein, Before forming the gate opening through the interlayer dielectric layer at the two sides of the gate structure, further comprising: forming a mask layer covering the interlayer dielectric layer; Patterning the mask layer to form a mask opening in the mask layer at the position to be cut off of the gate structure, the mask opening extending to the two sides of the gate structure along the first direction and exposing the top of the interlayer dielectric layer at the two sides of the gate structure; The step of forming the gate opening through the interlayer dielectric layer at the two sides of the gate structure comprises: removing the interlayer dielectric layer exposed by the mask opening with the mask layer as a mask. After forming the gate opening through the interlayer dielectric layer at the two sides of the gate structure, further comprising: removing the mask layer.

13. The method of forming a semiconductor structure of claim 12, wherein, After forming the isolation opening in the gate structure, the mask layer is removed.

14. The method of forming a semiconductor structure of claim 10, wherein, In the step of providing the substrate, a sidewall is formed on the sidewall of the gate structure; The step of forming the isolation opening further comprises: before the lateral etching of the gate structure along the first direction, performing the lateral etching of the sidewall along the first direction at the position to be cut off of the gate structure until the sidewall of the gate structure is exposed.

15. The method of forming a semiconductor structure of claim 11, wherein, In the step of providing the substrate, a gate cap layer is formed on the top of the gate structure; The interlayer dielectric layer also covers the sidewall of the gate cap layer.

16. The method of forming a semiconductor structure of claim 15, wherein, The step of forming the gate cap layer comprises: etching back a partial thickness of the gate structure to form a groove surrounded by the gate structure and the interlayer dielectric layer; The gate cap layer is formed in the groove, and the gate cap layer covers the top of the gate structure.

17. The method of forming a semiconductor structure of claim 15, wherein, During the lateral etching, the gate cap layer at the position to be cut off of the gate structure is removed; Or, After forming the isolation opening in the gate structure, the gate cap layer at the position to be cut off of the gate structure is removed. Or, After forming the isolation opening in the gate structure, the gate cap layer at the position to be cut off of the gate structure is retained.

18. The method of forming a semiconductor structure of claim 9 or 11, wherein, After forming the isolation opening, further comprising: forming a gate isolation structure in the isolation opening.

19. The method of forming a semiconductor structure of claim 10 or 14, wherein, The lateral etching process comprises one or more of an isotropic dry etching process, a remote plasma etching process, and a wet etching process.

20. The method of forming a semiconductor structure of claim 11, wherein, The step of forming the gate opening comprises: using an anisotropic dry etching process to etch the interlayer dielectric layer at the position to be cut off of the gate structure.

21. The method of forming a semiconductor structure of claim 9, wherein, The gate structure comprises a device gate structure or a dummy gate structure, and the device gate structure comprises a metal gate structure.

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