read only memory

Abstract

Embodiments of the present disclosure relate to read-only memories. The present description relates to a ROM comprising at least one first rewritable memory cell.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of French application number FR 2013741, filed on 18 December 2020, which is incorporated herein by reference. Technical Field

[0003] This disclosure generally relates to electronic systems and devices, and in particular to memory circuits or memories. More specifically, this disclosure relates to read-only memory (ROM). Background Technology

[0004] Currently, the miniaturization and performance improvement of electronic devices necessitate improvements in data storage devices. In fact, memory must become smaller and larger while storing increasingly more data.

[0005] There are many different types of memory. In fact, in some types of memory, the stored data can be accessed and / or modified at any time, while in others, data is stored only when power is applied.

[0006] Flash memory is a type of volatile storage, meaning that data can be written to and / or modified at any time.

[0007] ROM is a non-rewritable memory, in which data is typically written during manufacturing and cannot be modified. Data stored in ROM can only be viewed.

[0008] The aim is to at least partially improve certain aspects of known ROMs. Summary of the Invention

[0009] A smaller ROM is needed.

[0010] The ROM needs to be more resistant to hacking techniques, such as reverse engineering.

[0011] The embodiments overcome all or some of the shortcomings of known ROMs.

[0012] An embodiment provides a ROM that includes at least one first rewritable memory cell.

[0013] According to one embodiment, the first memory cell is of type e-STM.

[0014] According to one embodiment, the ROM further includes at least one second memory cell that includes a transistor.

[0015] According to the embodiment, the transistor is a MOS transistor.

[0016] According to the embodiment, the transistor is an N-channel MOS transistor.

[0017] According to an embodiment, when the threshold voltage of the first memory cell or the second memory cell is higher than the threshold, the first memory cell or the second memory cell represents a first bit value, and when the threshold voltage is lower than the threshold, the first memory cell or the second memory cell represents a second bit value that is different from the first bit value.

[0018] According to an embodiment, the first memory cell and the second memory cell include a structure that sequentially includes: a doped substrate of a first conductivity type; a first semiconductor layer of a second conductivity type located on the substrate; and a second semiconductor layer of the first conductivity type located on the first semiconductor layer.

[0019] According to an embodiment, the first memory cell includes a first insulating gate and a second insulating gate stacked on top of each other.

[0020] According to an embodiment, the first insulating gate and the second insulating gate of the first memory cell are disposed on a first portion of the surface of the structure.

[0021] According to an embodiment, the second memory cell includes a third insulating gate, the thickness of which is equal to the sum of the thicknesses of the first insulating gate and the second insulating gate of the first memory cell.

[0022] Another embodiment provides a method for manufacturing a ROM including at least one third rewritable memory cell and at least one fourth memory cell, the memory cell including a transistor, the method comprising the following sequential steps: sequentially depositing a first insulating layer and a first gate layer on a semiconductor structure; forming a cavity at the gate location of the transistor of the fourth memory cell in the first gate layer; and sequentially depositing a second insulating layer and a second gate layer.

[0023] According to one embodiment, the structure sequentially includes: a second doped substrate of a first conductivity type; a third semiconductor layer of a second conductivity type located on the substrate; and a third semiconductor layer of a first conductivity type located on the first semiconductor layer.

[0024] According to one embodiment, the method further includes the steps of etching a first insulating gate and a second insulating layer, and etching a second gate layer capable of forming the insulating gate of the at least one second memory cell.

[0025] According to an embodiment, the third rewritable memory cell is of type e-STM.

[0026] According to an embodiment, the method further includes the steps of etching a first insulating gate and a second insulating layer, and etching a first gate layer and a second gate layer, such that a stack of two insulating gates of a third memory cell of type e-STM can be formed.

[0027] According to an embodiment, the semiconductor structure includes at least one trench made of semiconductor material, and the gate location of the transistor of the fourth memory cell is laterally defined on one side by the at least one trench.

[0028] Another embodiment provides a ROM that includes at least a first memory cell and a second memory cell of type e-STM, each memory cell including a first insulating gate and a second insulating gate stacked on top of each other, wherein the first insulating gate is electrically coupled to the second insulating gate.

[0029] According to one embodiment, when the threshold voltage of the first memory cell or the second memory cell is higher than the threshold, the first memory cell or the second memory cell represents a first bit value, and when the threshold voltage is lower than the threshold, the first or the second memory cell represents a second bit value that is different from the first bit value.

[0030] According to an embodiment, the first memory cell further includes an N-type doped well.

[0031] According to one embodiment, the trap has a dopant implant concentration in the range of 1x10^13 to 5x10^13 at.cm^(-3).

[0032] According to one embodiment, the well is disposed under the first gate of the first memory cell.

[0033] According to one embodiment, the first insulating gate of the first memory cell includes a first insulating layer, and the first insulating gate of the second memory cell includes a second insulating layer.

[0034] According to an embodiment, the material of the first insulating layer is different from the material of the second insulating layer.

[0035] According to an embodiment, the materials of the first insulating layer and the second insulating layer are silicon oxide.

[0036] According to an embodiment, the thickness of the first insulating layer is different from the thickness of the second insulating layer.

[0037] According to an embodiment, the thickness of the first insulating layer and the thickness of the second insulating layer are in the range of 5 to 20 nm.

[0038] According to one embodiment, the thickness of the first insulating layer is about 15 nm, and the thickness of the second insulating layer is about 8.7 nm.

[0039] According to an embodiment, the first memory cell and the second memory cell are sequentially formed by the following structure: a doped substrate of a first conductivity type; a first semiconductor layer of a second conductivity type located on the substrate; and a second semiconductor layer of a first conductivity type located on the first semiconductor layer.

[0040] According to one embodiment, a first insulating gate and a second insulating gate are formed on a first portion of the surface of the structure.

[0041] Another embodiment provides a method of manufacturing a ROM, the ROM including at least a first memory cell and a second memory cell of type e-STM, each memory cell including a first insulating gate and a second insulating gate stacked on top of each other, wherein a via is formed through the first insulating gate to couple the first insulating gate to the second insulating gate. Attached Figure Description

[0042] The above features, advantages, and other contents will be described in detail in the following description of specific embodiments, which are given by way of illustration rather than limitation, with reference to the accompanying drawings, wherein:

[0043] Figure 1 A simplified top view in block form is shown in the ROM embodiment;

[0044] Figure 2 It shows Figure 1 A cross-sectional view of an embodiment of two memory cells of a ROM;

[0045] Figure 3 The illustration is shown. Figure 2 Charts showing the electronic properties of memory cells;

[0046] Figure 4 Two cross-sectional views are shown, illustrating the manufacturing process. Figure 2 Method steps for memory cell;

[0047] Figure 5 Two cross-sectional views are shown, illustrating the manufacturing process. Figure 2 Other steps in the method for memory cells;

[0048] Figure 6 It shows Figure 1 A more detailed top view of the ROM embodiment;

[0049] Figure 7 It shows Figure 1 A more detailed top view of another embodiment of the ROM;

[0050] Figure 8 It shows Figure 1 A cross-sectional view of an embodiment of the other two memory cells of the ROM;

[0051] Figure 9 It shows Figure 8 Electronic characteristic diagrams of memory cells; and

[0052] Figure 10 It shows Figure 1 A cross-sectional view of an embodiment of the other two memory cells of the ROM. Detailed Implementation

[0053] Similar features have been designated by similar reference numerals in the various figures. Specifically, common structural and / or functional features in the various embodiments may have the same reference numerals and may be configured with the same structure, dimensions, and material properties.

[0054] For clarity, only the steps and elements that aid in understanding the embodiments described herein are described in detail. Specifically, this document does not describe the read, power supply, write, and other circuitry typically associated with memory, and the ROM is compatible with the most commonly used read, power supply, write, and other circuitry.

[0055] Unless otherwise stated, when referring to two elements connected together, it means that there is no direct connection between them except for the conductor, and when referring to two elements coupled together, it means that the two elements can be connected or coupled through one or more other elements.

[0056] In the following disclosure, unless otherwise specified, when referring to absolute positional qualifiers such as the terms “front,” “back,” “up,” “down,” “left,” “right,” etc., or relative positional qualifiers such as the terms “above,” “below,” “upper,” “lower,” etc., or directional qualifiers such as “horizontal,” “vertical,” etc., refer to the directions shown in the figure.

[0057] Unless otherwise specified, the expressions “approximately,” “roughly,” “substantially,” and “basically” shall be within 10%, preferably within 5%.

[0058] Typically, the following terminology is used: a lightly doped semiconductor layer refers to a doping atom concentration of 10-1. 14 Up to 5x10 15 Layers within the range of at.cm^(-3); heavily doped semiconductor layers with a specified doping atom concentration of 10. 17 Up to 10 18 Layers within the range of at.cm^(-3); and very heavily doped semiconductor layers specify a doping atom concentration of 10. 18 Up to 10 20 Layers within the range of at.cm^(-3).

[0059] Figure 1 This is a very simplified top view of ROM 100.

[0060] ROM 100 includes memory cells arranged in an array, that is, arranged in rows and columns. Figure 1The image shows only two rows and two columns of memory cells. Each memory cell is suitable for representing binary information, i.e., "one" (1) or "zero" (0).

[0061] ROM 100 more specifically includes two different types of memory cells, each representing a bit value. The first type of memory cell 102 is adapted to represent a binary "1", and the second type of memory cell 104 is adapted to represent a binary "0". Figure 1 In the diagram, memory cell 102 is shown as an empty block, and memory cell 104 is shown as a block including a cross. Figure 2 A first embodiment of two types of memory cells capable of being used in a ROM of type 100 is shown. Similarly, Figure 8 and Figure 10 Examples of two types of memory cells that can be used in ROM are shown respectively.

[0062] ROM 100 may include circuitry that allows it to operate, such as readout circuitry, encryption and / or decryption circuitry, etc. Figure 1 These circuits are not shown in the diagram.

[0063] Figure 2 This is a cross-sectional view of one embodiment of two memory cells 200 and 202, which are adapted to be used with... Figure 1 The relevant ROM is of type 100.

[0064] Memory cell 200 is shown in Figure 2 Part (A)( Figure 2 On the left side, memory cell 202 is shown. Figure 2 Part (B)( Figure 2 On the right side). Combined Figure 4 and Figure 5 Examples of implementations of methods for manufacturing memory cells 200 and 202.

[0065] Memory cells 200 and 202 are formed side by side on structure 204. Structure 204 includes a p-type doped semiconductor substrate 206 (p-), for example, lightly p-type doped. Figure 2Only the upper portion of substrate 206 is shown. Substrate 206 is made of silicon doped with boron atoms, for example. The structure also includes a semiconductor layer 208 formed on surface 210 of substrate 206. Layer 208 (N-) is N-type doped, for example, lightly N-type doped. Layer 208 is made of silicon doped with phosphorus atoms, for example. The thickness of layer 208 ranges from 0.5 to 10 μm, for example, about 1 μm. The structure also includes a semiconductor layer 212 (P-) formed on surface 214 of layer 208. Layer 212 is P-type doped, for example, lightly P-type doped. Layer 212 is made of silicon doped with boron atoms, for example. The thickness of layer 212 ranges from 0.1 to 1 μm, for example, about 0.5 μm.

[0066] Memory cell 200 is an N-channel metal-oxide-semiconductor transistor, with its N-type doped source region formed by layer 208 and its P-type doped substrate region formed by layer 212. Here, the substrate region of the N-channel MOS transistor is defined as a P-type doped substrate or well, a portion of which forms the transistor channel region.

[0067] Well 216(N+) is formed by the first portion 218 of the surface of layer 212, located in Figure 2 The left side of part A. Well 216 is N-type doped, for example, heavily N-type doped. Well 216 forms the drain region of memory cell 200. Contact 217 may be formed on well 216. For example, well 216 is made of silicon doped with phosphorus atoms. The depth to which well 216 extends downward ranges from 0.01 to 0.5 μm, for example, about 0.2 μm.

[0068] An insulating gate 220 is formed on a second portion 222 of the surface of layer 212. The portion 222 is located on... Figure 2 To the right of portion (A), and arranged next to portion 218. An insulating gate 220 forms the gate of memory cell 200. The insulating gate 220 includes two insulating layers 224 and 226 and a gate layer 228. Insulating layer 224 is located on portion 222 of the surface of layer 212. Insulating layer 224 is made of silicon oxide (SiO2) and has a thickness ranging from 5 to 10 nm, for example, about 8.7 nm, or 87 angstroms. Insulating layer 226 is located on the surface of layer 224. Insulating layer 226 is made of oxide-nitride-oxide alloy and has a thickness ranging from 10 to 15 nm, for example, about 12.7 nm, or 127 angstroms. Gate layer 228 is located on the surface of insulating layer 226. Gate layer 228 is made of polysilicon and has a thickness ranging from 50 to 500 nm, for example, about 200 nm.

[0069] Optionally, the N-type doped well 230(I) can be formed from portion 222. Well 230 can enable adjustment of the threshold voltage of the transistor formed by the memory cell 200.

[0070] Memory cell 200 is separated from memory cell 202 by a semiconductor trench 232 that extends through the entire thickness of layer 212, i.e., all the way to the surface 214 of layer 208. Furthermore, layer 208 may include a thickened portion 234 at its contact point with the trench 232. The thickened portion 234 can be obtained by implanting phosphorus atoms. The trench 232 is made of, for example, polysilicon. The width of the trench 232 ranges from 50 nm to 500 nm, for example, approximately 120 nm.

[0071] Memory cell 202 is an e-STM (embedded selected in-Trench Memory) type memory cell. e-STM type memory cells are rewritable memory cells commonly used in flash memory. Memory cell 202 has a structure similar to that of memory cell 200, and is thus mirrored. Therefore, similar to memory cell 200, memory cell 202 includes a well 236 formed by a portion 238 on the surface of layer 212, similar to well 216. The portion 238 is located in... Figure 2 On the right side of portion (B), a contact 239 may be formed on well 236. Memory cell 202 also includes a stack of two insulated gates formed on portion 240 of the surface of layer 212, which is located on... Figure 2 The left side of section (B). Section 240 extends from trench 232 to section 238 on the surface of layer 212. The stack of two insulating gates on section 240 sequentially includes: an insulating layer 242 identical to the insulating layer 224 of the memory cell 200 in the fabrication dispersion, directly on section 240; a first gate layer 244 on insulating layer 242; an insulating layer 246 identical to the insulating layer 226 of the memory cell 200 (within the fabrication difference), directly on layer 244; and a second gate 248 on insulating layer 246.

[0072] Therefore, memory cell 202 includes a first insulating gate formed by layers 242 and 244, and a second insulating gate formed by layers 246 and 248.

[0073] Furthermore, similar to memory cell 200, memory cell 202 may optionally include an N-type doped well 250 (I) formed by a portion 240 of the surface of layer 212. Well 250 may enable adjustment of the threshold voltage of the transistor formed by memory cell 200.

[0074] Gate layers 244 and 248 are made of, for example, polysilicon. For example, gate layers 244 and 248 have similar or even equal thicknesses. The thickness of gate layers 244 and 248 ranges from 50 to 500 nm, for example, approximately 100 nm.

[0075] The stacked insulating gate 220 of memory cell 200 and the two insulating gates of memory cell 202 have similar or even equal thicknesses. More specifically, the thickness of gate layer 228 of memory cell 200 is equal to the sum of the thicknesses of gate layers 244 and 248 of memory cell 202.

[0076] Memory cells 200 and 202 have different threshold voltages, which allows them to be used as memory cells for ROM. In practice, the threshold voltage level of the memory cell can be used as a data bit encoding device. According to one example, when the threshold voltage level is greater than a reference level, the memory cell can represent binary "one" (1), and conversely, when the threshold voltage level is less than the reference level, the memory cell can represent binary "zero" (0). According to a variation, the opposite can be envisioned. For memory cells of type 200, i.e., for transistors, the threshold voltage is defined and adjusted by manufacturing based on the size and materials used. For memory cells of type 202, the threshold voltage is defined by manufacturing based on the size and materials used, but can also be adjusted during its use by erasing or writing to the memory cell. Regarding Figure 3 The threshold voltage adjustment of memory cells of type 202 is further described in detail.

[0077] Combination Figure 4 and Figure 5 Methods for manufacturing memory cells 200 and 202 are described.

[0078] Figure 3 It shows the combination Figure 2 A graph showing the threshold voltage levels of memory cells of types 200 and 202. The vertical axis of this graph is in volts (V).

[0079] By convention, the threshold voltage VTMOS of memory cells of type 200 (i.e., memory cells formed by MOS transistors) is set to 1V as a reference. This voltage is used by the VTMOS. Figure 3 The figure shows a wire-supported VTMOS symbol.

[0080] Figure 3 The graph was plotted by measuring the threshold voltage of multiple memory cells of the same size (within the range of manufacturing differences) of type 202 formed on the same substrate.

[0081] The first set of points 301 represents the measurement of the threshold voltage of a memory cell of type 202 at the end of manufacturing, i.e., before an erase or write operation. The threshold voltage extends from approximately -3V to approximately 1.8V. The range of the threshold voltage extension is quite wide and cannot distinguish between the threshold voltage of a memory cell of type 202 and the threshold voltage of a memory cell of type 200.

[0082] The second set of points 302 represents the threshold voltage measurement of a memory cell of type 202 after all erase operations have been committed. The threshold voltage extends from approximately -3.5V to approximately -1.2V. This range is quite far from the reference threshold voltage of VTMOS. According to an embodiment, consider a ROM comprising memory cells of type 200 and memory cells of type 202, where the memory cells of type 202 have a lower threshold than those of type 200, such that the memory cells of type 202 can represent binary "zero" (0) and the memory cells of type 200 can represent binary "one" (1). According to an alternative embodiment, the opposite is conceivable.

[0083] The third set of points 303 represents the threshold voltage measurement of a memory cell of type 202 after all write operations have been committed. The threshold voltage extends from approximately 2.6V to approximately 4.8V. This range differs significantly from the reference threshold voltage of VTMOS. According to another embodiment, consider a ROM comprising memory cells of type 200 and type 202, where the memory cells of type 202 have a higher threshold voltage than those of type 200, wherein the memory cells of type 202 can represent binary "1" (1) and the memory cells of type 200 can represent binary "0" (0). According to an alternative embodiment, the opposite is conceivable.

[0084] Figure 4 and Figure 5 Views (a), (b), (c), and (d) illustrate the sequential steps of a method for fabricating two memory cells of type 200 and 202 side-by-side on the same substrate.

[0085] and Figure 2 Similarly, each view (a), (b), (c), and (d) includes a portion (A) on the left side of the view and a portion (B) on the right side of the view. Memory cells of type 200 are manufactured in portion (A) of views (a) to (d), and memory cells of type 202 are manufactured in portion (B) of views (a) to (d).

[0086] View (a) shows the steps of manufacturing structure 401, which is for bonding Figure 2 The described structure is of type 204. Therefore, structure 401 includes, as partially shown, a P-type doped substrate 403 having a stack of N-type doped semiconductor layers 405 and P-type doped semiconductor layers 407 thereon. Substrate 403 and layers 405 and 407 are respectively bonded to substrate 206. Figure 2 Layers 208 and 212 are described as identical. Therefore, similar to layer 208, layer 405 exhibits a thickened portion 409 at the location of a trench of type 232, such as... Figure 2 Layers 206 and 208 are sequentially deposited on substrate 403 to form structure 401.

[0087] View (a) further illustrates the steps of forming the groove 411, which is in conjunction with... Figure 2 The trench 232 is identical. This formation step includes, for example, the step of horizontally etching a trench in the thickened portion 409 of layer 405 and the step of filling the trench. The filling step can be performed before the trench wall oxidation step. The oxidation step can, for example, prevent ohmic contact between the trench filling material and the material of layer 407. According to an example, the trench is filled with polycrystalline silicon. For this purpose, the trench can be filled with amorphous silicon, and then one or more crystallization steps are performed to form polycrystalline silicon.

[0088] After the etching trench step, an implantation step can be performed to form a bond. Figure 2 The described traps are of type 230 and 250.

[0089] View (a) further illustrates the step of depositing an insulating layer 413 on the entire surface of structure 401. This step follows the step of forming trench 411. The insulating layer 413 is formed by bonding... Figure 2 Layers 224 and 242 are made of the same material. The thickness of insulating layer 413 is in the range of 5 to 10 nm, for example, on the order of 8.7 nm, or 87 angstroms.

[0090] View (a) further illustrates the step of depositing a gate layer 415 on the entire surface of the insulating layer 413. The gate layer 415 is formed by bonding... Figure 2 The gate layer 244 described is made of the same material. The gate layer 415 has a thickness in the range of 20 nm to 200 nm, for example, on the order of 100 nm.

[0091] View (b) illustrates the step of etching a cavity 417 in layer 415 extending at least downwards to the surface of insulating layer 413. The cavity 417 is formed on the side of portion (A) of view (b). More specifically, the location of the cavity 417 specifies the location of the insulating gate of a memory cell of type 200 to be manufactured. The cavity 417 is formed, for example, by a method including a masking step and an etching step.

[0092] View (b) further illustrates the step of depositing an insulating layer 419 on the entire surface of the structure obtained after the etching step, particularly at the bottom of cavity 417. The insulating layer 419 is formed by bonding... Figure 2 Layers 226 and 246 are made of the same material. The thickness of insulating layer 413 ranges from 10 to 15 nm, for example, about 12.7 nm, or 127 angstroms.

[0093] View (c) illustrates the step of depositing a gate layer 421 on the entire surface of the structure shown in view (b). The gate layer 421 fills the entire cavity 417, and its surface is defined as horizontal in view (c). The gate layer 421 is formed by bonding... Figure 2 The gate layers 228 and 248 are made of the same material, i.e., polysilicon, for example. The thickness of the gate layer 421 ranges from 20 to 200 nm, for example, about 80 nm.

[0094] View (d) illustrates an etching step for isolating the insulating gate 423 of a memory cell of type 200 from the stack 425 of two insulating gates of a memory cell of type 202. During this step, the insulating gate 423 and the stack 425 are laterally defined, after which excess layers 413, 415, 419, and 421 are removed. This step may include the use of multiple successive masking and etching steps. (About...) Figure 6 and Figure 7 The results of this step in the top view are described in more detail.

[0095] View (d) further illustrates the completion of the manufacturing process. This completion includes: doping and Figure 2 Two similar wells 427 and 429 are described in relation to wells 216 and 218; and contacts 431 are formed on wells 427 and 429, similar to... Figure 2 The contacts 217 and 239 are mentioned.

[0096] Part (A) of view (d) then shows a memory cell 433 of type 200, and part (B) then shows a memory cell 435 of type 202.

[0097] The advantage of the method described in this article is that it can use Figure 2The memory cells are manufactured as ROMs, with only one etching step, namely the etching step shown in view (b), which is capable of distinguishing memory cells representing binary "zero" and memory cells representing binary "one".

[0098] Figure 6 It shows the relationship with Figure 1 A more detailed top view of a simplified embodiment of the related ROM 100 type ROM 500.

[0099] ROM 500 includes six memory cells arranged in two rows and three columns. According to one example, ROM 500 includes five memory cells 501, whose type is related to... Figure 2 The memory unit 202 and the memory unit 503 are of the type about Figure 2 The memory unit 200.

[0100] In ROM 500, rows of memory cells are formed in pairs. Within each pair, two rows of memory cells are formed by... Figure 2 The semiconductor trench 505 of the semiconductor trench type 232 is separated. The trench 505 extends completely along the row of memory cells, so it is common to all memory cells in the same row. According to the example, contacts may be formed at the ends of the trench 505. In a top view, the width of the trench 505 is, for example, in the range of 20 to 200 nm, on the order of 100 nm.

[0101] Furthermore, memory cells 501 and 503 in the same row share a common insulated gate 507. More specifically, memory cell 503 has its own insulated gate (i.e., Figure 2 The insulating gate 220 is the same as the second insulating gate of the memory cell 501 (i.e., it is formed by...). Figure 2 The layers 246 and 248 form an insulating gate. According to an example, contacts may be formed at the ends of the insulating gate 507. In a top view, the width of the insulating gate 507 is, for example, in the range of 50 to 500 nm, on the order of 90 nm.

[0102] Furthermore, the memory cells 501 in the same column share a common first insulating gate 509. The first insulating gate 509 of the memory cell 501 corresponds to the structure formed by the insulating layer 242 and the bonding... Figure 2 The gate layer 244 described is an insulating gate formed therefrom. When the column includes memory cell 503 (i.e., a memory cell including a single insulating gate), the insulating gate 509 shows a recess at the level of the insulating gate of that memory cell. In fact, as per [the description of the gate layer 244]... Figure 4 and Figure 5The gate layer capable of forming the first gate layer of the memory cell 501 is etched at the location where the insulating gate of the memory cell 503 is formed. According to an example, the contact 511 can be formed regarding... Figure 2 The ends of the N-type doped wells of types 216 and 236 are horizontal. In a top view, the width of the insulating gate 509 is, for example, in the range of 20 to 200 nm, on the order of 60 nm.

[0103] The advantage of using memory cells 501 and 503 is that they can be formed with a diameter of 0.037 μm. 2 The size of the memory cell in top view is smaller than the area of ​​a ROM memory cell, which is typically 0.052 μm. 2 size.

[0104] Another advantage is that the ROM using memory cells 501 and 503 is less sensitive to reverse engineering attacks.

[0105] Figure 7 A more detailed top view of another simplified embodiment of ROM 600 is shown.

[0106] ROM 600 is similar to ROM 500, including memory cells 501 and 503. In contrast to ROM 500, ROM 600 includes four memory cells 501 and two memory cells 503. Furthermore, the two memory cells 503 are located in the same column.

[0107] Similar to ROM 500, in ROM 600, memory cell rows are formed in pairs. In each pair of rows, the two memory cell rows are separated by a semiconductor trench 505 that extends along the memory cell row and is therefore shared by all memory cells in the same row. Furthermore, memory cells 501 and 503 in the same row have a common insulated gate 507.

[0108] Furthermore, similar to the insulating gate 509 of the ROM 500, the memory cells 501 in the same column share a common first insulating gate 601. The first insulating gate 601 of the memory cell 501 corresponds to the structure formed by the insulating layer 242 and the bonding... Figure 2 The gate layer 244 described is an insulating gate formed therefrom. When the column includes memory cells 503 (i.e., memory cells including a single insulating gate), the insulating gate 601 shows a groove at the level of the insulating gate of the memory cell 503. Furthermore, when the column includes two memory cells 503 side-by-side, forming a groove in the insulating gate 601 at the gate location of the transistor 503 may be technically difficult due to the precision requirements of the etching apparatus. Therefore, the width of the insulating gate 601 is increased such that the remaining portion after the groove is formed is within the... Figure 7 The horizontal width of the insulating gate 601 is sufficient to reach the insulating gate of the adjacent column. According to one example, contacts may be formed at the ends of the insulating gate 601.

[0109] Figure 8 This is a cross-sectional view of another embodiment of two memory cells 700 and 702, which are adapted to be used with... Figure 1 The relevant ROM type 100 is included in the ROM.

[0110] Memory cell 700 is shown in Figure 8 Part (A)( Figure 8 On the left side, memory cell 702 is shown. Figure 8 Part (B)( Figure 8 (on the right side of the text).

[0111] Memory cells 700 and 702 are combined with Figure 2 The memory cell 202 described is similar. The common elements of memory cells 202, 700 and 702 will not be described in detail below, and only their differences will be highlighted.

[0112] Similar to memory cell 202, memory cells 700 and 702 are formed on a stacked structure 204, which sequentially includes: a P-type doped semiconductor substrate 206; an N-type doped semiconductor layer 208; and a P-type doped semiconductor layer 212.

[0113] Layer 212 includes an N-type doped well 236 extending horizontally on its surface portion 238. Contact 239 is capable of contacting the well.

[0114] Similar to memory cells 200 and 202, memory cells 700 and 702 are separated by semiconductor trenches 232 formed in layer 208, which extend to the thickened portion 234 of layer 208.

[0115] Similar to memory cell 202, memory cells 700 and 702 include a stack of two insulating gates formed on a portion 240 of the surface of layer 212. A first insulating gate is formed by an insulating layer 242 and a gate layer 244, and a second insulating gate is formed by an insulating layer 246 and a gate layer 248. However, memory cells 700 and 702 differ from memory cell 202 in that their insulating gates are coupled (preferably connected) to each other. The operation of memory cells 700 and 702 then resembles that of a transistor. According to one example, the two insulating gates of memory cells 700 and 702 are connected by forming a via in the second insulating gate that extends to the first insulating gate. The two insulating gates are connected by connecting this via to another via connected to the second insulating gate.

[0116] The memory cells 700 and 702 differ from each other in that memory cell 700 includes a well 703(I) formed in layer 212 beneath the stack of two insulating gates, while memory cell 702 does not include this well 703. The well 703 and... Figure 2 The 250 wells are similar. Therefore, well 703 is obtained through N-type doping. The dopant concentration of well 703 can be in the range of 1 x 10^13 to 5 x 10^13 at.cm^(-3), for example, on the order of 3 x 10^13 at.cm^(-3). Well 703 makes it possible to adjust the threshold voltage of memory cell 700. (Regarding...) Figure 9 The effects of the trap were described in more detail.

[0117] The advantage of using memory cells 700 and 702 is that, in a top view, memory cells 700 and 702 are indivisible.

[0118] Figure 9 It is shown that... Figure 2 A graph showing the threshold voltage levels of memory cells of types 700 and 702. The vertical axis of this graph is in volts (V). The horizontal axis represents different doping levels of the 703 well in at.cm^(-3).

[0119] To obtain this graph, measurements were taken on two different sets of memory cells 700 and 702, where each doping level of well 703 includes two sets of points representing different voltage thresholds.

[0120] The two first groups 801 represent the measurement of the threshold voltage of the memory cell 702 excluding the well 703. The threshold voltage value extends between 0.850 and 1.350 V.

[0121] The two second groups 802 represent the threshold voltage measurements of memory cell 700, which includes a well 703 with a doping level on the order of 1 x 10^13 at.cm^(-3). The threshold voltage values ​​extend between 0.330 and 0.900 V.

[0122] The two third groups of 803 represent the threshold voltage measurements of memory cell 700, which includes a well 703 with a doping level on the order of 2 x 10^13 at.cm^(-3). The threshold voltage values ​​extend between -0.250 and 0.450 V.

[0123] The two fourth groups 804 represent the threshold voltage measurements of memory cell 700, which includes a well 703 with a doping level on the order of 3 x 10^13 at.cm^(-3). The threshold voltage values ​​extend between -1.270 and 0V.

[0124] The increase in the implanted dose level of trap 703 makes it possible to modify the threshold voltage of memory cell 700. Similar to memory cells 200 and 202, memory cells 700 and 702 can be used in a ROM of type memory 100 by using their threshold voltages as binary data encoding means. According to an example, memory cell 702 can, for example, represent binary "zero" (0), and memory cell 700 can, for example, represent binary "one" (1). According to a variation, the opposite is conceivable.

[0125] Figure 10 This is a cross-sectional view of another embodiment of two memory cells 900 and 902, which are adapted to be used with... Figure 1 The relevant ROM is of type 100.

[0126] Memory cell 900 is shown in Figure 10 Part (A)( Figure 10 In the left part, memory cell 902 is shown. Figure 10 Part (B)( Figure 10 (in the right part of the text).

[0127] Memory cells 900 and 902 and Figure 2 The memory cell 700 is similar. The common elements of memory cells 700, 900, and 902 will not be described in detail below, and only their differences will be highlighted.

[0128] Similar to memory cell 700, memory cells 900 and 902 are formed by a stacked structure 204, which sequentially includes: a P-type doped semiconductor substrate 206; an N-type doped semiconductor layer 208; and a P-type doped semiconductor layer 212.

[0129] Layer 212 includes an N-type doped well 236 extending horizontally on its surface portion 238. Contact 239 is capable of contacting the well.

[0130] Similar to memory cells 700 and 702, memory cells 900 and 902 are separated by semiconductor trenches 232 formed in layer 208, which extend to the thickened portion 234 of layer 208.

[0131] Similar to memory cell 700, memory cells 900 and 902 include a stack of two insulated gates formed on a portion 240 of the surface of layer 212. However, memory cells 900 and 902 include a stack of two different insulated gates. More specifically, memory cell 900 includes a stack 905 of two insulated gates formed on a portion 240 of the surface of layer 212. Stack 905 sequentially includes: an insulating layer 907 directly disposed on the portion 240; a first gate layer 244 disposed on the insulating layer 907; an insulating layer 246 disposed directly on the layer 244; and a second gate layer 248 disposed on the insulating layer 246.

[0132] The memory cell 902 includes a stack 909 of two insulated gates formed on a portion 240 of the surface of layer 212. The stack 909 includes, in sequence: an insulating layer 911 directly disposed on the portion 240; a first gate layer 244 disposed on the insulating layer 911; an insulating layer 246 directly disposed on the layer 244; and a second gate layer 248 disposed on the insulating layer 246.

[0133] Similar to memory cell 702, the two insulated gates of memory cells 900 and 902 are coupled to each other (preferably connected). Then, the operation of memory cells 900 and 902 is similar to the operation of a transistor.

[0134] According to one embodiment, insulating layers 907 and 911 are made of different materials, for example, with Figure 2 The insulating layer 242 is made of the same material as high-voltage insulating materials, such as silicon oxide. Layers 907 and 911 also have different thicknesses. By changing the thickness and material of layers 907 and 911, the threshold voltage of memory cells 900 and 902 can be adjusted.

[0135] According to one embodiment, insulating layer 907 is made of a high-voltage insulating material and has a thickness ranging from 10 to 20 nm, for example, about 15 nm. Insulating layer 911 and Figure 2 The insulating layer 242 is the same, that is, it is made of silicon oxide and has a thickness between 5 and 10 nm, for example, about 8.7 nm.

[0136] Memory cells 900 and 902 include a well 703 formed in layer 212 and extending from a portion 240 of the surface of layer 212. According to an alternative embodiment, memory cells 900 and 902 may not include the well 703.

[0137] The advantage of using memory cells 900 and 902 is that, in a top view, memory cells 900 and 902 are indivisible.

[0138] The embodiments described herein are further directed to ROMs having all or some of the features described below.

[0139] A ROM includes at least a first memory cell and a second memory cell (700, 702; 900, 902) of type e-STM, each memory cell including a first insulating gate (242, 244; 907; 909) and a second insulating gate (246, 248) stacked on top of each other, wherein the first insulating gate (242, 244; 907; 909) is electrically coupled to the second insulating gate (246, 248).

[0140] A memory wherein when a threshold voltage of a first memory cell (700; 900) or a second memory cell (702; 902) is higher than a threshold, the first memory cell or the second memory cell (702; 902) represents a first bit value, and when the threshold voltage is lower than the threshold, the first memory cell or the second memory cell (702; 902) represents a second bit value different from the first value.

[0141] A memory, wherein the first memory cell (700; 900) further includes an N-type doped well (703).

[0142] A memory wherein the well has a dopant implantation concentration in the range of 1 x 10^13 to 5 x 10^13 at.cm^(-3).

[0143] A memory wherein the trap (703) is disposed under the first gate (242, 244) of the first memory cell (700).

[0144] A memory wherein a first insulating gate (907, 244) of a first memory cell (900) includes a first insulating layer (907), and a first insulating gate (909, 244) of a second memory cell (902) includes a second insulating layer (909).

[0145] A memory in which the material of a first insulating layer (907) is different from the material of a second insulating layer (909).

[0146] A memory wherein the first insulating layer (907) and the second insulating layer (909) are made of silicon oxide.

[0147] A memory in which the thickness of a first insulating layer (907) is different from the thickness of a second insulating layer (909).

[0148] A memory wherein the thickness of a first insulating layer (907) and the thickness of a second insulating layer (909) are in the range of 5 to 20 nm.

[0149] A memory wherein a first insulating layer (907) has a thickness of about 15 nm and a second insulating layer (909) has a thickness of about 8.7 nm.

[0150] A memory, wherein a first memory cell and a second memory cell (700, 702; 900, 902) are sequentially formed by a structure (204): a doped substrate (206) of a first conductivity type; a first semiconductor layer (208) of a second conductivity type located on the substrate (206); and a second semiconductor layer (212) of a first conductivity type located on the first semiconductor layer (208).

[0151] A memory wherein a first insulating gate and a second insulating gate (242, 244, 246, 248; 907, 909) are formed on a first portion (240) of the surface of the structure (204).

[0152] A method of manufacturing a ROM, the ROM comprising at least a first memory cell and a second memory cell (700, 702; 900, 902) of e-STM type, each memory cell comprising a first insulating gate (242, 244; 907, 909) and a second insulating gate (246, 248) stacked on top of each other, wherein vias are formed through the first insulating gate (242, 244; 907, 909) to couple the first insulating gate (242, 244; 907, 909) to the second insulating gate (246, 248).

[0153] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these different embodiments and variations can be combined, and other variations will occur to those skilled in the art.

[0154] Finally, based on the functional indications given above, the actual implementation of the embodiments and variations is within the capabilities of those skilled in the art.

Claims

1. A memory, comprising: The first type of memory cell is an embedded trench-selectable memory type memory cell; as well as The second type of memory cell, each of the second type of memory cells including a transistor; The memory cell of the first type includes a first insulating gate and a second insulating gate stacked on top of each other; and The transistor of the second type of memory cell includes a third insulating gate, the thickness of which is equal to the sum of the thicknesses of the first insulating gate and the second insulating gate of the first type of memory cell.

2. The memory of claim 1, wherein during operation, the memory operates as a read-only memory, wherein bits of a first state are defined by memory cells of the first type, and bits of a second state are defined by memory cells of the second type.

3. The memory according to claim 1, wherein the transistor is a metal-oxide-semiconductor (MOS) transistor.

4. The memory according to claim 3, wherein the transistor is an N-channel MOS transistor.

5. The memory of claim 1, wherein when the first threshold voltage of the transistor of the first type of memory cell is higher than the reference threshold voltage, the transistor of the first type of memory cell represents a first bit value, and when the first threshold voltage of the transistor of the first type of memory cell is lower than the reference threshold voltage, the transistor of the first type of memory cell represents a second bit value different from the first bit value.

6. The memory according to claim 1, wherein the first type of memory cell and the transistor comprise a structure, the structure comprising: Doped substrate of the first conductivity type; A first semiconductor layer of a second conductivity type is located on the doped substrate; and A second semiconductor layer of a first conductivity type is located on the first semiconductor layer.

7. The memory of claim 6, wherein the first insulating gate and the second insulating gate of the first type of memory cell are disposed on a first portion of the surface of the structure.

8. A read-only memory (ROM), comprising: Multiple memory cells, each of the multiple memory cells comprising: Field-effect transistors are used to provide a reference threshold voltage; and A memory transistor has a first threshold voltage higher than the reference threshold voltage and a second threshold voltage lower than the reference threshold voltage. When the memory transistor has the first threshold voltage, the memory cell stores a first bit value, and when the memory transistor has the second threshold voltage, the memory cell stores a second bit value. The memory transistors mentioned above include a first insulating gate and a second insulating gate stacked on top of each other. The field-effect transistor includes a third insulating gate, the thickness of which is equal to the sum of the thicknesses of the first insulating gate and the second insulating gate of the memory transistor.

9. The read-only memory (ROM) according to claim 8, wherein the memory transistor is an embedded trench in-select memory (e-STM) type, and wherein the field-effect transistor is a metal-oxide-semiconductor (MOS) transistor.

10. The read-only memory (ROM) according to claim 8, wherein the field-effect transistor and the memory transistor comprise a structure, the structure comprising in sequence: Doped substrate of the first conductivity type; A first semiconductor layer of a second conductivity type is located on the doped substrate; as well as A second semiconductor layer of a first conductivity type is located on the first semiconductor layer.

11. The read-only memory (ROM) of claim 10, wherein the first insulating gate and the second insulating gate of the memory transistor are disposed on a first portion of the surface of the structure.

12. A method of manufacturing a read-only memory (ROM), the ROM comprising a plurality of memory cells, each of the plurality of memory cells comprising a rewritable first transistor and a second transistor, the method comprising: A first insulating layer and a first gate layer are sequentially deposited on a semiconductor structure; A cavity is formed at the location of the gate of the second transistor in the first gate layer; The second insulating layer and the second gate layer are deposited sequentially; Etching the first insulating layer, the second insulating layer, and the second gate layer enables the formation of the insulating gate of the second transistor; as well as The first insulating layer and the second insulating layer, as well as the first gate layer and the second gate layer, are etched to form a stack of two insulating gates of the first transistor, wherein the insulating gate of the second transistor has a thickness equal to the sum of the thicknesses of the two insulating gates of the first transistor.

13. The method according to claim 12, wherein the structure comprises, in sequence: Second doped substrate of first conductivity type; A third semiconductor layer of the second conductivity type is located on the second doped substrate; as well as A fourth semiconductor layer of the first conductivity type is located on the third semiconductor layer.

14. The method of claim 12, wherein the first transistor is of type e-STM.

15. The method of claim 12, wherein the semiconductor structure includes at least one trench made of a semiconductor material, and the location of the gate of the second transistor is laterally defined on one side by the at least one trench.

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