A manufacturing method of three-dimensional memory and three-dimensional memory

Abstract

An embodiment of the present invention discloses a three-dimensional memory and a manufacturing method thereof. The manufacturing method includes: providing a semiconductor structure, the semiconductor structure including a storage area and an alignment area, wherein a first conductive wire loop, a lower phase change memory unit, and a second conductive wire loop are arranged in the storage area; using an etching process to form a first trench and a second trench in the storage area and the alignment area, respectively, wherein the first trench is used to remove two ends of the first conductive wire loop and two ends of the second conductive wire loop to form a first conductive line and a second conductive line, respectively; forming a first dielectric layer, the first dielectric layer covering the semiconductor structure and filling the first trench and the second trench, and having a gap in the second trench; performing a planarization process on the first dielectric layer and the semiconductor structure to expose the second conductive line and the gap; and forming an upper phase change memory stack material layer on the semiconductor structure, wherein the upper phase change memory stack material layer has a recess formed above the gap, wherein the recess constitutes a first alignment mark.

Description

Technical Field

[0001] The present invention relates to the technical field of three-dimensional memory, and in particular to a manufacturing method of a three-dimensional memory and the three-dimensional memory. Background Art

[0002] A three-dimensional memory (e.g., a three-dimensional phase change memory) includes a storage area and an alignment area. The storage area is used to set the device structure. The device structure includes a memory cell array and a peripheral circuit. The memory cell array is mainly used to store data, and the peripheral circuit is mainly used to implement functional control of phase change memory operations (read operations, write operations, etc.).

[0003] During the manufacturing process of a three-dimensional memory, alignment marks in an alignment region are usually used for alignment control to achieve alignment between device structures formed in the device region. Summary of the Invention

[0004] In view of this, embodiments of the present invention provide a method for manufacturing a three-dimensional memory and a three-dimensional memory to solve at least one problem existing in the background technology.

[0005] To achieve the above object, the technical solution of the present invention is achieved as follows:

[0006] An embodiment of the present invention provides a method for manufacturing a three-dimensional memory, the method comprising:

[0007] A semiconductor structure is provided, comprising a storage area and an alignment area, wherein a first conductive wire loop, a lower phase-change memory unit, and a second conductive wire loop are arranged from bottom to top in the storage area;

[0008] Using an etching process, a first trench and a second trench are formed in the storage area and the alignment area, respectively; wherein the first trench is used to remove two ends of the first conductive wire loop and two ends of the second conductive wire loop to form a first conductive wire and a second conductive wire, respectively;

[0009] forming a first dielectric layer, wherein the first dielectric layer covers the semiconductor structure and fills the first trench and the second trench; wherein the second trench has a gap that is not filled by the first dielectric layer;

[0010] performing a planarization process on the first dielectric layer and the semiconductor structure to expose the second conductive line and the gap;

[0011] An upper phase-change memory stack material layer is formed on the semiconductor structure. A recess is formed in the upper phase-change memory stack material layer above the gap, and the recess constitutes a first alignment mark.

[0012] In the above solution, the aspect ratio of the second trench is greater than 2.

[0013] In the above solution, the first dielectric layer is formed on the semiconductor structure by chemical vapor deposition.

[0014] In the above solution, the semiconductor structure further includes a substrate and an insulating layer formed on the substrate; wherein the first conductive wire loop, the lower phase-change memory unit and the second conductive wire loop are located in the insulating layer.

[0015] In the above solution, the semiconductor structure further includes a second dielectric layer, and the second dielectric layer covers the surface of the second conductive wire loop and the surface of the insulating layer.

[0016] In the above solution, forming the second trench in the alignment region includes: etching and removing a portion of the second dielectric layer and a portion of the insulating layer located in the alignment region to form the second trench.

[0017] In the above scheme, forming a first trench in the storage area includes: etching and removing part of the second dielectric layer, part of the insulating layer, and the two ends of the first conductive wire loop and the two ends of the second conductive wire loop surrounded by part of the insulating layer located in the storage area to form the first trench; wherein, after the two ends of the first conductive wire loop are removed, a plurality of first conductive wires extending along the first direction are formed, and after the two ends of the second conductive wire loop are removed, a plurality of second conductive wires extending along the second direction are formed.

[0018] In the above solution, performing a planarization process on the first dielectric layer and the semiconductor structure includes performing a grinding process on the first dielectric layer, the second dielectric layer and the insulating layer to expose the second conductive line and the gap in the second trench.

[0019] In the above solution, after forming the upper phase change memory stack material layer, the method further includes:

[0020] Using the first alignment mark as an alignment base point, etching the upper phase change memory stack material layer and the insulating layer to form a third trench on the alignment area, wherein the third trench constitutes a second alignment mark;

[0021] The upper phase-change memory stack material layer located on the storage area is etched using the second alignment mark as an alignment base point to form a plurality of upper memory cell structures extending along the second direction.

[0022] An embodiment of the present invention further provides a three-dimensional memory, comprising:

[0023] A semiconductor structure comprising a storage area and an alignment area, wherein a first conductive line, a lower phase-change memory unit, and a second conductive line are arranged in the storage area from bottom to top;

[0024] A first groove and a second groove are respectively located in the storage area and the alignment area;

[0025] a first dielectric layer filling the first trench and the second trench; wherein the second trench has a gap not filled by the first dielectric layer;

[0026] An upper phase-change memory stack material layer is located on the semiconductor structure; wherein the upper phase-change memory stack material layer fills the gap and forms a recess above the gap, and the recess constitutes a first alignment mark.

[0027] An embodiment of the present invention provides a three-dimensional memory and a manufacturing method thereof, wherein the manufacturing method includes: providing a semiconductor structure, wherein the semiconductor structure includes a storage area and an alignment area; using an etching process to form a first trench and a second trench in the storage area and the alignment area, respectively; forming a first dielectric layer on the semiconductor structure, wherein the first dielectric layer fills the first trench and the second trench; wherein the second trench has a gap that is not filled by the first dielectric layer; performing a planarization process; wherein the planarization process exposes the gap in the second trench; and forming an upper phase-change storage stack material layer on the semiconductor structure, wherein the upper phase-change storage stack material layer has a recess formed at a position above the gap, wherein the recess constitutes a first alignment mark. The embodiment of the present invention adopts an etching process to form a first groove in the storage area and a second groove in the alignment area at the same time, and utilizes the gap formed in the second groove to transfer the position information of the second groove to the upper phase change storage stack material layer, that is, the recess constituting the first alignment mark. Therefore, the manufacturing method provided by the embodiment of the present invention can save a mask process for forming the alignment mark, which is conducive to simplifying the manufacturing process of the three-dimensional memory and improving the production efficiency of the three-dimensional memory.

[0028] Additional aspects and advantages of the present invention will be set forth in part in the description which follows and, in part, will be obvious from the description which follows, or may be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 A flowchart of a method for manufacturing a three-dimensional memory provided by an embodiment of the present invention;

[0030] Figure 2 A schematic top view of a three-dimensional memory provided by an embodiment of the present invention;

[0031] Figures 3 to 9A process flow chart of a three-dimensional memory provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0032] The following describes exemplary embodiments of the present invention in more detail with reference to the accompanying drawings. Although exemplary embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the specific embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.

[0033] In the following description, numerous specific details are provided to provide a more thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present invention; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0034] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0035] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there can be no intervening elements or layers. It should be understood that while the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another. Thus, without departing from the teachings of the present invention, a first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. Furthermore, when a second element, component, region, layer, or part is discussed, it does not necessarily mean that the first element, component, region, layer, or part is present in the present invention.

[0036] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the drawings is flipped, then the elements or features described as "under the other elements" or "under it" or "under it" will be oriented as "on" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0037] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present invention. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0038] In some related technologies, memory cells in different layers of a multi-layer stacked 3D memory are vertically aligned. This alignment requires the introduction of alignment marks during the 3D memory fabrication process. Below, a brief explanation of the fabrication method for a two-layer (2-stack) 3D phase-change memory is provided as an example.

[0039] First, a lower phase-change memory cell is formed on a substrate, and the lower phase-change memory cell is surrounded by a dielectric layer. Next, an alignment groove is formed on the dielectric layer in the alignment area by an etching process. Then, an upper phase-change memory stack material layer is formed above the lower phase-change memory cell and the alignment groove. The upper phase-change memory stack material layer has a recess formed based on the alignment groove, and the recess can be used as a first alignment mark to form a second alignment mark in the alignment area. Finally, the upper phase-change memory stack material layer is etched using the second alignment mark as an alignment reference to form an upper memory cell aligned with the lower phase-change memory cell.

[0040] However, in the above-mentioned related technologies, a separate mask and etching process are required when forming the alignment groove, which results in a complicated process and low production efficiency.

[0041] Based on this, the following technical solutions of the embodiments of the present invention are proposed:

[0042] The present invention provides a method for manufacturing a three-dimensional memory. Figure 1 As shown in the figure, the method includes the following steps:

[0043] Step 101: Provide a semiconductor structure, wherein the semiconductor structure includes a storage area and an alignment area, wherein a first conductive wire loop, a lower phase change memory unit, and a second conductive wire loop are arranged in the storage area from bottom to top;

[0044] Step 102: Using an etching process, a first trench and a second trench are formed in the storage area and the alignment area, respectively; wherein the first trench is used to remove two ends of the first conductive wire loop and two ends of the second conductive wire loop to form a first conductive wire and a second conductive wire, respectively;

[0045] Step 103: forming a first dielectric layer, wherein the first dielectric layer covers the semiconductor structure and fills the first trench and the second trench; wherein the second trench has a gap not filled by the first dielectric layer;

[0046] Step 104: performing a planarization process on the first dielectric layer and the semiconductor structure to expose the second conductive line and the gap;

[0047] Step 105 : forming an upper phase-change memory stack material layer on the semiconductor structure, wherein a recess is formed in the upper phase-change memory stack material layer above the gap, and the recess constitutes a first alignment mark.

[0048] The embodiment of the present invention adopts an etching process to form a first groove in the storage area and a second groove in the alignment area at the same time, and utilizes the gap formed in the second groove to transfer the position information of the second groove to the upper phase change storage stack material layer, that is, the recess constituting the first alignment mark. Therefore, the manufacturing method provided by the embodiment of the present invention can save a mask process for forming the alignment mark, which is conducive to simplifying the manufacturing process of the three-dimensional memory and improving the production efficiency of the three-dimensional memory.

[0049] The manufacturing method provided in the embodiment of the present invention can be used to manufacture a three-dimensional phase change memory (3D PCM), but is not limited thereto and can also be used to manufacture other types of three-dimensional memories.

[0050] The following is a detailed description of the specific embodiments of the present invention in conjunction with the accompanying drawings. When describing the embodiments of the present invention in detail, for the sake of convenience, the schematic diagrams will not be magnified according to the general scale, and the schematic diagrams are only examples and should not limit the scope of protection of the present invention.

[0051] Figure 2 A schematic top view of a three-dimensional memory provided by an embodiment of the present invention; Figures 3 to 9 A process flow chart of a three-dimensional memory provided by an embodiment of the present invention, wherein: Figure 3 、 Figure 4a 、 Figure 5 、 Figure 6 、 Figure 7 、 Figure 8 and Figure 9 For each step along Figure 2 A schematic diagram of the cross-sectional structure taken along line AA', Figure 4b Schematic diagram of the second groove provided by the embodiment of the present invention. Figures 2 to 9 The manufacturing method of the three-dimensional memory provided by the embodiment of the present invention is further described in detail.

[0052] First, execute step 101, such as Figures 2 to 3 As shown, a semiconductor structure 200 is provided. The semiconductor structure 200 includes a storage area 20a and an alignment area 20b. A first conductive wire ring 25, a lower phase change memory unit 26 and a second conductive wire ring 27 are arranged from bottom to top in the storage area 20a.

[0053] like Figure 2 As shown, the alignment area 20b is arranged adjacent to the storage area 20a. In actual process, the semiconductor structure 200 is formed on a wafer, including multiple storage areas 20a and multiple alignment areas 20b. The alignment areas 20b are usually placed on the cutting path. The multiple storage areas 20a can be separated into individual devices in subsequent process steps. It should be noted that the shape of the alignment area 20b is not limited to the following: Figure 2 The shape shown, Figure 2 This is just an illustration, and those skilled in the art can set the alignment area 20b in any shape as needed. In a specific embodiment, the alignment area 20b can also be ring-shaped, and the alignment area 20b is set around the storage area 20a.

[0054] like Figure 3 As shown, in one embodiment, the semiconductor structure 200 further includes a substrate 20 and an insulating layer 24 formed on the substrate 20; wherein the first conductive wire loop 25, the lower phase-change memory unit 26, and the second conductive wire loop 27 are located within the insulating layer 24. The material of the insulating layer 24 includes, but is not limited to, insulating materials such as tetraethyl orthosilicate (TEOS), silicon dioxide, silicon nitride, or silicon oxynitride.

[0055] Here, the substrate may be a semiconductor substrate, and may include at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In a specific embodiment, the substrate is a silicon substrate, which may be doped or undoped.

[0056] like Figure 2 As shown, the first conductive wire loop 25 extends along a first direction, and there are multiple first conductive wire loops 25, which are evenly arranged along a second direction. Each first conductive wire loop 25 has two opposite ends 251 and 252. The second conductive wire loop 27 extends along a second direction, and there are multiple second conductive wire loops 27, which are evenly arranged along the first direction. Each second conductive wire loop 27 has two opposite ends 271 and 272. The first direction is different from the second direction. In one embodiment, the first direction is perpendicular to the second direction. The materials of the first conductive wire loop 25 and the second conductive wire loop 27 include, but are not limited to, tungsten, cobalt, copper, aluminum, polysilicon, doped silicon, silicide, or any combination thereof.

[0057] The lower phase change memory unit 26 is located at the intersection of the first conductive wire loop 25 and the second conductive wire loop 27. In one embodiment, the lower phase change memory unit 26 includes a first lower electrode layer 261, a lower gating layer 262, a second lower electrode layer 263, a lower phase change memory layer 264 and a third lower electrode layer 265 arranged from bottom to top. The materials of the first lower electrode layer 261, the second lower electrode layer 263 and the third lower electrode layer 265 can be the same. In a specific embodiment, the materials of the first lower electrode layer 261, the second lower electrode layer 263 and the third lower electrode layer 265 include carbon materials, such as amorphous carbon or carbon nanotubes. The material of the lower gating layer 262 can include any appropriate bidirectional threshold switch (OTS) material, such as Zn x Te y 、Ge x Te y 、Nb x O y 、Si x As y Te z The material of the lower phase-change memory layer 264 may be a chalcogenide-based alloy, such as a GST (Ge—Sb—Te) alloy, or any other suitable phase-change material.

[0058] In one embodiment, the lower phase-change memory cell 26 further includes a first adhesive layer (not shown) located on the lower surface of the first lower electrode layer 261, a first lower barrier layer (not shown) located between the second lower electrode layer 263 and the lower phase-change memory layer 264, and a second lower barrier layer (not shown) located between the lower phase-change memory layer 264 and the third lower electrode layer 265. The first adhesive layer (not shown) is made of a metal nitride, such as tungsten nitride or titanium nitride. The first and second lower barrier layers (not shown) are made of conductive materials such as tungsten, tantalum, and titanium nitride.

[0059] In one embodiment, the semiconductor structure 200 further includes a second adhesive layer (not shown) located on the lower surface of the second conductive wire loop 27. Here, the material of the second adhesive layer (not shown) can be the same as the material of the first adhesive layer (not shown). In some embodiments, the semiconductor structure 200 further includes a protective layer (not shown) located on the side surface of the lower phase-change memory unit 26. The material of the protective layer (not shown) includes silicon nitride.

[0060] In one embodiment, the semiconductor structure 200 further includes a first interlayer dielectric layer 21 and a second interlayer dielectric layer 22 located between the substrate 20 and the insulating layer 24, with the second interlayer dielectric layer 22 located on the first interlayer dielectric layer 21. In a specific embodiment, a plurality of interconnects 211 are disposed within the first interlayer dielectric layer 21, and the second interlayer dielectric layer 22 is used to protect the interconnects 211. In a more specific embodiment, at least one of the interconnects 211 is electrically connected to any long side of the first conductive wire loop 25 via a contact plug 23. Here, the material of the first interlayer dielectric layer 21 and the insulating layer 24 can be the same. The material of the second interlayer dielectric layer 22 can include silicon nitride. The material of the interconnects 211 can include a conductive material such as tungsten, cobalt, copper, aluminum, graphene, or carbon nanotubes. The material of the contact plug 23 can include, but is not limited to, tungsten, cobalt, copper, aluminum, polysilicon, doped silicon, silicide, or any combination thereof.

[0061] In one embodiment, the semiconductor structure 200 further includes a second dielectric layer 28, which covers the surface of the second conductive wire loop 27 and the surface of the insulating layer 24. It should be noted that the second dielectric layer 28 may include a single material layer or multiple material layers. When multiple material layers are included, the materials of the multiple material layers may be the same or different. In a specific embodiment, the material of the second dielectric layer 28 includes, but is not limited to, silicon nitride.

[0062] Next, execute step 102, as Figures 4a to 4bAs shown, an etching process is used to form a first trench T1 and a second trench T2 in the storage area 20a and the alignment area 20b, respectively; wherein the first trench T1 is used to remove the two ends 251, 252 of the first conductive wire loop 25 and the two ends 271, 272 of the second conductive wire loop 27 to form a first conductive line 253 and a second conductive line 273, respectively.

[0063] In one embodiment, forming the second trench T2 in the alignment region 20 b includes etching away a portion of the second dielectric layer 28 and a portion of the insulating layer 24 located in the alignment region 20 b to form the second trench T2. In a specific embodiment, while removing the portion of the insulating layer 24, the portion of the second dielectric layer 28 on the insulating layer 24 is also removed.

[0064] In one embodiment, the number of the second trenches T2 is multiple, and the multiple second trenches T2 can constitute multiple alignment marks commonly used in the technical field. In a specific embodiment, the multiple second trenches T2 constitute multiple alignment marks. Figure 4b The alignment mark shown. Subsequently, the first dielectric layer 29 will be filled in the second trench T2 to form a gap 31 (see Figures 5 and 6 ), in a more specific embodiment, the aspect ratio of the second trench T2 is greater than 2, wherein the aspect ratio of the second trench T2 should not be too small, as too small an aspect ratio will result in a size of the gap 31 formed in the second trench T2 being too small.

[0065] Reference again Figure 2 and Figure 4a In one embodiment, forming the first trench T1 in the storage area 20a includes etching and removing a portion of the second dielectric layer 28, a portion of the insulating layer 24, and the two ends 251, 252 of the first conductive wire loop 25 and the two ends 271, 272 of the second conductive wire loop 27 within the storage area 20a to form the first trench T1. The removal of the two ends 251, 252 of the first conductive wire loop 25 forms a plurality of first conductive wires 253 extending along a first direction, and the removal of the two ends 271, 272 of the second conductive wire loop 27 forms a plurality of second conductive wires 273 extending along a second direction. In one specific embodiment, the first conductive wires 253 are word lines or bit lines, and the second conductive wires 273 are bit lines or word lines. More specifically, if the first conductive line 253 is a word line, the second conductive line 273 is a bit line; if the first conductive line 253 is a bit line, the second conductive line 273 is a word line.

[0066] Next, execute step 103, as Figure 5 As shown, a first dielectric layer 29 is formed, which covers the semiconductor structure 200 and fills the first trench T1 and the second trench T2 ; wherein the second trench T2 has a gap 31 which is not filled by the first dielectric layer 29 .

[0067] Specifically, chemical vapor deposition is used to form the first dielectric layer 29 on the semiconductor structure 200. Since the second trench T2 has a large depth-to-width ratio, the first dielectric layer 29 cannot completely fill the second trench T2, thereby forming the gap 31. The material of the first dielectric layer 29 can be an oxide, such as silicon oxide.

[0068] Next, execute step 104, as Figure 6 As shown, a planarization process is performed on the first dielectric layer 29 and the semiconductor structure 200 to expose the second conductive line 273 and the gap 31 .

[0069] Specifically, a planarization process is performed on the first dielectric layer 29 and the semiconductor structure 200, including performing a grinding process on the first dielectric layer 29, the second dielectric layer 28, and the insulating layer 24 to expose the second conductive line 273 and the gap 31 in the second trench T2. The planarization process includes a chemical mechanical polishing process, an etch-back process, or a combination thereof.

[0070] Finally, execute step 105, as Figure 7 As shown, an upper phase-change memory stack material layer 32 is formed on the semiconductor structure 200 . A recess 35 is formed in the upper phase-change memory stack material layer 32 above the gap 31 . The recess 35 constitutes a first alignment mark.

[0071] In this way, the position information of the second trench T2 is transferred to the upper phase change memory stack material layer 32 through the recess 35. In one embodiment, the upper phase change memory stack material layer 32 includes a first upper electrode material layer 321, an upper gating material layer 322, a second upper electrode material layer 323, an upper phase change memory material layer 324, a third upper electrode material layer 325 and a third dielectric layer 326 arranged from bottom to top, and the third dielectric layer 326 is used to protect the material layer located thereunder. The materials of the first upper electrode material layer 321, the second upper electrode material layer 323 and the third upper electrode material layer 325 may be the same. In a specific embodiment, the materials of the first upper electrode material layer 321, the second upper electrode material layer 323 and the third upper electrode material layer 325 include carbon materials, such as amorphous carbon or carbon nanotubes. The material of the upper gating material layer 322 may include any appropriate bidirectional threshold switch (OTS) material, such as Znx Te y 、Ge x Te y 、Nb x O y 、Si x As y Te z The material of the upper phase change memory material layer 324 can be a chalcogenide-based alloy, such as a GST (Ge-Sb-Te) alloy, or any other suitable phase change material. The material of the third dielectric layer 326 can be silicon nitride.

[0072] In one embodiment, the upper phase-change memory stack material layer 32 further includes a third adhesive layer (not shown) located on the lower surface of the first upper electrode material layer 321, a first upper barrier material layer (not shown) located between the second upper electrode material layer 323 and the upper phase-change memory material layer 324, and a second upper barrier material layer (not shown) located between the upper phase-change memory material layer 324 and the third upper electrode material layer 325. The material of the third adhesive layer can be the same as that of the first adhesive layer. The materials of the first upper barrier material layer (not shown) and the second upper barrier material layer (not shown) can be the same as that of the first lower barrier layer.

[0073] The above-mentioned layers are formed using one or more thin film deposition processes; specifically, the formation processes of each layer structure include but are not limited to chemical vapor deposition (CVD) process, plasma enhanced chemical vapor deposition (PECVD) process, atomic layer deposition (ALD) process or a combination thereof.

[0074] In one embodiment, after forming the upper phase change memory stack material layer 32, the method further includes:

[0075] Using the first alignment mark as an alignment base point, the upper phase change memory stack material layer 32 and the insulating layer 24 are etched to form a third trench T3 on the alignment area 20b. The third trench T3 constitutes a second alignment mark. Figure 8 As shown; the second alignment mark can be any alignment mark commonly used in the art;

[0076] Using the second alignment mark as an alignment base point, the upper phase change memory stack material layer 32 located on the storage area 20a is etched to form a plurality of upper memory unit structures 36 extending along the second direction. Figure 9 shown.

[0077] In one embodiment, after forming the upper memory cell structure, the method further includes:

[0078] forming a third conductive material layer on the upper memory cell structure;

[0079] The third conductive material layer and the upper memory cell structure are etched to form a third conductive line and an upper phase-change memory cell, wherein the third conductive line extends along the first direction, and the upper phase-change memory cell corresponds to the lower phase-change memory cell one by one.

[0080] It can be seen that the embodiment of the present invention adopts an etching process to form the first trench T1 in the storage area 20a and the second trench T2 in the alignment area 20b at the same time, and utilizes the gap 31 formed in the second trench T2 to transfer the position information of the second trench T2 to the upper phase change storage stack material layer 32, that is, the recess 35 constituting the first alignment mark. Therefore, the manufacturing method provided by the embodiment of the present invention can save a mask process for forming the alignment mark, which is conducive to simplifying the manufacturing process of the three-dimensional memory and improving the production efficiency of the three-dimensional memory.

[0081] It should be noted that those skilled in the art can make possible changes to the sequence of the above steps without departing from the scope of protection of the present invention.

[0082] The present invention also provides a three-dimensional memory, such as Figure 7 As shown, it includes: a semiconductor structure 200, the semiconductor structure 200 includes a storage area 20a and an alignment area 20b, and the storage area 20a is provided with a first conductive line 253, a lower phase-change memory unit 26 and a second conductive line 273 from bottom to top; a first trench T1 and a second trench T2, respectively located in the storage area 20a and the alignment area 20b; a first dielectric layer 29, filling the first trench T1 and the second trench T2; wherein the second trench T2 has a gap 31 not filled by the first dielectric layer 29; an upper phase-change memory stack material layer 32, located on the semiconductor structure 200; wherein the upper phase-change memory stack material layer 32 fills the gap 31 and forms a recess 35 above the gap 31, and the recess 35 constitutes a first alignment mark.

[0083] In one embodiment, the alignment area 20b is arranged adjacent to the storage area 20a. In actual process, the semiconductor structure 200 is formed on a wafer, including multiple storage areas 20a and multiple alignment areas 20b. The alignment areas 20b are usually placed on the cutting path. The multiple storage areas 20a can be separated into individual devices in subsequent process steps. It should be noted that the shape of the alignment area 20b is not limited to the following: Figure 2 The shape shown, Figure 2This is just an illustration, and those skilled in the art can set the alignment area 20b in any shape as needed. In a specific embodiment, the alignment area 20b can also be ring-shaped, and the alignment area 20b is set around the storage area 20a.

[0084] In one embodiment, the semiconductor structure 200 further includes a substrate 20 and an insulating layer 24 formed on the substrate 20; wherein the first conductive line 253, the lower phase-change memory unit 26, and the second conductive line 273 are located within the insulating layer 24. The material of the insulating layer 24 includes, but is not limited to, insulating materials such as tetraethyl orthosilicate (TEOS), silicon dioxide, silicon nitride, or silicon oxynitride.

[0085] Here, the substrate may be a semiconductor substrate, and may include at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In a specific embodiment, the substrate is a silicon substrate, which may be doped or undoped.

[0086] In one embodiment, the first conductive line 253 extends along a first direction, there are multiple first conductive lines 253, and the multiple first conductive lines 253 are evenly arranged along a second direction; the second conductive line 273 extends along a second direction, there are multiple second conductive lines 273, and the multiple second conductive lines 273 are evenly arranged along the first direction. The first direction is different from the second direction; for example, the first direction may be perpendicular to the second direction. In a specific embodiment, the first conductive line 253 is a word line or a bit line, and the second conductive line 273 is a bit line or a word line. More specifically, if the first conductive line 253 is a word line, the second conductive line 273 is a bit line; if the first conductive line 253 is a bit line, the second conductive line 273 is a word line. The materials of the first conductive line 253 and the second conductive line 273 include, but are not limited to, tungsten, cobalt, copper, aluminum, polysilicon, doped silicon, silicide, or any combination thereof.

[0087] The lower phase change memory unit 26 is located at the intersection of the first conductive line 253 and the second conductive line 273. In one embodiment, the lower phase change memory unit 26 includes a first lower electrode layer 261, a lower gating layer 262, a second lower electrode layer 263, a lower phase change memory layer 264 and a third lower electrode layer 265 arranged from bottom to top. The materials of the first lower electrode layer 261, the second lower electrode layer 263 and the third lower electrode layer 265 can be the same. In a specific embodiment, the materials of the first lower electrode layer 261, the second lower electrode layer 263 and the third lower electrode layer 265 include carbon materials, such as amorphous carbon or carbon nanotubes. The material of the lower gating layer 262 can include any appropriate bidirectional threshold switch (OTS) material, such as Zn x Te y 、Ge x Te y 、Nb x O y 、Si x As y Te z The material of the lower phase-change memory layer 264 may be a chalcogenide-based alloy, such as a GST (Ge—Sb—Te) alloy, or any other suitable phase-change material.

[0088] In one embodiment, the lower phase-change memory cell 26 further includes a first adhesive layer (not shown) located on the lower surface of the first lower electrode layer 261, a first lower barrier layer (not shown) located between the second lower electrode layer 263 and the lower phase-change memory layer 264, and a second lower barrier layer (not shown) located between the lower phase-change memory layer 264 and the third lower electrode layer 265. The first adhesive layer (not shown) is made of a metal nitride, such as tungsten nitride or titanium nitride. The first and second lower barrier layers (not shown) are made of conductive materials such as tungsten, tantalum, and titanium nitride.

[0089] In one embodiment, the semiconductor structure 200 further includes a second adhesive layer (not shown) located on the lower surface of the second conductive line 273. Here, the material of the second adhesive layer (not shown) can be the same as the material of the first adhesive layer (not shown). In some embodiments, the semiconductor structure 200 further includes a protective layer (not shown) located on the side surface of the lower phase-change memory unit 26. The material of the protective layer (not shown) includes silicon nitride.

[0090] In one embodiment, the semiconductor structure 200 further includes a first interlayer dielectric layer 21 and a second interlayer dielectric layer 22 located between the substrate 20 and the insulating layer 24, with the second interlayer dielectric layer 22 located on the first interlayer dielectric layer 21. In a specific embodiment, a plurality of interconnects 211 are disposed within the first interlayer dielectric layer 21, and the second interlayer dielectric layer 22 is used to protect the interconnects 211. In a more specific embodiment, at least one of the interconnects 211 is electrically connected to any of the first conductive lines 253 via a contact plug 23. Here, the material of the first interlayer dielectric layer 21 and the insulating layer 24 can be the same. The material of the second interlayer dielectric layer 22 can include silicon nitride. The material of the interconnects 211 can include a conductive material such as tungsten, cobalt, copper, aluminum, graphene, or carbon nanotubes. The material of the contact plug 23 can include, but is not limited to, tungsten, cobalt, copper, aluminum, polysilicon, doped silicon, silicide, or any combination thereof.

[0091] In one embodiment, the first trench T1 is used to form the first conductive line 253 and the second conductive line 273, and the second trench T2 and the first trench T1 are formed by a single etching process. In a specific embodiment, the number of the second trench T2 is multiple, and the multiple second trenches T2 can constitute multiple alignment marks commonly used in the art. For example, the multiple second trenches T2 constitute multiple alignment marks such as Figure 4b The alignment mark shown. In a specific embodiment, the aspect ratio of the second trench T2 is greater than 2. More specifically, the first dielectric layer 29 is formed on the semiconductor structure 200 by chemical vapor deposition. Due to the large aspect ratio of the second trench T2, the first dielectric layer 29 cannot completely fill the second trench T2, thereby forming the gap 31. The material of the first dielectric layer 29 can be an oxide, such as silicon oxide.

[0092] The upper phase change memory stack material layer 32 covers the second conductive line 273, the insulating layer 24, and the first dielectric layer 29. In one embodiment, the upper phase change memory stack material layer 32 includes a first upper electrode material layer 321, an upper gating material layer 322, a second upper electrode material layer 323, an upper phase change memory material layer 324, a third upper electrode material layer 325, and a third dielectric layer 326 arranged from bottom to top, and the third dielectric layer 326 is used to protect the material layer located thereunder. The materials of the first upper electrode material layer 321, the second upper electrode material layer 323, and the third upper electrode material layer 325 may be the same. In a specific embodiment, the materials of the first upper electrode material layer 321, the second upper electrode material layer 323, and the third upper electrode material layer 325 include carbon materials, such as amorphous carbon or carbon nanotubes. The material of the upper gating material layer 322 may include any appropriate bidirectional threshold switch (OTS) material, such as Zn x Te y 、Ge x Te y 、Nb x O y 、Si x As y Te z The material of the upper phase change memory material layer 324 can be a chalcogenide-based alloy, such as a GST (Ge-Sb-Te) alloy, or any other suitable phase change material. The material of the third dielectric layer 326 can be silicon nitride.

[0093] In one embodiment, the upper phase-change memory stack material layer 32 further includes a third adhesive layer (not shown) located on the lower surface of the first upper electrode material layer 321, a first upper barrier material layer (not shown) located between the second upper electrode material layer 323 and the upper phase-change memory material layer 324, and a second upper barrier material layer (not shown) located between the upper phase-change memory material layer 324 and the third upper electrode material layer 325. The material of the third adhesive layer can be the same as that of the first adhesive layer. The materials of the first upper barrier material layer (not shown) and the second upper barrier material layer (not shown) can be the same as that of the first lower barrier layer.

[0094] In the embodiment of the present invention, a first trench T1 is formed in the storage area 20a, and a second trench T2 is formed in the alignment area 20b at the same time by adopting an etching process, and the position information of the second trench T2 is transferred to the upper phase-change storage stack material layer 32, i.e., the recess 35 constituting the first alignment mark, by utilizing the gap 31 formed in the second trench T2. Therefore, in the process of forming the three-dimensional memory, the embodiment of the present invention can save a mask process for forming an alignment mark, which is conducive to simplifying the manufacturing process of the three-dimensional memory and improving the production efficiency of the three-dimensional memory.

[0095] In one embodiment, the first alignment mark can be used as an alignment base point to etch the upper phase change memory stack material layer 32 and the insulating layer 24 to form a third trench T3 on the alignment area 20b. Figure 8 The structure shown in FIG. 1 is shown in FIG. 2 ; the third trench T3 constitutes a second alignment mark, which can be any alignment mark commonly used in the art; then, using the second alignment mark as an alignment base point, the upper phase change memory stack material layer 32 located on the storage area 20a is etched to form a plurality of upper memory cell structures 36 extending along the second direction, and finally forming the structure shown in FIG. Figure 9 The structure shown.

[0096] The above description is only a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A method for manufacturing a three-dimensional memory, characterized in that: include: A semiconductor structure is provided, comprising a storage area and an alignment area, wherein a first conductive wire loop, a lower phase-change memory unit, and a second conductive wire loop are arranged from bottom to top in the storage area; Using an etching process, a first trench and a second trench are formed in the storage area and the alignment area, respectively; wherein the first trench is used to remove two ends of the first conductive wire loop and two ends of the second conductive wire loop to form a first conductive wire and a second conductive wire, respectively; forming a first dielectric layer, wherein the first dielectric layer covers the semiconductor structure and fills the first trench and the second trench; wherein the second trench has a gap that is not filled by the first dielectric layer; performing a planarization process on the first dielectric layer and the semiconductor structure to expose the second conductive line and the gap; An upper phase-change memory stack material layer is formed on the semiconductor structure. A recess is formed in the upper phase-change memory stack material layer above the gap, and the recess constitutes a first alignment mark.

2. The method according to claim 1, characterized in that The aspect ratio of the second trench is greater than 2.

3. The method according to claim 1, characterized in that The first dielectric layer is formed on the semiconductor structure by chemical vapor deposition.

4. The method according to claim 1, wherein The semiconductor structure further includes a substrate and an insulating layer formed on the substrate; wherein the first conductive wire loop, the lower phase-change memory unit and the second conductive wire loop are located in the insulating layer.

5. The method according to claim 4, characterized in that The semiconductor structure further includes a second dielectric layer, and the second dielectric layer covers a surface of the second conductive wire loop and a surface of the insulating layer.

6. The method according to claim 5, characterized in that The second trench is formed in the alignment area, comprising: etching and removing a portion of the second dielectric layer and a portion of the insulating layer located in the alignment area to form the second trench.

7. The method according to claim 5, characterized in that Forming a first trench in the storage area includes: etching and removing a portion of the second dielectric layer, a portion of the insulating layer, and the two ends of the first conductive wire loop and the two ends of the second conductive wire loop surrounded by a portion of the insulating layer located in the storage area to form the first trench; wherein, after the two ends of the first conductive wire loop are removed, a plurality of first conductive wires extending along the first direction are formed, and after the two ends of the second conductive wire loop are removed, a plurality of second conductive wires extending along the second direction are formed.

8. The method according to claim 5, characterized in that A planarization process is performed on the first dielectric layer and the semiconductor structure, including: performing a grinding process on the first dielectric layer, the second dielectric layer, and the insulating layer to expose the second conductive line and the gap in the second trench.

9. The method according to claim 4, characterized in that After forming the upper phase-change memory stack material layer, the method further includes: Using the first alignment mark as an alignment base point, etching the upper phase change memory stack material layer and the insulating layer to form a third trench on the alignment area, wherein the third trench constitutes a second alignment mark; The upper phase-change memory stack material layer located on the storage area is etched using the second alignment mark as an alignment base point to form a plurality of upper memory cell structures extending along the second direction.

10. A three-dimensional memory, characterized in that: include: A semiconductor structure comprising a storage area and an alignment area, wherein a first conductive line, a lower phase-change memory unit, and a second conductive line are arranged in the storage area from bottom to top; A first groove and a second groove are respectively located in the storage area and the alignment area; a first dielectric layer filling the first trench and the second trench; wherein the second trench has a gap not filled by the first dielectric layer; the gap is exposed after a planarization process is performed on the first dielectric layer; An upper phase-change memory stack material layer is located on the semiconductor structure; wherein the upper phase-change memory stack material layer fills the gap and forms a recess above the gap, and the recess constitutes a first alignment mark.

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