Semiconductor structure and its formation method

Abstract

A semiconductor structure and a method for forming the same are disclosed. The method includes: providing a substrate; forming a plurality of mutually discrete gate structures on the substrate; forming a plurality of source / drain structures within the substrate, the source / drain structures being located on both sides of the gate structures; forming a first sidewall on the sidewall of the gate structure, wherein the top surface of the first sidewall is lower than or flush with the top surface of the gate structure; after forming the first sidewall, forming a first conductive structure on the surface of the source / drain structure, wherein the sidewall surface of the first conductive structure contacts the first sidewall; forming a barrier layer on the top surface of the first sidewall using a selective film deposition process; and after forming the barrier layer, forming a first dielectric layer on the top surface of the gate structure and the top surface of the first conductive structure. This allows for the implementation of a self-aligned etching process while improving the stability of the electrical properties of the semiconductor structure, thereby enhancing the performance and reliability of the semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] With the rapid development of integrated circuit manufacturing technology, the size of semiconductor devices in integrated circuits is constantly shrinking, which effectively improves the operating speed of the entire integrated circuit. As the size requirements of components become smaller and smaller, the size of the conductive structures formed to connect with semiconductor devices also becomes smaller and smaller.

[0003] However, the performance and reliability of existing semiconductor structures still need to be improved. Summary of the Invention

[0004] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance and reliability of the formed semiconductor structure while realizing a self-aligned etching process.

[0005] To solve the above-mentioned technical problems, the present invention provides a semiconductor structure, comprising: a substrate; a plurality of gate structures located on the substrate and discretely arranged therefrom; a plurality of source / drain structures located within the substrate on both sides of the gate structures; a first conductive structure located on the surface of the source / drain structures; a first sidewall located on the sidewall of the gate structures, wherein the top surface of the first sidewall is lower than or flush with the top surface of the gate structures, and the sidewall surface of the first conductive structure contacts the first sidewall; a barrier layer located on the top surface of the first sidewall; and a first dielectric layer located on the top surface of the gate structures and the top surface of the first conductive structures, wherein the material of the first dielectric layer is different from the material of the barrier layer.

[0006] Optionally, the material of the first sidewall includes silicon oxide, and the material of the barrier layer includes oxide.

[0007] Optionally, the oxide includes aluminum oxide, zinc oxide, ruthenium oxide, or titanium oxide.

[0008] Optionally, the material of the first sidewall includes silicon nitride, and the material of the barrier layer includes titanium nitride, copper, aluminum, nickel, platinum, or ruthenium.

[0009] Optionally, the material of the first dielectric layer includes silicon carbide, silicon carbide, silicon carbonitride, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbonitride, or a metal compound.

[0010] Optionally, the thickness of the barrier layer in the direction perpendicular to the substrate surface ranges from 20 angstroms to 150 angstroms.

[0011] Optionally, it further includes: a gate sidewall located on a portion of the sidewall of the gate structure, wherein the first sidewall is located on the top surface of the gate sidewall.

[0012] Optionally, it further includes: an etch stop layer located between the gate sidewall and the sidewall of the first conductive structure, wherein the first sidewall is also located on the top surface of the etch stop layer.

[0013] Optionally, it may also include: a second conductive structure located on the top surface of the gate structure, wherein the second conductive structure is also located within the first dielectric layer.

[0014] Optionally, it further includes a third dielectric layer located on the top surface of the barrier layer and the first dielectric layer, wherein the second conductive structure is also located within the third dielectric layer.

[0015] Optionally, it may also include a third conductive structure located on the top surface of the first conductive structure, wherein the third conductive structure is also located within the first dielectric layer.

[0016] Optionally, it may also include a third dielectric layer located on the top surface of the barrier layer and the first dielectric layer, wherein the third conductive structure is also located within the third dielectric layer.

[0017] The present invention also provides another semiconductor structure, comprising: a substrate; a plurality of gate structures located on the substrate and discretely disposed therefrom; a plurality of source / drain structures located within the substrate on both sides of the gate structures; a first conductive structure located on the surface of the source / drain structures; a first sidewall located on the sidewall of the gate structures, wherein the top surface of the first sidewall is lower than or flush with the top surface of the gate structures, and the sidewall surface of the first conductive structure contacts the first sidewall; a first dielectric layer located on the top surface of the gate structures and the top surface of the first conductive structures; and a second dielectric layer located on the top surface of the first sidewall, wherein the material of the second dielectric layer is different from the material of the first dielectric layer.

[0018] Optionally, it further includes: a gate sidewall located on a portion of the sidewall of the gate structure, wherein the first sidewall is located on the top surface of the gate sidewall.

[0019] Optionally, it further includes: an etch stop layer located between the gate sidewall and the sidewall of the first conductive structure, wherein the first sidewall is also located on the top surface of the etch stop layer.

[0020] Optionally, it may also include: a second conductive structure located on the top surface of the gate structure, wherein the second conductive structure is also located within the first dielectric layer.

[0021] Optionally, it further includes a third dielectric layer located on the top surface of the first dielectric layer and the second dielectric layer, wherein the second conductive structure is also located within the third dielectric layer.

[0022] Optionally, it may also include a third conductive structure located on the top surface of the first conductive structure, wherein the third conductive structure is also located within the first dielectric layer.

[0023] Optionally, it may also include a third dielectric layer located on the top surface of the first dielectric layer and the second dielectric layer, wherein the third conductive structure is also located within the third dielectric layer.

[0024] Accordingly, the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a plurality of mutually discrete gate structures on the substrate; forming a plurality of source-drain structures within the substrate, the source-drain structures being located on both sides of the gate structures; forming a first sidewall on the sidewall of the gate structure, wherein the top surface of the first sidewall is lower than or flush with the top surface of the gate structure; after forming the first sidewall, forming a first conductive structure on the surface of the source-drain structure, wherein the sidewall surface of the first conductive structure is in contact with the first sidewall; forming a barrier layer on the top surface of the first sidewall using a selective film deposition process; and after forming the barrier layer, forming a first dielectric layer on the top surface of the gate structure and the top surface of the first conductive structure.

[0025] Optionally, the selective film formation process includes a selective atomic layer deposition process, and the parameters of the selective atomic layer deposition process further include: a temperature of 100 degrees Celsius to 300 degrees Celsius; a response time of 0.05 seconds to 0.5 seconds for the reactive gas pulse; and a purge gas time of 20 seconds to 60 seconds.

[0026] Optionally, the material of the first sidewall includes silicon oxide, and the material of the barrier layer includes oxide.

[0027] Optionally, it further includes: after forming the first dielectric layer, etching the first dielectric layer until the top surface of the gate structure is exposed to form a second opening in the first dielectric layer; forming a second conductive structure in the second opening; after forming the first dielectric layer, etching the first dielectric layer until the top surface of the first conductive structure is exposed to form a third opening in the first dielectric layer; and forming a third conductive structure in the third opening.

[0028] Optionally, it may also include forming a third dielectric layer on the top surface of the barrier layer and the first dielectric layer before etching the first dielectric layer.

[0029] Optionally, the material of the first sidewall includes silicon nitride, and the material of the barrier layer includes titanium nitride, copper, aluminum, nickel, platinum, or ruthenium.

[0030] Optionally, it further includes: after forming the first dielectric layer, etching back the barrier layer until the barrier layer is removed; and after removing the barrier layer, forming a second dielectric layer on the top surface of the first sidewall.

[0031] Optionally, it further includes: after forming the second dielectric layer, etching the first dielectric layer until the top surface of the gate structure is exposed to form a second opening in the first dielectric layer; forming a second conductive structure in the second opening; after forming the second dielectric layer, etching the first dielectric layer until the top surface of the first conductive structure is exposed to form a third opening in the first dielectric layer; and forming a third conductive structure in the third opening.

[0032] Optionally, it may also include forming a third dielectric layer on the top surface of the first dielectric layer and the second dielectric layer before etching the first dielectric layer.

[0033] Optionally, the method further includes: forming an initial gate sidewall before forming the source / drain structure, the initial gate sidewall covering the sidewall of the gate structure; forming a fourth dielectric layer on the substrate surface and the surfaces of the plurality of source / drain structures; after forming the fourth dielectric layer, etching back the initial gate sidewall to form a gate sidewall, and forming a sidewall opening on the gate sidewall, the bottom of the sidewall opening exposing the top surface of the gate sidewall, and the sidewall surfaces on both sides of the sidewall opening exposing the sidewall surfaces of the fourth dielectric layer and the sidewall surfaces of the gate structure, respectively; forming a first sidewall within the sidewall opening, the fourth dielectric layer also being located on the sidewalls of the gate sidewall and the first sidewall.

[0034] Optionally, it further includes: during the formation of the fourth dielectric layer, forming an initial etch stop layer on the surface of the source / drain structure and on the sidewall of the initial gate sidewall; etching the initial etch stop layer while etching the initial gate sidewall to form an etch stop layer, wherein the first sidewall is also located on the top surface of the etch stop layer; and removing the etch stop layer on the source / drain structure after the first sidewall is formed and before the first conductive structure is formed.

[0035] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0036] In the semiconductor structure formation method provided by the present invention, a barrier layer is formed on the top surface of a first sidewall located between adjacent first conductive structures and gate structures using a selective film deposition process. After forming the barrier layer, a first dielectric layer is formed on the top surface of the gate structure and the top surface of the first conductive structure. Therefore, the barrier layer is only located on the top surface of the first sidewall, and the barrier layer can space the first dielectric layer on the top surface of the gate structure and the first dielectric layer on the top surface of the first conductive structure. Furthermore, since the barrier layer and the first dielectric layer are formed separately, barrier layers and first dielectric layers made of different materials can be formed, i.e., the material of the first dielectric layer is different from the material of the barrier layer. On the one hand, when the material of the barrier layer is a dielectric material, different etching rates can be applied to the first dielectric layer and the barrier layer during subsequent etching of the first dielectric layer, achieving a self-aligned etching process. On the other hand, when the barrier layer is made of a non-dielectric material, different etching rates can be applied to the barrier layer and the first dielectric layer during etching, allowing the first dielectric layer to be retained while the barrier layer is removed. Therefore, it is possible to subsequently replace the barrier layer with a dielectric material different from the first dielectric layer. Furthermore, by using the dielectric material to separate the first dielectric layer located on the top surface of the gate structure and the first dielectric layer located on the top surface of the first conductive structure, different etching rates can be applied to the first dielectric layer and the dielectric material during subsequent etching of the first dielectric layer, achieving a self-aligned etching process. Based on this, since there is no etching process for the first conductive structure after its formation in the semiconductor structure formation method, the etching process has a smaller impact on the first conductive structure. Therefore, the electrical characteristics of the first conductive structures in different regions of the semiconductor structure are highly consistent, improving the stability of the semiconductor structure's electrical characteristics and enhancing its performance and reliability. In summary, this semiconductor structure can achieve a self-aligned etching process while simultaneously improving the stability of its electrical characteristics and enhancing its performance and reliability. Attached Figure Description

[0037] Figures 1 to 3 This is a schematic diagram of the steps involved in forming a semiconductor structure.

[0038] Figures 4 to 14 This is a cross-sectional structural schematic diagram of each step in a method for forming a semiconductor structure according to an embodiment of the present invention;

[0039] Figures 15 to 20 This is a cross-sectional structural schematic diagram of each step in the method for forming a semiconductor structure according to another embodiment of the present invention. Detailed Implementation

[0040] As described in the background section, the performance and reliability of existing semiconductor structures still need to be improved.

[0041] The following detailed explanation, in conjunction with the accompanying drawings, explains why the performance and reliability of semiconductor structures still need improvement.

[0042] Figures 1 to 3 This is a schematic diagram of the steps involved in forming a semiconductor structure.

[0043] Please refer to Figure 1 A substrate 100 is provided, the substrate 100 including a substrate (not shown) and a plurality of fin structures (not shown) disposed on the substrate and disposed therebetween; a first dielectric layer (not shown) is formed on the surface of the substrate 100, the first dielectric layer covering a portion of the sidewalls of the fin structures.

[0044] Please continue to refer to this. Figure 1 A second dielectric layer 110 is formed on the surface of the first dielectric layer. The second dielectric layer 110 has a plurality of gate openings (not shown) that span the fin structure. The gate openings expose the surface and part of the sidewall of the fin structure. A gate structure 120, a gate protection structure 130 located on the top surface of the gate structure 120, and sidewalls 140 located on the sidewalls of the gate structure 120 and the sidewalls of the gate protection structure 130 are formed in the gate openings.

[0045] Please refer to Figure 2 A first conductive opening mask layer (not shown) is formed on the top surface of the gate protection structure 130, the top surface of the sidewall 140, and the surface of the second dielectric layer 110. The first conductive opening mask layer has a plurality of first conductive mask openings (not shown). Using the first conductive opening mask layer as a mask, the second dielectric layer 110 is etched until the surface of the substrate 100 is exposed, forming a first conductive opening (not shown). An initial conductive structure 150 is formed in the first conductive opening.

[0046] The initial conductive structure 150 is made of cobalt, and thus, due to the material properties of cobalt, the parasitic resistance of the subsequently formed conductive structure is relatively small.

[0047] Please refer to Figure 3 The initial conductive structure 150 is etched back to form a first conductive structure 151, and a conductive protective structure opening (not shown) is formed in the second dielectric layer 110 on the first conductive structure 151; a conductive protective structure 160 is formed in the conductive protective structure opening.

[0048] Next, a second conductive opening mask layer (not shown) is formed on the surface of the conductive protection structure 160 and the surface of the second dielectric layer 110. The second conductive opening mask layer has a plurality of second conductive mask openings (not shown). The second conductive mask openings expose a portion of the conductive protection structure 160 and the top surface of the sidewall 140. Using the second conductive opening mask layer as a mask, a portion of the conductive protection structure 160 is etched until the top surface of the first conductive structure 151 is exposed, forming a second conductive opening (not shown) in the conductive protection structure 160 and the second dielectric layer 110. A second conductive structure (not shown) is formed in the second conductive opening, and the second conductive structure is electrically connected to the first conductive structure 151.

[0049] In the above embodiments, by etching back the initial conductive structure 150 to form a conductive protective structure opening, a conductive protective structure 160 with a critical dimension (CD) smaller than the limit of existing photolithography processes can be formed. Furthermore, since the material of the formed conductive protective structure 160 is different from the material of the sidewalls 140, by using different etching rates for the materials of the conductive protective structure 160 and the sidewalls 140, a self-aligned etching process can be achieved during the formation of the second conductive opening.

[0050] Specifically, in the direction perpendicular to the extension direction of the gate structure 120, the width of the second conductive mask opening is greater than the width of the second conductive opening (the second conductive mask opening exposes not only the top surface of the conductive protection structure 160 but also part of the top surface of the sidewall 140), thereby increasing the process window for the etching process forming the second conductive opening and reducing the difficulty of the photolithography process. Simultaneously, through the self-aligned etching process, a second conductive opening with a critical dimension smaller than the width of the second conductive mask opening can be formed.

[0051] However, while achieving the self-aligned etching process, due to the poor chemical stability of cobalt, the chemical reaction during the re-etching of the initial conductive structure 150 is highly reactive. This results in poor uniformity in the thickness and other properties of the etching byproducts formed on the surface of the initial conductive structure 150. Consequently, controlling the re-etching process of the initial conductive structure 150 is difficult, leading to poor consistency between the conductive structures 151 in different regions of the formed semiconductor structure. For example, the surface roughness of the conductive structures 151 in different regions is inconsistent, and the height H of the conductive structures 151 in different regions (e.g., ...) is also inconsistent. Figure 3 Inconsistencies, such as those shown, result in poor electrical characteristic consistency among the conductive structures 151 in different regions of the semiconductor structure, leading to unstable electrical characteristics and consequently poor performance and reliability of the semiconductor structure.

[0052] To address the aforementioned technical problems, embodiments of the present invention provide a semiconductor structure and a method for forming the same. By forming a barrier layer only on the top surface of the first sidewall, the first dielectric layer located on the top surface of the gate structure and the first dielectric layer located on the top surface of the first conductive structure can be spaced apart. This allows for the implementation of a self-aligned etching process while simultaneously improving the stability of the electrical properties of the semiconductor structure, thereby enhancing its performance and reliability.

[0053] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0054] Figures 4 to 14 This is a cross-sectional structural schematic diagram of each step in a method for forming a semiconductor structure according to an embodiment of the present invention.

[0055] Please refer to Figure 4 Provides a base.

[0056] In this embodiment, the substrate includes a substrate 200 and a plurality of fin structures 201 disposed on the substrate 200.

[0057] The substrate 200 is made of semiconductor materials.

[0058] In this embodiment, the substrate 200 is made of silicon.

[0059] In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI), etc. The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP, etc.

[0060] In other embodiments, the fin structure includes: a plurality of fin sacrificial layers arranged in a direction perpendicular to the substrate surface, and nanosheets located between adjacent fin sacrificial layers.

[0061] Next, a plurality of discrete gate structures are formed on the substrate, and a plurality of source / drain structures are formed within the substrate, the source / drain structures being located on both sides of the gate structures. For the specific process of forming the gate structures and source / drain structures, please refer to [reference needed]. Figures 5 to 6 .

[0062] Please refer to Figure 5 A plurality of mutually independent pseudo-gate structures 209 are formed on the surface of the substrate; an initial gate sidewall 210 is formed on the sidewall surface of the pseudo-gate structure 209.

[0063] In this embodiment, the material of the pseudo-gate structure 209 includes polycrystalline silicon.

[0064] In the subsequent formation of the gate structure, the pseudo-gate structure 209 in this embodiment is used to define the pattern of the gate structure.

[0065] In other embodiments, the pseudo-gate structure is directly used as the gate structure.

[0066] In this embodiment, the method for forming the pseudo-gate structure 209 includes: forming a pseudo-gate material film (not shown) covering the surface of the fin structure 201 on the substrate; patterning the pseudo-gate material film until the substrate surface is exposed, so as to form a plurality of mutually discrete pseudo-gate structures 209 on the substrate, the pseudo-gate structures 209 spanning the fin structure 201, and the top surface of the pseudo-gate structure 209 being higher than the top surface of the fin structure 201.

[0067] The formation process of the pseudogate material film includes epitaxial growth or deposition processes, such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition.

[0068] In this embodiment, on the one hand, the initial gate sidewall 210 is used to define the formation location of the source / drain structure during the subsequent formation of the source / drain structure. On the other hand, the initial gate sidewall 210 provides material for the subsequent formation of the gate sidewall.

[0069] In this embodiment, the method for forming the initial gate sidewall 210 includes: depositing a sidewall material film (not shown) on the substrate surface and the surface of the dummy gate structure 209; using an anisotropic etching process, etching back the sidewall material film until the sidewall material film on the substrate surface and the top surface of the dummy gate structure 209 is removed, thereby forming the initial gate sidewall 210 on the sidewall of the dummy gate structure 209.

[0070] In this embodiment, the material of the initial gate sidewall 210 includes a combination of various low-k dielectric materials (K less than 3.9). The low-k dielectric materials include SiOC, SiOCN, and SiBCN, etc.

[0071] Similarly, the materials used for the subsequently formed gate sidewalls include a combination of various low-k dielectric materials. These low-k dielectric materials include SiOC, SiOCN, and SiBCN, among others.

[0072] In other embodiments, the material of the initial gate sidewall comprises a low-k dielectric material.

[0073] Similarly, the material of the subsequently formed grid sidewalls includes a low-K dielectric material.

[0074] In this embodiment, the initial gate sidewall 210 includes multiple sub-sidewalls (not shown) arranged in a direction perpendicular to the sidewall of the pseudo-gate structure 209, and the material of each sub-sidewall includes a low-K dielectric material.

[0075] In other embodiments, the initial gate sidewall is a single-layer structure in a direction perpendicular to the sidewall of the pseudo-gate structure.

[0076] In this embodiment, before forming the dummy gate material film, a substrate isolation dielectric layer (not shown) is formed on the substrate surface. The substrate isolation dielectric layer also covers part of the sidewall of the fin structure 201, thereby enabling electrical insulation between adjacent fin structures 201 and between the semiconductor device and the substrate 200 through the substrate isolation dielectric layer.

[0077] Please continue to refer to this. Figure 5 After the initial gate sidewall 210 is formed, a plurality of source-drain structures 202 are formed in the substrate.

[0078] Specifically, the method for forming a plurality of source-drain structures 202 includes: after forming an initial gate sidewall 210, forming source-drain openings (not shown) in the fin structures 201 on both sides of the pseudo-gate structure 209; and forming source-drain structures 202 in the source-drain openings using an epitaxial growth process.

[0079] Please refer to Figure 6 After the source-drain structure 202 is formed and before the gate sidewall is subsequently formed, a fourth dielectric layer 220 is formed on the substrate surface and the surface of the plurality of source-drain structures 202.

[0080] In this embodiment, the fourth dielectric layer 220 is also located on the sidewall of the initial gate sidewall 210.

[0081] The fourth dielectric layer 220 provides support for the subsequent formation of the gate structure, the first conductive structure, and the first sidewall.

[0082] In this embodiment, the material of the fourth dielectric layer 220 is silicon oxide.

[0083] In other embodiments, the material of the fourth dielectric layer includes at least one of SiOCH, SiOH, and SiCN.

[0084] In this embodiment, the method for forming the fourth dielectric layer 220 includes: forming a fourth dielectric material layer (not shown) on the pseudo-gate structure 209 and the substrate surface, wherein the surface of the fourth dielectric material layer is higher than the top surface of the pseudo-gate structure 209; and planarizing the fourth dielectric material layer until the top surface of the pseudo-gate structure 209 is exposed.

[0085] The formation process of the fourth dielectric material layer includes spin coating or deposition processes, such as chemical vapor deposition, physical vapor deposition or atomic layer deposition.

[0086] The process for planarizing the fourth dielectric material layer includes: etch-back process or chemical mechanical polishing process, etc.

[0087] In this embodiment, during the formation of the fourth dielectric layer 220, an initial etch stop layer 221 is also formed on the substrate surface, the source / drain structure 202 surface, and the sidewall of the initial gate sidewall 210.

[0088] Specifically, the method for forming the initial etch stop layer 221 includes: forming an etch stop layer material film (not shown) on the substrate surface, the source / drain structure 202 surface, the initial gate sidewall 210 surface, and the dummy gate structure 209 surface before forming the fourth dielectric material layer; and further planarizing the etch stop layer material film during the planarization of the fourth dielectric material layer until the top surface of the dummy gate structure 209 and the top surface of the initial gate sidewall 210 are exposed to form the initial etch stop layer 221.

[0089] On the one hand, the initial etch stop layer 221 protects the initial gate sidewall 210 and source / drain structure 202 during the subsequent etching process to form the first opening, thereby reducing the damage to the surfaces of the initial gate sidewall 210 and source / drain structure 202 caused by the etching process and improving the performance of the semiconductor structure. On the other hand, the initial etch stop layer 221 provides material for the subsequent formation of the etch stop layer.

[0090] In this embodiment, the material of the initial etch stop layer 221 includes silicon nitride. Correspondingly, the material of the etch stop layer includes silicon oxide.

[0091] Please continue to refer to this. Figure 6 After forming the fourth dielectric layer 220 and the initial etch stop layer 221, the dummy gate structure 209 is removed, and a plurality of gate openings (not shown) are formed in the fourth dielectric layer 220; the gate openings are filled with the material of the gate structure to form a plurality of gate structures 211 located in the fourth dielectric layer 220 on the substrate.

[0092] The gate structure 211 spans the fin structure 201, the initial gate sidewall 210 covers the sidewall of the gate structure 211, and the source / drain structure 202 is located in the substrate on both sides of the gate structure 211.

[0093] Similarly, in this embodiment, the multilayer sub-sidewalls are arranged in a direction perpendicular to the sidewall of the gate structure 211. In other embodiments, the initial gate sidewall is a single-layer structure in a direction perpendicular to the sidewall of the gate structure.

[0094] In this embodiment, the method for forming the gate structure 211 includes: forming a gate dielectric material layer (not shown) on the surface of the fourth dielectric layer 220 and the inner wall surface of the gate opening; forming a work function material layer (not shown) on the surface of the gate dielectric material layer; forming a gate electrode material layer (not shown) on the surface of the work function material layer, wherein the gate electrode material layer fills the gate opening; planarizing the gate electrode material layer, the work function material layer and the gate dielectric material layer until the surface of the fourth dielectric layer 220 is exposed, thereby forming the gate structure 211.

[0095] In this embodiment, the gate structure 211 includes: a gate dielectric layer (not shown) located on the inner wall of the gate opening, a work function layer (not shown) located on the surface of the gate dielectric layer, and a gate electrode layer (not shown) located on the surface of the work function layer.

[0096] The gate dielectric layer is made of a high-K dielectric material (K greater than 3.9). The high-K dielectric material includes: hafnium dioxide, hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, or aluminum oxide, etc.

[0097] The material of the gate electrode layer includes metallic materials, such as one or a combination of tungsten, copper, aluminum, titanium and tantalum.

[0098] The material of the work function layer includes titanium nitride, tantalum nitride, or titanium aluminum.

[0099] Please refer to Figure 7 After forming the gate structure 211, the initial gate sidewall 210 is etched back to form the gate sidewall 211. A sidewall opening 213 is formed on the gate sidewall 212. The bottom of the sidewall opening 213 exposes the top surface of the gate sidewall 212. The sidewalls on both sides of the sidewall opening 213 expose the sidewalls of the fourth dielectric layer 220 and the sidewalls of the gate structure 211, respectively.

[0100] The side wall opening 213 provides space for the subsequent formation of the first side wall.

[0101] In this embodiment, the process of etching back the initial gate sidewall 210 includes a dry etching process or a wet etching process.

[0102] In this embodiment, while etching the initial gate sidewall 211, the initial etch stop layer 221 is also etched to form an etch stop layer 222, and the bottom of the sidewall opening 213 also exposes the top surface of the etch stop layer 222.

[0103] By etching back the initial gate sidewall 210 and the initial etch stop layer 221, a sidewall opening 213 is formed. This allows the first sidewall subsequently formed within the sidewall opening 213 to simultaneously contact the sidewall of the first conductive structure and the sidewall of the gate structure 211. That is, before the barrier layer is formed, the top surfaces of the first conductive structure and the gate structure 211 are separated by the top surface of the first sidewall. Thus, after a barrier layer located only on the top surface of the first sidewall is formed using a selective film deposition process, the first dielectric layer formed on the top surface of the first conductive structure and the top surface of the gate structure 211 is separated by the barrier layer.

[0104] Please refer to Figure 8 A first sidewall 214 is formed on the sidewall of the gate structure 211, and the top surface of the first sidewall 214 is flush with the top surface of the gate structure 211.

[0105] In other embodiments, the top surface of the first sidewall is lower than the top surface of the gate structure.

[0106] Specifically, in this embodiment, the gate sidewall 212 is located on a portion of the sidewall of the gate structure 211, and the first sidewall 214 is located on the top surface of the gate sidewall 212.

[0107] Furthermore, the first sidewall 214 is located on the top surface of the etching stop layer 222, and the fourth dielectric layer 220 is located on the sidewalls of the gate sidewall 212 and the first sidewall 214.

[0108] Specifically, in this embodiment, the method for forming the first sidewall 214 includes: forming a first sidewall material layer (not shown) within the sidewall opening 213, the top surface of the gate structure 211, and the surface of the fourth dielectric layer 220, wherein the first sidewall material layer provides material for forming the first sidewall 214, and the first sidewall material layer fills the sidewall opening 213; planarizing the first sidewall material layer until the top surface of the gate structure 211 is exposed, thereby filling the sidewall opening 213 with the material of the first sidewall 214 to form the first sidewall 214.

[0109] In this embodiment, the process for forming the first sidewall material layer includes spin coating or deposition processes, such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition.

[0110] In this embodiment, the process for planarizing the first sidewall material layer includes dry etching, wet etching, or chemical mechanical polishing.

[0111] In this embodiment, the material of the first sidewall 214 includes silicon oxide.

[0112] Next, after forming the first sidewall 214, a first conductive structure is formed on the surface of the source / drain structure 202, and the sidewall of the first conductive structure contacts the first sidewall 214. For details on the process of forming the first conductive structure, please refer to [link to documentation]. Figures 9 to 10 .

[0113] Please refer to Figure 9 After the first sidewall 214 is formed and before the barrier layer is formed, the fourth dielectric layer 220 is etched until a first opening 232 is formed between adjacent first sidewalls 214 and between adjacent gate sidewalls 212, the bottom of the first opening 232 exposing the surface of the source / drain structure 202.

[0114] The first opening 232 provides space for the subsequent formation of the first conductive structure.

[0115] Specifically, in this embodiment, the method for forming the first opening 232 includes: forming a first opening mask layer 231 on the top surface of the first sidewall 214 and the gate structure 211, wherein the surface of the first opening mask layer 231 exposes the surface of the fourth dielectric layer 220 on the source / drain structure 202; using the first opening mask layer 231 as a mask, etching the fourth dielectric layer 220 until the surface of the source / drain structure 202 is exposed, thereby forming the first opening 232.

[0116] In this embodiment, after the first sidewall 214 is formed and before the first conductive structure is subsequently formed, the etch stop layer 222 on the source / drain structure 202 is removed.

[0117] Specifically, during the etching of the fourth dielectric layer 220, the first opening mask layer 231 is also used as a mask to etch the etching stop layer 222 on the source / drain structure 202 to expose the surface of the source / drain structure 202.

[0118] Please refer to Figure 10 A first conductive structure 230 is formed on the surface of the source-drain structure 202, and the sidewall of the first conductive structure 230 is in contact with the first sidewall 214.

[0119] Specifically, after the first opening 232 is formed, the material of the first conductive structure 230 is filled into the first opening 232 to form the first conductive structure 230.

[0120] The method of forming the first conductive structure 230 includes: forming a first conductive structure material layer in the first opening 232, on the first sidewall 214, and on the gate structure 211, wherein the first conductive structure material layer fills the first opening 232; planarizing the first conductive structure material layer until the surface of the gate structure 211 and the surface of the first sidewall 214 are exposed, thereby forming the first conductive structure 230.

[0121] The process for forming the first conductive structural material layer includes: deposition process, electroplating process or metal electroless plating process, etc. The deposition process is, for example, physical vapor deposition process or chemical vapor deposition process, etc., and the metal electroless plating process is, for example, selective metal electroless plating process, etc.

[0122] The process for planarizing the first conductive structural material includes: dry etching process, wet etching process, or chemical mechanical polishing process, etc.

[0123] In this embodiment, the material of the first conductive structure 230 includes cobalt, tungsten, or ruthenium.

[0124] In this embodiment, the first opening mask layer 231 is removed simultaneously during the planarization of the first conductive structural material layer. Therefore, during the planarization of the first conductive structural material layer, the first opening mask layer 231 can protect the top surface of the first sidewall 214 and the top surface of the gate structure 211, reducing damage to the surfaces of the first sidewall 214 and the gate structure 211 caused by the planarization process. On the one hand, a barrier layer with better quality and fewer defects can be formed subsequently through the first sidewall 214; on the other hand, the impact on the semiconductor structure performance is also reduced.

[0125] In other embodiments, the first opening mask layer is removed before the material is filled into the first conductive structure.

[0126] Please refer to Figure 11 A barrier layer 240 is formed on the top surface of the first sidewall 214 using a selective film-forming process.

[0127] The selective film formation process for forming the barrier layer 240 includes a selective atomic layer deposition process.

[0128] The selective atomic layer deposition process allows for selective deposition of a film on the top surface of the first sidewall 214, which is made of silicon oxide, to form a barrier layer 240 made of oxide. That is, the material of the barrier layer 240 includes oxide.

[0129] In this embodiment, the material of the barrier layer 240 is aluminum oxide.

[0130] In other embodiments, the material of the barrier layer includes zinc oxide, ruthenium oxide, or titanium oxide.

[0131] In this embodiment, the reactive gas used in the selective atomic layer deposition process includes a gas containing aluminum, such as gaseous AlCl3 and Al(Ch3)3.

[0132] In this embodiment, the parameters of the selective atomic layer deposition process further include: a temperature of 100 degrees Celsius to 200 degrees Celsius; a response time of 0.05 seconds to 0.5 seconds for the reactive gas pulse; and a purge time of 20 seconds to 40 seconds.

[0133] Therefore, by controlling the parameters of the selective atomic layer deposition process, the thickness range of the barrier layer 240 can be controlled so that the thickness range of the barrier layer 240 is between 20 angstroms and 150 angstroms.

[0134] Specifically, the thickness of the barrier layer 240 in the direction perpendicular to the substrate surface ranges from 20 angstroms to 150 angstroms.

[0135] If the barrier layer 240 is too thin, it is more easily worn away during the etching process of the second opening that provides space for the second conductive structure, or the etching process of the third opening that provides space for the third conductive structure. This results in low pattern accuracy of the self-aligned etching process, or the second and third openings may not be spaced, easily causing short circuits between the second and third conductive structures, affecting the reliability of the semiconductor structure. If the barrier layer 240 is too thick, it increases the aspect ratio of the second or third opening, which is not conducive to subsequent material filling within the second or third opening. This can lead to defects such as voids within the formed second or third conductive structure, affecting the performance of the semiconductor structure. Therefore, choosing an appropriate thickness for the barrier layer 240, i.e., when the thickness of the barrier layer 240 is in the range of 20 angstroms to 150 angstroms, can, on the one hand, improve pattern accuracy and improve the reliability of the semiconductor structure while achieving self-alignment of the etching; on the other hand, it is conducive to the subsequent material filling, forming a second and third conductive structure of better quality, thereby improving the performance of the semiconductor structure.

[0136] Please refer to Figure 12 After the barrier layer 240 is formed, a first dielectric layer 250 is formed on the top surface of the gate structure 211 and the top surface of the first conductive structure 230.

[0137] In this embodiment, a selective film deposition process is employed to form a barrier layer 240 on the top surface of the first sidewall 214 located between adjacent first conductive structures 230 and gate structures 211. After forming the barrier layer 240, a first dielectric layer 250 is formed on the top surfaces of the gate structure 211 and the first conductive structure 230. Therefore, the barrier layer 240 is only located on the top surface of the first sidewall 214, and it can space the first dielectric layer 250 on the top surface of the gate structure 211 and the first dielectric layer 250 on the top surface of the first conductive structure 230. Furthermore, since the barrier layer 240 and the first dielectric layer 250 are formed separately, barrier layers 240 and first dielectric layers 250 of different materials can be formed; that is, the material of the first dielectric layer 250 is different from the material of the barrier layer 240. Thus, during subsequent etching of the first dielectric layer 250, different etching rates can be applied to the first dielectric layer 250 and the barrier layer 240, achieving a self-aligned etching process. Based on this, since the semiconductor structure formation method does not involve etching the first conductive structure 230 after its formation, the etching process has a minimal impact on the first conductive structure 230. Consequently, the electrical characteristics of the first conductive structures 230 in different regions of the semiconductor structure exhibit high consistency, improving the stability of the semiconductor structure's electrical characteristics and enhancing its performance and reliability. In summary, this semiconductor structure achieves self-aligned etching while simultaneously improving the stability of its electrical characteristics, thereby enhancing its performance and reliability.

[0138] In this embodiment, the material of the first dielectric layer 250 includes silicon carbide, silicon carbide, silicon carbonitride, silicon nitride, silicon oxynitride, or silicon boronitride.

[0139] In other embodiments, the material of the first dielectric layer includes a metal compound. The metal compound is, for example, aluminum nitride or titanium oxide.

[0140] In this embodiment, the method of forming the first dielectric layer 250 includes: forming a first dielectric material layer (not shown) on the top surface of the gate structure 211, the top surface of the first conductive structure 230 and the surface of the barrier layer 240; planarizing the first dielectric material layer until the top surface of the barrier layer 240 is exposed.

[0141] In this embodiment, the process for forming the first dielectric material layer includes physical vapor deposition, chemical vapor deposition, or atomic layer deposition. In other embodiments, the process for forming the first dielectric material layer includes a flowable chemical vapor deposition process followed by an annealing process.

[0142] In this embodiment, the process for planarizing the first dielectric material layer includes a chemical mechanical polishing (CMP) process. In other embodiments, the process for planarizing the first dielectric material layer includes a dry etching process or a wet etching process.

[0143] Please refer to Figure 13 After the first dielectric layer 250 is formed, the first dielectric layer 250 is etched until the top surface of the gate structure 211 is exposed, so as to form a second opening 251 in the first dielectric layer 250.

[0144] The second opening 251 provides space for the subsequent formation of the second conductive structure.

[0145] In this embodiment, a third dielectric layer 270 is formed on the top surface of the barrier layer 240 and the first dielectric layer 250 before the second opening 251 is formed.

[0146] Specifically, the method for forming the second opening 251 includes: forming a second opening mask layer (not shown) on the surface of the third dielectric layer 270, the second opening mask layer exposing a portion of the surface of the third dielectric layer 270 on the gate structure 211; using the second opening mask layer and the barrier layer 240 as masks, etching the third dielectric layer 270 and the first dielectric layer 250 until the top surface of the gate structure 211 is exposed, thereby forming the second opening 251.

[0147] The etching process for the third dielectric layer 270 and the first dielectric layer 250 includes a dry etching process or a wet etching process.

[0148] In this embodiment, after the first dielectric layer 250 is formed, the first dielectric layer 250 is further etched until the top surface of the first conductive structure 230 is exposed, so as to form a third opening 252 in the first dielectric layer 250.

[0149] The third opening 252 provides space for the subsequent formation of the third conductive structure.

[0150] Similarly, in this embodiment, the third dielectric layer 270 is formed before the third opening 252 is formed.

[0151] Specifically, the method for forming the third opening 252 includes: forming a third opening mask layer (not shown) on the surface of the third dielectric layer 270, the third opening mask layer exposing a portion of the surface of the third dielectric layer 270 on the first conductive structure 230; using the third opening mask layer and the barrier layer 240 as masks, etching the third dielectric layer 270 and the first dielectric layer 250 until the top surface of the first conductive structure 230 is exposed, thereby forming the third opening 252.

[0152] In this embodiment, during the etching process of the first dielectric layer 250, specifically during the formation of the second opening 251 and the third opening 252, the etching selectivity ratio of the first dielectric layer 250 to the barrier layer 240 is greater than 8:1. Therefore, by using a larger etching selectivity ratio, the wear on the barrier layer 240 can be reduced while etching the first dielectric layer 250, thus achieving better self-alignment of the etching process.

[0153] It should be noted that, in order to reduce the etching load when etching the second opening 251 and the third opening 252, the second opening 251 and the third opening 252 are formed respectively.

[0154] In other embodiments, a second opening and a third opening are formed simultaneously.

[0155] In other embodiments, the third dielectric layer is not formed.

[0156] Please refer to Figure 14 A second conductive structure 262 is formed in the second opening 251; a third conductive structure 263 is formed in the third opening 252.

[0157] In this embodiment, the material of the second conductive structure 262 includes cobalt, tungsten, or ruthenium.

[0158] In this embodiment, the material of the third conductive structure 263 includes cobalt, tungsten, or ruthenium.

[0159] Specifically, the method for forming the second conductive structure 262 and the third conductive structure 263 includes: forming a conductive structure material layer (not shown) in the second opening 251, the third opening 252 and on the surface of the third dielectric layer 270; planarizing the conductive structure material layer until the surface of the third dielectric layer 270 is exposed, so as to form the second conductive structure 262 in the second opening 251 and the third conductive structure 263 in the third opening 252.

[0160] Accordingly, one embodiment of the present invention also provides a semiconductor structure formed by the above-described forming method. Please refer to [the original text]. Figure 14The system includes: a substrate; a plurality of gate structures 211 disposed on the substrate and discretely disposed therefrom; a plurality of source / drain structures 202 disposed in the substrate on both sides of the gate structures 211; a first conductive structure 230 disposed on the surface of the source / drain structures 202; a first sidewall 214 disposed on the sidewall of the gate structure 211, wherein the top surface of the first sidewall 214 is lower than or flush with the top surface of the gate structure 211, and the sidewall of the first conductive structure 230 is in contact with the first sidewall 214; a barrier layer 240 disposed on the top surface of the first sidewall 214; and a first dielectric layer 250 disposed on the top surface of the gate structure 211 and the top surface of the first conductive structure 230, wherein the material of the first dielectric layer 250 is different from the material of the barrier layer 240.

[0161] In this embodiment, the substrate includes a substrate 200 and a plurality of fin structures 201 disposed on the substrate 200, wherein the gate structure 211 spans the fin structures 201.

[0162] The substrate 200 is made of semiconductor materials.

[0163] In this embodiment, the substrate 200 is made of silicon.

[0164] In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI), etc. The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP, etc.

[0165] In other embodiments, the fin structure includes: a plurality of fin sacrificial layers arranged in a direction perpendicular to the substrate surface, and nanosheets located between adjacent fin sacrificial layers.

[0166] In this embodiment, the gate structure 211 includes: a gate dielectric layer (not shown) located on the inner wall of the gate opening, a work function layer (not shown) located on the surface of the gate dielectric layer, and a gate electrode layer (not shown) located on the surface of the work function layer.

[0167] The gate dielectric layer is made of a high-K dielectric material (K greater than 3.9). The high-K dielectric material includes: hafnium dioxide, hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, or aluminum oxide, etc.

[0168] The material of the gate electrode layer includes metallic materials, such as one or a combination of tungsten, copper, aluminum, titanium and tantalum.

[0169] The material of the work function layer includes titanium nitride, tantalum nitride, or titanium aluminum.

[0170] In other embodiments, the gate structure is made of polycrystalline silicon.

[0171] In this embodiment, the material of the first dielectric layer 250 includes silicon carbide, silicon carbide, silicon carbonitride, silicon nitride, silicon oxynitride, or silicon boronitride.

[0172] In other embodiments, the material of the first dielectric layer includes a metal compound. The metal compound is, for example, aluminum nitride or titanium oxide.

[0173] In this embodiment, the material of the first sidewall 214 includes silicon oxide, and the material of the barrier layer 240 includes oxide.

[0174] In this embodiment, the material of the barrier layer 240 is aluminum oxide.

[0175] In other embodiments, the material of the barrier layer includes zinc oxide, ruthenium oxide, or titanium oxide.

[0176] In another embodiment, the material of the first sidewall includes silicon nitride, and the material of the barrier layer includes titanium nitride, copper, aluminum, nickel, platinum, or ruthenium.

[0177] In this embodiment, the thickness of the barrier layer 240 in the direction perpendicular to the substrate surface ranges from 20 angstroms to 150 angstroms.

[0178] In this embodiment, the semiconductor structure further includes a gate sidewall 212 located on a portion of the sidewall of the gate structure 211, and the first sidewall 214 is located on the top surface of the gate sidewall 212.

[0179] In this embodiment, the material of the gate sidewall 212 includes a combination of various low-k dielectric materials. The low-k dielectric materials include SiOC, SiOCN, and SiBCN, etc.

[0180] In this embodiment, the gate sidewall 212 includes multiple sub-sidewalls (not shown) arranged along a direction perpendicular to the sidewall of the gate structure 211, and each sub-sidewall is made of a low-k dielectric material. In other embodiments, the gate sidewall is a single-layer structure in the direction perpendicular to the sidewall of the gate structure.

[0181] In this embodiment, the semiconductor structure further includes an etch stop layer 222 located between the gate sidewall 212 and the sidewall of the first conductive structure 230, wherein the first sidewall 214 is also located on the top surface of the etch stop layer 222.

[0182] In this embodiment, the material of the etch stop layer 222 includes silicon oxide.

[0183] In this embodiment, the semiconductor structure further includes: a second conductive structure 262 located on the top surface of the gate structure 211, the second conductive structure 262 also located within the first dielectric layer 250; a third conductive structure 263 located on the top surface of the first conductive structure 230, the third conductive structure 263 also located within the first dielectric layer 250; and a third dielectric layer 270 located on the top surface of the barrier layer 240 and the first dielectric layer 250, the second conductive structure 262 also located within the third dielectric layer 270, and the third conductive structure 263 also located within the third dielectric layer 270.

[0184] In this embodiment, the material of the first conductive structure 230 includes cobalt, tungsten, or ruthenium. The material of the second conductive structure 262 includes cobalt, tungsten, or ruthenium. The material of the third conductive structure 263 includes cobalt, tungsten, or ruthenium.

[0185] Figures 15 to 20 This is a cross-sectional structural schematic diagram of each step in the method for forming a semiconductor structure according to another embodiment of the present invention. This embodiment is similar to... Figures 4 to 14 The main difference in the illustrated embodiment is that the material of the first sidewall is different, and correspondingly, the material of the barrier layer is also different.

[0186] Please Figure 7 Continue to refer to Figure 15 A first sidewall 314 is formed on the sidewall of the gate structure 211, and the top surface of the first sidewall 314 is flush with the top surface of the gate structure 211.

[0187] In other embodiments, the top surface of the first sidewall is lower than the top surface of the gate structure.

[0188] Specifically, in this embodiment, the gate sidewall 212 is located on a portion of the sidewall of the gate structure 211, and the first sidewall 314 is located on the top surface of the gate sidewall 212.

[0189] Furthermore, the first sidewall 314 is located on the top surface of the etching stop layer 222, and the fourth dielectric layer 220 is located on the sidewalls of the gate sidewall 212 and the first sidewall 314.

[0190] In this embodiment, the material of the first sidewall 314 includes silicon nitride.

[0191] The specific method for forming the first sidewall 314 and Figures 4 to 14 The method for forming the first sidewall 214 in the illustrated embodiment is the same and will not be described again here.

[0192] In this embodiment, after the first sidewall 314 is formed, a first conductive structure 330 is formed on the surface of the source-drain structure 202, and the sidewall of the first conductive structure 330 is in contact with the first sidewall 314.

[0193] The specific method for forming the first conductive structure 330 and Figures 4 to 14 The method for forming the first conductive structure 230 in the illustrated embodiment is the same and will not be described again here.

[0194] In this embodiment, the material of the first conductive structure 330 includes cobalt, tungsten, or ruthenium.

[0195] Please refer to Figure 16 A barrier layer 340 is formed on the top surface of the first sidewall 314 using a selective film-forming process.

[0196] The selective film formation process for forming the barrier layer 340 includes a selective atomic layer deposition process.

[0197] The selective atomic layer deposition process described above enables the selective deposition of a barrier layer 340 on the top surface of the first sidewall 314, which is made of silicon nitride.

[0198] In this embodiment, the material of the barrier layer 340 includes titanium nitride.

[0199] In other embodiments, the barrier layer may also be made of copper, aluminum, nickel, platinum, or ruthenium.

[0200] In this embodiment, the reactive gas used in the selective atomic layer deposition process includes a gas containing titanium, such as TiCl4.

[0201] Specifically, the parameters of the selective atomic layer deposition process also include: a temperature of 150 degrees Celsius to 300 degrees Celsius; a response time of 0.05 seconds to 0.5 seconds for the reactive gas pulse; and a purge time of 40 seconds to 60 seconds.

[0202] Therefore, by controlling the parameters of the selective atomic layer deposition process, the thickness range of the barrier layer 340 can be controlled so that the thickness range of the barrier layer 240 is between 20 angstroms and 150 angstroms.

[0203] Specifically, the thickness of the barrier layer 340 in the direction perpendicular to the substrate surface ranges from 20 angstroms to 150 angstroms.

[0204] The reason for selecting the thickness range of the barrier layer 340 is related to... Figures 4 to 14 The reasons for selecting the thickness range of the barrier layer 240 in the illustrated embodiment are the same and will not be repeated here.

[0205] Please refer to Figure 17 After the barrier layer 340 is formed, a first dielectric layer 350 is formed on the top surface of the gate structure 211 and the top surface of the first conductive structure 330.

[0206] In this embodiment, due to the use of a selective film deposition process, a barrier layer 340 is formed on the top surface of the first sidewall 314 located between adjacent first conductive structures 330 and gate structures 211. After forming the barrier layer 340, a first dielectric layer 350 is formed on the top surfaces of the gate structure 211 and the first conductive structure 330. Therefore, the barrier layer 340 is only located on the top surface of the first sidewall 314, and the barrier layer 340 can space the first dielectric layer 350 located on the top surface of the gate structure 211 and the first dielectric layer 350 located on the top surface of the first conductive structure 330. Furthermore, since the barrier layer 340 and the first dielectric layer 350 are formed separately, barrier layers 340 and first dielectric layers 350 with different materials can be formed, that is, the material of the first dielectric layer 350 is different from the material of the barrier layer 340.

[0207] In this embodiment, the barrier layer 340 is made of a non-dielectric material. Since the barrier layer 340 and the first dielectric layer 350 can be etched at different rates during subsequent etching, allowing the first dielectric layer 350 to be retained while the barrier layer 340 is removed, it is possible to subsequently replace the barrier layer 340 with a dielectric material (second dielectric layer) different from the material of the first dielectric layer 350. Furthermore, by using the dielectric material to separate the first dielectric layer 350 located on the top surface of the gate structure 211 and the first dielectric layer 350 located on the top surface of the first conductive structure 330, different etching rates can be applied to the first dielectric layer 350 and the dielectric material (second dielectric layer) during subsequent etching, thus achieving a self-aligned etching process.

[0208] Based on this, since the semiconductor structure formation method does not involve etching the first conductive structure 330 after its formation, the etching process has minimal impact on the first conductive structure 330. Consequently, the electrical characteristics of the first conductive structures 330 in different regions of the semiconductor structure exhibit high consistency, improving the stability of the semiconductor structure's electrical characteristics and enhancing its performance and reliability. In summary, this semiconductor structure achieves self-aligned etching while simultaneously improving the stability of its electrical characteristics, thereby enhancing its performance and reliability.

[0209] In this embodiment, the material of the first dielectric layer 350 includes silicon carbide, silicon carbide, silicon carbonitride, silicon nitride, silicon oxynitride, or silicon boronitride.

[0210] In other embodiments, the material of the first dielectric layer includes a metal compound. The metal compound is, for example, aluminum nitride or titanium oxide.

[0211] The specific method for forming the first dielectric layer 350 and Figures 4 to 14 The method for forming the first dielectric layer 250 in the illustrated embodiment is the same and will not be described again here.

[0212] Please refer to Figure 18 After the first dielectric layer 350 is formed, the barrier layer 340 is etched back until the barrier layer 340 is removed; after the barrier layer 340 is removed, a second dielectric layer 380 is formed on the top surface of the first sidewall 314.

[0213] Therefore, it is possible to replace the non-dielectric barrier layer 340 with a dielectric second dielectric layer 380. This enables electrical insulation between the subsequently formed second and third conductive structures.

[0214] In this embodiment, the process of etching back the barrier layer 340 includes a dry etching process or a wet etching process.

[0215] In this embodiment, during the etch-back process of the barrier layer 340, the etch selectivity ratio of the barrier layer 340 to the first dielectric layer 350 is greater than 5:1. Therefore, by using a larger etch selectivity ratio, the wear on the first dielectric layer 350 can be reduced while etching the barrier layer 340, allowing for the subsequent formation of a second dielectric layer with a better morphology. Furthermore, this reduces the impact of the etch-back process on the performance of the semiconductor structure and enables better self-alignment of the subsequent etching process.

[0216] Please refer to Figure 19 After the second dielectric layer 380 is formed, the first dielectric layer 350 is etched until the top surface of the gate structure 211 is exposed to form a second opening 351 in the first dielectric layer 350.

[0217] The second opening 351 provides space for the subsequent formation of the second conductive structure.

[0218] In this embodiment, a third dielectric layer 370 is formed on the top surface of the second dielectric layer 380 and the first dielectric layer 350 before the second opening 351 is formed.

[0219] Specifically, the method for forming the second opening 351 includes: forming a second opening mask layer (not shown) on the surface of the third dielectric layer 370, the second opening mask layer exposing a portion of the surface of the third dielectric layer 370 on the gate structure 211; using the second opening mask layer and the second dielectric layer 380 as masks, etching the third dielectric layer 370 and the first dielectric layer 350 until the top surface of the gate structure 211 is exposed, thereby forming the second opening 351.

[0220] The etching process for the third dielectric layer 370 and the first dielectric layer 350 includes a dry etching process or a wet etching process.

[0221] In this embodiment, after the first dielectric layer 350 is formed, the first dielectric layer 350 is further etched until the top surface of the first conductive structure 330 is exposed, so as to form a third opening 352 in the first dielectric layer 350.

[0222] The third opening 352 provides space for the subsequent formation of the third conductive structure.

[0223] Similarly, in this embodiment, the third dielectric layer 370 is formed before the third opening 352 is formed.

[0224] Specifically, the method for forming the third opening 352 includes: forming a third opening mask layer (not shown) on the surface of the third dielectric layer 370, the third opening mask layer exposing a portion of the surface of the third dielectric layer 370 on the first conductive structure 330; using the third opening mask layer and the second dielectric layer 380 as masks, etching the third dielectric layer 370 and the first dielectric layer 350 until the top surface of the first conductive structure 330 is exposed, thereby forming the third opening 352.

[0225] In this embodiment, during the etching process of the first dielectric layer 350, specifically during the formation of the second opening 351 and the third opening 352, the etching selectivity ratio of the first dielectric layer 350 to the second dielectric layer 380 is within the range of 5:1. Therefore, by using a larger etching selectivity ratio, the wear on the second dielectric layer 380 can be reduced while etching the first dielectric layer 350, thus achieving better self-alignment of the etching process.

[0226] It should be noted that, in order to reduce the etching load when etching the second opening 351 and the third opening 352, the second opening 351 and the third opening 352 are formed respectively.

[0227] In other embodiments, a second opening and a third opening are formed simultaneously.

[0228] In other embodiments, the third dielectric layer is not formed.

[0229] Please refer to Figure 20 A second conductive structure 362 is formed in the second opening 351; a third conductive structure 363 is formed in the third opening 352.

[0230] In this embodiment, the material of the second conductive structure 362 includes cobalt, tungsten, or ruthenium.

[0231] In this embodiment, the material of the third conductive structure 363 includes cobalt, tungsten, or ruthenium.

[0232] Specifically, the method for forming the second conductive structure 362 and the third conductive structure 363 includes: forming a conductive structure material layer (not shown) in the second opening 351, the third opening 352 and on the surface of the third dielectric layer 270; planarizing the conductive structure material layer until the surface of the third dielectric layer 370 is exposed, so as to form the second conductive structure 362 in the second opening 351 and the third conductive structure 363 in the third opening 352.

[0233] Accordingly, another embodiment of the present invention also provides a semiconductor structure formed by the above-described forming method. Please refer to [the original text]. Figure 20 The system includes: a substrate; a plurality of gate structures 211 located on the substrate and discretely arranged therein; a plurality of source / drain structures 202 located within the substrate on both sides of the gate structures 211; a first conductive structure 330 located on the surface of the source / drain structures 202; a first sidewall 314 located on the sidewall of the gate structure 211, the top surface of the first sidewall 314 being lower than or flush with the top surface of the gate structure 211, and the sidewall of the first conductive structure 330 contacting the first sidewall 314; a first dielectric layer 350 located on the top surface of the gate structure 211 and the top surface of the first conductive structure 330; and a second dielectric layer 380 located on the top surface of the first sidewall 314, the material of the second dielectric layer 380 being different from the material of the first dielectric layer 350.

[0234] In this embodiment, the substrate includes a substrate 200 and a plurality of fin structures 201 disposed on the substrate 200, wherein the gate structure 211 spans the fin structures 201.

[0235] The substrate 200 is made of semiconductor materials.

[0236] In this embodiment, the substrate 200 is made of silicon.

[0237] In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI), etc. The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP, etc.

[0238] In other embodiments, the fin structure includes: a plurality of fin sacrificial layers arranged in a direction perpendicular to the substrate surface, and nanosheets located between adjacent fin sacrificial layers.

[0239] In this embodiment, the material of the first sidewall 314 includes silicon nitride.

[0240] In this embodiment, the gate structure 211 includes: a gate dielectric layer (not shown) located on the inner wall of the gate opening, a work function layer (not shown) located on the surface of the gate dielectric layer, and a gate electrode layer (not shown) located on the surface of the work function layer.

[0241] The gate dielectric layer is made of a high-K dielectric material (K greater than 3.9). The high-K dielectric material includes: hafnium dioxide, hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, or aluminum oxide, etc.

[0242] The material of the gate electrode layer includes metallic materials, such as one or a combination of tungsten, copper, aluminum, titanium and tantalum.

[0243] The material of the work function layer includes titanium nitride, tantalum nitride, or titanium aluminum.

[0244] In other embodiments, the gate structure is made of polycrystalline silicon.

[0245] In this embodiment, the material of the first dielectric layer 350 includes silicon carbide, silicon carbide, silicon carbonitride, silicon nitride, silicon oxynitride, or silicon boronitride.

[0246] In other embodiments, the material of the first dielectric layer includes a metal compound. The metal compound is, for example, aluminum nitride or titanium oxide.

[0247] In this embodiment, the semiconductor structure further includes a gate sidewall 212 located on a portion of the sidewall of the gate structure 211, and the first sidewall 314 is located on the top surface of the gate sidewall 212.

[0248] In this embodiment, the material of the gate sidewall 212 includes a combination of various low-k dielectric materials. The low-k dielectric materials include SiOC, SiOCN, and SiBCN, etc.

[0249] In this embodiment, the gate sidewall 212 includes multiple sub-sidewalls (not shown) arranged along a direction perpendicular to the sidewall of the gate structure 211, and each sub-sidewall is made of a low-k dielectric material. In other embodiments, the gate sidewall is a single-layer structure in the direction perpendicular to the sidewall of the gate structure.

[0250] In this embodiment, the semiconductor structure further includes an etch stop layer 222 located between the gate sidewall 212 and the sidewall of the first conductive structure 330, wherein the first sidewall 314 is also located on the top surface of the etch stop layer 222.

[0251] In this embodiment, the material of the etch stop layer 222 includes silicon oxide.

[0252] In this embodiment, the semiconductor structure further includes: a second conductive structure 362 located on the top surface of the gate structure 211, the second conductive structure 362 also located within the first dielectric layer 350; a third conductive structure 363 located on the top surface of the first conductive structure 330, the third conductive structure 363 also located within the first dielectric layer 350; and a third dielectric layer 370 located on the top surfaces of the second dielectric layer 380 and the first dielectric layer 350, the second conductive structure 362 also located within the third dielectric layer 370, and the third conductive structure 363 also located within the third dielectric layer 370.

[0253] In this embodiment, the material of the first conductive structure 330 includes cobalt, tungsten, or ruthenium; the material of the second conductive structure 362 includes cobalt, tungsten, or ruthenium; and the material of the third conductive structure 363 includes cobalt, tungsten, or ruthenium.

[0254] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: Base; A plurality of gate structures located on the substrate and being discrete from each other, and gate sidewalls located on a portion of the sidewalls of the gate structures; Several source / drain structures located in the substrate on both sides of the gate structure; A first conductive structure located on the surface of the source / drain structure; A first sidewall is located on the sidewall of the gate structure, the top surface of the first sidewall is lower than or flush with the top surface of the gate structure, and the sidewall surface of the first conductive structure is in contact with the first sidewall; the first sidewall is located on the top surface of the gate sidewall. A barrier layer located only on the top surface of the first sidewall; A first dielectric layer is located on the top surface of the gate structure and the top surface of the first conductive structure, wherein the material of the first dielectric layer is different from the material of the barrier layer and is located between the barrier layers; And a second conductive structure located on the top surface of the gate structure, the second conductive structure also being located within the first dielectric layer; The second conductive structure is formed by filling the opening formed by etching the first dielectric layer using the barrier layer as a mask with conductive material.

2. The semiconductor structure as described in claim 1, characterized in that, The material of the first sidewall includes silicon oxide, and the material of the barrier layer includes oxide.

3. The semiconductor structure as described in claim 2, characterized in that, The oxides include aluminum oxide, zinc oxide, ruthenium oxide, or titanium oxide.

4. The semiconductor structure as described in claim 1, characterized in that, The material of the first sidewall includes silicon nitride, and the material of the barrier layer includes titanium nitride, copper, aluminum, nickel, platinum, or ruthenium.

5. The semiconductor structure as described in claim 1, characterized in that, The material of the first dielectric layer includes silicon carbide, silicon carbide, silicon carbonitride, silicon nitride, silicon oxynitride, silicon carbonitride, or a metal compound.

6. The semiconductor structure as described in claim 1, characterized in that, The thickness of the barrier layer ranges from 20 angstroms to 150 angstroms in the direction perpendicular to the substrate surface.

7. The semiconductor structure as described in claim 1, characterized in that, Also includes: An etch stop layer is located between the gate sidewall and the sidewall of the first conductive structure, the first sidewall also being located on the top surface of the etch stop layer.

8. The semiconductor structure as described in claim 1, characterized in that, Also includes: The third dielectric layer is located on the top surface of the barrier layer and the first dielectric layer, and the second conductive structure is also located within the third dielectric layer.

9. The semiconductor structure as described in claim 1, characterized in that, Also includes: A third conductive structure is located on the top surface of the first conductive structure, and the third conductive structure is also located within the first dielectric layer.

10. The semiconductor structure as described in claim 9, characterized in that, Also includes: The third dielectric layer is located on the top surface of the barrier layer and the first dielectric layer, and the third conductive structure is also located within the third dielectric layer.

11. A semiconductor structure, characterized in that, include: Base; A plurality of gate structures located on the substrate and being discrete from each other, and gate sidewalls located on a portion of the sidewalls of the gate structures; Several source / drain structures located in the substrate on both sides of the gate structure; A first conductive structure located on the surface of the source / drain structure; A first sidewall is located on the sidewall of the gate structure, the top surface of the first sidewall is lower than or flush with the top surface of the gate structure, and the sidewall surface of the first conductive structure is in contact with the first sidewall; the first sidewall is located on the top surface of the gate sidewall. A first dielectric layer located on the top surface of the gate structure and the top surface of the first conductive structure; A second dielectric layer located only on the top surface of the first sidewall, the material of the second dielectric layer being different from that of the first dielectric layer; the second dielectric layer is located between the first dielectric layers; And a second conductive structure located on the top surface of the gate structure, the second conductive structure also being located within the first dielectric layer; The second conductive structure is formed by filling the opening formed after etching the first dielectric layer using the second dielectric layer as a mask with conductive material.

12. The semiconductor structure as claimed in claim 11, characterized in that, Also includes: An etch stop layer is located between the gate sidewall and the sidewall of the first conductive structure, the first sidewall also being located on the top surface of the etch stop layer.

13. The semiconductor structure as described in claim 11, characterized in that, Also includes: A third dielectric layer is located on top of the first and second dielectric layers, and the second conductive structure is also located within the third dielectric layer.

14. The semiconductor structure as claimed in claim 11, characterized in that, Also includes: A third conductive structure is located on the top surface of the first conductive structure, and the third conductive structure is also located within the first dielectric layer.

15. The semiconductor structure as described in claim 14, characterized in that, Also includes: A third dielectric layer is located on top of the first dielectric layer and the second dielectric layer, and the third conductive structure is also located within the third dielectric layer.

16. A method for forming a semiconductor structure, characterized in that, include: Provide a base; Several mutually discrete gate structures are formed on the substrate; A plurality of source-drain structures are formed within the substrate, and the source-drain structures are also located on both sides of the gate structure; A first sidewall is formed on the sidewall of the gate structure, and the top surface of the first sidewall is lower than or flush with the top surface of the gate structure. After the first sidewall is formed, a first conductive structure is formed on the surface of the source-drain structure, and the sidewall of the first conductive structure is in contact with the first sidewall. A barrier layer is formed on the top surface of the first sidewall using a selective film-forming process; After the barrier layer is formed, a first dielectric layer is formed on the top surface of the gate structure and the top surface of the first conductive structure. The method further includes: After the first dielectric layer is formed, the first dielectric layer is etched using the barrier layer as a mask until the top surface of the gate structure is exposed, and a second opening is formed in the first dielectric layer; a second conductive structure is formed in the second opening. Alternatively, the method may further include: After forming the first dielectric layer, the barrier layer is etched back until it is removed; after removing the barrier layer, a second dielectric layer is formed on the top surface of the first sidewall; after forming the second dielectric layer, the first dielectric layer is etched using the second dielectric layer as a mask until the top surface of the gate structure is exposed, and a second opening is formed in the first dielectric layer; a second conductive structure is formed in the second opening.

17. The method for forming a semiconductor structure as described in claim 16, characterized in that, The selective film formation process includes a selective atomic layer deposition process, and the parameters of the selective atomic layer deposition process further include: a temperature of 100 degrees Celsius to 300 degrees Celsius; a response time of 0.05 seconds to 0.5 seconds for the reactive gas pulse; and a purge time of 20 seconds to 60 seconds.

18. The method for forming a semiconductor structure as described in claim 16, characterized in that, The material of the first sidewall includes silicon oxide, and the material of the barrier layer includes oxide.

19. The method for forming a semiconductor structure as described in claim 18, characterized in that, When the first dielectric layer is etched using the barrier layer as a mask to form a second opening in the first dielectric layer, the method further includes: forming a third dielectric layer on the top surface of the barrier layer and the first dielectric layer before etching the first dielectric layer.

20. The method for forming a semiconductor structure as described in claim 16, characterized in that, The material of the first sidewall includes silicon nitride, and the material of the barrier layer includes titanium nitride, copper, aluminum, nickel, platinum, or ruthenium.

21. The method for forming a semiconductor structure as described in claim 16, characterized in that, Also includes: The first dielectric layer is etched until the top surface of the first conductive structure is exposed, so as to form a third opening in the first dielectric layer; A third conductive structure is formed within the third opening.

22. The method for forming a semiconductor structure as described in claim 21, characterized in that, When the first dielectric layer is etched using the second dielectric layer as a mask to form a second opening in the first dielectric layer, the method further includes: forming a third dielectric layer on the top surface of the first dielectric layer and the second dielectric layer before etching the first dielectric layer.

23. The method for forming a semiconductor structure as described in claim 16, characterized in that, Also includes: An initial gate sidewall is formed before the source / drain structure is formed, and the initial gate sidewall covers the sidewall of the gate structure; a fourth dielectric layer is formed on the substrate surface and the surfaces of the plurality of source / drain structures; after the fourth dielectric layer is formed, the initial gate sidewall is etched back to form the gate sidewall, and a sidewall opening is formed on the gate sidewall, the bottom of the sidewall opening exposing the top surface of the gate sidewall, and the sidewall surfaces on both sides of the sidewall opening exposing the sidewall surfaces of the fourth dielectric layer and the sidewall surfaces of the gate structure, respectively; A first sidewall is formed within the sidewall opening, and the fourth dielectric layer is also located on the sidewalls of the grid sidewall and the first sidewall.

24. The method for forming a semiconductor structure as described in claim 23, characterized in that, Also includes: During the formation of the fourth dielectric layer, an initial etching stop layer is formed on the surface of the source / drain structure and on the sidewall of the initial gate sidewall. While etching the initial gate sidewall, the initial etch stop layer is etched to form an etch stop layer, and the first sidewall is also located on the top surface of the etch stop layer; after the first sidewall is formed and before the first conductive structure is formed, the etch stop layer on the source / drain structure is removed.

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