Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same include: providing a substrate; forming a plurality of discrete gate structures on the substrate; forming a source / drain structure within the substrate, the source / drain structure also being located on either side of the gate structure; forming a first conductive structure on the surface of the source / drain structure, wherein the top surface of the first conductive structure is higher than the top surface of the gate structure; forming a first etch stop layer on the top surface of the first conductive structure and on the sidewalls of the first conductive structure that are higher than the top surface of the gate structure; and forming a first dielectric layer on the top surface of the gate structure and on the surface of the first etch stop layer, wherein the material of the first dielectric layer is different from that of the first etch stop layer. Thus, while achieving a self-aligned etching process, the stability of the electrical characteristics of the semiconductor structure is improved, thereby enhancing the performance and reliability of the semiconductor structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] With the rapid development of integrated circuit manufacturing technology, the size of semiconductor devices in integrated circuits has continued to shrink, effectively increasing the operating speed of the entire integrated circuit. As the size requirements of components become smaller and smaller, the size of the conductive structures connected to the semiconductor devices also becomes smaller and smaller.

[0003] However, the performance and reliability of existing semiconductor structures still need to be improved. Summary of the Invention

[0004] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance and reliability of the formed semiconductor structure while realizing a self-alignment process of etching.

[0005] To solve the above technical problems, the technical solution of the present invention provides a semiconductor structure, comprising: a substrate; a plurality of gate structures separated from each other and located on the substrate; a plurality of source-drain structures located in the substrate on both sides of the gate structure; a first conductive structure located on the surface of the source-drain structure, wherein the top surface of the first conductive structure is higher than the top surface of the gate structure; a first etch stop layer located on the top surface of the first conductive structure, wherein the first etch stop layer is also located on the sidewall of the first conductive structure higher than the top surface of the gate structure; and a first dielectric layer located on the top surface of the gate structure and on the surface of the first etch stop layer, wherein the material of the first dielectric layer is different from the material of the first etch stop layer.

[0006] Optionally, the method further includes: a second opening located in the first dielectric layer, and a second conductive structure located in the second opening, wherein the bottom of the second opening exposes the top surface of the gate structure.

[0007] Optionally, the material of the first etch stop layer includes silicon oxycarbide, silicon carbide or carbon-doped silicon nitride.

[0008] Optionally, the method further includes: a first protective layer located on the top surface of the gate structure and between the first etch stop layer and the first conductive structure.

[0009] Optionally, it further includes: a second protective layer located on the top surface of the gate structure.

[0010] Optionally, the method further includes: a second etch stop layer located between the gate structure and the sidewall of the first conductive structure.

[0011] Optionally, it further includes: an oxide film located on the top surface of the first conductive structure.

[0012] Optionally, the gate structure includes a gate and a gate spacer located on a sidewall surface of the gate.

[0013] Optionally, the base includes a substrate and a plurality of fin structures located on the substrate, and the gate structure spans the fin structures.

[0014] Optionally, the fin structure includes: a plurality of fin sacrificial layers arranged in a direction perpendicular to the substrate surface, and nanosheets located between adjacent fin sacrificial layers.

[0015] Correspondingly, the technical solution of the present invention also provides a method for forming a semiconductor structure, including: providing a substrate; forming a plurality of mutually independent gate structures on the substrate; forming a source-drain structure in the substrate, and the source-drain structure is also located on both sides of the gate structure; forming a first conductive structure on the surface of the source-drain structure, and the top surface of the first conductive structure is higher than the top surface of the gate structure; forming a first etch stop layer on the top surface of the first conductive structure and on the side wall of the first conductive structure higher than the top surface of the gate structure; forming a first dielectric layer on the top surface of the gate structure and on the surface of the first etch stop layer, and the material of the first dielectric layer is different from the material of the first etch stop layer.

[0016] Optionally, the method for forming the first etch barrier layer includes: forming an initial first etch barrier structure on the top surface of the gate structure, the top surface of the first conductive structure, and the side wall of the first conductive structure higher than the top surface of the gate structure, the initial first etch barrier structure including an initial first etch barrier layer; forming an etch by-product layer on the top surface of the initial first etch barrier layer, the etch by-product layer exposing the initial first etch barrier layer on the top surface of the gate structure; etching the initial first etch barrier layer using the etch by-product layer as a mask until the initial first etch barrier layer on the top surface of the gate structure is removed.

[0017] Optionally, the process of forming the etching byproduct layer includes a plasma etching process.

[0018] Optionally, the gases used in the plasma etching process include: methane, oxygen and argon.

[0019] Optionally, the process parameters of the plasma etching process also include: a high-frequency radio frequency power range of 100 watts to 1000 watts; and a low-frequency radio frequency power range of 0 watts to 500 watts.

[0020] Optionally, the initial first etch stop structure further includes a first protective layer, and the initial first etch stop layer is located on the surface of the first protective layer.

[0021] Optionally, the material of the first protective layer includes silicon nitride.

[0022] Optionally, the material of the first etch stop layer includes silicon oxycarbide, silicon carbide or carbon-doped silicon nitride.

[0023] Optionally, the method further includes: after forming the first dielectric layer, forming a second conductive structure on the top surface of the gate structure, wherein the second conductive structure is also located in the first dielectric layer.

[0024] Optionally, the method for forming the second conductive structure includes: forming a first mask structure on the first dielectric layer, the first mask structure having a first mask opening, the width of the first mask opening being greater than the width of the gate structure; using the first mask structure and the first etch barrier layer as masks, etching the first dielectric layer until the top surface of the gate structure is exposed to form a second opening in the first dielectric layer; and filling the second opening with a material of the second conductive structure to form a second conductive structure.

[0025] Optionally, in the etching process for forming the second opening, the etching ratio of the first dielectric layer and the first etch stop layer is selected to be greater than 10:1.

[0026] Optionally, the method further includes: before forming the first conductive structure, forming a second dielectric structure on the surface of the source / drain structure and the surface of the substrate, wherein the surface of the second dielectric structure is higher than the surface of the gate structure.

[0027] Optionally, the method for forming the first conductive structure includes: after forming the second dielectric structure, etching the second dielectric structure until the surface of the source / drain structure is exposed to form a first opening in the second dielectric structure; and filling the first opening with a material of the first conductive structure to form the first conductive structure.

[0028] Optionally, the second dielectric structure includes: a lower second dielectric layer located on the sidewall surface of the gate structure, a second protective layer located on the top surface of the gate structure and the surface of the lower second dielectric layer, and an upper second dielectric layer located on the surface of the second protective layer.

[0029] Optionally, the material of the second protective layer includes silicon nitride.

[0030] Optionally, it also includes: before forming the first etch stop layer, oxidizing the top surface of the first conductive structure to form an oxide film on the top surface of the first conductive structure; after forming the oxide film and before forming the first etch stop layer, etching back the upper second dielectric layer until the upper second dielectric layer is removed.

[0031] Optionally, it also includes: before forming the second dielectric structure, forming a second etch stop layer on the surface of the source-drain structure, the second etch stop layer is also located on the side wall of the gate structure; before forming the first conductive structure, removing the second etch stop layer on the surface of the source-drain structure.

[0032] Optionally, the gate structure includes a gate and a gate spacer located on a sidewall surface of the gate.

[0033] Optionally, the base includes a substrate and a plurality of fin structures located on the substrate, and the gate structure spans the fin structures.

[0034] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0035] In the method for forming a semiconductor structure provided by the technical method of the present invention, a first etch stop layer is formed on the top surface of the first conductive structure and on the sidewalls of the first conductive structure that are higher than the top surface of the gate structure, and a first dielectric layer is formed on the top surface of the gate structure and on the surface of the first etch stop layer. Therefore, the first etch stop layer can separate the first conductive structure and the first dielectric layer located on the top surface of the gate structure. Furthermore, since the first etch stop layer and the first dielectric layer are formed separately, a first etch stop layer and a first dielectric layer made of different materials can be formed. That is, the material of the first dielectric layer is different from the material of the first etch stop layer. Consequently, when the first dielectric layer is subsequently etched, the first dielectric layer and the first etch stop layer can have different etching rates, thereby achieving a self-aligned etching process. On this basis, since the first conductive structure is protected by the first etch stop layer during the self-aligned etching process, the etching process has less impact on the first conductive structure, resulting in a high degree of consistency in the electrical characteristics of the same first conductive structure at various locations in the semiconductor structure, and a high degree of consistency in the electrical characteristics between the first conductive structures in various regions. This improves the stability of the electrical characteristics of the semiconductor structure, and improves the performance and reliability of the semiconductor structure. In summary, while achieving a self-aligned etching process, it is possible to improve the stability of the electrical characteristics of the semiconductor structure, and improve the performance and reliability of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figures 1 to 3 The present invention is a structural schematic diagram of each step of a method for forming a semiconductor structure;

[0037] Figures 4 to 14 1 is a schematic cross-sectional structural diagram of each step of a method for forming a semiconductor structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0038] As described in the background art, the performance and reliability of existing semiconductor structures still need to be improved.

[0039] The reasons why the performance and reliability of semiconductor structures still need to be improved are described in detail below with reference to the accompanying drawings.

[0040] Figures 1 to 3 The present invention is a structural schematic diagram of each step of a method for forming a semiconductor structure.

[0041] Please refer to Figure 1 , providing a substrate 100, wherein the substrate 100 includes a substrate (not shown) and a plurality of fin structures (not shown) located separately from each other on the substrate; forming a first dielectric layer (not shown) on the surface of the substrate 100, wherein the first dielectric layer covers a portion of the sidewall surface of the fin structure.

[0042] Please continue to refer to Figure 1 A second dielectric layer 110 is formed on the surface of the first dielectric layer. The second dielectric layer 110 has a plurality of gate openings (not shown) extending across the fin structure. The gate openings expose the surface and a portion of the sidewalls of the fin structure. A gate structure 120, a gate protection structure 130 located on the top surface of the gate structure 120, and spacers 140 located on the sidewalls of the gate structure 120 and the gate protection structure 130 are formed in the gate openings.

[0043] Please refer to Figure 2 A first conductive opening mask layer (not shown) is formed on the top surface of the gate protection structure 130, the top surface of the sidewall 140, and the surface of the second dielectric layer 110. The first conductive opening mask layer has a plurality of first conductive mask openings (not shown). The second dielectric layer 110 is etched using the first conductive opening mask layer as a mask until the surface of the substrate 100 is exposed to form first conductive openings (not shown). An initial conductive structure 150 is formed in the first conductive openings.

[0044] The material of the initial conductive structure 150 is cobalt. Therefore, due to the material properties of cobalt, the parasitic resistance of the conductive structure formed subsequently is relatively small.

[0045] Please refer to Figure 3 , the initial conductive structure 150 is etched back to form a first conductive structure 151, and a conductive protection structure opening (not shown) is formed in the second dielectric layer 110 and located on the first conductive structure 151; a conductive protection structure 160 is formed in the conductive protection structure opening.

[0046] Next, a second conductive opening mask layer (not shown) is formed on the surface of the conductive protection structure 160 and the surface of the second dielectric layer 110. The second conductive opening mask layer has a plurality of second conductive mask openings (not shown). The second conductive mask openings expose a portion of the conductive protection structure 160 and the top surface of the sidewall 140. Using the second conductive opening mask layer as a mask, a portion of the conductive protection structure 160 is etched until the top surface of the first conductive structure 151 is exposed, forming a second conductive opening (not shown) in the conductive protection structure 160 and the second dielectric layer 110. A second conductive structure (not shown) is formed in the second conductive opening, and the second conductive structure is electrically connected to the first conductive structure 151.

[0047] In the above embodiment, by etching back the initial conductive structure 150 to form a conductive protection structure opening, a conductive protection structure 160 having a critical dimension (CD) smaller than the limit dimension of existing photolithography processes can be formed. Furthermore, since the material of the conductive protection structure 160 is different from that of the sidewall spacer 140, a self-aligned etching process can be achieved during the formation of the second conductive opening by etching the conductive protection structure 160 and the sidewall spacer 140 at different rates.

[0048] Specifically, in a direction perpendicular to the extension direction of the gate structure 120, the width of the second conductive mask opening is greater than the width of the second conductive opening (the second conductive mask opening not only exposes the top surface of the conductive protection structure 160, but also partially exposes the top surface of the sidewall spacer 140). This increases the process window of the etching process for forming the second conductive opening and reduces the difficulty of the photolithography process. Furthermore, through the self-aligned etching process, a second conductive opening with a critical dimension smaller than the width of the second conductive mask opening can be formed.

[0049] However, while achieving the self-aligned etching process, on the one hand, due to the poor chemical stability of cobalt, when the initial conductive structure 150 is etched back, the chemical reaction in the etching process is active, and the thickness of the etching byproducts formed on the surface of each part of the initial conductive structure 150 is less uniform. Therefore, it is difficult to control the etching process of etching back the initial conductive structure 150, resulting in poor consistency between the conductive structures 151 in various regions of the formed semiconductor structure. For example, the surface roughness of the conductive structures 151 in various regions is inconsistent, and the height H of the conductive structures 151 in various regions (such as Figure 3On the other hand, due to the different projected shapes of the initial conductive structures 150 on the surface of the substrate 100, or the difference between the projected area of ​​the initial conductive structure 150 on the surface of the substrate 100 in each region and the total area of ​​the region, it will also make the etching process of etching back the initial conductive structure 150 more difficult to control, resulting in a height difference between different parts of the same conductive structure 151 in the formed semiconductor structure, and the consistency between the conductive structures 151 in each region is poor. In summary, in the semiconductor structure, the consistency of the electrical characteristics of the same conductive structure 151 at different locations is poor, and the consistency of the electrical characteristics between the conductive structures 151 in each region is also poor, making the electrical characteristics of the semiconductor structure unstable, and thus, the performance and reliability of the semiconductor structure are poor.

[0050] To solve the technical problem, an embodiment of the present invention provides a semiconductor structure and a method for forming the same. Since a first conductive structure is formed on the surface of the source-drain structure, the top surface of the first conductive structure is higher than the top surface of the gate structure, and a first etch stop layer is formed on the top surface of the first conductive structure and on the sidewalls of the first conductive structure higher than the top surface of the gate structure, and a first dielectric layer is formed on the top surface of the gate structure and on the surface of the first etch stop layer, the material of the first dielectric layer is different from the material of the first etch stop layer, thereby improving the performance and reliability of the formed semiconductor structure while realizing a self-aligned etching process.

[0051] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0052] Figures 4 to 14 1 is a schematic cross-sectional structural diagram of each step of a method for forming a semiconductor structure according to an embodiment of the present invention.

[0053] Please refer to Figure 4 , providing a substrate.

[0054] In this embodiment, the base includes a substrate 200 and a plurality of fin structures 201 separated from each other and located on the substrate 200 .

[0055] The substrate 200 is made of a semiconductor material.

[0056] In this embodiment, the substrate 200 is made of silicon.

[0057] In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multinary semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). Among them, the multinary semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0058] In other embodiments, the fin structure includes: a plurality of fin sacrificial layers arranged in a direction perpendicular to the substrate surface, and nanosheets located between adjacent fin sacrificial layers.

[0059] Next, a plurality of gate structures separated from each other are formed on the substrate, wherein the gate structure includes a gate and a gate spacer located on the sidewall of the gate, and a plurality of source and drain structures are formed in the substrate, wherein the source and drain structures are located on both sides of the gate structure. For the specific process of forming the gate structure and the source and drain structure, please refer to Figures 5 and 6 .

[0060] Please refer to Figure 5 , a plurality of separate dummy gate structures 209 are formed on the surface of the substrate; and gate spacers 210 are formed on the sidewalls of the dummy gate structures 209 .

[0061] In this embodiment, the material of the dummy gate structure 209 includes polysilicon.

[0062] In the subsequent process of forming the gate structure, the dummy gate structure 209 in this embodiment is used to define the pattern of the gate.

[0063] In other embodiments, the dummy gate structure is directly used as the gate.

[0064] In this embodiment, the method for forming the dummy gate structure 209 includes: forming a dummy gate material film (not shown) on the substrate covering the surface of the fin structure 201; patterning the dummy gate material film until the substrate surface is exposed to form a plurality of separate dummy gate structures 209 on the substrate, wherein the dummy gate structure 209 spans the fin structure 201, and the top surface of the dummy gate structure 209 is higher than the top surface of the fin structure 201.

[0065] The formation process of the dummy gate material film includes: an epitaxial growth process or a deposition process, etc. The deposition process is, for example, a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process, etc.

[0066] In this embodiment, in the subsequent process of forming the source-drain structure, the gate spacer 210 is used to define the formation position of the source-drain structure.

[0067] In this embodiment, the method for forming the gate sidewall 210 includes: depositing a sidewall material film (not shown) on the surface of the substrate and the surface of the dummy gate structure 209; using an anisotropic etching process to etch back the sidewall material film until the sidewall material film on the surface of the substrate and the top surface of the dummy gate structure 209 is removed, thereby forming a gate sidewall 210 on the sidewall of the dummy gate structure 209.

[0068] In this embodiment, the gate spacer 210 is made of a low-K dielectric material (K is less than 3.9) or a combination of multiple low-K dielectric materials, such as SiOC, SiOCN, and SiBCN.

[0069] In this embodiment, before forming the pseudo gate material film, a substrate isolation dielectric layer (not shown) is formed on the surface of the substrate, and the substrate isolation dielectric layer also covers a portion of the side wall surface of the fin structure 201, so that the adjacent fin structures 201 and the semiconductor device and the substrate 200 can be electrically insulated through the substrate isolation dielectric layer.

[0070] Please continue to refer to Figure 5 After forming the gate spacer 210, a plurality of source and drain structures 202 are formed in the substrate.

[0071] Specifically, the method for forming the source-drain structures 202 includes: after forming the gate sidewalls 210, forming source-drain openings (not shown) in the fin structure 201 on both sides of the dummy gate structure 209; and forming the source-drain structures 202 in the source-drain openings using an epitaxial growth process.

[0072] Please refer to Figure 6 Before subsequently forming the first conductive structure, a lower second dielectric layer 221 is formed on the surface of the source / drain structure 202 and the surface of the substrate. The lower second dielectric layer 221 is located on the sidewall surface of the gate spacer 210 .

[0073] The lower second dielectric layer 221 provides support for the subsequent formation of a gate and a first conductive structure.

[0074] In this embodiment, the material of the lower second dielectric layer 221 is silicon oxide.

[0075] In other embodiments, the material of the lower second dielectric layer includes at least one of SiOCH, SiOH, and SiCN.

[0076] In this embodiment, the method for forming the lower second dielectric layer 221 includes: forming a lower second dielectric material layer (not shown) on the surface of the dummy gate structure 209 and the substrate, wherein the surface of the lower second dielectric material layer is higher than the top surface of the dummy gate structure 209; and flattening the lower second dielectric material layer until the top surface of the dummy gate structure 209 is exposed.

[0077] The formation process of the lower second dielectric material layer includes: a spin coating process or a deposition process, and the deposition process is, for example, a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

[0078] The process of planarizing the lower second dielectric material layer includes an etch-back process or a chemical mechanical polishing process.

[0079] In this embodiment, before forming the second dielectric structure, a second etch stop layer 212 is formed on the surface of the source / drain structure 202 . The second etch stop layer 212 is also located on the sidewalls of the gate spacer 210 .

[0080] Specifically, the method for forming the second etch stop layer 212 includes: before forming the lower second dielectric material layer, forming a second etch stop layer material film (not shown) on the surface of the substrate, the surface of the source and drain structure 202, the surface of the gate sidewall 210, and the surface of the dummy gate structure 209; in the process of planarizing the lower second dielectric material layer, the second etch stop layer material film is also planarized until the top surface of the dummy gate structure 209 and the top surface of the gate sidewall 210 are exposed to form the second etch stop layer 212.

[0081] The second etch stop layer 212 can protect the gate sidewall 210 and the source-drain structure 202 during the subsequent etching process for forming the first opening, thereby reducing damage to the surface of the gate sidewall 210 and the source-drain structure 202 caused by the etching process and improving the performance of the semiconductor structure.

[0082] Please continue to refer to Figure 6 After forming the lower second dielectric layer 221 and the second etch stop layer 212, a gate structure is formed, the gate structure including a gate 211 and a gate spacer 210 located on the side wall of the gate 211, and the second dielectric layer 221 is located on the side wall of the gate structure.

[0083] The gate structure spans the fin structure 201 , and the source / drain structure 202 is located in a base of the gate structure.

[0084] Specifically, after forming the lower second dielectric layer 221 and the second etch stop layer 212, the dummy gate structure 209 is removed, and a plurality of gate openings (not shown) are formed in the lower second dielectric layer 221; the gate material is filled in the gate openings to form a plurality of gates 211 located in the lower second dielectric layer 221 on the substrate, thereby forming the gate structure.

[0085] In this embodiment, the gate 211 includes: a gate dielectric layer (not shown) located on the inner wall of the gate opening, a work function layer (not shown) located on the surface of the gate dielectric layer, and a gate electrode layer (not shown) located on the surface of the work function layer.

[0086] In this embodiment, the method for forming the gate 211 includes: forming a gate dielectric material layer (not shown) on the surface of the lower second dielectric layer 221 and the inner wall of the gate opening; forming a work function material layer (not shown) on the surface of the gate dielectric material layer; forming a gate electrode material layer (not shown) on the surface of the work function material layer, and the gate electrode material layer fills the gate opening; flattening the gate electrode material layer, the work function material layer and the gate dielectric material layer until the surface of the lower second dielectric layer 221 is exposed to form the gate 211.

[0087] The gate dielectric layer comprises a high-K dielectric material (K greater than 3.9), including hafnium dioxide, hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, or aluminum oxide.

[0088] The material of the gate electrode layer includes a metal material, for example, one or a combination of tungsten, copper, aluminum, titanium and tantalum.

[0089] The material of the work function layer includes titanium nitride, tantalum nitride or titanium aluminum.

[0090] Please continue to refer to Figure 6 After forming the gate 211, a second protective layer 222 is formed on the top surface of the gate structure and the surface of the lower second dielectric layer 211; an upper second dielectric layer 223 is formed on the surface of the second protective layer 222 to form a second dielectric structure 220, and the surface of the second dielectric structure is higher than the surface of the gate structure.

[0091] Specifically, the second dielectric structure 220 includes: a lower second dielectric layer 221 located on the sidewall surface of the gate structure, a second protective layer 222 located on the top surface of the gate structure and the surface of the lower second dielectric layer 221, and an upper second dielectric layer 223 located on the surface of the second protective layer 222.

[0092] On the one hand, since the second protective layer 222 and the upper second dielectric layer 223 are formed separately, the second protective layer 222 and the upper second dielectric layer 223 can be made of different materials. Therefore, in the subsequent etching process of the upper second dielectric layer 223 and the lower second dielectric layer 221 to form the first opening, the second protective layer 222 can serve as an etch stop layer between the upper second dielectric layer 223 and the lower second dielectric layer 221, thereby reducing the etching load between various regions of the semiconductor structure. This improves the consistency of the first opening depth in various regions, reduces the risk of over-etching or insufficient etching depth during the formation of the first opening, and improves the reliability of the semiconductor structure.

[0093] Similarly, in the subsequent etching process for forming the second opening, the second protective layer 222 located on the top surface of the gate structure can also serve as an etching stop layer to reduce the etching load between the various regions of the semiconductor structure, thereby improving the consistency of the second opening depth in each region, reducing the risk of over-etching or insufficient etching depth in the process of forming the second opening, and improving the reliability of the semiconductor structure.

[0094] On the other hand, the second protective layer 222 located on the top surface of the gate structure can also protect the gate structure, reducing the damage to the gate structure caused by the subsequent etching process of forming the first opening, the second opening and the first etching barrier layer, thereby improving the performance of the semiconductor structure.

[0095] In this embodiment, the material of the second protection layer 222 includes silicon nitride.

[0096] In this embodiment, the upper second dielectric layer 223, on the one hand, provides support for the subsequent formation of a first conductive structure whose top surface is higher than the gate structure. On the other hand, after the first conductive structure is formed, it can protect the sidewalls of the first conductive structure, reducing the exposure time of the first conductive structure before the first etch stop layer is formed, thereby reducing oxidation of the sidewalls of the first conductive structure. Furthermore, during the subsequent formation of the oxide film on the top surface of the first conductive structure, it can serve as a barrier layer to limit the location of the oxide film, that is, to ensure that the oxide film is formed only on the top surface of the first conductive structure.

[0097] In this embodiment, the material of the upper second dielectric layer 223 is silicon oxide.

[0098] In other embodiments, the material of the upper second dielectric layer includes at least one of SiOCH, SiOH, and SiCN.

[0099] Next, please refer to Figure 7A first conductive structure 230 is formed on the surface of the source-drain structure 202 , and a top surface of the first conductive structure 230 is higher than a top surface of the gate structure.

[0100] Because the top surface of the first conductive structure 230 is higher than the top surface of the gate structure, the depth of the subsequently formed third opening is relatively small and does not easily reach the depth of the gate structure top surface. As a result, the risk of short circuit between the third conductive structure subsequently formed on the top surface of the first conductive structure 230 and the gate structure is relatively low. In addition, during the etching process for forming the third opening, there is no need to use a self-aligned etching process. This reduces the difficulty of the semiconductor structure formation process.

[0101] In this embodiment, the method for forming the first conductive structure 230 includes: after forming the second dielectric structure, etching the second dielectric structure until the surface of the source-drain structure 202 is exposed to form a first opening (not shown) in the second dielectric structure; and filling the first opening with a material of the first conductive structure 230 to form the first conductive structure 230.

[0102] Specifically, a first opening mask layer (not shown) is formed on the top surface of the second dielectric structure, and the surface of the first opening mask layer exposes the top surface of the second dielectric structure on the source-drain structure 202; the second dielectric structure is etched using the first opening mask layer as a mask until the surface of the source-drain structure 202 is exposed, thereby forming the first opening; after the first opening is formed, a first conductive structure material layer (not shown) is formed within the first opening and on the top surface of the second dielectric structure; and the first conductive structure material layer is planarized until the top surface of the second dielectric structure is exposed.

[0103] The process of etching the second dielectric structure includes a dry etching process or a wet etching process.

[0104] The process of forming the first conductive structure material layer includes: deposition process, electroplating process or metal chemical plating process, etc. The deposition process is, for example, physical vapor deposition process or chemical vapor deposition process, etc. The metal chemical plating process is, for example, selective metal chemical plating process, etc.

[0105] The process of planarizing the first conductive structure material includes a dry etching process, a wet etching process, or a chemical mechanical polishing process.

[0106] In this embodiment, the material of the first conductive structure 230 includes cobalt.

[0107] In other embodiments, the material of the first conductive structure includes tungsten or ruthenium.

[0108] In this embodiment, before filling the first opening with the material of the first conductive structure 230 to form the first conductive structure 230 , the second etch stop layer 212 on the surface of the source / drain structure 202 is removed.

[0109] Specifically, during the etching of the second dielectric structure, the exposed second etch stop layer 212 is also etched to remove the second etch stop layer 212 on the surface of the source / drain structure 202 , so that the surface of the source / drain structure 202 can be exposed.

[0110] In this embodiment, the first opening mask layer is removed simultaneously during the planarization of the first conductive structure material layer. Thus, during the planarization of the first conductive structure material layer, the first opening mask layer can protect the second dielectric structure on the gate structure 211, thereby reducing surface damage to the second dielectric structure on the gate structure 211 caused by the planarization process.

[0111] In other embodiments, before filling the first conductive structure with material, the first opening mask layer is removed.

[0112] In this embodiment, after forming the first conductive structure 230 and before subsequently forming the first etch stop layer, the top surface of the first conductive structure 230 is oxidized to form an oxide film 231 on the top surface of the first conductive structure 230 .

[0113] In this embodiment, the material of the oxide film 231 includes cobalt oxide.

[0114] The oxide film 231 can protect the top surface of the first conductive structure 230 to prevent the top surface of the first conductive structure 230 from being exposed and oxidized before the subsequent formation of the first etch stop layer, thereby improving the performance and reliability of the semiconductor structure.

[0115] In this embodiment, before the first opening is filled with the material of the first conductive structure 230, a buffer layer (not shown) is formed on the sidewall surface of the first opening. Thus, the buffer layer can reduce the outward diffusion of elements in the material of the first conductive structure 230, thereby improving the performance of the semiconductor structure.

[0116] Please refer to Figure 8 After the oxide film 231 is formed, the upper second dielectric layer 223 is etched back until the upper second dielectric layer 223 is removed.

[0117] By removing the upper second dielectric layer 223 , space can be provided for the subsequent formation of the first etching stop layer.

[0118] In this embodiment, the process of etching back the upper second dielectric layer 223 includes a wet etching process.

[0119] In other embodiments, the process of etching back the upper second dielectric layer includes a dry etching process.

[0120] Next, after removing the upper second dielectric layer 223, a first etch stop layer is formed on the top surface of the first conductive structure 230 and on the sidewall of the first conductive structure 230 that is higher than the top surface of the gate structure. For details on the process of forming the first etch stop layer, please refer to Figures 9 to 11 .

[0121] Please refer to Figure 9 An initial first etch stop structure 240 is formed on the top surface of the gate structure, the top surface of the first conductive structure 230, and the sidewall of the first conductive structure 230 higher than the top surface of the gate structure, and the initial first etch stop structure 240 includes an initial first etch stop layer 241.

[0122] The initial first etch stop layer 241 provides material for subsequently forming a first etch stop layer.

[0123] In this embodiment, the initial first etch stop structure 240 further includes a first protection layer 242 , and the initial first etch stop layer 241 is located on the surface of the first protection layer 242 .

[0124] Specifically, a deposition process is used to form a first protective layer 242 on the top surface of the gate structure, the top surface of the first conductive structure 230, and the side wall of the first conductive structure 230 higher than the top surface of the gate structure; after the first protective layer 242 is formed, a deposition process is used to form an initial first etching stopper layer 241 on the surface of the first protective layer 242.

[0125] On the one hand, the first protective layer 242 can protect the surface of the first conductive structure 230 during the deposition process of forming the initial first etch barrier layer 241 and the subsequent etching process of the initial first etch barrier layer 241, thereby reducing the impact of the deposition process and the etching process on the first conductive structure 230 and improving the performance and reliability of the semiconductor structure.

[0126] On the other hand, since the first protective layer 242 and the initial first etch stop layer 241 are formed separately, the first protective layer 242 and the initial first etch stop layer 241 can be formed with different materials. During the subsequent etching of the initial first etch stop layer 241 to form the first etch stop layer, the first protective layer 242 can serve as an etch stop layer to protect the top surface of the gate structure, reduce damage to the gate structure caused by the etching process, and thus improve the performance and reliability of the semiconductor structure.

[0127] The deposition process for forming the first protection layer 242 includes an atomic layer deposition process.

[0128] The deposition process for forming the initial first etch stop layer 241 includes a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

[0129] In this embodiment, the thickness of the first protection layer 242 ranges from 1 nm to 8 nm.

[0130] If the thickness of the first protective layer 242 is too large, it increases the difficulty of etching to remove it, making it difficult to completely remove it before the subsequent formation of the second conductive structure, resulting in increased contact resistance between the second conductive structure and the gate structure, or forming a short circuit defect, which deteriorates the performance and reliability of the semiconductor structure. If the thickness of the first protective layer 242 is too small, it cannot provide reliable protection for the gate structure and the surface of the first conductive structure 230 during the formation of the initial first etch stop layer 241 and the subsequent etching of the initial first etch stop layer 241, making the gate structure and the first conductive structure 230 easily affected by the process of forming the initial first etch stop layer 241 and the subsequent etching of the initial first etch stop layer 241, and is not conducive to improving the performance of the semiconductor structure. Therefore, selecting an appropriate thickness range for the first protective layer 242, that is, when the thickness range of the first protective layer 242 is 1 nanometer to 8 nanometers, it can provide reliable protection for the gate structure and the first conductive structure 230 while making it easier to completely remove the first protective layer 242 on the gate structure before the subsequent formation of the second conductive structure, thereby improving the performance and reliability of the semiconductor structure.

[0131] More preferably, the thickness of the first protection layer 242 is in a range of 2 nm to 5 nm.

[0132] In this embodiment, the material of the first protection layer 242 includes silicon nitride.

[0133] In this embodiment, the material of the initial first etch stop layer 241 includes silicon oxycarbide. Accordingly, the material of the first etch stop layer includes silicon oxycarbide.

[0134] In other embodiments, the material of the initial first etch stop layer includes silicon carbide or carbon-doped silicon nitride. Accordingly, the material of the first etch stop layer includes silicon carbide or carbon-doped silicon nitride.

[0135] In other embodiments, the first protection layer is not formed.

[0136] Please refer to Figure 10An etching byproduct layer 250 is formed on the top surface 2411 of the initial first etch stop layer 241 , and the etching byproduct layer 250 exposes the initial first etch stop layer 241 on the top surface of the gate structure.

[0137] When the initial first etch stop layer 241 on the top surface of the gate structure is subsequently removed to form a first etch stop layer, the etch byproduct layer 250 is used as a mask layer in the etching process.

[0138] In this embodiment, the process of forming the etching byproduct layer 250 includes a plasma etching process.

[0139] In this embodiment, during the plasma etching process, etching by-products are formed on the top surface 2411 of the initial first etch barrier layer 241. At the same time, the etching by-products formed on the side wall surface of the initial first etch barrier layer 241 and the top surface of the gate structure are etched and removed, thereby achieving the formation of the etching by-product layer 250 on the top surface 2411 of the initial first etch barrier layer 241.

[0140] Specifically, in this embodiment, the plasma etching process is a process of dynamic balance between the material forming the etching by-product 250 and the material etching the etching by-product 250 .

[0141] In this embodiment, the gases used in the plasma etching process include methane, oxygen and argon.

[0142] Specifically, in the plasma etching process, when methane, oxygen and argon are introduced, etching by-products are formed on the top surface of the initial first etch barrier layer 241, the side wall surface of the initial first etch barrier layer 241 and the top surface 2411 of the gate structure; when argon is introduced, the etching by-products formed on the side wall surface of the initial first etch barrier layer 241 and the top surface of the gate structure are etched and removed.

[0143] In this embodiment, the process parameters of the plasma etching process further include: a high-frequency radio frequency power range of 100 watts to 1000 watts; and a low-frequency radio frequency power range of 0 watts to 500 watts.

[0144] Preferably, the high frequency radio frequency power ranges from 100 watts to 300 watts, and the low frequency radio frequency power ranges from 0 watts to 200 watts.

[0145] Specifically, when methane, oxygen, and argon are introduced, by controlling the high-frequency radio frequency power within a range of 100 watts to 1000 watts, the material forming the etching byproducts on the top surface of the initial first etch stop layer 241, the sidewalls of the initial first etch stop layer 241, and the top surface 2411 of the gate structure can be more effectively removed. When argon is introduced, by controlling the high-frequency radio frequency power within a range of 100 watts to 1000 watts while also controlling the low-frequency radio frequency power within a range of 0 watts to 500 watts, the etching byproducts formed on the sidewalls of the initial first etch stop layer 241 and the top surface of the gate structure can be more effectively etched and removed. Thus, while forming the etching byproduct layer 250, the etching byproducts formed on the sidewalls of the initial first etch stop layer 241 and the top surface of the gate structure can be more accurately etched, thereby reducing the residue of etching byproducts on the sidewalls of the initial first etch stop layer 241 and the top surface of the gate structure.

[0146] Please refer to Figure 11 , using the etching by-product layer 250 as a mask, the initial first etch stop layer 241 is etched until the initial first etch stop layer 241 on the top surface of the gate structure is removed, thereby forming a first etch stop layer 243 on the top surface of the first conductive structure 230 and on the sidewalls of the first conductive structure 230 higher than the top surface of the gate structure.

[0147] In this embodiment, during the process of etching the initial first etch stop layer 241, the etching selectivity ratio between the material of the initial first etch stop layer 241 and the material of the first protective layer 242 is greater than 8:1. Therefore, due to the large etching selectivity, the loss of the first protective layer 242 is reduced during the etching process of the initial first etch stop layer 241, thereby enabling the first protective layer 242 to protect the gate structure and the first conductive structure 230.

[0148] In this embodiment, the process of etching the initial first etch stop layer 241 includes a dry etching process or a wet etching process.

[0149] In this embodiment, after the first etch stop layer 243 is formed, the etch byproduct layer 250 is removed.

[0150] In this embodiment, the process of removing the etching byproduct layer 250 includes an ashing process.

[0151] Please refer to Figure 12 A first dielectric layer 260 is formed on the top surface of the gate structure and the surface of the first etch stop layer 243 . The material of the first dielectric layer 260 is different from that of the first etch stop layer 243 .

[0152] Because a first etch stop layer 243 is formed on the top surface of the first conductive structure 230 and on the sidewalls of the first conductive structure 230 that are higher than the top surface of the gate structure, and because a first dielectric layer 260 is formed on the top surface of the gate structure and on the surface of the first etch stop layer 243, the first etch stop layer 243 can separate the first conductive structure 230 from the first dielectric layer 260 located on the top surface of the gate structure. Furthermore, because the first etch stop layer 243 and the first dielectric layer 260 are formed separately, the first etch stop layer 243 and the first dielectric layer 260 can be formed of different materials. That is, the material of the first dielectric layer 260 is different from that of the first etch stop layer 243. Consequently, when the first dielectric layer 260 is subsequently etched, the first dielectric layer 260 and the first etch stop layer 243 can have different etch rates, achieving a self-aligned etching process.

[0153] On this basis, since the first conductive structure 230 is protected by the first etch stop layer 243 during the self-aligned etching process, the etching process has little impact on the first conductive structure 230, resulting in a high consistency in the electrical characteristics of the same first conductive structure 230 at various locations in the semiconductor structure, and a high consistency in the electrical characteristics between the first conductive structures 230 in various regions, thereby improving the stability of the electrical characteristics of the semiconductor structure and improving the performance and reliability of the semiconductor structure. In summary, while achieving a self-aligned etching process, it is possible to improve the stability of the electrical characteristics of the semiconductor structure and improve the performance and reliability of the semiconductor structure.

[0154] Specifically, the first dielectric layer 260 provides support for the subsequent formation of the second conductive structure and the third conductive structure.

[0155] In this embodiment, the material of the first dielectric layer 260 includes silicon oxide.

[0156] The first dielectric layer 260 is formed by a process including a spin coating process or a deposition process. The deposition process is, for example, a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

[0157] Next, after forming the first dielectric layer 260, a second conductive structure is formed on the top surface of the gate structure, and the second conductive structure is also located in the first dielectric layer 260. For the specific process of forming the second conductive structure, please refer to Figures 13 and 14 .

[0158] Please refer to Figure 13A first mask structure 270 is formed on the first dielectric layer 260. The first mask structure 270 has a first mask opening 271. The width of the first mask opening 271 is greater than the width of the gate structure. Using the first mask structure 270 and the first etch stop layer 243 as masks, the first dielectric layer 260 is etched until the top surface of the gate structure is exposed, thereby forming a second opening 261 in the first dielectric layer 260.

[0159] The second opening 261 provides space for subsequently forming a second conductive structure.

[0160] In this embodiment, during the etching process for forming the second opening 261, the etching selectivity ratio between the first dielectric layer 260 and the first etch stop layer 243 is greater than 10:1. This higher etching selectivity improves the blocking capability of the first etch stop layer 243 during the etching of the first dielectric layer 260, thereby improving the precision of the formed second opening 261 and further enhancing the performance and reliability of the semiconductor structure.

[0161] In this embodiment, the process of etching the first dielectric layer 260 includes a dry etching process or a wet etching process.

[0162] In this embodiment, during the etching process of forming the second opening 261 , the first protection layer 242 and the second protection layer 222 on the top surface of the gate 211 are also etched and removed, so that the top surface of the gate 211 is exposed.

[0163] In this embodiment, after the second opening 261 is formed, the first mask structure 270 is removed.

[0164] In this embodiment, before subsequently filling the second conductive structure with material, the first dielectric layer 260 is further etched until a portion of the top surface of the first conductive structure 230 is exposed to form a third opening (not shown).

[0165] The third opening provides space for subsequently forming a third conductive structure.

[0166] Similarly, in this embodiment, during the etching process of forming the third opening, the first etch stop layer 243, the first protective layer 242 and the oxide film 231 exposed on the first conductive structure 230 are also etched and removed at the same time to expose the top surface of the first conductive structure 230.

[0167] Specifically, the method for forming the third opening includes: forming a second mask structure (not shown) on the surface of the first dielectric layer 260, wherein the second mask structure exposes a portion of the surface of the first dielectric layer 260 on the first conductive structure 230; using the second mask structure as a mask, etching the first dielectric layer 260 until the top surface of the first conductive structure 230 is exposed to form the third opening.

[0168] Please refer to Figure 14 , a second conductive structure 280 is formed in the second opening 261 .

[0169] In this embodiment, the material of the second conductive structure 280 includes cobalt.

[0170] In other embodiments, the material of the second conductive structure includes tungsten or ruthenium.

[0171] Specifically, the material of the second conductive structure 280 is filled into the second opening 261 to form the second conductive structure 280 .

[0172] In this embodiment, while the second opening 261 is filled with the material of the second conductive structure 280 , the third opening is also filled with the material of the third conductive structure (not shown) to form the third conductive structure on the top surface of the first conductive structure 230 .

[0173] Specifically, the method for forming the second conductive structure 280 and the third conductive structure includes: forming a conductive structure material layer (not shown) in the second opening 261, in the third opening, and on the surface of the first dielectric layer 260; planarizing the conductive structure material layer until the surface of the first dielectric layer 260 is exposed, so as to form the second conductive structure 280 in the second opening 261 and the third conductive structure in the third opening.

[0174] Likewise, in this embodiment, the material of the third conductive structure includes cobalt.

[0175] In other embodiments, the material of the third conductive structure includes tungsten or ruthenium.

[0176] It should be noted that in other embodiments, the second conductive structure material and the third conductive structure material may be filled separately. The order of filling the second conductive structure material and the third conductive structure material has no effect on the effect of this embodiment.

[0177] Accordingly, an embodiment of the present invention further provides a semiconductor structure formed by the above-mentioned formation method, please continue to refer to Figure 14, including: a substrate; a plurality of gate structures that are separate from each other and located on the substrate; a plurality of source-drain structures 202 located in the substrate on both sides of the gate structures; a first conductive structure 230 located on the surface of the source-drain structure 202, wherein the top surface of the first conductive structure 230 is higher than the top surface of the gate structure; a first etch stop layer 243 located on the top surface of the first conductive structure 230, wherein the first etch stop layer 243 is also located on the sidewall of the first conductive structure 230 that is higher than the top surface of the gate structure; a first dielectric layer 260 located on the top surface of the gate structure and on the surface of the first etch stop layer 243, wherein the material of the first dielectric layer 260 is different from the material of the first etch stop layer 243.

[0178] In this embodiment, the material of the first dielectric layer 260 includes silicon oxide.

[0179] In this embodiment, the material of the first etch stop layer 243 includes silicon oxycarbide.

[0180] In other embodiments, the material of the first etch stop layer includes silicon carbide or carbon-doped silicon nitride.

[0181] In this embodiment, the semiconductor structure further includes a first protection layer 242 located on the top surface of the gate structure and between the first etch stop layer 243 and the first conductive structure 230 .

[0182] In this embodiment, the thickness of the first protective layer 242 ranges from 1 nm to 8 nm, and more preferably, the thickness of the first protective layer 242 ranges from 2 nm to 5 nm.

[0183] In this embodiment, the material of the first protection layer 242 includes silicon nitride.

[0184] In other embodiments, the semiconductor structure does not have a first protection layer.

[0185] In this embodiment, the base includes a substrate 200 and a plurality of fin structures 201 separated from each other and located on the substrate 200 . The gate structure spans across the fin structures 201 .

[0186] The substrate 200 is made of a semiconductor material.

[0187] In this embodiment, the substrate 200 is made of silicon.

[0188] In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multinary semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). Among them, the multinary semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0189] In this embodiment, the gate structure includes a gate 211 and a gate spacer 210 located on a sidewall surface of the gate 211 .

[0190] In this embodiment, the gate 211 includes: a gate dielectric layer (not shown) located on the inner wall of the gate opening, a work function layer (not shown) located on the surface of the gate dielectric layer, and a gate electrode layer (not shown) located on the surface of the work function layer.

[0191] The gate dielectric layer comprises a high-K dielectric material (K greater than 3.9), including hafnium dioxide, hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, or aluminum oxide.

[0192] The material of the gate electrode layer includes a metal material, for example, one or a combination of tungsten, copper, aluminum, titanium and tantalum.

[0193] The material of the work function layer includes titanium nitride, tantalum nitride or titanium aluminum.

[0194] In other embodiments, the gate is made of polysilicon.

[0195] In this embodiment, the gate spacer 210 is made of a low-K dielectric material (K is less than 3.9) or a combination of multiple low-K dielectric materials, such as SiOC, SiOCN, and SiBCN.

[0196] In this embodiment, the material of the first conductive structure 230 includes cobalt.

[0197] In other embodiments, the material of the first conductive structure includes tungsten or ruthenium.

[0198] In this embodiment, the semiconductor structure further includes a second etch stop layer 212 located between the gate spacer 210 and the sidewall of the first conductive structure 230 .

[0199] In this embodiment, the semiconductor structure further includes a second protection layer 222 located on the top surface of the gate structure.

[0200] In this embodiment, the material of the second protection layer 222 includes silicon nitride.

[0201] In this embodiment, the semiconductor structure further includes an oxide film 231 located on the top surface of the first conductive structure 230 .

[0202] In this embodiment, the material of the oxide film 231 includes cobalt oxide.

[0203] In this embodiment, the semiconductor structure further includes a buffer layer (not shown) located on the sidewall surface of the first conductive structure 230 .

[0204] In this embodiment, the semiconductor structure further includes: a second opening 261 (eg, Figure 13 ), and the second conductive structure 280 is located in the second opening 261 , the bottom of the second opening 261 exposes the top surface of the gate structure. Specifically, the bottom of the second opening 261 exposes the top surface of the gate 211.

[0205] In this embodiment, the material of the second conductive structure 280 includes cobalt.

[0206] In other embodiments, the material of the second conductive structure includes tungsten or ruthenium.

[0207] In this embodiment, the semiconductor structure further includes: a third opening (not shown) located in the first dielectric layer 260 , and a third conductive structure (not shown) located in the third opening. The bottom of the third opening exposes the top surface of the first conductive structure 230 .

[0208] In this embodiment, the material of the third conductive structure includes cobalt.

[0209] In other embodiments, the material of the third conductive structure includes tungsten or ruthenium.

[0210] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that include: substrate; a plurality of gate structures separated from each other and located on the substrate; a plurality of source and drain structures located in the substrate on both sides of the gate structure; a first conductive structure located on the surface of the source / drain structure, wherein the top surface of the first conductive structure is higher than the top surface of the gate structure; a first etch stop layer located on a top surface of the first conductive structure, wherein the first etch stop layer is also located on a sidewall of the first conductive structure that is higher than a top surface of the gate structure; a first dielectric layer located on the top surface of the gate structure and on the surface of the first etch stop layer, wherein the material of the first dielectric layer is different from that of the first etch stop layer; a first protective layer located on the top surface of the gate structure and between the first etch stop layer and the first conductive structure, wherein the first etch stop layer is located on the surface of the first protective layer; The first etch stop layer exposes a top surface position of the gate corresponding to the first protection layer.

2. The semiconductor structure according to claim 1, wherein Also includes: A second opening is located in the first dielectric layer, and a second conductive structure is located in the second opening, wherein the bottom of the second opening exposes the top surface of the gate structure.

3. The semiconductor structure according to claim 1, wherein: The material of the first etch stop layer includes silicon oxycarbide, silicon carbide or carbon-doped silicon nitride.

4. The semiconductor structure according to claim 1, wherein: Also includes: A second protection layer is located on the top surface of the gate structure.

5. The semiconductor structure according to claim 1, wherein Also includes: A second etch stop layer is located between the gate structure and the sidewall of the first conductive structure.

6. The semiconductor structure according to claim 1, wherein Also includes: An oxide film is located on the top surface of the first conductive structure.

7. The semiconductor structure according to claim 1, wherein: The gate structure includes a gate and a gate spacer located on a sidewall surface of the gate.

8. The semiconductor structure according to claim 1, wherein: The base includes a substrate and a plurality of fin structures located on the substrate, and the gate structure spans the fin structures.

9. The semiconductor structure according to claim 8, wherein: The fin structure includes: a plurality of fin sacrificial layers arranged in a direction perpendicular to a substrate surface, and nanosheets located between adjacent fin sacrificial layers.

10. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; forming a plurality of mutually separated gate structures on the substrate; forming a source-drain structure in the substrate, wherein the source-drain structure is also located on both sides of the gate structure; forming a first conductive structure on the surface of the source-drain structure, wherein the top surface of the first conductive structure is higher than the top surface of the gate structure; forming a first etch stop layer on a top surface of the first conductive structure and on a sidewall of the first conductive structure that is higher than a top surface of the gate structure; forming a first dielectric layer on the top surface of the gate structure and the surface of the first etch stop layer, wherein the material of the first dielectric layer is different from the material of the first etch stop layer; The method for forming the first etch barrier layer includes: forming an initial first etch barrier structure on the top surface of the gate structure, the top surface of the first conductive structure, and the side wall of the first conductive structure higher than the top surface of the gate structure, the initial first etch barrier structure including an initial first etch barrier layer; forming an etch by-product layer on the top surface of the initial first etch barrier layer, the etch by-product layer exposing the initial first etch barrier layer on the top surface of the gate structure; etching the initial first etch barrier layer using the etch by-product layer as a mask until the initial first etch barrier layer on the top surface of the gate structure is removed.

11. The method for forming a semiconductor structure according to claim 10, wherein: The process of forming the etching byproduct layer includes a plasma etching process.

12. The method for forming a semiconductor structure according to claim 11, wherein: The gases used in the plasma etching process include methane, oxygen and argon.

13. The method for forming a semiconductor structure according to claim 12, wherein: The process parameters of the plasma etching process also include: a high-frequency radio frequency power range of 100 watts to 1000 watts; and a low-frequency radio frequency power range of 0 watts to 500 watts.

14. The method for forming a semiconductor structure according to claim 10, wherein: The initial first etch stop structure further includes a first protection layer, and the initial first etch stop layer is located on the surface of the first protection layer.

15. The method for forming a semiconductor structure according to claim 14, wherein: The material of the first protection layer includes silicon nitride.

16. The method for forming a semiconductor structure according to claim 10, wherein: The material of the first etch stop layer includes silicon oxycarbide, silicon carbide or carbon-doped silicon nitride.

17. The method for forming a semiconductor structure according to claim 10, wherein: Also includes: After forming the first dielectric layer, a second conductive structure is formed on the top surface of the gate structure, and the second conductive structure is also located in the first dielectric layer.

18. The method for forming a semiconductor structure according to claim 17, wherein: The method for forming the second conductive structure includes: forming a first mask structure on the first dielectric layer, wherein the first mask structure has a first mask opening, and the width of the first mask opening is greater than the width of the gate structure; using the first mask structure and the first etch stop layer as masks, etching the first dielectric layer until the top surface of the gate structure is exposed to form a second opening in the first dielectric layer; and filling the second opening with a material of the second conductive structure to form the second conductive structure.

19. The method for forming a semiconductor structure according to claim 18, wherein: In the etching process for forming the second opening, an etching selectivity ratio of the first dielectric layer to the first etch stop layer is greater than 10:

1.

20. The method for forming a semiconductor structure according to claim 10, wherein: Also includes: Before forming the first conductive structure, a second dielectric structure is formed on the surface of the source / drain structure and the surface of the substrate, and the surface of the second dielectric structure is higher than the surface of the gate structure.

21. The method for forming a semiconductor structure according to claim 20, wherein: The method for forming the first conductive structure includes: after forming the second dielectric structure, etching the second dielectric structure until the surface of the source / drain structure is exposed to form a first opening in the second dielectric structure; and filling the first opening with a material of the first conductive structure to form the first conductive structure.

22. The method for forming a semiconductor structure according to claim 20, wherein: The second dielectric structure includes: a lower second dielectric layer located on the sidewall surface of the gate structure, a second protection layer located on the top surface of the gate structure and the surface of the lower second dielectric layer, and an upper second dielectric layer located on the surface of the second protection layer.

23. The method for forming a semiconductor structure according to claim 22, wherein: The material of the second protection layer includes silicon nitride.

24. The method for forming a semiconductor structure according to claim 22, wherein: Also includes: Before forming the first etch stop layer, performing oxidation treatment on the top surface of the first conductive structure to form an oxide film on the top surface of the first conductive structure; After forming the oxide film and before forming the first etch stop layer, the upper second dielectric layer is etched back until the upper second dielectric layer is removed.

25. The method for forming a semiconductor structure according to claim 20, wherein: Also includes: Before forming the second dielectric structure, forming a second etch stop layer on the surface of the source / drain structure, wherein the second etch stop layer is also located on the sidewall of the gate structure; The second etch stop layer on the surface of the source / drain structure is removed before forming the first conductive structure.

26. The method for forming a semiconductor structure according to claim 10, wherein: The gate structure includes a gate and a gate spacer located on a sidewall surface of the gate.

27. The method for forming a semiconductor structure according to claim 10, wherein: The base includes a substrate and a plurality of fin structures located on the substrate, and the gate structure spans the fin structures.

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