Semiconductor structure with trench junction barrier Schottky diode

Abstract

The present invention provides a semiconductor structure with a trench junction barrier Schottky diode, comprising: a trench gate power metal oxide semiconductor field effect transistor structure; and a trench junction barrier Schottky diode; wherein an insulating layer of a side wall of the trench junction barrier Schottky diode does not have a side gate. The semiconductor structure with a trench junction barrier Schottky diode provided by the present invention has the shortest current path, and the current path is perpendicular to a horizontal plane or a Schottky barrier.

Description

Technical Field

[0001] The invention relates to a semiconductor structure, in particular to a semiconductor structure with a trench junction barrier Schottky diode. Background Art

[0002] Metal oxide semiconductor field effect transistors are often connected in parallel with diodes in applications. The general practice is to implement them individually on a circuit board or in a module in the form of individual chips, which increases packaging costs and increases the volume of circuits and modules. The present invention proposes a method of integrating power metal oxide semiconductor field effect transistors and diodes on the same chip, which can effectively solve the above problems and reduce costs.

[0003] However, in the prior art, since the position of the Schottky junction barrier affects the current path, the current path of the semiconductor structure in the prior art is too long and therefore cannot have a lower resistance. Summary of the invention

[0004] The object of the present invention is to provide a semiconductor structure with a trench junction barrier Schottky diode, which provides a shorter current path and a shorter resistance value than the prior art.

[0005] An embodiment of the present invention discloses a semiconductor structure, comprising a trench gate power metal oxide semiconductor field effect transistor (UMOS) structure; and a trench junction barrier Schottky (TJBS) diode; wherein an insulating layer on the side wall of the trench junction barrier Schottky diode structure does not have a side gate.

[0006] An embodiment of the present invention discloses a current path flowing from the source through the gap in a vertical direction.

[0007] The semiconductor structure with the trench junction barrier Schottky diode provided by the present invention has the shortest current path, and the current path is perpendicular to the horizontal plane or the Schottky barrier. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 A schematic top view of an embodiment of the present invention is shown.

[0009] Figure 2 A schematic diagram showing a cross section AB of an embodiment of the present invention.

[0010] Figure 3 to Figure 5 Schematic diagrams showing three structures of a UMOS at section AA' according to an embodiment of the present invention.

[0011] Figure 6-7 A schematic top view of an embodiment of the present invention is shown.

[0012] Reference numerals:

[0013] 100, 600, 700: semiconductor structure

[0014] 10, 30, 40, 50: diode

[0015] 10a, 20a: Metal layer

[0016] 10b, 20b: substrate

[0017] 10c, 20c: Drift zone

[0018] 10d, 20d: Dispersion layer

[0019] 10e, 20e: P-type well

[0020] 10g, 10f, 20g, 20f: semiconductor layer

[0021] T1, T2: Groove

[0022] O: Insulation layer

[0023] K: Protective layer

[0024] G: Gate

[0025] SG: Separate Gate

[0026] S: Source

[0027] D: Drain

[0028] C1, C2: Distance DETAILED DESCRIPTION

[0029] Please refer to Figure 1 , Figure 1 A schematic top view of a semiconductor structure 100 with a trench junction barrier Schottky diode according to an embodiment of the present invention is shown; wherein the distance C1 represents the trench width of the UMOS structures 30 , 40 , 50 ; and the distance C2 represents the trench width of the trench junction barrier Schottky diode 10 .

[0030] Please note that each unit of the semiconductor structure 100 is a structure in which a UMOS structure and a trench junction barrier Schottky diode are connected in parallel.

[0031] Please refer to Figure 2 , Figure 2 Show the invention Figure 1AB cross-section of an embodiment schematic diagram, the semiconductor structure 100 includes a trench junction barrier Schottky diode 10, the trench junction barrier Schottky diode 10 includes: a metal layer 10a, an N-type semiconductor substrate 10b, an N-drift region (N-drift region) 10c, an N-current spread layer (N-CSL) 10d, a P-well (P-well) 10e, a trench T1, an insulating layer O, and a P-type semiconductor protection layer K.

[0032] A metal layer 10a is disposed on the upper surface and the bottom surface of the trench junction barrier Schottky diode 10 to form a source S and a drain D respectively; an N-type semiconductor substrate 10b is disposed on the drain D; an N-type drift region 10c is disposed on the N-type semiconductor substrate 10b; an N-type current dispersion layer 10d is disposed on the N-type drift region 10c; a P-type well 10e is disposed on the N-type current dispersion layer 10d; and an N-type semiconductor layer 10f and a P-type semiconductor layer 10g are disposed on the P-type well 10e.

[0033] In addition, the trench T1 extends from the bottom surface of the metal layer 10a (source S) through the N-type semiconductor layer 10f, the P-type well 10e and the N-type current spreading layer 10d, and the bottom of the trench T1 terminates at the N-type drift region 10c.

[0034] The insulating layer O is disposed on both side walls of the trench T1 , and the metal layer 10 a of the source S extends into the trench T1 , and both sides of the metal layer 10 a in the trench T1 contact the insulating layer O on both side walls of the trench T1 .

[0035] The P-type semiconductor protection layer K is arranged below the bottom of the trench T1 and on both sides of the bottom of the trench T1 and adjacent to the N-type drift region 10c; the insulating layer O is arranged on the P-type semiconductor protection layer K, and there is a gap L between the two parts of the P-type semiconductor protection layer K, and above the gap L is the bottom surface of the metal layer 10a (source S) in the trench T1; the insulating layer O is used to prevent the side of the metal layer 10a in the trench T1 from contacting the P-type well 10e, or the N-type current dispersion layer 10d, or the N-type semiconductor layer 10f.

[0036] In another embodiment, the other side wall of the insulating layer O contacts the P-type well 10e, the N-type current dispersion layer 10d, and the N-type semiconductor layer 10f, and the bottom of the insulating layer O contacts the upper surface of a portion of the P-type semiconductor protection layer K, and the N-type drift region 10c has a convex portion, and the width of the convex portion is the gap L.

[0037] The structure of the trench junction barrier Schottky diode 10 can control the current to flow out from the bottom of the metal layer 10a (source S), so the current path flows from the source S through the gap L in a vertical direction. Since the Schottky barrier is located at the intersection of the lowest point of the metal layer 10a of the source S and the N-type drift region 10c, its current path is the shortest and perpendicular to the horizontal plane or the Schottky barrier.

[0038] In addition, the insulating layer O on the sidewall of the trench junction barrier Schottky diode 10 does not include a side gate, so the area of ​​the trench junction barrier Schottky diode 10 can be reduced.

[0039] Please also refer to Figure 3 , Figure 3 Show the invention Figure 1 1 is a schematic diagram of an embodiment of the AB cross section of the semiconductor structure 100, and a schematic diagram of an embodiment of the UMOS structure included in the semiconductor structure 100. The UMOS structure 30 includes: a metal layer 20a, an N-type semiconductor substrate 20b, an N-drift region 20c, an N-current spread layer (N-CSL) 20d, a P-well 20e, a trench T2, an insulating layer O, a gate G, and a P-type semiconductor protection layer K.

[0040] The metal layer 20a is respectively disposed on the upper surface and the bottom surface of the UMOS structure 30 to form a source S and a drain D respectively, and serves as an electrode in parallel between the UMOS structure 30 and the trench junction barrier Schottky diode 20; the N-type semiconductor substrate 20b is disposed on the drain D of the UMOS structure 30; the N-type drift region 20c is disposed on the N-type semiconductor substrate 20b of the UMOS structure 30; the N-type current dispersion layer 20d is disposed on the N-type drift region 20c; the P-type well 20e is disposed on the N-type current dispersion layer 20d; and the N-type semiconductor layer 20f and the P-type semiconductor layer 20g are disposed on the P-type well 20e.

[0041] In addition, the trench T2 extends from the bottom surface of the metal layer 20a (source S) of the UMOS structure 30 through the N-type semiconductor layer 20f, the P-type well 20e and the N-type current spreading layer 20d, and the bottom of the trench T2 ends at the N-type drift region 20c.

[0042] The insulating layer O is disposed in the trench T2; the gate G is disposed in the insulating layer O of the trench T2 and is covered by the insulating layer O; the P-type semiconductor protection layer K is disposed below the bottom of the trench T2 and adjacent to the N-type drift region 20c, and the insulating layer O is disposed on the P-type semiconductor protection layer K.

[0043] The P-type semiconductor protection layer K is disposed below the bottom of the trench T1 and on both sides of the bottom of the trench T1 and adjacent to the N-type drift region 20 c ; the insulating layer O is disposed on and in contact with the P-type semiconductor protection layer K .

[0044] Please also refer to Figure 4 , Figure 4 The difference between the UMOS structure 40 and the UMOS structure 30 is that the UMOS structure 40 further includes a split gate SG disposed in the insulating layer O of the trench T2 , and the split gate SG is covered by the insulating layer O.

[0045] In addition, the gate G and the separation gate SG are separated by the insulating layer O by a preset interval X; the bottom depth of the gate G is deeper than the interface between the P-type well 20 e and the N-type current spreading layer 20 d.

[0046] Please also refer to Figure 5 , Figure 5 The UMOS structure 50 is different from the UMOS structure 40 in that the bottom of the separation gate SG of the UMOS structure 50 contacts the upper surface of the P-type semiconductor protection layer K.

[0047] Please also refer to Figure 6 and Figure 7 , Figure 6 and Figure 7 The schematic top views of one embodiment of the present invention are shown respectively. Figure 6 The semiconductor structure 600 may be a hexagonal arrangement structure, and Figure 7 The semiconductor structure 700 may be a strip-shaped staggered arrangement structure.

[0048] In summary, the semiconductor structure of the present invention is a field effect transistor of a trench junction barrier Schottky diode in parallel with a UMOS structure, wherein the Schottky barrier is located at the lowest position of the diode metal layer (the bottom of the trench), and the Schottky barrier is located at the junction of the metal layer and the N-type drift region, so that the present invention has the shortest current path, and the current path is perpendicular to the horizontal plane or the Schottky barrier.

Claims

1. A semiconductor structure having a trench junction barrier Schottky diode, characterized in that: A diode structure is included, the diode structure comprising: A first metal layer is disposed on the upper surface and the bottom surface of the diode structure to form a source and a drain respectively; A first N-type semiconductor substrate, disposed on the drain; A first N-type drift region is disposed on the first N-type semiconductor substrate; a first N-type current spreading layer, disposed on the first N-type drift region; A first P-type well, disposed on the first N-type current spreading layer; A first N-type semiconductor layer is disposed on the first P-type well; A first P-type semiconductor layer is disposed on the first P-type well; A first trench extending through the first N-type semiconductor layer, the first P-type well and the first N-type current spreading layer, wherein the bottom of the first trench terminates at the first N-type drift region; A first insulating layer is disposed on two side walls of the first trench, and the first metal layer of the source extends into the first trench, and two sides of the metal layer in the first trench contact the first insulating layer on the two side walls; as well as A first P-type semiconductor protection layer is arranged below the bottom of the first trench and on both sides of the bottom of the first trench and adjacent to the first N-type drift region. The first insulating layer is arranged on the first P-type semiconductor protection layer. There is a gap between the two parts of the first P-type semiconductor protection layer, and the metal layer in the first trench is above the gap. The first insulating layer is used to prevent the side of the first metal layer in the first trench from contacting the first P-type well, or the first N-type current dispersion layer, or the first N-type semiconductor layer.

2. The semiconductor structure according to claim 1, wherein: The first groove is a U-shaped groove.

3. The semiconductor structure according to claim 2, wherein: A current path flows from the source through the gap in a vertical direction.

4. The semiconductor structure according to claim 3, characterized in that The semiconductor structure includes a UMOS structure, and the UMOS structure includes: A second metal layer is disposed on the upper surface and the bottom surface of the UMOS structure to form the source and the drain respectively, so as to serve as electrodes of the UMOS structure connected in parallel with the diode; A second N-type semiconductor substrate, disposed on the drain of the UMOS structure; A second N-type drift region is disposed on the second N-type semiconductor substrate of the UMOS structure; a second N-type current spreading layer, disposed on the second N-type drift region; a second P-type well disposed on the second N-type current spreading layer; A second N-type semiconductor layer, disposed on the second P-type well; A second P-type semiconductor layer, disposed on the second P-type well; A second trench extending through the second N-type semiconductor layer and the second N-type current spreading layer, wherein the bottom of the second trench terminates at the second N-type drift region; a second insulating layer disposed in the second trench; a gate disposed in the second insulating layer of the second trench and covered by the second insulating layer; as well as A second P-type semiconductor protection layer is disposed below the bottom of the second trench and adjacent to the second N-type drift region, and the second insulating layer is disposed on the second P-type semiconductor protection layer.

5. The semiconductor structure according to claim 3, wherein: The semiconductor structure includes a UMOS structure, and the UMOS structure includes: A second metal layer is disposed on the upper surface and the bottom surface of the UMOS structure to form the source and the drain respectively, so as to serve as electrodes of the UMOS structure connected in parallel with the diode; A second N-type semiconductor substrate, disposed on the drain of the UMOS structure; A second N-type drift region is disposed on the second N-type semiconductor substrate of the UMOS structure; a second N-type current spreading layer, disposed on the second N-type drift region; a second P-type well disposed on the second N-type current spreading layer; A second N-type semiconductor layer, disposed on the second P-type well; a second P-type semiconductor layer disposed on the second P-type well; a second trench extending through the second N-type semiconductor layer and the second N-type current spreading layer, wherein the bottom of the second trench terminates at the second N-type drift region; a second insulating layer disposed in the second trench; a separation gate disposed in the second insulating layer of the second trench and covered by the second insulating layer; a gate disposed in the second insulating layer of the second trench and on the separation gate, the gate being covered by the second insulating layer; as well as a second P-type semiconductor protection layer, disposed below the bottom of the second trench and adjacent to the second N-type drift region, and the second insulating layer is disposed on the second P-type semiconductor protection layer; The gate and the separation gate are separated by a preset distance by the second insulating layer; and a depth position of a bottom of the gate is deeper than the interface between the P-type well and the second N-type current spreading layer.

6. The semiconductor structure according to claim 3, characterized in that The semiconductor structure includes a UMOS structure, and the UMOS structure includes: A second metal layer is disposed on the upper surface and the bottom surface of the UMOS structure to form the source and the drain respectively, so as to serve as electrodes of the UMOS structure and the diode; A second N-type semiconductor substrate, disposed on the drain of the UMOS structure; A second N-type drift region is disposed on the second N-type semiconductor substrate of the UMOS structure; a second N-type current spreading layer, disposed on the second N-type drift region; a second P-type well disposed on the second N-type current spreading layer; A second N-type semiconductor layer, disposed on the second P-type well; A second P-type semiconductor layer, disposed on the second P-type well; A second trench extending through the second N-type semiconductor layer and the second N-type current spreading layer, wherein the bottom of the second trench terminates at the second N-type drift region; a second insulating layer disposed in the second trench; a separation gate disposed in the second insulating layer of the second trench and covered by the second insulating layer; a gate disposed in the second insulating layer of the second trench and on the separation gate, the gate being covered by the second insulating layer; as well as a second P-type semiconductor protection layer, disposed below the bottom of the second trench and adjacent to the second N-type drift region, and the second insulating layer is disposed on the second P-type semiconductor protection layer; The gate and the separation gate are separated by a preset distance by the second insulating layer; and the bottom depth of the gate is deeper than the interface between the second P-type well and the second N-type current dispersion layer, and the bottom of the separation gate contacts the upper surface of the second P-type semiconductor protection layer.

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