Lighting devices and projectors

Abstract

A light-emitting device and a projector can be miniaturized. The light-emitting device comprises a substrate, a transistor, a light-emitting element, and a wiring electrically connecting the transistor and the light-emitting element, wherein the transistor comprises a first impurity region provided on the substrate, a second impurity region provided on the substrate and having the same conductivity type as the first impurity region, and a gate, wherein the light-emitting element comprises a stacked body having a plurality of columnar portions, wherein each of the plurality of columnar portions comprises a first semiconductor layer, a second semiconductor layer, and a light-emitting layer, wherein the first semiconductor layer is arranged between the substrate and the light-emitting layer, wherein the wiring is a third impurity region provided on the substrate, wherein the stacked body is arranged in the third impurity region, wherein the conductivity type of the third impurity region is the same as that of the first semiconductor layer, wherein the third impurity region is electrically connected to the first semiconductor layer, and wherein the third impurity region is continuous with the first impurity region.

Description

Technical Field

[0001] The invention relates to a light emitting device and a projector. Background Art

[0002] Semiconductor lasers are expected to be the next generation of high-brightness light sources. Among them, semiconductor lasers using nanorods are expected to be able to emit high-power light at a narrow radiation angle due to the photonic crystal effect of the nanorods.

[0003] For example, Patent Document 1 describes an optical integrated device in which a light-emitting element having a plurality of pillars and a transistor for driving the light-emitting element are integrated on the same substrate.

[0004] Patent Document 1: Japanese Patent Application Publication No. 2009-105182

[0005] However, in Patent Document 1, since the light emitting element and the transistor are electrically connected by metal wiring, there is a possibility that the device becomes larger. Summary of the invention

[0006] One mode of the light-emitting device of the present invention comprises: a substrate; a transistor, which is arranged on the substrate; a light-emitting element, which is arranged on the substrate; and a wiring, which electrically connects the transistor and the light-emitting element, wherein the transistor comprises: a first impurity region, which is arranged on the substrate; a second impurity region, which is arranged on the substrate, and the conductivity type of the second impurity region is the same as that of the first impurity region; and a gate, which controls the current between the first impurity region and the second impurity region, and the light-emitting element comprises a stacked body, the stacked body comprises a plurality of columnar portions, and each of the plurality of columnar portions has : a first semiconductor layer; a second semiconductor layer, the conductivity type of the second semiconductor layer is different from that of the first semiconductor layer; and a light-emitting layer, which is arranged between the first semiconductor layer and the second semiconductor layer, the first semiconductor layer is arranged between the substrate and the light-emitting layer, the wiring is provided in a third impurity region of the substrate, the stack is arranged in the third impurity region, the conductivity type of the third impurity region is the same as that of the first semiconductor layer, the third impurity region is electrically connected to the first semiconductor layer, and the third impurity region is continuous with the first impurity region.

[0007] One aspect of a projector according to the present invention includes one aspect of the above-mentioned light emitting device. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a cross-sectional view schematically showing the light emitting device of this embodiment.

[0009] Figure 2 It is a cross-sectional view schematically showing the manufacturing process of the light emitting device of this embodiment.

[0010] Figure 3 It is a cross-sectional view schematically showing the manufacturing process of the light emitting device of this embodiment.

[0011] Figure 4 It is a cross-sectional view schematically showing the manufacturing process of the light emitting device of this embodiment.

[0012] Figure 5 It is a cross-sectional view schematically showing the manufacturing process of the light emitting device of this embodiment.

[0013] Figure 6 It is a cross-sectional view schematically showing the manufacturing process of the light emitting device of this embodiment.

[0014] Figure 7 It is a cross-sectional view schematically showing the manufacturing process of the light emitting device of this embodiment.

[0015] Figure 8 It is a cross-sectional view schematically showing the manufacturing process of the light emitting device of this embodiment.

[0016] Fig. 9 It is a cross-sectional view schematically showing a light emitting device according to a first modified example of the present embodiment.

[0017] Fig.10 It is a cross-sectional view schematically showing a light emitting device according to a second variation of the present embodiment.

[0018] Fig.11 It is a diagram schematically showing a projector according to this embodiment.

[0019] Description of symbols

[0020] 10: substrate; 12: well; 20: element isolation region; 30: transistor; 32: first impurity region; 34: second impurity region; 36: gate; 37: gate insulating film; 38: gate electrode; 39: sidewall; 40: passivation film; 50: first interlayer insulating film; 52: first via; 54: first metal wiring; 60: second interlayer insulating film; 60a: through hole; 62: second via; 64: second metal wiring; 70: wiring; 80: light emitting element; 81: laminate; 82: strain relaxation layer; 83: buffer layer; 84: mask layer; 85: columnar portion; 86: 6: 1st semiconductor layer; 87: light-emitting layer; 88: 2nd semiconductor layer; 89: electrode; 90: lead-out wiring; 100: light-emitting device; 100R: red light source; 100G: green light source; 100B: blue light source; 200, 300: light-emitting device; 900: projector; 902R: 1st optical element; 902G: 2nd optical element; 902B: 3rd optical element; 904R: 1st light modulator; 904G: 2nd light modulator; 904B: 3rd light modulator; 906: cross-dichroic prism; 908: projection device; 910: screen. DETAILED DESCRIPTION

[0021] Hereinafter, preferred embodiments of the present invention will be described in detail using the accompanying drawings. In addition, the embodiments described below do not unduly limit the contents of the present invention described in the claims. In addition, the structures described below are not necessarily all necessary components of the present invention.

[0022] 1. Light-emitting device

[0023] First, a light emitting device according to this embodiment will be described with reference to the drawings. Figure 1 2 is a cross-sectional view schematically showing the light emitting device 100 according to the present embodiment.

[0024] like Figure 1 As shown, the light emitting device 100 includes, for example, a substrate 10, an element isolation region 20, a transistor 30, a passivation film 40, a first interlayer insulating film 50, a first via 52, a first metal wiring 54, a second interlayer insulating film 60, a second via 62, a second metal wiring 64, a wiring 70, a light emitting element 80, and an extraction wiring 90. The light emitting device 100 has a monolithic structure in which the transistor 30 and the light emitting element 80 are provided on the same substrate 10.

[0025] The substrate 10 is a semiconductor substrate. The substrate 10 is, for example, a silicon substrate. The substrate 10 may also be a p-type silicon substrate.

[0026] The device isolation region 20 is provided on the substrate 10. The device isolation region 20 is, for example, LOCOS (Local Oxidation of Silicon) or STI (Shallow Trench Isolation). The device isolation region 20 can electrically isolate the transistor 30 and the light emitting element 80 from other elements not shown.

[0027] The transistor 30 is provided on the substrate 10. The transistor 30 may be a CMOS (Complementary Metal Oxide Semiconductor) or a bipolar transistor. The transistor 30 constitutes a circuit for driving the light emitting element 80. The transistor 30 includes a first impurity region 32, a second impurity region 34, and a gate 36.

[0028] The first impurity region 32 is provided in the substrate 10 . The first impurity region 32 is, for example, an n-type impurity region. The first impurity region 32 functions as one of the source and the drain of the transistor 30 .

[0029] The second impurity region 34 is provided in the substrate 10. The second impurity region 34 is separated from the first impurity region 32. The conductivity type of the second impurity region 34 is the same as that of the first impurity region 32. The second impurity region 34 functions as the other of the source and the drain of the transistor 30.

[0030] The gate 36 is disposed on the substrate 10. The gate 36 includes a gate insulating film 37, a gate electrode 38, and a side wall 39. The material of the gate insulating film 37 and the side wall 39 is, for example, silicon oxide. The material of the gate electrode 38 is, for example, Al, Cu, Al-Cu (alloy of Al and Cu), W, or Ti. The gate 36 controls the current between the first impurity region 32 and the second impurity region 34.

[0031] The passivation film 40 covers the transistor 30. In the example shown in the figure, the passivation film 40 is arranged on the gate 36 and on the impurity regions 32 and 34. The passivation film 40 is, for example, a silicon nitride film, a silicon nitride oxide film, or a silicon oxide film.

[0032] The first interlayer insulating film 50 covers the transistor 30. The first interlayer insulating film 50 is arranged on the substrate 10 via the passivation film 40. The first via 52 is arranged in the through hole formed in the first interlayer insulating film 50. The first via 52 is connected to the transistor 30. In the example shown in the figure, three first vias 52 are arranged, and the three first vias 52 are respectively connected to the first impurity region 32, the second impurity region 34, and the gate 36. The first metal wiring 54 is arranged on the first interlayer insulating film 50. The first metal wiring 54 is connected to the first via 52.

[0033] The second interlayer insulating film 60 is disposed on the first interlayer insulating film 50. The second interlayer insulating film 60 covers the first metal wiring 54. A through hole 60a is formed in the second interlayer insulating film 60. The second via 62 is disposed in the through hole formed in the second interlayer insulating film 60. The second metal wiring 64 is disposed on the second interlayer insulating film 60. The second metal wiring 64 is connected to the second via 62. The material of the interlayer insulating films 50 and 60 is, for example, silicon oxide. The material of the vias 52 and 62 and the metal wirings 54 and 64 is, for example, Al, Cu, Al-Cu, W, or Ti.

[0034] The wiring 70 electrically connects the transistor 30 and the light emitting element 80. The wiring 70 is a third impurity region 72 provided in the substrate 10. That is, the wiring 70 is a diffusion layer wiring composed of the third impurity region 72 provided in the substrate 10. The third impurity region 72 is, for example, an n-type impurity region. The third impurity region 72 is continuous with the first impurity region 32. The first impurity region 32 and the third impurity region 72 are provided as a whole. The substrate 10 has impurity regions 32, 34, and 72.

[0035] The light emitting element 80 is provided on the substrate 10. The light emitting element 80 includes a stacked body 81 and an electrode 89. The light emitting element 80 is, for example, a semiconductor laser. The stacked body 81 is arranged in the third impurity region 72. In the example shown in the figure, the stacked body 81 is arranged on the third impurity region 72. The stacked body 81 includes a strain relaxation layer 82, a buffer layer 83, a mask layer 84, and a plurality of columnar portions 85.

[0036] In this specification, in the stacking direction of the stacked body 81 (hereinafter, also referred to as the "stacking direction"), when the light-emitting layer 87 is used as a reference, the direction from the light-emitting layer 87 toward the second semiconductor layer 88 is referred to as "upward", and the direction from the light-emitting layer 87 toward the first semiconductor layer 86 is referred to as "downward". In addition, the direction perpendicular to the stacking direction is also referred to as the "in-plane direction". In addition, the "stacking direction of the stacked body 81" refers to the stacking direction of the first semiconductor layer 86 and the light-emitting layer 87 of the columnar portion 85.

[0037] The strain relaxation layer 82 is arranged on the third impurity region 72. The strain relaxation layer 82 is arranged between the substrate 10 and the first semiconductor layer 86. The lattice constant of the strain relaxation layer 82 is a value between the lattice constant of the substrate 10 and the lattice constant of the first semiconductor layer 86 of the columnar portion 85. The strain relaxation layer 82 is, for example, an AlN layer. The strain relaxation layer 82 is formed thin so as not to become a high resistance to the current from the third impurity region 72. The thickness of the strain relaxation layer 82 is, for example, not less than 3 nm and not more than 500 nm.

[0038] The buffer layer 83 is disposed on the strain relaxation layer 82. The buffer layer 83 is, for example, an n-type GaN layer doped with Si.

[0039] The mask layer 84 is disposed on the buffer layer 83. The mask layer 84 is a layer for forming the columnar portion 85. The mask layer 84 is, for example, a silicon oxide layer, a titanium layer, a titanium oxide layer, an aluminum oxide layer, or the like.

[0040] The columnar portion 85 is disposed on the buffer layer 83. The columnar portion 85 has a columnar shape protruding upward from the buffer layer 83. In other words, the columnar portion 85 protrudes upward from the substrate 10 via the buffer layer 83. The columnar portion 85 is also called, for example, a nanocolumn, a nanowire, a nanorod, or a nanopillar. The planar shape of the columnar portion 85 is, for example, a polygon such as a regular hexagon or a circle.

[0041] The diameter of the columnar portion 85 is, for example, not less than 50 nm and not more than 500 nm. By making the diameter of the columnar portion 85 not more than 500 nm, a high-quality crystalline light-emitting layer 87 can be obtained, and the strain inside the light-emitting layer 87 can be reduced. As a result, the light generated by the light-emitting layer 87 can be amplified with higher efficiency.

[0042] In addition, the so-called "diameter of the columnar portion" is the diameter when the planar shape of the columnar portion 85 is a circle, and is the diameter of the smallest circle when the planar shape of the columnar portion 85 is a shape other than a circle. For example, the diameter of the columnar portion 85 is the diameter of the smallest circle that includes the polygon when the planar shape of the columnar portion 85 is a polygon, and is the diameter of the smallest circle that includes the ellipse when the planar shape of the columnar portion 85 is an ellipse.

[0043] There are multiple columnar portions 85. The interval between adjacent columnar portions 85 is, for example, greater than 1 nm and less than 500 nm. When observed from the stacking direction, the multiple columnar portions 85 are arranged at a specified interval in a specified direction. The multiple columnar portions 85 are, for example, arranged in a triangular lattice. In addition, the arrangement of the multiple columnar portions 85 is not particularly limited, and can also be arranged in a square lattice. The multiple columnar portions 85 can show the effect of a photonic crystal.

[0044] In addition, the "pitch of the columnar portion" refers to the distance between the centers of the columnar portions 85 adjacent to each other in a predetermined direction. The so-called "center of the columnar portion" is the center of the circle when the planar shape of the columnar portion 85 is a circle, and is the center of the smallest circle when the planar shape of the columnar portion 85 is a shape other than a circle. For example, the center of the columnar portion 85 is the center of the smallest circle that includes the polygon when the planar shape of the columnar portion 85 is a polygon, and is the center of the smallest circle that includes the ellipse when the planar shape of the columnar portion 85 is an ellipse.

[0045] The columnar portion 85 includes a first semiconductor layer 86 , a light emitting layer 87 , and a second semiconductor layer 88 .

[0046] The first semiconductor layer 86 is disposed on the buffer layer 83. The first semiconductor layer 86 is disposed between the substrate 10 and the light emitting layer 87. The first semiconductor layer 86 is, for example, an n-type GaN layer doped with Si. The conductivity type of the third impurity region 72 is the same as that of the first semiconductor layer 86. The third impurity region 72 is electrically connected to the first semiconductor layer 86. The third impurity region 72 functions as an electrode for injecting current into the light emitting layer 87.

[0047] The light emitting layer 87 is arranged on the first semiconductor layer 86. The light emitting layer 87 is arranged between the first semiconductor layer 86 and the second semiconductor layer 88. The light emitting layer 87 generates light by injecting current. The light emitting layer 87 has an i-type well layer and a barrier layer that are not intentionally doped with impurities. The well layer is, for example, an InGaN layer. The barrier layer is, for example, a GaN layer. The light emitting layer 87 has an MQW (Multiple Quantum Well: multiple quantum well) structure composed of a well layer and a barrier layer.

[0048] The number of well layers and barrier layers constituting the light emitting layer 87 is not particularly limited. For example, only one well layer may be provided, in which case the light emitting layer 87 has an SQW (Single Quantum Well) structure.

[0049] The second semiconductor layer 88 is disposed on the light emitting layer 87. The second semiconductor layer 88 is a layer of conductivity type different from that of the first semiconductor layer 86. The second semiconductor layer 88 is, for example, a p-type GaN layer doped with Mg. The first semiconductor layer 86 and the second semiconductor layer 88 are cladding layers having a function of confining light in the light emitting layer 87.

[0050] Although not shown, an OCL (Optical Confinement Layer) may be disposed between the first semiconductor layer 86 and the light emitting layer 87 . Also, an EBL (Electron Blocking Layer) may be disposed between the light emitting layer 87 and the second semiconductor layer 88 .

[0051] In the light emitting device 100, a pin diode is formed by a p-type second semiconductor layer 88, an i-type light emitting layer 87 not doped with impurities, and an n-type first semiconductor layer 86. In the light emitting device 100, when a forward bias voltage of the pin diode is applied between the third impurity region 72 and the electrode 89, a current is injected into the light emitting layer 87 to generate recombination of electrons and holes in the light emitting layer 87. Light is emitted by this recombination. The light generated by the light emitting layer 87 propagates in the in-plane direction, forms a standing wave by the photonic crystal effect generated by the plurality of columnar portions 85, and receives gain in the light emitting layer 87 to perform laser oscillation. Then, the light emitting element 80 emits the +1st order diffracted light and the -1st order diffracted light as laser light in the stacking direction. The light is emitted through the through hole 60a formed in the second interlayer insulating film 60. The light extraction efficiency can be improved by the through hole 60a. In addition, the light toward the substrate 10 side is reflected by the substrate 10 and then emitted through the through hole 60a.

[0052] The electrode 89 is disposed on the second semiconductor layer 88. The electrode 89 is electrically connected to the second semiconductor layer 88. The second semiconductor layer 88 may also be in ohmic contact with the electrode 89. The electrode 89 is another electrode for injecting current into the light emitting layer 87. As the electrode 89, for example, ITO (indium tin oxide) or the like is used.

[0053] Lead wiring 90 is arranged on electrode 89 and first interlayer insulating film 50. In the example shown in the figure, lead wiring 90 is covered by second interlayer insulating film 60. The material of lead wiring 90 is, for example, the same as that of first metal wiring 54. Lead wiring 90 is a wiring for passing current through electrode 89.

[0054] In the above description, the InGaN-based light emitting layer 87 is described, but various materials that can emit light by injecting current can be used as the light emitting layer 87, depending on the wavelength of the emitted light. For example, semiconductor materials such as AlGaN-based, AlGaAs-based, InGaAs-based, InGaAsP-based, InP-based, GaP-based, and AlGaP-based can be used.

[0055] In addition, although not shown, a light shielding portion for shielding light from the light emitting element 80 may be disposed between the transistor 30 and the light emitting element 80. Thus, the influence of the light from the light emitting element 80 on the operation of the transistor 30 can be reduced. The light shielding portion may be made of the same material as the via 52, or may be formed simultaneously in the process of forming the via 52. Alternatively, the light shielding portion may be formed by growing a semiconductor layer and disposing a metal layer on the semiconductor layer.

[0056] In addition, the light emitting element 80 is not limited to a laser, and may be an LED (Light Emitting Diode).

[0057] The light emitting device 100 has the following effects, for example.

[0058] In the light emitting device 100, the wiring 70 is a third impurity region 72 provided on the substrate 10, the stacked body 81 is arranged in the third impurity region 72, the conductivity type of the third impurity region 72 is the same as the conductivity type of the first semiconductor layer 86, the third impurity region 72 is electrically connected to the first semiconductor layer 86, and the third impurity region 72 is continuous with the first impurity region 32. Therefore, in the light emitting device 100, miniaturization can be achieved compared with the case where metal wiring is used as wiring for electrically connecting the transistor and the light emitting element. For example, if metal wiring is used, the wiring becomes complicated and there is a case where the device is enlarged. In addition, in the light emitting device 100, it is not necessary to provide an element isolation region between the transistor 30 and the light emitting element 80, so the transistor 30 and the light emitting element 80 can be arranged close to each other, thereby achieving miniaturization.

[0059] Furthermore, in the light emitting device 100, the light emitting element 80 has a plurality of columnar portions 85, so strain can be minimized even when the light emitting element 80 is provided on the same substrate as the transistor 30. Therefore, a highly efficient light emitting element 80 can be realized. Furthermore, since a hybrid mounting technique such as transfer mounting or substrate bonding is not used, cost reduction can be achieved.

[0060] In the light emitting device 100, the stacked body 81 includes a strain relaxation layer 82 disposed between the substrate 10 and the first semiconductor layer 86, and the lattice constant of the strain relaxation layer 82 is a value between the lattice constant of the substrate 10 and the lattice constant of the first semiconductor layer 86. Therefore, in the light emitting device 100, the strain generated in the first semiconductor layer 86 can be reduced compared to a case where the strain relaxation layer 82 is not disposed.

[0061] The light emitting device 100 includes the passivation film 40 covering the transistor 30. Therefore, in the light emitting device 100, damage to the transistor 30 due to heat during formation of the light emitting element 80 can be reduced compared to a case where the passivation film 40 is not provided. During formation of the light emitting element 80, heat of about 1000° C. may be applied.

[0062] 2. Method for manufacturing a light-emitting device

[0063] Next, a method for manufacturing the light emitting device of this embodiment will be described with reference to the drawings. Figure 2 to Figure 8 It is a cross-sectional view schematically showing the manufacturing process of the light emitting device 100 according to the present embodiment.

[0064] like Figure 2 As shown in FIG. 1 , an element isolation region 20 is formed on a substrate 10. The element isolation region 20 is formed by, for example, a LOCOS method or an STI method.

[0065] Next, a gate insulating film 37 is formed on the substrate 10. The gate insulating film 37 is formed, for example, by a thermal oxidation method. Next, a gate electrode 38 is formed on the gate insulating film 37. The gate electrode 38 is formed, for example, by a sputtering method, a CVD (Chemical Vapor Deposition) method, or a vacuum evaporation method. Next, a side wall 39 is formed on the side of the gate electrode 38. The side wall 39 is formed, for example, by forming a silicon oxide film by a CVD method or the like, and etching back the silicon oxide film. Through this process, the gate 36 can be formed.

[0066] Next, the first impurity region 32, the second impurity region 34, and the third impurity region 72 are formed by, for example, ion implantation. The first impurity region 32 and the third impurity region 72 are formed integrally. Through this process, the transistor 30 can be formed.

[0067] Next, the passivation film 40 is formed on the substrate 10 so as to cover the transistor 30. The passivation film 40 is formed by, for example, a sputtering method or a CVD method.

[0068] like Figure 3 As shown, a part of the passivation film 40 is removed by etching, and a strain relaxation layer 82 is formed in the removed part. The strain relaxation layer 82 is formed by, for example, a CVD method or a sputtering method.

[0069] like Figure 4 As shown, a buffer layer 83 is epitaxially grown on the strain relaxation layer 82. Examples of epitaxial growth methods include MOCVD (Metal Organic Chemical Vapor Deposition) and MBE (Molecular Beam Epitaxy). The buffer layer 83 is selectively grown on the strain relaxation layer 82.

[0070] like Figure 5 As shown, a mask layer 84 is formed on the buffer layer 83. The mask layer 84 is formed by film formation and patterning using, for example, electron beam evaporation or sputtering. The patterning is performed by photolithography and etching.

[0071] Next, using the mask layer 84 as a mask, the first semiconductor layer 86, the light emitting layer 87, and the second semiconductor layer 88 are epitaxially grown in sequence on the buffer layer 83. As a method of epitaxial growth, for example, MOCVD method, MBE method, etc. can be cited. Through this process, a plurality of columnar portions 85 can be formed. And through this process, the stacked body 81 can be formed.

[0072] like Figure 6 As shown, an electrode 89 is formed on the second semiconductor layer 88. The electrode 89 is formed by, for example, vacuum deposition. Through this process, the light emitting element 80 can be formed. Although not shown, a passivation film covering the light emitting element 80 may also be formed.

[0073] like Figure 7 As shown, a first interlayer insulating film 50 is formed on the passivation film 40 so as to cover the transistor 30. The first interlayer insulating film 50 is formed by, for example, a spin coating method.

[0074] like Figure 8 As shown, the first interlayer insulating film 50 is patterned to form a through hole, and the first via 52 is formed in the through hole. Next, the first metal wiring 54 is formed on the first via 52. And, the lead wiring 90 is formed on the electrode 89. The first metal wiring 54 and the lead wiring 90 are formed by the same process. The first via 52, the first metal wiring 54 and the lead wiring 90 are formed by, for example, plating, sputtering, CVD, etc.

[0075] Next, the second interlayer insulating film 60 is formed on the first interlayer insulating film 50. The second interlayer insulating film 60 is formed by, for example, a spin coating method.

[0076] Next, the second interlayer insulating film 60 is patterned to form a through hole, and a second via 62 is formed in the through hole. Next, a second metal wiring 64 is formed on the second via 62. The second via 62 and the second metal wiring 64 are formed by, for example, plating, sputtering, CVD, or the like.

[0077] like Figure 1 As shown, the second interlayer insulating film 60 is patterned to form a through hole 60 a.

[0078] Through the above steps, the light emitting device 100 can be manufactured.

[0079] 3. Modifications of Light Emitting Device

[0080] 3.1. First Modification

[0081] Next, a light emitting device according to a first modification example of the present embodiment will be described with reference to the drawings. Fig. 9It is a cross-sectional view schematically showing a light emitting device 200 according to a first modified example of the present embodiment.

[0082] Hereinafter, in the light emitting device 200 of the first variant of the present embodiment, components having the same functions as the components of the light emitting device 100 of the present embodiment described above are denoted by the same reference numerals, and their detailed descriptions are omitted. This is also the same for the light emitting device of the second variant of the present embodiment described below.

[0083] In the above-mentioned light emitting device 100, Figure 1 As shown, the depth of the first impurity region 32 and the depth of the third impurity region 72 are the same.

[0084] In contrast, in the light emitting device 200, as Fig. 9 As shown, the depth D3 of the third impurity region 72 is greater than the depth D1 of the first impurity region 32. The depth D1 is the maximum size of the first impurity region 32 in the stacking direction. The depth D3 is the maximum size of the third impurity region 72 in the stacking direction. In the example shown in the figure, the third impurity region 72 does not have a portion other than the depth D3. The depth D1 is, for example, greater than 50 μm and less than 500 μm. The depth D3 is, for example, greater than 100 μm and less than 2000 μm.

[0085] When viewed from the stacking direction, the area of ​​the third impurity region 72 is larger than the area of ​​the stacked body 81. The stacked body 81 is disposed only in the third impurity region 72. The stacked body 81 is not disposed in a region other than the third impurity region 72.

[0086] The first impurity region 32 and the third impurity region 72 are formed in different steps. For example, the third impurity region 72 is formed first, and then the first impurity region 32 is formed. Alternatively, the first impurity region 32 may be formed first, and then the third impurity region 72 may be formed.

[0087] In the light emitting device 200, the depth D3 of the third impurity region 72 is greater than the depth D1 of the first impurity region 32. Therefore, even if a crystal defect caused by the stress of the strain relaxation layer 82 is generated in the third impurity region 72, the difference between the resistance of the first impurity region 32 and the resistance of the third impurity region 72 can be reduced compared to the case where the depth D3 is the same as the depth D1.

[0088] In the light emitting device 200 , when viewed from the stacking direction, the area of ​​the third impurity region 72 is larger than the area of ​​the stacked body 81 . Therefore, in the light emitting device 200 , the stacked body 81 can be disposed only in the third impurity region 72 .

[0089] 3.2. Second Modification

[0090] Next, a light emitting device according to a second modified example of the present embodiment will be described with reference to the drawings. Fig.10 It is a cross-sectional view schematically showing a light emitting device 300 according to a second modification example of the present embodiment.

[0091] In the light emitting device 300, as Fig.10 As shown, the light emitting device 100 described above is different in that the substrate 10 has a well 12 .

[0092] The depth of the well 12 is greater than the depths of the impurity regions 32, 34, and 72. The conductivity type of the well 12 is different from the conductivity type of the first impurity region 32. The well 12 is, for example, a p-type well. The transistor 30 is provided in the well 12. The first impurity region 32, the second impurity region 34, and the third impurity region 72 are provided in the well 12.

[0093] The well 12 is formed by, for example, ion implantation before forming the impurity regions 32 , 34 , and 72 .

[0094] In the light-emitting device 300, the substrate 10 has a well 12 having a conductivity type different from that of the first impurity region 32, and the first impurity region 32, the second impurity region 34, and the third impurity region 72 are provided in the well 12. Therefore, in the light-emitting device 300, the insulation between the substrate 10 and the impurity regions 32, 34, and 72 can be improved compared to a case where the well 12 is not provided.

[0095] 4. Projector

[0096] Next, a projector according to the present embodiment will be described with reference to the drawings. Fig.11 1 is a diagram schematically showing a projector 900 according to this embodiment.

[0097] The projector 900 includes, for example, a light emitting device 100 as a light source.

[0098] The projector 900 includes a housing (not shown) and a red light source 100R, a green light source 100G, and a blue light source 100B disposed in the housing and emitting red light, green light, and blue light, respectively. Fig.11 In FIG. 1 , the red light source 100R, the green light source 100G, and the blue light source 100B are simplified.

[0099] The projector 900 further includes a first optical element 902R, a second optical element 902G, a third optical element 902B, a first light modulator 904R, a second light modulator 904G, a third light modulator 904B, and a projection device 908, which are arranged in a housing. The first light modulator 904R, the second light modulator 904G, and the third light modulator 904B are, for example, transmissive liquid crystal light valves. The projection device 908 is, for example, a projection lens.

[0100] The light emitted from the red light source 100R enters the first optical element 902R. The light emitted from the red light source 100R is condensed by the first optical element 902R. The first optical element 902R may have functions other than condensing light. The same is true for the second optical element 902G and the third optical element 902B described later.

[0101] The light focused by the first optical element 902R enters the first light modulator 904R. The first light modulator 904R modulates the incident light according to image information. Then, the projection device 908 magnifies the image formed by the first light modulator 904R and projects it onto the screen 910.

[0102] The light emitted from the green light source 100G enters the second optical element 902G. The light emitted from the green light source 100G is condensed by the second optical element 902G.

[0103] The light focused by the second optical element 902G enters the second light modulator 904G. The second light modulator 904G modulates the incident light according to the image information. Then, the projection device 908 enlarges the image formed by the second light modulator 904G and projects it onto the screen 910.

[0104] The light emitted from the blue light source 100B enters the third optical element 902B. The light emitted from the blue light source 100B is condensed by the third optical element 902B.

[0105] The light focused by the third optical element 902B enters the third light modulator 904B. The third light modulator 904B modulates the incident light according to the image information. Then, the projection device 908 enlarges the image formed by the third light modulator 904B and projects it onto the screen 910.

[0106] Furthermore, the projector 900 can include a cross dichroic prism 906 that combines the light emitted from the first light modulator 904R, the second light modulator 904G, and the third light modulator 904B and guides the combined light to the projection device 908 .

[0107] The three color lights modulated by the first light modulator 904R, the second light modulator 904G, and the third light modulator 904B are incident on the cross dichroic prism 906. The cross dichroic prism 906 is formed by bonding four right-angle prisms, and a dielectric multilayer film reflecting red light and a dielectric multilayer film reflecting blue light are arranged on its inner surface. The three color lights are synthesized by these dielectric multilayer films to form light representing a color image. Then, the synthesized light is projected onto the screen 910 through the projection device 908 to display the enlarged image.

[0108] In the light emitting device 100 , since the light emitting element 80 and the transistor 30 for driving the light emitting element 80 are provided on the same substrate, grayscale control and “on” / “off” control can be performed for each pixel.

[0109] Although not shown, the red light source 100R, the green light source 100G, and the blue light source 100B may be provided on the same substrate. This can form an imager based on RGB pixels and an imager integrated with a driving circuit.

[0110] In addition, the red light source 100R, the green light source 100G, and the blue light source 100B may be controlled according to image information by using the light emitting device 100 as a pixel of the image, and may directly form an image without using the first light modulator 904R, the second light modulator 904G, and the third light modulator 904B. Furthermore, the projection device 908 may enlarge the image formed by the red light source 100R, the green light source 100G, and the blue light source 100B and project it onto the screen 910.

[0111] In the above example, a transmissive liquid crystal light valve is used as the light modulating device, but a light valve other than liquid crystal may be used, or a reflective light valve may be used. Examples of such light valves include reflective liquid crystal light valves and digital micro mirror devices. In addition, the structure of the projection device may be appropriately changed according to the type of light valve used.

[0112] Furthermore, the light source can also be applied to a light source device of a scanning type image display device having a scanning unit which is an image forming device that displays an image of a desired size on a display surface by scanning light from a light source on a screen.

[0113] The light-emitting device of the above embodiment can also be used in devices other than projectors. In applications other than projectors, there are, for example, smart glasses, indoor and outdoor lighting, display backlights, laser printers, scanners, vehicle-mounted lights, sensors using light, light sources for communication equipment, and the like. In the case of using the light-emitting device of the above embodiment as a sensor, regions with different wavelength sensitivities and a readout circuit (ROIC) can also be formed simultaneously on the same substrate. In addition, the light-emitting device of the above embodiment can also be applied to light-emitting elements of an LED display that displays images by arranging tiny light-emitting elements in an array. In addition, an LED display to which the light-emitting device of the above embodiment is applied can be used as a display device for smart glasses.

[0114] The above-mentioned embodiment and modification examples are examples, and the present invention is not limited thereto. For example, each embodiment and each modification example may be appropriately combined.

[0115] The present invention includes structures that are substantially the same as the structures described in the embodiments, such as structures with the same functions, methods and results, or structures with the same purposes and effects. In addition, the present invention includes structures obtained by replacing non-essential parts of the structures described in the embodiments. In addition, the present invention includes structures that can play the same role and effect as the structures described in the embodiments, or structures that can achieve the same purpose. In addition, the present invention includes structures obtained by adding known technologies to the structures described in the embodiments.

[0116] The following contents are derived from the above-mentioned embodiments and modifications.

[0117] One embodiment of a light emitting device has:

[0118] substrate;

[0119] A transistor, which is disposed on the substrate;

[0120] a light emitting element disposed on the substrate; and

[0121] a wiring electrically connecting the transistor and the light emitting element,

[0122] The transistor has:

[0123] a first impurity region disposed on the substrate;

[0124] a second impurity region provided in the substrate, the conductivity type of the second impurity region being the same as that of the first impurity region; and

[0125] a gate for controlling a current between the first impurity region and the second impurity region,

[0126] The light emitting element includes a laminate having a plurality of columnar portions.

[0127] Each of the plurality of columnar portions has:

[0128] A first semiconductor layer;

[0129] a second semiconductor layer having a conductivity type different from that of the first semiconductor layer; and

[0130] a light emitting layer disposed between the first semiconductor layer and the second semiconductor layer,

[0131] The first semiconductor layer is disposed between the substrate and the light emitting layer.

[0132] The wiring is provided in a third impurity region of the substrate,

[0133] The stacked body is arranged in the third impurity region,

[0134] The conductivity type of the third impurity region is the same as the conductivity type of the first semiconductor layer,

[0135] The third impurity region is electrically connected to the first semiconductor layer.

[0136] The third impurity region is continuous with the first impurity region.

[0137] According to this light-emitting device, it is possible to achieve miniaturization compared to the case where metal wiring is used as wiring for electrically connecting the transistor and the light-emitting element.

[0138] In one embodiment of the light emitting device,

[0139] The third impurity region may have a depth greater than a depth of the first impurity region.

[0140] According to this light emitting device, even if crystal defects due to stress of the strain relaxation layer occur in the third impurity region, the difference between the resistance of the first impurity region and the resistance of the third impurity region can be reduced.

[0141] In one embodiment of the light emitting device,

[0142] When viewed from a stacking direction of the first semiconductor layer and the light emitting layer, the area of ​​the third impurity region may be larger than an area of ​​the stacked body.

[0143] According to this light-emitting device, the stacked body can be arranged only in the third impurity region.

[0144] In one embodiment of the light emitting device,

[0145] The stacked body may include a strain relaxation layer disposed between the substrate and the first semiconductor layer.

[0146] The lattice constant of the strain relaxation layer is a value between the lattice constant of the substrate and the lattice constant of the first semiconductor layer.

[0147] According to this light emitting device, the strain generated in the first semiconductor layer can be reduced compared to a case where the strain relaxation layer is not provided.

[0148] In one embodiment of the light emitting device,

[0149] The light-emitting device may include a passivation film covering the transistor.

[0150] According to this light-emitting device, compared with a case where a passivation film is not provided, damage to the transistor due to heat during formation of the light-emitting element can be reduced.

[0151] In one embodiment of the light emitting device,

[0152] The substrate may include a well having a conductivity type different from that of the first impurity region.

[0153] The first impurity region, the second impurity region, and the third impurity region are provided in the well.

[0154] According to this light-emitting device, compared with a case where no well is provided, the insulation between the substrate and the first impurity region, the second impurity region, and the third impurity region can be improved.

[0155] One embodiment of a projector includes one embodiment of the above-mentioned light emitting device.

Claims

1. A light emitting device, comprising: substrate; A transistor, which is disposed on the substrate; a light emitting element disposed on the substrate; and a wiring electrically connecting the transistor and the light emitting element, The transistor has: a first impurity region disposed on the substrate; a second impurity region disposed in the substrate, the conductivity type of the second impurity region being the same as that of the first impurity region; as well as a gate for controlling a current between the first impurity region and the second impurity region, The light emitting element includes a laminate having a plurality of columnar portions. Each of the plurality of columnar portions has: A first semiconductor layer; a second semiconductor layer, the conductivity type of the second semiconductor layer being different from that of the first semiconductor layer; as well as a light emitting layer disposed between the first semiconductor layer and the second semiconductor layer, The first semiconductor layer is disposed between the substrate and the light emitting layer. The wiring is provided in a third impurity region of the substrate, The stacked body is arranged in the third impurity region, The conductivity type of the third impurity region is the same as the conductivity type of the first semiconductor layer, The third impurity region is electrically connected to the first semiconductor layer. The third impurity region is continuous with the first impurity region, The substrate has a first element isolation region on the side of the second impurity region opposite to the gate, and has a second element isolation region on the side of the third impurity region opposite to the gate. The light emitting device further comprises: a first interlayer insulating layer provided on a side of the first element isolation region, the transistor, and the second element isolation region opposite to the substrate; a second interlayer insulating layer provided on a side of the first interlayer insulating layer opposite to the substrate; a first conductive member electrically connected to the second impurity region via a first through hole provided in the first interlayer insulating layer; a second conductive member electrically connected to the gate via a second through hole provided in the first interlayer insulating layer; a third conductive member electrically connected to the first impurity region via a third through hole provided in the first interlayer insulating layer; a fourth conductive member electrically connected to the first conductive member via a fourth through hole provided in the second interlayer insulating layer; and a fifth conductive member electrically connected to the third conductive member via a fifth through hole provided in the second interlayer insulating layer, The second interlayer insulating layer has a through hole in a region overlapping with the laminated body in a plan view.

2. The light emitting device according to claim 1, wherein: The depth of the third impurity region is greater than the depth of the first impurity region.

3. The light emitting device according to claim 2, wherein: When viewed from a stacking direction of the first semiconductor layer and the light emitting layer, an area of ​​the third impurity region is larger than an area of ​​the stacked body.

4. The light emitting device according to any one of claims 1 to 3, wherein: The stacked body has a strain relaxation layer disposed between the substrate and the first semiconductor layer. The lattice constant of the strain relaxation layer is a value between the lattice constant of the substrate and the lattice constant of the first semiconductor layer.

5. The light emitting device according to any one of claims 1 to 3, wherein: The substrate has a well having a conductivity type different from that of the first impurity region. The first impurity region, the second impurity region, and the third impurity region are provided in the well.

6. A projector, wherein: This projector has the light emitting device according to any one of claims 1 to 5.

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