A storage system and data cross method

Abstract

The application discloses a storage system and a data cross method, relates to the technical field of optical transmission networks, and aims to solve the problem of physical line congestion in the data cross process of the prior art. The storage system comprises control logic (101), a write control interface (103) and a read control interface (104) coupled with a memory (102), the storage area of the memory (102) comprises a first page and a second page, and the control logic (101) is used for: based on the ping-pong use of the first page and the second page, writing data input in a time division form into the storage area through the write control interface (103) and outputting data included in the storage area in a time division form through the read control interface (104), so as to complete the cross of data within a preset time slot. The depth of the first page and the second page is equal to the preset time slot, so that the cross of data can be realized with the smallest storage area, and the advantages of good physical realization and the most saved resources are achieved.

Description

TECHNICAL FIELD

[0001] The present application relates to the optical transmission network technical field, and particularly relates to a storage system and a data cross method. BACKGROUND

[0002] With the rapid development of data services, new requirements are put forward for the optical transport network (OTN) of an operator, which requires the OTN to provide massive bandwidth to adapt to such growth, and to perform faster and more flexible service scheduling, and to perfect convenient network maintenance and management to adapt to the needs of services. Based on the multiplexing and cross function of the optical channel data unit (ODU), the OTN equipment can cross and convert low-speed small-granularity ODU service data into high-speed large-granularity ODU service data, so as to realize flexible scheduling and protection of large-granularity data. The high-speed cross granularity has higher cross efficiency, so that the OTN equipment can realize greater cross connection capability, thereby reducing the cost of the OTN equipment.

[0003] In the OTN equipment of the prior art, a register group is usually used to buffer the data to be crossed, and finally the data after the cross is completed is output. However, with the continuous increase of the OTN transmission service bandwidth, the register group required by the scheme of using the register group to buffer the data to be crossed is larger and larger, so that the area resource consumption is larger and larger; in addition, a large number of selector devices (MUX) and physical connections are introduced when the data to be crossed is crossed, which will cause physical congestion and exist physical implementation problems, and can no longer adapt to the subsequent larger multiplexing and cross capacity scenarios. SUMMARY

[0004] The present application provides a storage system and a data cross method, which are used to solve the problem of physical line congestion in the data cross process of the prior art, and can be applied to larger multiplexing and cross capacity scenarios.

[0005] To achieve the above-mentioned purpose, the embodiments of the present application adopt the following technical solutions:

[0006] In a first aspect, a storage system is provided, which includes control logic, and a write control interface and a read control interface coupled with a memory, a storage area in the memory including a first page and a second page, the control logic being configured to: set the first page as writable only and the second page as read only; write data into the first page through the write control interface and read data in the second page through the read control interface in a specified time slot; when a number of the specified time slots reaches a preset number of time slots, set the first page as read only and the second page as writable only; read data from the first page through the read control interface and write data into the second page through the write control interface in a next round of the specified time slot.

[0007] In the above technical solution, the first page and the second page are set as read only or writable only in a ping-pong manner, data is written into the page set as writable only through the write control interface and data in the page set as read only is read out through the read control interface in a specified time slot, so that the first page and the second page are used in a ping-pong manner to realize cross of data. Compared with the register group cache mode in the prior art, the method greatly reduces the introduced selector and physical connection, thereby solving the problem of physical congestion in the prior art, and can be further applied to a scenario with larger multiplexing cross capacity.

[0008] In a possible implementation manner of the first aspect, depths of the first page and the second page are equal. In the above possible implementation manner, the data amount of the written data and the read data in the specified time slot is consistent, and when the depths of the first page and the second page are equal, the first page and the second page can support the data amount of the written data and the read data in the specified time slot when set as read only or writable only, thereby avoiding the problem of waste of page storage space due to unequal capacities of the first page and the second page.

[0009] In a possible implementation manner of the first aspect, depths of the first page and the second page are equal to a preset number of time slots. In the above possible implementation manner, when the specified time slot reaches the preset number of time slots, the data amount of the written data and the read data is consistent, and the storage space of each page needs to be greater than or equal to the data amount, and when the depths of the first page and the second page are equal to the preset number of time slots, the storage space of the first page and the second page can be reduced to the maximum, thereby saving the storage space of the memory.

[0010] In a possible implementation of the first aspect, the control logic is further configured to set a storage area in the memory, the storage area including the first page and the second page. In the possible implementation, the control logic can flexibly set the storage space of the first page and the second page according to actual needs, so that the first page and the second page can meet the needs of different cross capacities, and the performance of the storage system is improved.

[0011] In a possible implementation of the first aspect, for each time slot in the specified time slots, the data in the second page corresponding to the time slot includes N output data units; and before reading out the data in the second page, the control logic is further configured to determine a second column address common to the N output data units in the second page; and the control logic is specifically configured to read out the N output data units from the second page according to the second column address. In the possible implementation, the provided manner can realize time-division continuous reading out of data.

[0012] In a possible implementation of the first aspect, for each write data unit, the control logic is further specifically configured to: determine the output time slot corresponding to the write data unit according to a first configuration relationship, the first configuration relationship being used to indicate the relationship between each write data unit of the N write data units and the output time slot; determine the first column address of the write data unit in the first page according to the output time slot corresponding to the write data unit, the depth of the first page, and the first page indication; and determine the row address in the idle state in the plurality of storage units corresponding to the first column address of the write data unit as the first row address corresponding to the write data unit, and the first row addresses of the N write data units are different from each other. In the possible implementation, a manner of determining the first column address and the first row address of each write data unit is provided, and through the manner, the input data can be time-division continuously written.

[0013] In a possible implementation of the first aspect, for each time slot in the specified time slots, the data in the second page corresponding to the time slot includes N output data units; and before reading out the data in the second page, the control logic is further configured to determine a second column address common to the N output data units in the second page; and the control logic is specifically configured to read out the N output data units from the second page according to the second column address. In the possible implementation, the provided manner can realize time-division continuous reading out of data.

[0014] In a possible implementation of the first aspect, the control logic is further configured to determine a second column address shared by the N output data units in the second page according to a column address and a second page indication of the data read out from a previous time slot of the time slot. In the possible implementation, a simple and effective manner of determining the second column address is provided.

[0015] In a possible implementation of the first aspect, the control logic is further configured to determine position information of the N output data units according to a second configuration relationship, the position information being used to indicate an arrangement order of the N output data units when output, and the second configuration relationship being used to indicate the arrangement order of the N output data units corresponding to the same time slot when output; and sort and output the N output data units read out according to the position information. In the possible implementation, when the control logic outputs the N output data units of each time slot, the N output data units can be sorted and output according to actual needs, so that the ordered output of the data units is realized.

[0016] In a possible implementation of the first aspect, the storage region includes at least 2N-1 RAM blocks, and the first page and the second page each occupy half of the 2N-1 RAM blocks, for example, the first page occupies a high address region of the 2N-1 RAM blocks, and the second page occupies a low address region of the 2N-1 RAM blocks. In the possible implementation, the data written in each time slot includes N data units, the maximum number of write conflicts between the N data units of the same time slot is N-1, the maximum number of write conflicts between the N data units at the same column address of different time slots is N-1, and when the storage region includes at least 2N-1 RAM blocks, write conflicts can be effectively avoided, and data crossing can be realized with the least number of RAM blocks.

[0017] In a possible implementation of the first aspect, a data bit width of each storage unit in the storage region is greater than or equal to a data bit width of the data unit. In the possible implementation, when the data bit width of each storage unit is equal to the data bit width of the data unit, each data unit occupies exactly one storage unit, and when the data bit width of each storage unit is greater than the data bit width of the data unit, the position information and other information of the data unit can also be stored in the storage unit.

[0018] In a second aspect, a data cross method is provided, which is applied to a storage system. The storage system comprises control logic, a write control interface and a read control interface coupled with a memory. The memory comprises a first page and a second page. The method comprises: setting the first page as write-only and setting the second page as read-only; writing data into the first page through the write control interface and reading data from the second page through the read control interface in a specified time slot; setting the first page as read-only and setting the second page as write-only when a number of specified time slots reaches a preset number of time slots; reading data from the first page through the read control interface and writing data into the second page through the write control interface in a next round of specified time slots.

[0019] In a possible implementation of the second aspect, depths of the first page and the second page are equal.

[0020] In a possible implementation of the second aspect, depths of the first page and the second page are equal to the preset number of time slots.

[0021] In a possible implementation of the second aspect, the method further comprises: setting a storage area in the memory, the storage area comprising the first page and the second page.

[0022] In a possible implementation of the second aspect, for each time slot in the specified time slots, the data written into the first page in the time slot comprises N write data units; before the data is written into the first page, the method further comprises: determining a first column address and a first row address of each write data unit in the N write data units in the first page, the first row addresses of the N write data units being different from each other, because a block of RAM can only write one data unit in one clock cycle, so the row addresses are different from each other; accordingly, the data is written into the first page, comprising: writing the N write data units into the first page according to the first column address and the first row address of each write data unit in the N write data units.

[0023] In a possible implementation of the second aspect, the determination of the first column address and the first row address of each write data unit in the N write data units in the first page comprises: for each write data unit, determining a corresponding output time slot according to a first configuration relationship, the first configuration relationship being used to indicate a relationship between each write data unit in the N write data units and the output time slot; determining the first column address of the write data unit in the first page according to the corresponding output time slot of the write data unit, the depth of the first page and the first page indication; determining a row address in a plurality of storage units corresponding to the first column address of the write data unit as the first row address of the write data unit, and the first row addresses of the N write data units being different from each other.

[0024] In a possible implementation of the second aspect, for each of the specified time slots, the data in the second page corresponding to the time slot includes N output data units; and before the data in the second page is read out, the method further includes: determining a second column address shared by the N output data units in the second page; and accordingly, the reading out of the data in the second page includes: reading out the N output data units from the second page at a time according to the second column address.

[0025] In a possible implementation of the second aspect, the determining of the second column address shared by the N output data units in the second page includes: determining the second column address shared by the N output data units in the second page according to a column address of reading out data of a previous time slot of the time slot and a second page indication.

[0026] In a possible implementation of the second aspect, the method further includes: determining position information of the N output data units according to a second configuration relationship, the position information being used to indicate an arrangement order of the N output data units when outputting, and the second configuration relationship being used to indicate the arrangement order of the N output data units corresponding to the same time slot when outputting; and sorting and outputting the read-out N output data units according to the position information.

[0027] In a possible implementation of the second aspect, the storage region includes at least 2N-1 RAM blocks, and the first page and the second page occupy half of the 2N-1 RAM blocks respectively, for example, the first page occupies a high address region of the 2N-1 RAM blocks, and the second page occupies a low address region of the 2N-1 RAM blocks.

[0028] In a possible implementation of the second aspect, a data bit width of each storage unit in the memory is greater than or equal to a data bit width of the data unit.

[0029] It can be understood that any one of the data cross methods, computer storage media or computer program products provided above can be applied to the storage system provided above, and thus the beneficial effects achieved can refer to the beneficial effects of the corresponding storage system provided above, which will not be described here again. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figure 1 A structural schematic diagram of a storage system provided for an embodiment of the present application;

[0031] Figure 2 A flowchart of a data cross method provided for an embodiment of the present application;

[0032] Figure 3 A schematic diagram of a first page and a second page provided for an embodiment of the present application;

[0033] Figure 4 A use schematic diagram of a first page and a second page provided for an embodiment of the present application;

[0034] Figure 5 Another use schematic diagram of a first page and a second page provided for an embodiment of the present application;

[0035] Figure 6 A structure schematic diagram of a control logic provided for an embodiment of the present application;

[0036] Figure 7 Another structure schematic diagram of a control logic provided for an embodiment of the present application;

[0037] Figure 8 A structure schematic diagram of an ODUCn frame provided for an embodiment of the present application;

[0038] Figure 9 A schematic diagram of a cross matrix provided for an embodiment of the present application. DETAILED DESCRIPTION

[0039] In the present application, "at least one" means one or more, and "multiple" means two or more. "And / or" describes the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B, which can represent the following three cases: A exists alone, A and B exist together, and B exists alone, where A and B can be singular or plural. "At least one of the following" or similar expressions means any combination of these items, including any combination of single or multiple items. For example, at least one of a, b or c can represent a, b, c, a-b, a-c, b-c or a-b-c, where a, b and c can be single or multiple. In addition, in the embodiments of the present application, "first", "second", etc. do not limit the quantity and execution order.

[0040] It should be noted that in the present application, "exemplary" or "for example" is used to represent an example, illustration or description. Any embodiment or design scheme described as "exemplary" or "for example" in the present application should not be interpreted as more preferred or more advantageous than other embodiments or design schemes. Rather, the use of "exemplary" or "for example" is intended to present the relevant concept in a specific manner. In the present application, "coupling" can be understood as direct connection or indirect connection, for example, A is coupled to B, which can mean that A is directly connected to B or A is indirectly connected to B.

[0041] Figure 1A structural diagram of a storage system is provided in the embodiments of the present application. The storage system comprises: control logic 101, and a write control interface 103 and a read control interface 104 coupled with a memory 102. The write control interface 103 can be a write interface, and the read control interface 104 can be a read interface. The memory 102 can be located in the storage system or outside the storage system, Figure 1 For example, the memory 102 is located in the storage system.

[0042] The control logic 101 can be used to control the access to the memory 102 (including read control and write control, etc.), and manage the storage space of the memory 102, etc. For example, the control logic 101 can be used to set a storage area in the memory 102. The storage area can comprise a first page and a second page. The control logic 101 can further set the read and write of the first page and the second page, and allocate a storage address for the written data or obtain a storage address of the data stored in the memory 102, etc.

[0043] Optionally, the control logic 101 in the above storage system can be a processor or a controller, or a software program in the processor, or a combination of the processor, the controller and / or the software program. When the control logic 101 is the processor or the software program in the processor, the control logic 101 and the memory 102 can be separate chips. When the control logic 101 is the controller, the control logic 101 and the memory 102 can be integrated together or be separate chips. In actual applications, the processor can be a central processing unit, a general-purpose processor, a digital signal processor, a neural network processor, an application-specific integrated circuit, a field programmable gate array or other programmable logic device, a transistor logic device, a hardware component or any combination thereof. The controller can be a memory controller, etc.

[0044] Based on the storage system shown in Figure 1 The embodiments of the present application provide a data cross method, as shown in Figure 2 The method can comprise the following steps.

[0045] S201: The control logic 101 sets a storage area in the memory 102. The storage area comprises a first page and a second page.

[0046] The memory 102 can be a memory with read-write function. For example, the memory 102 can be a random access memory (RAM). The RAM can have at least one read interface and at least one write interface. When there is only one read interface and one write interface, the RAM can be referred to as a two port RAM (TPRAM). The storage area can be all storage areas corresponding to the memory 102 or part of the storage areas corresponding to the memory 102. In the storage area, the first page and the second page can occupy continuous storage spaces respectively. Of course, the first page and the second page can also occupy discontinuous storage spaces. In this embodiment of this application, the first page and the second page occupy continuous storage spaces as an example.

[0047] For example, the storage area includes 15 RAM blocks, each of which has a depth of 18, and the depths of the first page and the second page are the same and equal to 9. As shown in FIG. 2, the storage area can be as shown in FIG. 2. Figure 3 Figure 3 In this embodiment, the address corresponding to the depth of each RAM block is used as the column address of the storage area. The column address range is col_add_0 to col_add_17. The address corresponding to each of the 15 RAM blocks is used as the row address of the storage area. The row address range is row_add_0 to row_add_14. Figure 3 Each small square in FIG. 2 can be referred to as a storage unit. Each storage unit can correspond to a row address and a column address.

[0048] It should be noted that, Figure 3 In this embodiment, the first page occupies the high address range in the column address (that is, the column address range occupied by the first page is col_add_9 to col_add_17), and the second page occupies the low address range in the column address (the column address range occupied by the second page is col_add_0 to col_add_8). Of course, the first page can also occupy the low address range in the column address, and the second page can occupy the high address range in the column address. This embodiment of this application does not make a specific limitation.

[0049] S202: The control logic 101 sets the first page as write-only and sets the second page as read-only.

[0050] The read-write of the first page and the second page can be set by the control logic 101. After the first page is set as write-only, data can only be written into the first page. After the second page is set as read-only, data can only be read from the second page. ​

[0051] S203: The control logic 101 writes data into the first page through the write control interface 103 and reads data in the second page through the read control interface 104 in the specified time slot.

[0052] The specified time slot can be continuous time slots or discrete time slots. In the data cross process, the data to be crossed is input in time division form. Here, the data written into the first page by the control logic 101 in the specified time slot is the data to be crossed input in time division form. Meanwhile, the crossed data is also output in time division form. Here, the data read from the second page by the control logic 101 in the specified time slot is the crossed data output in time division form. The process of writing data into the first page in the specified time slot is the process of crossing the data to be crossed input in time division form.

[0053] For each time slot in the specified time slot, the data written into the first page corresponding to the time slot can be referred to as a beat data. The written beat data includes N write data units, and N is an integer greater than 1. The control logic 101 can write N write data units into the first page according to the first column address and the first row address of each write data unit in the N write data units corresponding to each time slot in the specified time slot. Here, the control logic 101 writes into the first page in units of beat data in each time slot, that is, the control logic 101 simultaneously writes N write data units in the beat data corresponding to each time slot into the first page. The write data unit here can be understood as a written data unit. Similarly, the output data unit in the following can be understood as an output data unit. The write data unit and the output data unit are essentially data units. The concepts of write data unit and output data unit are introduced only for convenience of description and distinction, and do not limit the embodiments of the present application.

[0054] It should be noted that the first column address and the first row address of each write data unit in the N write data units corresponding to each time slot can be obtained by the control logic 101 in advance. The process of obtaining the first column address and the first row address of each write data unit in the N write data units can be referred to the related description in S203a below.

[0055] For example, assuming that N is equal to 8, the specified time slot includes two time slots TS0 and TS1, the 8 write data units corresponding to TS0 written into the first page are 0 to 7, and the 8 write data units corresponding to TS1 written into the first page are 8 to 15, the data written into the first page in TS0 and TS1 can be shown as the input data in Figure 4 Figure 3 ​Taking the first page as an example, within TS0, if the first column address corresponding to write data units 0 to 6 is col_add_9 and the corresponding row addresses are row_add_0 to row_add_6 respectively, and the first column address corresponding to write data unit 7 is col_add_17 and the corresponding row address is row_add_7, then control logic 101 writes the eight write data units 0 to 7 to the first page. Within TS1, if the first column address corresponding to write data units 8 to 14 is col_add_10 and the corresponding row addresses are row_add_0 to row_add_6 respectively, and the first column address corresponding to write data unit 15 is col_add_17 and the corresponding row address is row_add_8, then control logic 101 writes the eight write data units 8 to 15 to the first page. The first page after writing write data units 0 to 7 and 8 to 15 can be viewed as follows: Figure 4 As shown on the first page of the document.

[0056] For each time slot within a specified time slot, the data read from the second page corresponding to that time slot can be called a "one-shot data," which includes N output data units. Control logic 101, within each specified time slot, can read the N output data units corresponding to that time slot from the second page based on the second column address of the second page. Furthermore, control logic 101 can also sort these N output data units according to their position information before outputting them. The N output data units corresponding to each time slot share a single second column address in the second page, and the position information corresponding to the N written data units is used to indicate the output order of these N output data units. Specifically, control logic 101 reads data from the second page in units of one-shot data within each time slot; that is, control logic 101 reads the N output data units corresponding to each time slot simultaneously.

[0057] It should be noted that the addresses and position information of the N output data units corresponding to each time slot in the second page can be obtained in advance by the control logic 101. The process of obtaining the second column address and position information can be found in the relevant description in S203b below.

[0058] For example, with Figure 3 Taking the second page as an example, assuming N equals 8, the specified time slots include two time slots, TS0 and TS1, the eight output data units corresponding to TS0 are 0, 2, 4, 6, 8, 10, 12, and 14, and the second column address shared in the second page is col_add_0, and the eight output data units corresponding to TS1 are 1, 3, 5, 7, 9, 11, 13, and 15, and the second column address shared in the second page is col_add_1, then the second page can be configured as follows: Figure 4If the position information of the 8 output data units corresponding to TS0 indicates the order as 14, 12, 10, 8, 6, 4, 2, 0, in TS0, the control logic 101 can read out 0, 2, 4, 6, 8, 10, 12, and 14 from the second page according to col_add_0, sort them as 14, 12, 10, 8, 6, 4, 2, 0, and output them; if the position information of the 8 output data units corresponding to TS1 indicates the order as 15, 13, 11, 9, 7, 5, 3, 1, in TS1, the control logic 101 can read out 1, 3, 5, 7, 9, 11, 13, and 15 from the second page according to col_add_1, sort them as 15, 13, 11, 9, 7, 5, 3, 1, and output them. The output data of the control logic 101 after sorting in TS0 and TS1 can be seen from the output data in Figure 4

[0059] It should be noted that the above description of the writing data units and the output data units is only for facilitating the description of the writing data and the output data, and the writing data units and the output data units are not essentially different and can be both referred to as data units; similarly, the above description of the first column address, the first row address, and the second column address is also only for facilitating the description of the storage addresses of the writing data and the output data. The description of the writing data units, the output data units, the first column address, the first row address, and the second column address below can be understood in the same way. Figure 4

[0060] In addition, the above writing data units and output data units are only for facilitating the description of the writing data and the output data, and the writing data units and the output data units are not essentially different and can be both referred to as data units; similarly, the above first column address, first row address, and second column address and the like are also only for facilitating the description of the storage addresses of the writing data and the output data. The description of the writing data units, the output data units, the first column address, the first row address, and the second column address below can be understood in the same way.

[0061] S204: When the number of the specified time slots reaches the preset number of time slots, the control logic 101 sets the first page as read-only, reads out data from the first page through the readout control interface 104 in the next round of the specified time slots, sets the second page as write-only, and writes data into the second page through the writing control interface 103 in the next round of the specified time slots.

[0062] In each time slot, the data read out from the first page can be a beat of data, and the beat of data can include N output data units; in each time slot, the data written into the second page can also be a beat of data, and the beat of data can include N writing data units.

[0063] ​​Specifically, when the number of specified time slots reaches the preset number of time slots, the control logic 101 has written the preset number of time slots of data in the first page, sets the first page as read-only, and can read out the data written in the last round of specified time slots from the first page in the next round of specified time slots; at the same time, when the number of specified time slots reaches the preset number of time slots, the control logic 101 has read out the preset number of time slots of data from the second page, sets the second page as write-only, and can write the data corresponding to the next round of specified time slots into the second page in the next round of specified time slots. Further, when the number of specified time slots reaches the preset number of time slots, the control logic 101 can return to S202 for continuous execution. In this way, the control logic 101 sets one of the first page and the second page as read-only and the other as write-only in a ping-pong processing manner, and can read out the data of the second page when writing data in the first page and read out the data of the first page when writing data in the second page, thereby improving the efficiency of data multiplexing.

[0064] Optionally, when the number of specified time slots reaches the preset number of time slots, the control logic 101 can also clear the data in the second page, so as to facilitate writing data into the second page in the next round of specified time slots. Similarly, when the control logic 101 sets the first page as read-only and reads out data from the first page in the next round of specified time slots, the data in the first page can also be cleared.

[0065] It should be noted that the process of reading out data from the first page in the next round of specified time slots by the control logic 101 is similar to the process of reading out data from the second page in S203, and the process of writing data into the second page in the next round of specified time slots is similar to the process of writing data into the first page in S203. For details, refer to the related description in S203, and the embodiments of the present application will not be repeated here.

[0066] In addition, the preset number of time slots can be set by a person skilled in the art according to actual needs in advance, or configured by the control logic 101, and the preset number of time slots can be fixed or different preset numbers of time slots can be set according to different application requirements.

[0067] Optionally, the depth of the first page and the second page can be equal to the preset number of time slots. When the depth of the first page and the second page is equal to the preset number of time slots, the size of the storage area occupied by the first page and the second page can be set according to the preset number of time slots without affecting use, so that the storage space of the memory 102 can be saved.

[0068] For example, when the depth of the first page and the second page is equal to the preset number of time slots T and T=9 and N=8, based on the above, when the number of specified time slots reaches the preset number of time slots T, the first page and the second page can be as follows: Figure 4 ​Figure 5 The data written in the first page is shown as input data in Figure 5 The data written in the first page is shown as input data in Figure 5 The data written in the first page is shown as input data in

[0069] Further, in the above S203, for each time slot in the specified time slots, before writing the N write data units corresponding to the time slot into the first page, the method further comprises: S203a.

[0070] S203a: the control logic 101 determines a first column address and a first row address of each write data unit in the N write data units in the first page, and the first row addresses of the N write data units are different from each other.

[0071] The first page can include a plurality of storage units, each storage unit can correspond to a first column address and a first row address, and the control logic 101 can first allocate a storage unit for each write data unit in the N write data units before writing the N write data units included in the beat data into the first page, that is, allocate a first row address and a first column address for each write data unit, and then write the N write data units into the corresponding storage units according to the first row address and the first column address allocated for each write data unit.

[0072] In addition, the control logic 101 can allocate addresses to the N write data units one by one, that is, the control logic 101 allocates addresses to one write data unit in the N write data units at a time, and completes the address allocation of the N write data units in N times. The first column addresses allocated by the control logic 101 to the N write data units can be the same or different (specifically related to the configuration of the time slot for outputting each write data unit), and the first row addresses allocated to the N write data units are different from each other. Optionally, the control logic 101 can allocate the corresponding first row addresses to the N write data units in the order from large to small.

[0073] For example, in the case of Figure 5As shown in the TS0, the control logic 101 allocates the first column address col_add_9 for 0 to 6 of the 8 write data units corresponding to TS0, and allocates the first row address row_add_0 to row_add_6 in turn, allocates the first column address col_add_17 for 7 of the 8 write data units corresponding to TS0, and allocates the first row address row_add_7.

[0074] Specifically, the control logic 101 determines the first column address of each write data unit in the first page, which can be: for each write data unit, determining the output time slot corresponding to the write data unit according to the first configuration relationship, the first configuration relationship being used to indicate the relationship between each write data unit in the N write data units and the output time slot; determining the first column address of the write data unit in the first page according to the output time slot corresponding to the write data unit, the depth of the first page and the first page indication.

[0075] The output time slot corresponding to the write data unit can be the time slot for outputting the write data unit. The output time slot corresponding to each write data unit in the N write data units can be configured in advance, that is, the first configuration relationship can be configured in advance, and then the output time slot corresponding to each write data unit in the N write data units can be determined according to the first configuration relationship. For example, with N = 8, the first configuration relationship can be used to indicate that the output time slot corresponding to the first 7 write data units of the 8 write data units included in a beat data is slot_i, and the output time slot corresponding to the 8th write data unit is slot_k, i≠k.

[0076] In addition, since the column address ranges corresponding to the first page and the second page are different, and the first page and the second page are used in a ping-pong manner, in order to ensure that the allocated first column address is within the column address range corresponding to the first page or the second page, the page indication can be used to indicate the first page and the second page. The first page indication is used to indicate the first page, and the second page indication is used to indicate the second page. Optionally, the page indication can be represented by a one-bit binary number, for example, when the binary number is 1, the page indication is the first page indication, and when the binary number is 0, the page indication is the second page indication.

[0077] For example, with N = 8, the first configuration relationship can be used to indicate that the output time slot corresponding to the first 7 write data units of the 8 write data units included in a beat data is slot_i, and the output time slot corresponding to the 8th write data unit is slot_k, i≠k. Figure 5For example, if the preset time slot number T is equal to the depth of the first page and the second page and is equal to 9, the page indication is represented as blk_sel, blk_sel = 1 represents the first page indication, and blk_sel = 0 represents the second page indication, when the output time slot corresponding to a write data unit is T1, the control logic 101 can determine the first column address of the write data unit in the first page according to the formula col_add_(T1+T×blk_sel). For example, if the output time slot corresponding to the write data unit 7 in TS0 is T1 = 8, the first column address of the write data unit 7 in the first page is col_add_(8+9×1) = col_add_17. Figure 5 For example, if the output time slot corresponding to the write data unit 7 in TS0 is T1 = 8, the first column address of the write data unit 7 in the first page is col_add_(8+9×1) = col_add_17.

[0078] Specifically, the control logic 101 can determine the first row address of each write data unit in the N write data units in the first page, which can be: for each write data unit, the control logic 101 can determine the row address of the storage unit in an idle state in the plurality of storage units corresponding to the first column address of the write data unit as the first row address of the write data unit, and the first row addresses of the N write data units are different from each other.

[0079] For example, if the output time slot corresponding to the write data unit 7 in TS0 is T1 = 8, the first column address of the write data unit 7 in the first page is col_add_(8+9×1) = col_add_17. Figure 5 For example, if the output time slot corresponding to the write data unit 7 in TS0 is T1 = 8, the first column address of the write data unit 7 in the first page is col_add_(8+9×1) = col_add_17.

[0080] Similarly, in the ping-pong write-only mode of the first page and the second page, if the second page is set as write-only in the next round of specified time slots, the control logic 101 determines the first column address of each write data unit in the second page, which can be: for each write data unit, according to the first configuration relationship, determine the output time slot corresponding to the write data unit; according to the output time slot corresponding to the write data unit, the depth of the second page and the second page indication, determine the first column address of the write data unit in the second page; correspondingly, the control logic 101 determines the first row address of each write data unit in the second page, which can be: for each write data unit, the control logic 101 determines the row address of the storage unit in the idle state in the plurality of storage units corresponding to the first column address of the write data unit as the first row address of the write data unit, and the first row addresses of the N write data units are different from each other.

[0081] It should be noted that, when the second page is set as write-only, before data is written into the second page in the next round of specified time slots, the specific process of determining the first column address and the first row address of the N write data units corresponding to each time slot in the next round of specified time slots in the second page is similar to the related description of S203a above, and the embodiments of the present application will not be repeated here.

[0082] As can be known from the above related description in S203a, when data is written into the first page or the second page, the control logic 101 allocates different first row addresses to the N write data units corresponding to each time slot, and the storage units corresponding to the first row address and the first column address are in an idle state, so that when the N write data units of the same time slot are written into the first page or the second page at the same time, the occurrence of write conflict can be effectively avoided.

[0083] Wherein, taking the first page and the second page shown in Figure 3 As an example, each row address corresponds to a RAM block, and each RAM block can only allow one write data unit to write at the same time, and the storage unit that has already written the write data unit cannot write other write data units, so there are two cases of write conflict.

[0084] The first one is the write conflict between the N data units of the same time slot, and the maximum number of write conflicts is N-1, which can be effectively avoided by allocating different row addresses to the N data units of the same time slot. For example, taking the last data unit in the N data units of the same time slot as an example, the maximum number of write conflicts between the last data unit and the previous N-1 data units is N-1, and the row address of the last data unit is different from the row addresses of the previous N-1 data units. Figure 5Taking the write data unit 7 corresponding to TS0 as an example, the first row address of write data unit 7 in the first page cannot be the same as the first row addresses row_add_0 to row_add_6 corresponding to the first seven write data units 0 to 6 of TS0, so that row_add_7 can be assigned to write data unit 7.

[0085] The second type involves write conflicts between N data units at the same column address across different time slots. The maximum number of write conflicts is N-1, which can be effectively avoided by allocating row addresses to idle storage units. Since the data read in the same time slot also includes N data units, and these N data units share a single column address, meaning that for a given column address, only N data units can be stored in the corresponding storage units. Taking the last data unit among these N data units as an example, the maximum number of write conflicts between the last data unit and the preceding N-1 data units is N-1. Figure 5 Taking the write data unit 63 corresponding to TS7 as an example, the write data unit 63 cannot have the same row address (row_add_7 to row_add_13) as the six previously written data units (i.e., 7, 15, 23, 31, 39, 47, 55) under column address col_add_17, so that row_add_14 can be assigned to the write data unit 63.

[0086] Therefore, in passing Figure 5 When the storage structure of the first page and the second page shown implements data crossover, in order to completely avoid the above two types of write conflicts, it can be implemented with a maximum of 2N-1 RAM blocks. N-1 RAM blocks of the 2N-1 RAM blocks are used to resolve the write conflict in the first case, the other N-1 RAM blocks are used to resolve the write conflict in the second case, and the remaining 1 RAM block is used to write the last data unit described above.

[0087] In S203 above, for each time slot in the specified time slot, before reading the N output data units corresponding to the time slot from the second page, the method further includes: S203b.

[0088] S203b: Control logic 101 determines the address of the second column shared by N output data units on the second page.

[0089] Specifically, for the first time slot in the specified time slot, the control logic 101 can determine the smallest second column address in the second page as the second column address shared by the N output data units corresponding to the first time slot in the second page according to the second page indication; for each time slot in the specified time slot, the control logic 101 can determine the second column address shared by the N output data units corresponding to each time slot in the second page in an incremental manner from the second column address corresponding to the previous time slot.

[0090] Optionally, the control logic 101 can also determine the position information of the N output data units, which is used to indicate the arrangement order when the N output data units are output.

[0091] Specifically, for each time slot in the specified time slot, the control logic 101 can determine the position information of the N output data units corresponding to the time slot according to the second configuration relationship, which is used to indicate the arrangement order when the N output data units corresponding to the same time slot are output. The second configuration relationship can be configured in advance, for example, the second configuration relationship can be used to indicate the output bit sequence of each output data unit in the N output data units included in a beat data, and then the N output data units can be sorted and output according to the output bit sequence of each output data unit.

[0092] Similarly, in the way of setting the first page and the second page as read-only in a ping-pong manner, if the first page is set as read-only in the next round of specified time slots, in the first time slot in the next round of specified time slots, the control logic 101 can determine the smallest second column address in the first page as the second column address shared by the N output data units corresponding to the first time slot in the first page according to the first page indication; for each time slot in the specified time slot, the control logic 101 can determine the second column address shared by the N output data units corresponding to each time slot in the first page in an incremental manner from the second column address corresponding to the previous time slot. The method of determining the position information of the N output data units corresponding to each time slot in the next round of specified time slots is consistent with the related description in S203b above, and the embodiments of the present application will not be repeated here.

[0093] Further, the bit width of each data unit in the write data unit and the output data unit can be equal to the bit width of each storage unit in the memory 102, or can be less than the bit width of each storage unit in the memory 102. For example, the bit width of each data unit can be 128 bits (bit), and the bit width of each storage unit in the memory 102 can be greater than or equal to 128 bits.

[0094] When the bit width of each data unit is equal to the bit width of each storage unit in the memory 102, the second configuration relationship involved above can be stored in other storage area of the memory 102 except the first page or the second page, or stored in other memory except the memory 102. When the bit width of each data unit is less than the bit width of each storage unit in the memory 102, the position information of each data unit in the second configuration relationship involved above can be stored by the corresponding storage unit. For example, the bit width of each data unit is 128 bits, and the bit width of each storage unit in the memory 102 is 132 bits, then the position information corresponding to the data unit stored by each storage unit can be stored by 4 bits in the bit width of each storage unit.

[0095] When the data cross method provided by the embodiment of the present application is used to implement data cross, the data cross of different granularities can be implemented by configuring the number N of data units in the same time slot, the preset time slot number T and the bit width W of the data unit.

[0096] For the convenience of understanding, the technical solutions provided by the embodiments of the present application are exemplarily described below by taking the block diagram of the control logic shown in FIG. 1 as an example. Figure 6 In FIG. 1, the control logic 101 includes an address allocation calculation unit 1011, a first address cache unit 1012, a second address cache unit 1013 and a read-write control unit 1014. Figure 6

[0097] The address allocation calculation unit 1011 can be used to allocate a first column address and a first row address for the data to be written according to the first configuration relationship before the data is written into the set storage area, and determine a second column address and position information for the data to be read according to the second configuration relationship before the data is read from the set storage area. The first address cache unit 1012 is used to cache the first column address and the first row address allocated by the address allocation calculation unit 1011 for the data to be written. The second address cache unit 1013 caches the second column address and the position information determined by the address allocation calculation unit 1011 for the data to be read.

[0098] ​Specifically, after the read-write control unit 1014 sets the first page as writable and the second page as readable, when data is written into the first page in the specified time slots, for each time slot in the specified time slots, the read-write control unit 1014 can obtain the first column address and the first row address of the N data units corresponding to the time slot in the first page from the first address cache unit 1012, and then write the N data units into the first page according to the corresponding first column address and first row address; when data in the second page is read out in the specified time slots, for each time slot in the specified time slots, the read-write control unit 1014 can obtain the second column address and the position information of the N data units corresponding to the time slot in the second page from the second address cache unit 1013, and then read out the N data units corresponding to the time slot from the second page according to the second column address, and output after sorting according to the position information.

[0099] Similarly, when the number of specified time slots reaches the preset number of time slots, after the first page is set as readable and the second page is set as writable, the control logic 101 can read data from the first page in the next round of specified time slots and write data into the second page in the next round of specified time slots according to the above similar manner.

[0100] Optionally, the address allocation calculation unit 1011 can also be implemented by software, that is, the software allocates the first column address and the first row address for the written data before the data is written into the set storage area, and determines the second column address and the position information for the read data before the data is read from the set storage area. Further, the software can also cache the allocated first column address and first row address in the first address cache unit 1012 through a message passing interface (MPI), and cache the allocated second column address and position information in the second address cache unit 1013 through the MPI.

[0101] Further, by converting the read-write control in Figure 6 , the block diagram of the control logic shown in Figure 6 can also be used to implement data de-interleaving. As shown in Figure 7 , in the de-interleaving process, the read address (i.e. the second column address) in Figure 6 can be used as the write address for de-interleaving, and the outputted interleaved data is written into the storage area; the write address (i.e. the first column address and the first row address) in Figure 6 can be used as the read address for de-interleaving, and the data is read out from the storage area, thereby completing the process of data de-interleaving; and the read-write control unit 1014 in Figure 6 is replaced by the read-write control unit 2014.

[0102] Specifically, after the read-write control unit 2014 sets the second page as writable and the first page as read-only, when writing data (i.e. the data after interleaving) into the second page in the specified time slots, for each time slot in the specified time slots, the read-write control unit 2014 can obtain the second column address of the N data units corresponding to the time slot in the second page from the second address cache unit 1014, and then write the N data units into the second page according to the second column address; when reading data in the first page in the specified time slots, for each time slot in the specified time slots, the read-write control unit 2014 can obtain the first column address and the first row address of the N data units corresponding to the time slot in the first page from the first address cache unit 1013, and then read the N data units from the first page according to the corresponding first column address and first row address.

[0103] Similarly, when the number of specified time slots reaches the preset number of time slots, after setting the second page as read-only and the first page as writable, the control logic 101 can read data from the second page and write data into the first page in the next round of specified time slots according to the above similar manner.

[0104] In a possible implementation, the data interleaving method provided by the embodiment of the present application can be applied to data multiplexing, and specifically, the data after mapping of low-order optical channel data unit (ODU) frames can be multiplexed into high-order ODU frames, for example, the data after mapping of multiple service channels in time division form can be interleaved in 16 byte (Bytes) granularity according to multiplexing time slots and multiplexed into high-order ODU Cn frames by using the data interleaving method provided by the present application. When the data interleaving method provided by the present application is applied to the data multiplexing process, the data written in the specified time slots can be the data after mapping of low-order ODU frames, the written data is the data to be multiplexed, and the data output in the specified time slots can be high-order ODU frames, that is, the output data is the data after multiplexing.

[0105] It should be noted that the low-order ODU frame can refer to an ODU frame with a low rate, and the high-order ODU frame can refer to an ODU frame with a high rate. For details, refer to the related description in the G.709 protocol, which will not be described herein.

[0106] For example, Figure 8A structure diagram of a 100GB ODUCn frame is provided in the embodiments of the present application, the ODU frame includes 20 5G multiplexing time slots, i.e. TS.1 to TS.20, each of which is of 16 Bytes granularity, and the 20 5G multiplexing time slots are arranged in a cyclic interleaving manner in the payload area of the ODUCn frame. Figure 8 The corresponding bits, OPUCn tributary slots, OMFIs and TSOHs are shown in each column. Further, a plurality of 100G ODUCn frames can also constitute a group (gid), and constitute n*20 5G multiplexing time slots, where n is an integer greater than 1.

[0107] When the data multiplexing is implemented by the method provided in the present application, the data to be multiplexed can be multiplexed into the ODUCn frame in one service channel, or can be multiplexed into the ODUCn frames in a plurality of different service channels in the same group (gid), i.e. the input data is cross-connected in the data of one or more service channel ODUCn frames in the same group (gid). For example, when the data to be multiplexed is multiplexed into the ODUCn frames in three different service channels in the same group (gid), if TSA.1 to TSA.20 represent the data to be multiplexed corresponding to the 20 time slots included in each ODUCn frame in the first service channel, TSB.1 to TSB.20 represent the data to be multiplexed corresponding to the 20 time slots included in each ODUCn frame in the second service channel, and TSC.1 to TSC.20 represent the data to be multiplexed corresponding to the 20 time slots included in each ODUCn frame in the third service channel, then the multiplexed data formed by one ODUCn frame in each service channel can be as shown in Figure 9 The multiplexed data can also be referred to as a cross-connect matrix.

[0108] In the embodiments of the present application, the first page and the second page are set to be read-only or write-only in a ping-pong manner, and the data is written into the page set to be write-only through the write control interface and the data in the page set to be read-only is read out through the read control interface in the specified time slot, so that the cross-connection of the data is realized by using the first page and the second page in a ping-pong manner. Compared with the prior art, the method can greatly reduce the selector and the physical connection, thereby solving the problem of physical congestion in the prior art, and further can be applied to a larger multiplexing cross-connection capacity scenario.

[0109] The embodiments of the present application provide a storage system, which can be as shown in Figure 1 The storage system includes a control logic 101, and a write control interface 103 and a read control interface 104 coupled with a memory 102. The storage area in the memory 102 includes a first page and a second page.

[0110] In the embodiment of the present application, the control logic 101 is configured to: set the first page as writable and set the second page as read-only; in a specified time slot, write data into the first page through the write control interface 103 and read data in the second page through the read control interface 104; when the number of specified time slots reaches a preset number of time slots, set the first page as read-only and set the second page as writable; in the next round of specified time slots, read data from the first page through the read control interface 104 and write data into the second page through the write control interface 103.

[0111] Optionally, the depths of the first page and the second page are equal; and / or, the depths of the first page and the second page are equal to the preset number of time slots.

[0112] Further, the control logic 101 is further configured to: set a storage area in the memory 102, the storage area including the first page and the second page.

[0113] In a possible embodiment, for each time slot in the specified time slots, the data written into the first page corresponding to the time slot includes N write data units; before the data is written into the first page, the control logic 101 is further configured to: determine a first column address and a first row address of each write data unit in the N write data units in the first page, the first row addresses of the N write data units being different from each other; accordingly, the control logic 101 is specifically configured to: write the N write data units into the first page according to the first column address and the first row address of each write data unit in the N write data units.

[0114] Optionally, for each write data unit, the control logic 101 is further specifically configured to: determine a corresponding output time slot of the write data unit according to a first configuration relationship, the first configuration relationship being used to indicate the relationship between each write data unit in the N write data units and the output time slot; determine the first column address of the write data unit in the first page according to the corresponding output time slot of the write data unit, the depth of the first page and the first page indication; determine a row address in an idle state in a plurality of storage units corresponding to the corresponding first column address of the write data unit as the corresponding first row address of the write data unit, and the first row addresses of the N write data units being different from each other.

[0115] In another possible embodiment, for each of the specified time slots, the data in the second page corresponding to the time slot includes N output data units; before reading out the data in the second page, the control logic 101 is further configured to determine a second column address that is common to the N output data units in the second page; accordingly, the control logic is specifically configured to read out the N output data units from the second page according to the second column address. Optionally, the control logic 101 is further specifically configured to determine the second column address that is common to the N output data units in the second page according to the column address of reading out data of a previous time slot of the time slot and the second page indication.

[0116] Further, the control logic 101 is further configured to determine position information of the N output data units according to the second configuration relationship, the position information being used to indicate an arrangement order of the N output data units when output, and the second configuration relationship being used to indicate the arrangement order of the N output data units corresponding to the same time slot when output; and sort and output the read-out N output data units according to the position information.

[0117] Optionally, a data bit width of each storage unit in the memory 102 is greater than or equal to a data bit width of a data unit, the data unit including a write-in data unit or an output data unit.

[0118] It should be noted that the storage system is a device embodiment corresponding to the method embodiments described above, and the specific implementation of the control logic 101 can refer to the detailed description provided in the data cross method, which will not be described herein again.

[0119] In the embodiments of the present application, the control logic 101 sets the first page and the second page as read-only or write-only by ping-pong, writes data into the page set as write-only through the write-in control interface in the specified time slot, and reads out the data in the page set as read-only through the read-out control interface, so as to realize the cross of data by ping-pong using the first page and the second page. Compared with the prior art, the method can greatly reduce the selector device and the physical connection, thereby solving the problem of physical congestion in the prior art, and further applied to a larger multiplex cross capacity scenario.

[0120] In another embodiment of the present application, a computer readable storage medium is also provided, and the computer readable storage medium stores instructions, when a device (which can be a single-chip microcomputer, a chip or a processor, etc.) runs the instructions, the device executes the data cross method provided above. The computer readable storage medium described above can include a U disk, a mobile hard disk, a read-only memory, a random access memory, a magnetic disk or an optical disk, and various media that can store program codes.

[0121] In another embodiment of the present application, a computer program product is also provided, which comprises instructions stored in a computer readable storage medium; when a device (which can be a single-chip microcomputer, a chip, a processor, etc.) executes the instructions, the device performs the data cross method provided above. The aforementioned computer readable storage medium can include a U disk, a mobile hard disk, a read-only memory, a random access memory, a magnetic disk or an optical disk, and various media that can store program codes.

[0122] Finally, it should be noted that the above description is merely a specific implementation of the present application, but the protection scope of the present application is not limited thereto, and any change or replacement within the technical scope disclosed in the present application should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A storage system, characterized by, The storage system comprises control logic, and a write control interface and a read control interface coupled with a memory, a storage area in the memory comprises a first page and a second page, and the control logic is configured to: set the first page as writable only and the second page as read only; write data into the first page through the write control interface and read data in the second page through the read control interface in a specified time slot; when a number of specified time slots reaches a preset number of time slots, set the first page as read only and the second page as writable only; for each time slot in the specified time slots, data corresponding to the time slot in the second page comprises N output data units; before the data in the second page is read out, the control logic is further configured to determine a second column address in the second page that is shared by the N output data units; and correspondingly, the control logic is specifically configured to read out the N output data units from the second page according to the second column address. the control logic is further configured to:

2. The storage system of claim 1, wherein, set the storage area in the memory, and the storage area comprises the first page and the second page.

3. The storage system of claim 2, wherein, the storage area comprises at least 2N-1 RAM blocks, and the first page and the second page each occupy half of the 2N-1 RAM blocks.

4. The storage system according to any of claims 1-3, characterized in that, for each write data unit, the control logic is further specifically configured to: determine an output time slot corresponding to the write data unit according to a first configuration relationship, the first configuration relationship being used to indicate a relationship between each write data unit in the N write data units and an output time slot; 5. The storage system of claim 4, wherein, determine a first column address of the write data unit in the first page according to the output time slot corresponding to the write data unit, a depth of the first page, and a first page indication; 6. The storage system of claim 1, wherein, determine a first row address corresponding to the write data unit from row addresses in a plurality of storage units corresponding to the first column address of the write data unit in an idle state, and the first row addresses of the N write data units are different from each other. for each time slot in the specified time slots, the data corresponding to the time slot in the second page comprises N output data units; before the data in the second page is read out, the control logic is further configured to determine a second column address in the second page that is shared by the N output data units; and correspondingly, the control logic is specifically configured to read out the N output data units from the second page according to the second column address.

7. The storage system of any of claims 1-3, 6, wherein, the control logic is further configured to: ​ ​ 8. The storage system of claim 7, wherein, ​ According to a column address and a second page indication of reading out data of a previous time slot of the time slot, a second column address which is common to the N output data units in the second page is determined.

9. The storage system of claim 7, wherein, The control logic is further configured to: According to a second configuration relationship, position information of the N output data units is determined, the position information being used to indicate an arrangement order of the N output data units when outputting, and the second configuration relationship being used to indicate the arrangement order of the N output data units corresponding to a same time slot when outputting; According to the position information, the N output data units are sorted and outputted.

10. A data cross method, characterized by, The method is applied to a storage system, the storage system comprising control logic, and a write control interface and a readout control interface coupled with a memory, a storage area in the memory comprising a first page and a second page, the method comprising: The first page is set as write-only, and the second page is set as read-only; In a specified time slot, data is written into the first page through the write control interface, and data in the second page is read out through the readout control interface; When a specified time slot number reaches a preset time slot number, the first page is set as read-only, and the second page is set as write-only; For each time slot in the specified time slot, data written into the first page corresponding to the time slot comprises N write data units; Before the data is written into the first page, the method further comprises: determining a first column address and a first row address of each write data unit in the N write data units in the first page, the first row addresses of the N write data units being different from each other; Correspondingly, the data is written into the first page, comprising: according to the first column address and the first row address of each write data unit in the N write data units, the N write data units are written into the first page; In a next round of specified time slot, data is read out from the first page through the readout control interface, and data is written into the second page through the write control interface.

11. The method of claim 10, wherein, The depths of the first page and the second page are equal.

12. The method of claim 11, wherein, The depths of the first page and the second page are equal to the preset time slot number.

13. The method according to any one of claims 10-12, characterized in that, The method further comprises: The storage area in the memory is set, the storage area comprising the first page and the second page.

14. The method of claim 13, wherein, The storage area comprises at least 2N-1 RAM blocks, and the first page and the second page occupy half of the 2N-1 RAM blocks respectively.

15. The method of claim 10, wherein, The determination of the first column address and the first row address of each write data unit in the N write data units in the first page comprises: For each write data unit, according to a first configuration relationship, a corresponding output time slot of the write data unit is determined, the first configuration relationship being used to indicate a relationship between each write data unit in the N write data units and an output time slot; According to the corresponding output time slot of the write data unit, the depth of the first page and a first page indication, a first column address of the write data unit in the first page is determined; The row address in the idle state in the plurality of memory cells corresponding to the first column address corresponding to the write data unit is determined as the first row address corresponding to the write data unit, and the first row addresses of the N write data units are different from each other.

16. The method according to any of claims 10-12, 15, characterized by, For each time slot in the specified time slot, the data in the second page corresponding to the time slot includes N output data units; Before the data in the second page is read out, the method further includes: determining a second column address shared by the N output data units in the second page; Correspondingly, the reading out of the data in the second page includes: reading out the N output data units from the second page according to the second column address.

17. The method of claim 16, wherein, The determination of the second column address shared by the N output data units in the second page includes: According to the column address of the data read out by the last time slot of the time slot and the second page indication, the second column address shared by the N output data units in the second page is determined.

18. The method of claim 16, wherein, The method further includes: According to a second configuration relationship, position information of the N output data units is determined, the position information being used to indicate the arrangement order when the N output data units are output, and the second configuration relationship being used to indicate the arrangement order when the N output data units corresponding to the same time slot are output; According to the position information, the N output data units read out are sorted and output.

19. A computer-readable storage medium, characterized in that, The computer readable storage medium stores instructions, when the instructions run on the device, make the device execute the data cross method in any one of claims 10-18.

20. A computer program product, characterised in that, When the computer program product runs on the device, make the device execute the data cross method in any one of claims 10-18.

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