Display substrate and display device

Abstract

The present disclosure relates to a display substrate and a display device, and belongs to the field of display. The display substrate has a first transparent display area, a second transparent display area and a non-transparent display area. The display substrate comprises a plurality of first pixels and a plurality of second pixels. The plurality of first pixels are arranged in the first transparent display area, and each first pixel comprises a first light emitting device and a first pixel circuit. The first pixel circuits in the same row are electrically connected to the same first gate line, and the first pixel circuits in the same column are electrically connected to the same first data line. The second pixel comprises a second light emitting device and a second pixel circuit. The second light emitting device is located in the second transparent display area, and the second pixel circuit is located outside the first transparent display area and the second transparent display area. The second light emitting device and the second pixel circuit are electrically connected through transparent traces. The embodiments of the present disclosure can control the light emitting devices in the first transparent display area and the second transparent display area to emit light through fewer signal lines, and facilitate wiring.

Description

Technical Field

[0001] This disclosure relates to the field of displays, and more particularly to a display substrate and a display device. Background Technology

[0002] Under-display camera technology refers to placing the camera under the display screen. The area where the camera is located is a transparent display area of ​​the screen. Pixels are arranged in the transparent display area. When the screen displays an image, the transparent display area also displays the image. The camera cannot be seen from the front of the screen, and the camera is hidden, thereby increasing the screen-to-body ratio of the display. Summary of the Invention

[0003] This disclosure provides a display substrate and a display device, facilitating the arrangement of signal lines for controlling the emission of light from light-emitting devices in a transparent display area. The technical solution is as follows:

[0004] This disclosure provides a display substrate having a first transparent display area, a second transparent display area surrounding the first transparent display area, and a non-transparent display area surrounding the second transparent display area;

[0005] The display substrate includes:

[0006] Multiple first pixels, each first pixel including a first light-emitting device and a first pixel circuit electrically connected to the first light-emitting device, the multiple first pixel arrays are distributed in the first transparent display area, the first pixel circuits of the first pixels in the same row are electrically connected to the same first gate line, and the first pixel circuits of the first pixels in the same column are electrically connected to the same first data line;

[0007] Multiple second pixels, each second pixel including a second light-emitting device and a second pixel circuit, the second light-emitting device being located in the second transparent display area, the second pixel circuit being located outside the first transparent display area and the second transparent display area, and the second light-emitting device and the second pixel circuit being electrically connected through transparent traces.

[0008] In one implementation of this disclosure, the first gate line is on a different layer from the transparent trace, and the first data line is on a different layer from the transparent trace.

[0009] In one implementation of this disclosure, the difference between the number of rows and the number of columns of the first pixel is between 0 and 2.

[0010] In one implementation of this disclosure, the first gate line located within the second transparent display area is a transparent trace;

[0011] The first data line located within the second transparent display area is a transparent trace.

[0012] In one implementation of this disclosure, the display substrate further has a non-display area surrounding the non-transparent display area, and the second pixel circuit is located in the non-display area.

[0013] In one implementation of this disclosure, the ratio of the area of ​​the orthographic projection of the first transparent display area onto the surface of the display substrate to the sum of the areas of the orthographic projections of the first transparent display area onto the surface of the display substrate and the areas of the orthographic projections of the second transparent display area onto the surface of the display substrate is less than or equal to 15%.

[0014] In one implementation of this disclosure, the display substrate further includes:

[0015] Multiple third pixels are arrayed in the non-transparent display area. Each third pixel includes a third light-emitting device and a third pixel circuit electrically connected to the third light-emitting device. The area of ​​the orthographic projection of the third pixel on the surface of the display substrate is larger than the area of ​​the orthographic projection of the first pixel on the surface of the display substrate.

[0016] In one implementation of this disclosure, the number of components in the first pixel circuit is less than the number of components in the third pixel circuit, or the circuit structure of the first pixel circuit is the same as that of the third pixel circuit.

[0017] In one implementation of this disclosure, the display substrate further includes a shielding structure located in a first transparent display area, the shielding structure being configured to block light passing through the first pixel circuit from the display surface of the display substrate.

[0018] In one implementation of this disclosure, the shielding structure is a shielding layer located below the first light-emitting device, and the projection of the first pixel circuit on the surface of the display substrate is located within the projection of the shielding structure on the surface of the display substrate.

[0019] In one implementation of this disclosure, the shielding layer is a metal shielding layer.

[0020] In one implementation of this disclosure, the blocking structure is the anode of the first light-emitting device.

[0021] In one implementation of this disclosure, the plurality of transparent traces are located in different layers of the display substrate.

[0022] In one implementation of this disclosure, the film layer containing the transparent trace is located on a first side of the thin-film transistor array layer of the display substrate, and the first side is the side of the thin-film transistor array layer that is close to the display surface of the display substrate.

[0023] On the other hand, embodiments of this disclosure provide a display device, the display device including the display substrate described in any of the above aspects.

[0024] The beneficial effects of the technical solutions provided in this disclosure are:

[0025] In this embodiment, since both the first pixel circuit and the first light-emitting device are located in the first transparent display area, the traces electrically connected between the first pixel circuit and the first light-emitting device do not need to pass through the second transparent display area. Simultaneously, a scan signal is provided to the first pixel circuit of the first pixel in the same row via the same first gate line, and a data signal is provided to the first pixel circuit of the first pixel in the same column via the same first data line. Therefore, the number of signal lines electrically connected to the first pixels in the first transparent display area is equal to the sum of the number of rows and columns of the first pixels. The number of transparent traces in the second transparent display area is equal to the number of second pixels. Therefore, the number of signal lines used to control the light emission of the light-emitting device in the transparent display area is equal to the sum of the number of first gate lines, first data lines, and transparent traces.

[0026] Given a fixed number of signal lines extending into the transparent display area from outside the first and second transparent display areas, compared to each signal line controlling one pixel, the embodiments of this disclosure can control more pixels with fewer signal lines, which is beneficial for increasing the pixel density in the transparent display area, increasing the resolution of the transparent display area, and improving the display effect of the transparent display area.

[0027] Given a fixed number of pixels arranged within the transparent display area, compared to each signal line controlling one pixel, the number of signal lines used to control the light emission of the light-emitting devices in the transparent display area is reduced in this embodiment, facilitating wiring. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 This is a top view of a display substrate provided in an embodiment of this disclosure;

[0030] Figure 2This is a pixel distribution diagram of a display substrate provided in an embodiment of this disclosure;

[0031] Figure 3 This is a cross-sectional schematic diagram of a display substrate provided in an embodiment of this disclosure;

[0032] Figure 4 This is a cross-sectional schematic diagram of a third pixel provided in an embodiment of this disclosure;

[0033] Figure 5 This is a circuit structure diagram of a pixel circuit provided in an embodiment of the present disclosure;

[0034] Figure 6 This is a timing diagram of a pixel circuit provided in an embodiment of this disclosure;

[0035] Figure 7 This is a distribution map of a second pixel provided in an embodiment of this disclosure;

[0036] Figure 8 This is a cross-sectional schematic diagram of a second pixel provided in an embodiment of this disclosure;

[0037] Figure 9 This is a cross-sectional schematic diagram of a second pixel provided in an embodiment of this disclosure;

[0038] Figure 10 This is a connection diagram of a first pixel circuit provided in an embodiment of this disclosure;

[0039] Figure 11 This is a cross-sectional schematic diagram of a first pixel provided in an embodiment of this disclosure;

[0040] Figure 12 This is a top view of a first pixel provided in an embodiment of this disclosure;

[0041] Figure 13 This is a cross-sectional schematic diagram of a first pixel provided in an embodiment of this disclosure;

[0042] Figure 14 This is a top view of a first pixel provided in an embodiment of this disclosure;

[0043] Figure 15 This is a cross-sectional schematic diagram of a first pixel provided in an embodiment of this disclosure. Detailed Implementation

[0044] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.

[0045] In related technologies, in electronic devices using under-display camera technology, the camera is set in the transparent display area of ​​the display substrate, and the light-emitting devices of each pixel in the transparent display area are electrically connected to the pixel circuit located outside the transparent display area through a transparent trace.

[0046] When there are many pixels in the transparent display area, the number of transparent traces increases accordingly. However, since the area of ​​the transparent display area is limited, routing transparent traces is more difficult.

[0047] Figure 1 This is a top view of a display substrate provided in an embodiment of this disclosure. See also... Figure 1 The display substrate has a first transparent display area 1, a second transparent display area 2 surrounding the first transparent display area 1, and a non-transparent display area 3 surrounding the second transparent display area 2.

[0048] Figure 2 This is a pixel distribution diagram of a display substrate provided in an embodiment of this disclosure. See also... Figure 2 The display substrate includes a plurality of first pixels 10 and a plurality of second pixels 20. The plurality of first pixels 10 are arrayed in a first transparent display area 1. Each first pixel 10 includes a first light-emitting device 101 and a first pixel circuit 102 electrically connected to the first light-emitting device 101. The first pixel circuits 102 of the first pixels 10 in the same row are electrically connected to the same first gate line 103, and the first pixel circuits 102 of the first pixels 10 in the same column are electrically connected to the same first data line 104. Each second pixel 20 includes a second light-emitting device 201 and a second pixel circuit 202. The second light-emitting device 201 is located in a second transparent display area 2, and the second pixel circuit 202 is located outside both the first and second transparent display areas 1 and 2. The second light-emitting device 201 and the second pixel circuit 202 are electrically connected through a transparent trace 100.

[0049] like Figure 1 and Figure 2 As shown, the first transparent display area 1 and the second transparent display area 2 together form the transparent display area of ​​the display panel, which is used to house the camera. The orthographic projection of the camera lens onto the display substrate is the camera area, and the orthographic projection of the first transparent display area 1 onto the display substrate is located within the camera area, which is also located within the transparent display area.

[0050] In this embodiment of the disclosure, a transparent display area indicates that the display area has a certain transmittance, allowing light to pass through and enabling the camera to form an image normally. For example, both the first transparent display area 1 and the second transparent display area 2 have a certain transmittance.

[0051] In this embodiment of the disclosure, since the second pixel circuit 202 is located outside the first transparent display area 1 and the second transparent display area 2, and the first pixel circuit 102 is located in the first transparent display area 1, and the transmittance of the area where the pixel circuit is located is low, the transmittance of the second transparent display area 2 is greater than the transmittance of the first transparent display area 1.

[0052] In this embodiment, since both the first pixel circuit and the first light-emitting device are located in the first transparent display area, the traces electrically connected between the first pixel circuit and the first light-emitting device do not need to pass through the second transparent display area. Simultaneously, a scan signal is provided to the first pixel circuit of the first pixel in the same row via the same first gate line, and a data signal is provided to the first pixel circuit of the first pixel in the same column via the same first data line. Therefore, the number of signal lines electrically connected to the first pixels in the first transparent display area is equal to the sum of the number of rows and columns of the first pixels. The number of transparent traces in the second transparent display area is equal to the number of second pixels. Therefore, the number of signal lines used to control the light emission of the light-emitting device in the transparent display area is equal to the sum of the number of first gate lines, first data lines, and transparent traces.

[0053] Given a fixed number of signal lines extending into the transparent display area from outside the first and second transparent display areas, this embodiment of the present disclosure can control more pixels with fewer signal lines compared to each signal line controlling one pixel. This is beneficial for increasing the pixel density (Pixels Per Inch, PPI) in the transparent display area, improving the resolution of the transparent display area, and enhancing the display effect of the transparent display area.

[0054] Given a fixed number of pixels arranged within the transparent display area, compared to each signal line controlling one pixel, the number of signal lines used to control the light emission of the light-emitting devices in the transparent display area is reduced in this embodiment, facilitating wiring.

[0055] Furthermore, since the second transparent display area is set around the first transparent display area, and the space occupied by the first transparent display area is small, the first pixel in the first transparent display area has little impact on the camera's imaging.

[0056] Optionally, the first transparent display area 1 and the second transparent display area 2 have the same pixel density, and are less than or equal to the pixel density of the non-transparent display area 3.

[0057] like Figure 1 and Figure 2 As shown, the display substrate also has a non-display area 4 surrounding the non-transparent display area 3, and the second pixel circuit 202 is located in the non-display area 4. The area in the non-display area 4 used to arrange the second pixel circuit 202 can be referred to as the dummy pixel area.

[0058] Arranging the second pixel circuit 202 in the non-display area 4 avoids affecting the pixel density of the non-transparent display area 3 compared to arranging it in the non-transparent display area 3. Furthermore, since the second light-emitting device 201 and the second pixel circuit 202 are located in different areas, the transparent trace 100 extends from the non-display area 4 to the second transparent display area 2 and is electrically connected to the second light-emitting device 201.

[0059] For example, a transparent display area is used to house a camera, which is typically located in the upper half of the display device. Figure 1 As shown, the transparent display area, which is composed of the first transparent display area 1 and the second transparent display area 2, is also located in the upper half of the display substrate.

[0060] like Figure 2 As shown, the second pixel circuit 202 is located in the upper half of the display substrate, which makes the second pixel circuit 202 closer to the second light-emitting device 201. This can shorten the length of the transparent trace 100, which can reduce the obstruction of the camera by the transparent trace 100 and reduce the voltage drop generated by the transparent trace 100, thereby improving the uniformity of the signal.

[0061] It should be noted that, in Figure 2 In order to clearly show the distribution of pixels in the display substrate, the electrical connection between some of the second light-emitting devices 201 and the second pixel circuit 202 is not shown. In practice, each second light-emitting device 201 is electrically connected to the second pixel circuit 202 through a corresponding transparent trace 100.

[0062] Alternatively, in other implementations, the second pixel circuit 202 may also be located in the non-transparent display area 3. In this implementation, a portion of the pixels in the non-transparent display area 3 adjacent to the second transparent display area 2 are set as dummy pixels, that is, only the second pixel circuit 202 is included, without the light-emitting device.

[0063] In this embodiment of the disclosure, the difference between the number of rows and the number of columns of the first pixel 10 is between 0 and 2.

[0064] Since the first pixel circuit 102 of the first pixel 10 in the same row is electrically connected to the same first gate line 103, and the first pixel circuit 102 of the first pixel 10 in the same column is electrically connected to the same first data line 104, the sum of the number of first gate lines 103 and first data lines 104 is equal to the sum of the number of rows and columns of the first pixel 10. By changing the arrangement of the first pixels 10, the sum of the number of rows and columns of the first pixel 10 changes accordingly, thereby changing the sum of the number of first gate lines 103 and first data lines 104. When the sum of the number of first pixels 10 remains constant, the closer the number of rows and columns of the first pixel 10 are, the smaller the sum of the number of rows and columns of the first pixel 10, and therefore the smaller the sum of the number of first gate lines 103 and first data lines 104.

[0065] For example, if there are 100 first pixels 10, when both the number of rows and columns of the first pixel 10 are 10, the total number of first gate lines 103 and first data lines 104 is 20. When the number of rows of the first pixel 10 is 5 and the number of columns is 20, the total number of first gate lines 103 and first data lines 104 is 25. When the number of rows of the first pixel 10 is 4 and the number of columns is 25, the total number of first gate lines 103 and first data lines 104 is 29. It can be seen that the closer the number of rows and columns of the first pixel 10 are, the smaller the sum of the number of rows and columns of the first pixel 10.

[0066] It should be noted that, in Figure 2 In order to clearly display the first pixel 10 in the first transparent display area 1, only 4 first pixels 10 are displayed. The number of first pixels 10 can be arranged according to the actual situation.

[0067] For example, such as Figure 2 As shown, the orthographic projection of the first transparent display area 1 onto the display substrate is a rectangle, and the orthographic projection of the second transparent display area 2 onto the display substrate is also a rectangle.

[0068] like Figure 2 As shown, the first transparent display area 1 is located in the middle of the second transparent display area 2. In other implementations, the first transparent display area 1 can be located at any position in the second transparent display area 2, as long as at least two sides of the first transparent display area 1 are surrounded by the second transparent display area 2. For example, the first transparent display area 1 can be located at the upper left of the second transparent display area 2.

[0069] In other implementations, the outer contours of the orthographic projections of the first transparent display area 1 and the second transparent display area 2 onto the display substrate can also be other shapes. For example, the outer contours of the orthographic projections of the first transparent display area 1 and the second transparent display area 2 onto the display substrate can both be circular. This disclosure does not limit this.

[0070] The outer contour shapes of the first transparent display area 1 and the second transparent display area 2 projected onto the display substrate may be the same or different, and this disclosure does not impose any restrictions on this.

[0071] In this embodiment of the disclosure, the transparent trace 100 is an indium tin oxide (ITO) trace.

[0072] Indium tin oxide (ITO) has good transparency, which can ensure the transparency of transparent traces. Transparent trace 100 is used to transmit electrical signals. ITO is conductive and can be used to transmit electrical signals.

[0073] In this embodiment, the transparent trace 100 can also be made of other materials with good transparency and conductivity, such as indium zinc oxide (IZO).

[0074] In this embodiment, the first gate line 103 located within the second transparent display area 2 is a transparent trace, and the first data line 104 located within the second transparent display area 2 is a transparent trace. That is, in this embodiment, the first gate line 103 is divided into three sequentially connected parts, located in the first transparent display area 1, the second transparent display area 2, and the non-transparent display area 3, respectively. The portion of the first gate line 103 located in the second transparent display area 2 is transparent to avoid affecting the transmittance of the second transparent display area 2.

[0075] See you again Figure 1 The display substrate also includes a driving integrated circuit 40 located in the non-display area 4. The driving integrated circuit 40 provides a scanning signal to the first pixel circuit 102 of the first pixel 10 in the same row through a first gate line 103, and simultaneously provides a data signal to the first pixel circuit 102 of the first pixel 10 in the same column through a first data line 104. Therefore, both the first gate line 103 and the first data line 104 need to pass through the second transparent display area 2. By arranging the first gate line 103 and the first data line 104 located in the second transparent display area 2 as transparent traces, even if the first transparent display area 1 has a large number of first pixels 10, making the traces of the first gate line 103 and the first data line 104 dense, the obstruction of the camera by the first gate line 103 and the first data line 104 can be reduced.

[0076] In this embodiment of the disclosure, the first gate line 103 located in the second transparent display area 2 and the first data line 104 located in the second transparent display area 2 are both indium tin oxide traces.

[0077] Indium tin oxide has good transparency, which can ensure the transparency of the first gate line 103 and the first data line 104. The first gate line 103 and the first data line 104 are used to transmit electrical signals. Indium tin oxide is conductive and can be used to transmit electrical signals.

[0078] In this embodiment, the first gate line 103 and the first data line 104 located within the second transparent display area 2 can also be made of other materials with good transparency and conductivity, such as indium zinc oxide.

[0079] In this embodiment of the disclosure, the materials of the first gate line 103 and the first data line 104 may be the same or different.

[0080] In this embodiment of the disclosure, the first gate line 103 located in the first transparent display area 1 and the non-transparent display area 3 can be a transparent trace or an opaque trace, and the first data line 104 located in the first transparent display area 1 and the non-transparent display area 3 can be a transparent trace or an opaque trace.

[0081] For example, the first gate line 103 and the first data line 104 located in the first transparent display area 1 and the non-transparent display area 3 can be metal traces.

[0082] In this embodiment of the disclosure, the ratio of the area of ​​the orthographic projection of the first transparent display area 1 onto the surface of the display substrate to the sum of the area of ​​the orthographic projection of the first transparent display area 1 onto the surface of the display substrate and the area of ​​the orthographic projection of the second transparent display area 2 onto the surface of the display substrate is less than or equal to 15 percent.

[0083] Because both the first light-emitting device 101 and the first pixel circuit 102 are arranged in the first transparent display area 1, the area occupied by the first pixel 10 in the first transparent display area 1 is relatively large. Since the first pixel 10 is not transparent, if the area occupied by the first transparent display area 1 is large, it may obstruct the camera and affect the camera's imaging effect. In this embodiment, the ratio of the area of ​​the first transparent display area 1 to the total area of ​​the transparent area is limited, making the area of ​​the first transparent display area 1 smaller. This effectively reduces the obstruction of the camera by the first transparent display area 1.

[0084] In this embodiment of the disclosure, the ratio of the first transparent display area 1 to the second transparent display area 2 can be adjusted by simulation to reduce the impact of the first transparent display area 1 on camera imaging while optimizing the layout.

[0085] Figure 3 This is a cross-sectional schematic diagram of a display substrate provided in an embodiment of this disclosure. See also... Figure 3 The display substrate includes a substrate 500, a buffer layer 501, a thin film transistor (TFT) array layer 502, an insulating (PVX) layer 503, a wiring layer 504, a first planarization (PLN) layer 505, a pixel definition layer (PDL) 506, a light-emitting device array layer 507, a second planarization layer 508, and an encapsulation layer 509, which are stacked sequentially.

[0086] In this embodiment of the disclosure, the substrate 500 provides support for the entire display substrate. The substrate 500 is a transparent substrate to ensure its transparency; for example, the substrate 500 can be a glass substrate.

[0087] For example, the buffer layer 501 may be a resin layer.

[0088] Multiple thin-film transistors are arranged in the thin-film transistor array layer 502, and each pixel circuit includes multiple thin-film transistors. The driving integrated circuit controls the light emission of the pixel through the thin-film transistors. The first gate line 103 and the first data line 104 are both located in the thin-film transistor array layer 502.

[0089] The insulating layer 503 separates the thin-film transistor array layer 502 from the wiring layer 504, preventing interference between the thin-film transistors in the thin-film transistor array layer 502 and the wiring in the wiring layer 504, which would affect the transmission of electrical signals. The insulating layer 503 can be an inorganic insulating layer, such as a silicon nitride (SiN) layer or a silicon oxynitride (SiON) layer, or an organic insulating layer, such as an epoxy resin insulating layer. Silicon nitride and epoxy resin have good insulating properties, ensuring the insulation of the insulating layer 503.

[0090] The trace layer 504 is used to arrange the transparent trace 100. The trace layer 504 is an indium tin oxide layer.

[0091] The first planarization layer 505 is located between the pixel defining layer 506 and the wiring layer 504. Exemplarily, the first planarization layer 505 may be a resin layer, a silicon-on-glass (SOG) layer, or other organic film layer.

[0092] The pixel defining layer 506 has grooves for arranging light-emitting devices. The light-emitting devices emit light, enabling the display substrate to display an image.

[0093] The second planarization layer 508 makes the surface of the display substrate after the formation of the light-emitting device array layer 507 flatter, facilitating subsequent encapsulation and improving the display effect of the display panel. For example, the second planarization layer 508 can be a resin layer, a silicon-glass layer, or other organic film layer. The materials of the first planarization layer 505 and the second planarization layer 508 can be the same or different.

[0094] The encapsulation layer 509 encapsulates the display substrate and protects its internal structure.

[0095] For example, thin-film encapsulation (TFE) can be used for encapsulation to ensure the encapsulation effect.

[0096] In this embodiment, the first gate line 103 and the transparent trace 100 are on different layers, and the first data line 104 and the transparent trace 100 are on different layers. The fact that the first gate line 103 and the transparent trace 100 are on different layers indicates that they were not fabricated using the same patterning process. Similarly, the fact that the first data line 104 and the transparent trace 100 are on different layers indicates that they were not fabricated using the same patterning process.

[0097] Since both the first gate line 103 and the first data line 104 need to pass through the second transparent display area 2, and the transparent trace 100 electrically connecting the second light-emitting device 201 and the second pixel circuit 202 also needs to pass through the second transparent display area 2, if the first gate line 103 and the first data line 104 are arranged on the same layer as the transparent trace 100, the first gate line 103 and the first data line 104 will occupy a portion of the area in the second transparent display area 2, resulting in a reduction in the area available for arranging the transparent trace 100, making the routing of the transparent trace 100 difficult. By arranging the first gate line 103 and the transparent trace 100 on separate layers, and the first data line 104 and the transparent trace 100 on the same separate layers, the transparent trace 100 can be arranged in the original positions where the first gate line 103 and the first data line 104 were arranged, thus increasing the area available for arranging the transparent trace 100 and facilitating its arrangement. Since the area of ​​the transparent traces 100 is increased, more transparent traces 100 can be arranged to electrically connect the second light-emitting devices 201 and the second pixel circuit 202 when more second light-emitting devices 201 and second pixel circuits 202 are arranged, thereby increasing the number of second light-emitting devices 201 in the second transparent display area 2, which in turn improves the resolution of the second transparent display area 2.

[0098] In this embodiment of the disclosure, multiple transparent traces 100 are located in different layers of the display substrate.

[0099] Although the first gate line 103 and the first data line 104 are arranged in different film layers from the transparent trace 100, the number of transparent traces 100 remains large when the number of second light-emitting devices 201 in the second transparent display area 2 increases. If multiple transparent traces 100 are arranged in the same layer, fabrication becomes difficult. Furthermore, due to limitations in the fabrication process, the linewidth and pitch of the transparent traces 100 cannot be made sufficiently small, thus limiting the number of transparent traces 100 that can pass through the second transparent display area 2. Arranging multiple transparent traces 100 in different layers of the display substrate facilitates their arrangement and avoids excessive numbers of transparent traces 100 in a single layer, which could lead to contact between the traces and affect signal transmission. Simultaneously, since the transparent traces 100 are located in different film layers, more transparent traces 100 can be arranged, allowing for the arrangement of more second light-emitting devices 201 and improving the resolution of the second transparent display area 2.

[0100] In this embodiment of the present disclosure, when only one insulating layer 503 and one wiring layer 504 are arranged in the display substrate, the insulating layer 503 and the wiring layer 504 are stacked. When multiple insulating layers 503 and multiple wiring layers 504 are arranged in the display substrate, the multiple insulating layers 503 and multiple wiring layers 504 are stacked alternately.

[0101] For example, in this embodiment of the disclosure, there are a total of three wiring layers for arranging transparent traces 100, and multiple transparent traces 100 are evenly distributed in these three wiring layers.

[0102] like Figure 3 As shown, the three wiring layers are the first wiring layer 541, the second wiring layer 542, and the third wiring layer 543. The first wiring layer 541 is separated from the thin-film transistor array layer 502 by a first insulating layer 531, the first wiring layer 541 is separated from the second wiring layer 542 by a second insulating layer 532, and the second wiring layer 542 is separated from the third wiring layer 543 by a third insulating layer 533, so as to avoid affecting the transmission of electrical signals.

[0103] In this embodiment, a first insulating layer 531 is fabricated on the thin-film transistor array layer 502, and then a first wiring layer 541 is fabricated on the first insulating layer 531 for arranging a portion of the transparent wiring 100. A second insulating layer 532 is then fabricated on the first wiring layer 541, and a second wiring layer 542 is fabricated on the second insulating layer 532 for arranging a portion of the transparent wiring 100. A third insulating layer 533 is then fabricated on the second wiring layer 542, and a third wiring layer 543 is fabricated on the third insulating layer 533 for arranging the final portion of the transparent wiring 100. A total of three wiring layers are fabricated for arranging the transparent wiring 100.

[0104] See you again Figure 2 The display substrate also includes a plurality of third pixels 30. The plurality of third pixels 30 are arrayed in the non-transparent display area 3. Each third pixel 30 includes a third light-emitting device 301 and a third pixel circuit 302 electrically connected to the third light-emitting device 301. The area of ​​the orthographic projection of the third pixel 30 onto the surface of the display substrate is larger than the area of ​​the orthographic projection of the first pixel 10 onto the surface of the display substrate.

[0105] The non-transparent display area 3 is a display area without a camera. Since the non-transparent display area 3 does not need to have a camera, the third pixel 30 in the non-transparent display area 3 can be made larger, reducing the manufacturing difficulty.

[0106] The area of ​​the orthographic projection of the third pixel 30 onto the surface of the display substrate is the sum of the areas of the orthographic projections of the third light-emitting device 301 and the third pixel circuit 302 onto the surface of the display substrate. Similarly, the area of ​​the orthographic projection of the first pixel 10 onto the surface of the display substrate is the sum of the areas of the orthographic projections of the first light-emitting device 101 and the first pixel circuit 102 onto the surface of the display substrate. Reducing the area of ​​the orthographic projection of the first pixel 10 onto the surface of the display substrate can reduce the size of the first pixel circuit 102.

[0107] For example, the size of the gate and source / drain in the first pixel circuit 102 can be reduced, for example, by reducing the length and width of the gate and source / drain, or the size of the gate line and data line can be reduced, for example, by reducing the line width of the gate line and data line, to reduce the size of the first pixel circuit 102.

[0108] As the size of the first pixel circuit 102 is reduced, the space in the first transparent display area 1 where the pixel circuit is not arranged increases, thereby improving the transmittance of the first transparent display area 1.

[0109] like Figure 2 As shown, the third pixel circuit 302 and the second pixel circuit 202 are both electrically connected to the driver integrated circuit 40 through data lines and gate lines.

[0110] like Figure 2 As shown, some third pixel circuits 302 are located in the same row or column as the first pixel circuit 102; some third pixel circuits 302 are located in different rows and different columns as the first pixel circuit 102.

[0111] The first pixel circuit 102 and the third pixel circuit 302, located in the same row, are electrically connected to the same gate line. At this time, the third pixel circuit 302 is electrically connected to the portion of the first gate line 103 located in the non-transparent display area 3. The first pixel circuit 102 and the third pixel circuit 302, located in the same column, are electrically connected to the same data line. At this time, the third pixel circuit 302 is electrically connected to the portion of the first data line 104 located in the non-transparent display area 3.

[0112] For the third pixel circuit 302 which is neither in the same row nor the same column as the first pixel circuit 102, the third pixel circuit 302 located in the same row is electrically connected to the same second gate line 107, and the third pixel circuit 302 located in the same column is electrically connected to the same second data line 106.

[0113] See you again Figure 2 If a portion of the second pixel circuit 202 is located in the same column as the first pixel circuit 102, then this portion of the second pixel circuit 202 is electrically connected to the corresponding portion of the first data line 104 located in the non-display area 4. If another portion of the second pixel circuit 202 is located in a different column from the first pixel circuit 102, then this other portion of the second pixel circuit 202 is electrically connected to the corresponding portion of the second data line 106 located in the non-display area 4.

[0114] In this embodiment of the disclosure, the second pixel circuit 202 and the third pixel circuit 302 have the same structure.

[0115] Figure 4 This is a schematic cross-sectional view of a third pixel provided in an embodiment of this disclosure. See also... Figure 4 The thin-film transistor array layer 502 includes an active (Act) layer 521, a gate insulator (GI) layer 522, a gate layer 523, and a source drain (SD) layer 524, which are stacked sequentially.

[0116] In this embodiment, the gate insulating layer 522 is located between the active layer 521 and the gate layer 523. The gate insulating layer 522 separates the active layer 521 and the gate layer 523, ensuring that the active layer 521 and the gate layer 523 are isolated from each other and can transmit signals independently.

[0117] For example, the gate insulating layer 522 can be an inorganic insulating layer, such as a silicon nitride (SiN) layer or a silicon oxynitride (SiON) layer, or an organic insulating layer, such as an epoxy resin insulating layer. Silicon nitride and epoxy resin have good insulating properties, ensuring the insulation of the gate insulating layer 522.

[0118] Since the third pixel circuit is located in the non-transparent display area 3, the gate layer 523 and the source / drain layer 524 in the third pixel circuit can be indium tin oxide layers or metal layers, such as copper (Cu) layers. That is, in the non-transparent display area 3, the gate layer 523 and the source / drain layer 524 can be opaque.

[0119] Figure 4 The diagram shows a top-gate TFT structure, except... Figure 4 Besides the TFT structure shown, the TFT can also be a bottom-gate or dual-gate TFT structure. In other structures, the TFT can also include two gate layers 523 or two source-drain layers 523. When there are two gate layers 523, there are also two gate insulating layers 522. When there are two source-drain layers 523, an inter-layer dielectric (ILD) can also be disposed between the two source-drain layers.

[0120] like Figure 4 As shown, the pixel defining layer 506 is used to separate the individual sub-pixels of the Organic Light Emitting Display (OLED). That is, the pixel defining layer 60 forms multiple sub-pixel regions in the display area 2 through its own groove structure. Light-emitting devices are formed within the grooves of the pixel defining layer 506. These devices include an anode layer 571, a hole transport layer 572, an organic light-emitting layer 573, an electron transport layer 574, and a cathode layer 575 shared by each pixel, all disposed within the grooves of the pixel defining layer 506. The anode layer 571, hole transport layer 572, organic light-emitting layer 573, electron transport layer 574 in one groove, along with the cathode layer 575 shared by each pixel, form one organic light-emitting device.

[0121] In one implementation of this disclosure, the number of components in the first pixel circuit 102 is less than the number of components in the third pixel circuit 302.

[0122] Since the first pixel circuit 102 is located in the first transparent display area 1, reducing the number of components in the first pixel circuit 102 can reduce its size, thereby reducing the obstruction of the camera by the first pixel 10. When the number of components in the first pixel circuit 102 is less than the number of components in the third pixel circuit 302, it is easier to make the first pixel circuit 102 smaller, further reducing the obstruction of the camera by the first pixel 10. For example, the third pixel circuit 302 has a 7T1C (7 thin-film transistors, 1 capacitor) structure, while the first pixel circuit 102 has a 2T1C structure.

[0123] In another implementation of this embodiment, the circuit structure of the first pixel circuit 102 is the same as that of the third pixel circuit 302. In this case, when the number of components in the first pixel circuit 102 is equal to the number of components in the third pixel circuit 302, the first pixel circuit 102 and the third pixel circuit 302 have identical structures, which facilitates manufacturing. Furthermore, it improves the uniformity of the display effect in the display area.

[0124] For example, the third pixel circuit 302 has a 7T1C structure, and the first pixel circuit 102 also adopts a 7T1C structure.

[0125] Figure 5 This is a circuit structure diagram of a pixel circuit provided in an embodiment of this disclosure. See also... Figure 5The transistor configuration is as follows: Data is the data input terminal, Reset is the reset signal terminal, Gate is the scan signal terminal, EM is the light emission control signal terminal, Vinit is the initialization voltage, VDD is the first voltage signal terminal, and VSS is the second voltage signal terminal. The first voltage signal (VDD) is used to provide the first voltage signal, and the second voltage signal terminal (VSS) is used to provide the second voltage signal. The first voltage signal is a high-level signal relative to the second voltage signal. T3 is a driving transistor, and T4 is a switching transistor. The gate of T1 is electrically connected to the reset signal terminal, and the source of T1 is electrically connected to the first initialization voltage (Vinit1). The drain of T1 is electrically connected to the drain of T2 and the gate of T3, and simultaneously electrically connected to one plate of capacitor Cst. The gate of T2 is electrically connected to the scan signal terminal, and the source of T2 is electrically connected to the drain of T3 and the source of T6. The drain of T4 is electrically connected to the source of T3 and the drain of T5. The source of T4 is electrically connected to the data input terminal, and the gate of T4 is electrically connected to the scan signal terminal. The source of T5 is electrically connected to the other plate of capacitor Cst, and the source of T5 is also electrically connected to the first voltage signal terminal. The gate of T5 is electrically connected to the light emission control signal terminal. The gate of T6 is electrically connected to the light emission control signal terminal, the drain of T6 is electrically connected to the drain of T7, and is also electrically connected to one end of the Organic Light-Emitting Diode (OLED). The other end of the OLED is electrically connected to the second voltage signal terminal. The source of T7 is electrically connected to the second initialization voltage (Vinit2), and the gate of T7 is electrically connected to the scan signal terminal.

[0126] Figure 6 This is a timing diagram of a pixel circuit provided in an embodiment of this disclosure. See also... Figure 6 During the reset phase t1, T1 is turned on, resetting the gate of T3 to Vinit1. During the data writing phase t2, T2, T4, and T7 are turned on, writing a data signal to the source of T4. The data signal passes through T3 and T2, charging capacitor Cst, causing the gate voltage of T3 to become Vdata. Since T5 and T6 are both low-level turned on, and high-level turned on during both the reset phase t1 and the data writing phase t2, T5 and T6 are turned off during both phases, and the OLED does not emit light. During the light-emitting phase t3, a low-level signal is input to T5 and T6, turning them on, and the OLED emits light.

[0127] In this embodiment of the disclosure, the structure of the first pixel circuit 102 can be simplified by external compensation, thereby reducing the size of the first pixel circuit 102, reducing the obstruction of the camera by the first pixel circuit 102, and ensuring that the first pixel circuit 102 can provide sufficient voltage.

[0128] In this embodiment, the area where the second pixel circuit 202 is located can be divided into multiple first sub-regions, and the area where the second light-emitting device 201 is located can be divided into multiple second sub-regions corresponding to the first sub-regions. The number of second pixel circuits 202 in a first sub-region is equal to the number of second light-emitting devices 201 in a second sub-region. The second pixel circuits 202 in a first sub-region are electrically connected to the corresponding second light-emitting devices 201 in the second sub-region.

[0129] Figure 7 This is a distribution map of a second pixel provided in an embodiment of this disclosure. See also... Figure 7 The second pixel circuit 202 located above the display substrate can be divided into 8 regions, namely A1, A2, A3, A4, A5, A6, A7, and A8. The second light-emitting device 201 surrounding the first transparent display area 1 can also be divided into 8 regions, namely B1, B2, B3, B4, B5, B6, B7, and B8. Specifically, the second pixel circuit 202 in region A1 is electrically connected to the second light-emitting device 201 in region B1, the second pixel circuit 202 in region A2 is electrically connected to the second light-emitting device 201 in region B2, the second pixel circuit 202 in region A3 is electrically connected to the second light-emitting device 201 in region B3, the second pixel circuit 202 in region A4 is electrically connected to the second light-emitting device 201 in region B4, the second pixel circuit 202 in region A5 is electrically connected to the second light-emitting device 201 in region B5, the second pixel circuit 202 in region A6 is electrically connected to the second light-emitting device 201 in region B6, the second pixel circuit 202 in region A7 is electrically connected to the second light-emitting device 201 in region B7, and the second pixel circuit 202 in region A8 is electrically connected to the second light-emitting device 201 in region B8.

[0130] exist Figure 7 In order to clearly show the second light-emitting device 201 and the second pixel circuit 202, pixels and wiring in other areas are omitted.

[0131] Figure 7 The area division shown is just an example. The area where the second pixel circuit 202 is located and the area where the second light-emitting device 201 is located can be divided according to the actual situation.

[0132] Figure 8 This is a cross-sectional schematic diagram of a second pixel provided in an embodiment of this disclosure. See also... Figure 8 The second light-emitting device 201 is electrically connected to the second pixel circuit 202 through the transparent trace 100 in the trace layer 504.

[0133] Figure 8 The second pixel shown has only one insulating layer 503 and one wiring layer 504.

[0134] Figure 9 This is a cross-sectional schematic diagram of a second pixel provided in an embodiment of this disclosure. See also... Figure 9 The second pixel contains only three insulating layers 503 and three wiring layers 504. Each second pixel circuit 202 is electrically connected to a second light-emitting device 201 through a corresponding transparent trace 100.

[0135] like Figure 8 and Figure 9 As shown, the transparent trace 100 is located on the thin-film transistor array layer 502. The film layer containing the transparent trace 100 is located on a first side of the thin-film transistor array layer 502 of the display substrate, which is the side of the thin-film transistor array layer 502 closest to the display surface of the display substrate. For example, the transparent trace 100 is located above the source-drain layer 524 of the thin-film transistor array layer 502, that is, the distance between the film layer containing the transparent trace 100 and the surface of the substrate 500 is greater than the distance between the source-drain layer 524 and the surface of the substrate 500.

[0136] In this embodiment, the thin-film transistor is a bottom-gate thin-film transistor. The transparent trace 100 is arranged on the source-drain layer, that is, the transparent trace 100 is on a different layer from the gate layer 523 and the source-drain layer 524. Therefore, the transparent trace 100 is on a different layer from the first gate line 103 and the first data line 104, which facilitates the arrangement of the trace.

[0137] Figure 10 This is a schematic diagram of the connection of a first pixel circuit according to an embodiment of this disclosure. See also... Figure 10 ,lie in Figure 10 The third pixel circuit 302 is located on the left. Figure 10 The right side is the first pixel circuit 102. The first data line 104 passes through the fourth insulating layer 511 located on the thin film transistor array layer 502 and electrically connects the first pixel circuit 102 and the third pixel circuit 302. The third pixel circuit 302 is electrically connected to the driver integrated circuit 40 through the second gate line.

[0138] Figure 10 The diagram shows the arrangement of the first data line 104. Similarly, the first gate line 103 can also be arranged in the same way, that is, the first gate line 103 is arranged in the fourth insulating layer 511.

[0139] Figure 10 The film layer above the fourth insulating layer 511 is omitted simply to show the arrangement of the first data line 104.

[0140] Figure 11 This is a cross-sectional schematic diagram of a first pixel provided in an embodiment of this disclosure. See also... Figure 11The first pixel 10 has a shielding structure 105 that shields the first pixel circuit 102. The shielding structure 105 is located below the first light-emitting device 101, that is, on the side of the first light-emitting device 101 away from the display surface of the display substrate. The projection of the first pixel circuit 102 on the surface of the display substrate and the projection of the shielding structure 105 on the surface of the display substrate at least partially overlap. That is, the orthographic projection of the first pixel circuit 102 on the surface of the display substrate and the orthographic projection of the shielding structure 105 on the surface of the display substrate partially overlap, or the orthographic projection of the first pixel circuit 102 on the surface of the display substrate and the orthographic projection of the shielding structure 105 on the surface of the display substrate completely overlap.

[0141] Multiple first pixels 10 are arranged at intervals, with gaps between them. During camera capture, diffraction occurs between these gaps, affecting the camera's imaging performance. A blocking structure 105 is created within each first pixel 10. This blocking structure 105 is located between the first pixel circuit 102 and the light-emitting layer of the first light-emitting device 101. The blocking structure 105 blocks the first pixel circuit 102 and also blocks the gaps within it, thus preventing diffraction from affecting the camera's imaging performance. Since the blocking structure 105 is designed to block light entering the camera through the gaps without affecting the light emission of the light-emitting layer, it is located below the first light-emitting device 101.

[0142] In one embodiment of this disclosure, the shielding layer is an integral structure located in the entire first transparent display area 1, and the shielding layer is used to shield a plurality of first pixel circuits 102 in the first transparent display area 1.

[0143] Figure 12 This is a top view of a first pixel provided in an embodiment of this disclosure. See also... Figure 12 The shielding layer is an integral structure, and the orthographic projection of the first pixel circuit 102 on the shielding layer is located within the shielding layer. In addition to shielding the gaps between the components of the first pixel circuit 102, this integral structure can also shield the gaps between adjacent first pixel circuits 102, thereby reducing the impact of diffraction on the imaging effect of the camera.

[0144] For example, the shielding structure 105 is opaque and can block the gaps between the first pixel circuits 102, reducing the impact on the imaging effect of the camera.

[0145] In one implementation of this disclosure, the shielding structure 105 is a shielding layer, located between the substrate 500 and the buffer layer 501 in a direction perpendicular to the surface of the display substrate, such as... Figure 11As shown.

[0146] In another implementation of the present disclosure, the occlusion layer is located between the first light-emitting device 101 and the first pixel circuit 102 of the first pixel 10. Figure 13 This is a cross-sectional schematic diagram of a first pixel provided in an embodiment of this disclosure. For example... Figure 13 As shown, a fifth insulating layer 510 is arranged between the shielding structure 105 and the thin film transistor array layer 502.

[0147] like Figure 13 As shown, the shielding structure 105 has multiple openings, each of which has a via 151 that passes through the shielding structure 105 and the fifth insulating layer 510. The anode of the first light-emitting device 101 is electrically connected to the first pixel circuit through the via 151.

[0148] In one implementation of this disclosure, the shielding layer is a metal shielding layer. Metal is low in cost and easy to manufacture. In other implementations, the shielding layer can also be made of other opaque materials.

[0149] like Figure 13 As shown, when the shielding layer is a metal shielding layer, an insulating material 152 is arranged on the inner sidewall of the opening to prevent multiple first pixel circuits 102 from being electrically connected through the metal shielding layer, thus affecting the transmission of electrical signals.

[0150] Alternatively, in other implementations, the occlusion layer includes multiple occlusion regions, each occluding a first pixel circuit 102.

[0151] Figure 14 This is a top view of a first pixel provided in an embodiment of this disclosure. The occlusion structure 105 is the anode of the first light-emitting device 101.

[0152] Since the anode layer 571 is opaque, that is, the anode of the first light-emitting device 101 is opaque, the anode of the first light-emitting device 101 can be made larger, and the first pixel circuit 102 can be placed below the first light-emitting device 101. The anode can then shield the first pixel circuit 102 without adding any process steps, making it easy to manufacture.

[0153] Figure 15 This is a cross-sectional schematic diagram of a first pixel provided in an embodiment of this disclosure. See also... Figure 15 The first pixel circuit 102 is located below the anode layer 571.

[0154] For example, the projection of the first pixel circuit 102 onto the surface of the display substrate at least partially overlaps with the projection of the anode of the first light-emitting device 101 onto the surface of the display substrate.

[0155] The first pixel circuit 102 is arranged below the anode of the first light-emitting device 101. The anode of the first light-emitting device 101 is used to block the gaps between the components of the first pixel circuit 102, so as to avoid diffraction between the gaps between the components of the first pixel circuit 102 and affect the imaging effect of the camera.

[0156] This disclosure also provides a display device, which includes a display substrate shown in any of the foregoing figures.

[0157] In specific implementation, the display device provided in the embodiments of this disclosure can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0158] The above description is merely an optional embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A display substrate, characterized in that, The display substrate has a first transparent display area, a second transparent display area surrounding the first transparent display area, a non-transparent display area surrounding the second transparent display area, and a non-display area surrounding the non-transparent display area; The display substrate includes: Multiple first pixels, each first pixel including a first light-emitting device and a first pixel circuit electrically connected to the first light-emitting device, the multiple first pixel arrays are distributed in the first transparent display area, the first pixel circuits of the first pixels in the same row are electrically connected to the same first gate line, and the first pixel circuits of the first pixels in the same column are electrically connected to the same first data line. Multiple second pixels, each second pixel including a second light-emitting device and a second pixel circuit, the second light-emitting device being located in the second transparent display area, the second pixel circuit being located in the non-display area, and the second light-emitting device and the second pixel circuit being electrically connected through transparent traces; Multiple third pixels are arrayed in the non-transparent display area, and each third pixel includes a third light-emitting device and a third pixel circuit electrically connected to the third light-emitting device. All pixels in the first transparent display area are the first pixels, and all light-emitting devices in the second transparent display area are the second light-emitting devices; The multiple transparent traces are located in different layers of the display substrate, the first gate line is on a different layer from the transparent traces, and the first data line is on a different layer from the transparent traces; The first gate line and the first data line located within the second transparent display area are transparent traces, while the first gate line and the first data line located within the first transparent display area and the non-transparent display area are metal traces. The first pixel circuit and the third pixel circuit located in the same row are electrically connected to the same first gate line, and the third pixel circuit is electrically connected to the portion of the corresponding first gate line located in the non-transparent display area; the first pixel circuit, the second pixel circuit and the third pixel circuit located in the same column are electrically connected to the same first data line, and the second pixel circuit is electrically connected to the portion of the corresponding first data line located in the non-display area, and the third pixel circuit is electrically connected to the portion of the corresponding first data line located in the non-transparent display area.

2. The display substrate according to claim 1, characterized in that, The difference between the number of rows and the number of columns of the first pixel is between 0 and 2.

3. The display substrate according to claim 1, characterized in that, The ratio of the area of ​​the first transparent display area projected onto the surface of the display substrate to the sum of the areas of the first transparent display area projected onto the surface of the display substrate and the areas of the second transparent display area projected onto the surface of the display substrate is less than or equal to 15 percent.

4. The display substrate according to claim 1, characterized in that, The area of ​​the orthographic projection of the third pixel on the surface of the display substrate is larger than the area of ​​the orthographic projection of the first pixel on the surface of the display substrate.

5. The display substrate according to claim 4, characterized in that, The number of components in the first pixel circuit is less than the number of components in the third pixel circuit, or the circuit structure of the first pixel circuit is the same as that of the third pixel circuit.

6. The display substrate according to claim 1 or 5, characterized in that, It also includes a blocking structure located in the first transparent display area, the blocking structure being configured to block light from the display surface of the display substrate passing through the first pixel circuit.

7. The display substrate according to claim 6, characterized in that, The shielding structure is a shielding layer located on the side of the first light-emitting device away from the display surface of the display substrate, and the projection of the first pixel circuit on the surface of the display substrate is located within the projection of the shielding structure on the surface of the display substrate.

8. The display substrate according to claim 7, characterized in that, The shielding layer is a metal shielding layer.

9. The display substrate according to claim 6, characterized in that, The shielding structure is the anode of the first light-emitting device.

10. The display substrate according to claim 1, characterized in that, The transparent trace is located on the first side of the thin-film transistor array layer of the display substrate, which is the side of the thin-film transistor array layer that is close to the display surface of the display substrate.

11. A display device, characterized in that, The display device includes a display substrate as described in any one of claims 1 to 10.

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